Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml


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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/starfive,jh8100-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: StarFive External Interrupt Controller

description:
  StarFive SoC JH8100 contain a external interrupt controller. It can be used
  to handle high-level input interrupt signals. It also send the output
  interrupt signal to RISC-V PLIC.

maintainers:
  - Changhuang Liang <changhuang.liang@starfivetech.com>

properties:
  compatible:
    const: starfive,jh8100-intc

  reg:
    maxItems: 1

  clocks:
    description: APB clock for the interrupt controller
    maxItems: 1

  resets:
    description: APB reset for the interrupt controller
    maxItems: 1

  interrupts:
    maxItems: 1

  interrupt-controller: true

  "#interrupt-cells":
    const: 1

required:
  - compatible
  - reg
  - clocks
  - resets
  - interrupts
  - interrupt-controller
  - "#interrupt-cells"

additionalProperties: false

examples:
  - |
    interrupt-controller@12260000 {
      compatible = "starfive,jh8100-intc";
      reg = <0x12260000 0x10000>;
      clocks = <&syscrg_ne 76>;
      resets = <&syscrg_ne 13>;
      interrupts = <45>;
      interrupt-controller;
      #interrupt-cells = <1>;
    };