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|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mailbox/fsl,mu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP i.MX Messaging Unit (MU)
maintainers:
- Dong Aisheng <aisheng.dong@nxp.com>
description: |
The Messaging Unit module enables two processors within the SoC to
communicate and coordinate by passing messages (e.g. data, status
and control) through the MU interface. The MU also provides the ability
for one processor to signal the other processor using interrupts.
Because the MU manages the messaging between processors, the MU uses
different clocks (from each side of the different peripheral buses).
Therefore, the MU must synchronize the accesses from one side to the
other. The MU accomplishes synchronization using two sets of matching
registers (Processor A-facing, Processor B-facing).
properties:
compatible:
oneOf:
- const: fsl,imx6sx-mu
- const: fsl,imx7ulp-mu
- const: fsl,imx8ulp-mu
- const: fsl,imx8-mu-scu
- const: fsl,imx8-mu-seco
- const: fsl,imx8ulp-mu-s4
- const: fsl,imx93-mu-s4
- const: fsl,imx95-mu
- const: fsl,imx95-mu-ele
- const: fsl,imx95-mu-v2x
- items:
- const: fsl,imx93-mu
- const: fsl,imx8ulp-mu
- items:
- enum:
- fsl,imx7s-mu
- fsl,imx8mq-mu
- fsl,imx8mm-mu
- fsl,imx8mn-mu
- fsl,imx8mp-mu
- fsl,imx8qm-mu
- fsl,imx8qxp-mu
- const: fsl,imx6sx-mu
- description: To communicate with i.MX8 SCU with fast IPC
items:
- const: fsl,imx8-mu-scu
- enum:
- fsl,imx8qm-mu
- fsl,imx8qxp-mu
- const: fsl,imx6sx-mu
reg:
maxItems: 1
interrupts:
minItems: 1
maxItems: 2
interrupt-names:
minItems: 1
items:
- const: tx
- const: rx
"#mbox-cells":
description: |
<&phandle type channel>
phandle : Label name of controller
type : Channel type
channel : Channel number
This MU support 6 type of unidirectional channels, each type
has 4 channels except RST channel which only has 1 channel.
A total of 21 channels. Following types are
supported:
0 - TX channel with 32bit transmit register and IRQ transmit
acknowledgment support.
1 - RX channel with 32bit receive register and IRQ support
2 - TX doorbell channel. Without own register and no ACK support.
3 - RX doorbell channel.
4 - RST channel
5 - Tx doorbell channel. With S/W ACK from the other side.
const: 2
clocks:
maxItems: 1
fsl,mu-side-b:
description: boolean, if present, means it is for side B MU.
type: boolean
power-domains:
maxItems: 1
ranges: true
'#address-cells':
const: 1
'#size-cells':
const: 1
patternProperties:
"^sram@[a-f0-9]+":
$ref: /schemas/sram/sram.yaml#
unevaluatedProperties: false
required:
- compatible
- reg
- interrupts
- "#mbox-cells"
allOf:
- if:
properties:
compatible:
enum:
- fsl,imx93-mu-s4
then:
properties:
interrupt-names:
minItems: 2
interrupts:
minItems: 2
else:
properties:
interrupts:
maxItems: 1
not:
required:
- interrupt-names
- if:
not:
properties:
compatible:
const: fsl,imx95-mu
then:
patternProperties:
"^sram@[a-f0-9]+": false
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
mailbox@5d1b0000 {
compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
reg = <0x5d1b0000 0x10000>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
};
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
mailbox@445b0000 {
compatible = "fsl,imx95-mu";
reg = <0x445b0000 0x10000>;
ranges;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
#mbox-cells = <2>;
sram@445b1000 {
compatible = "mmio-sram";
reg = <0x445b1000 0x400>;
ranges = <0x0 0x445b1000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
scmi-sram-section@0 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x80>;
};
scmi-sram-section@80 {
compatible = "arm,scmi-shmem";
reg = <0x80 0x80>;
};
};
};
|
