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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/i2c/st,st-mipid02.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
maintainers:
- Benjamin Mugnier <benjamin.mugnier@foss.st.com>
- Sylvain Petinot <sylvain.petinot@foss.st.com>
description:
MIPID02 has two CSI-2 input ports, only one of those ports can be
active at a time. Active port input stream will be de-serialized
and its content outputted through PARALLEL output port.
CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2
second input port is a single lane 800Mbps. Both ports support clock
and data lane polarity swap. First port also supports data lane swap.
PARALLEL output port has a maximum width of 12 bits.
Supported formats are RAW6, RAW7, RAW8, RAW10, RAW12, RGB565, RGB888,
RGB444, YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
properties:
compatible:
const: st,st-mipid02
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
const: xclk
VDDE-supply:
description:
Sensor digital IO supply. Must be 1.8 volts.
VDDIN-supply:
description:
Sensor internal regulator supply. Must be 1.8 volts.
reset-gpios:
description:
Reference to the GPIO connected to the xsdn pin, if any.
This is an active low signal to the mipid02.
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: CSI-2 first input port
properties:
endpoint:
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-lanes:
description:
Single-lane operation shall be <1> or <2> .
Dual-lane operation shall be <1 2> or <2 1> .
minItems: 1
maxItems: 2
lane-polarities:
description:
Any lane can be inverted or not.
minItems: 1
maxItems: 2
required:
- data-lanes
port@1:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: CSI-2 second input port
properties:
endpoint:
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-lanes:
description:
Single-lane operation shall be <1> or <2> .
maxItems: 1
lane-polarities:
description:
Any lane can be inverted or not.
maxItems: 1
required:
- data-lanes
port@2:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: Output port
properties:
endpoint:
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
properties:
bus-width:
enum: [6, 7, 8, 10, 12]
required:
- bus-width
anyOf:
- required:
- port@0
- required:
- port@1
required:
- port@2
additionalProperties: false
required:
- compatible
- reg
- clocks
- clock-names
- VDDE-supply
- VDDIN-supply
- ports
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
mipid02: csi2rx@14 {
compatible = "st,st-mipid02";
reg = <0x14>;
clocks = <&clk_ext_camera_12>;
clock-names = "xclk";
VDDE-supply = <&vdd>;
VDDIN-supply = <&vdd>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ep0: endpoint {
data-lanes = <1 2>;
remote-endpoint = <&mipi_csi2_in>;
};
};
port@2 {
reg = <2>;
ep2: endpoint {
bus-width = <8>;
hsync-active = <0>;
vsync-active = <0>;
remote-endpoint = <¶llel_out>;
};
};
};
};
};
...
|
