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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/mediatek,mdp3-hdr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Media Data Path 3 HDR
maintainers:
- Matthias Brugger <matthias.bgg@gmail.com>
- Moudy Ho <moudy.ho@mediatek.com>
description:
A Media Data Path 3 (MDP3) component used to perform conversion from
High Dynamic Range (HDR) to Standard Dynamic Range (SDR).
properties:
compatible:
enum:
- mediatek,mt8195-mdp3-hdr
reg:
maxItems: 1
mediatek,gce-client-reg:
description:
The register of display function block to be set by gce. There are 4 arguments,
such as gce node, subsys id, offset and register size. The subsys id that is
mapping to the register of display function blocks is defined in the gce header
include/dt-bindings/gce/<chip>-gce.h of each chips.
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
items:
- description: phandle of GCE
- description: GCE subsys id
- description: register offset
- description: register size
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- reg
- mediatek,gce-client-reg
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mt8195-clk.h>
#include <dt-bindings/gce/mt8195-gce.h>
display@14004000 {
compatible = "mediatek,mt8195-mdp3-hdr";
reg = <0x14004000 0x1000>;
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
clocks = <&vppsys0 CLK_VPP0_MDP_HDR>;
};
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