1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
|
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/mediatek,mt8195-jpegenc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek JPEG Encoder
maintainers:
- kyrie wu <kyrie.wu@mediatek.corp-partner.google.com>
description:
MediaTek JPEG Encoder is the JPEG encode hardware present in MediaTek SoCs
properties:
compatible:
const: mediatek,mt8195-jpgenc
power-domains:
maxItems: 1
iommus:
maxItems: 4
description:
Points to the respective IOMMU block with master port as argument, see
Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
Ports are according to the HW.
"#address-cells":
const: 2
"#size-cells":
const: 2
ranges: true
# Required child node:
patternProperties:
"^jpgenc@[0-9a-f]+$":
type: object
description:
The jpeg encoder hardware device node which should be added as subnodes to
the main jpeg node.
properties:
compatible:
const: mediatek,mt8195-jpgenc-hw
reg:
maxItems: 1
iommus:
minItems: 1
maxItems: 32
description:
List of the hardware port in respective IOMMU block for current Socs.
Refer to bindings/iommu/mediatek,iommu.yaml.
interrupts:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: jpgenc
power-domains:
maxItems: 1
required:
- compatible
- reg
- iommus
- interrupts
- clocks
- clock-names
- power-domains
additionalProperties: false
required:
- compatible
- power-domains
- iommus
- ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/memory/mt8195-memory-port.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/mt8195-clk.h>
#include <dt-bindings/power/mt8195-power.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
jpgenc-master {
compatible = "mediatek,mt8195-jpgenc";
power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
<&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
<&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
<&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
jpgenc@1a030000 {
compatible = "mediatek,mt8195-jpgenc-hw";
reg = <0 0x1a030000 0 0x10000>;
iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>,
<&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>,
<&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>,
<&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>;
interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vencsys CLK_VENC_JPGENC>;
clock-names = "jpgenc";
power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
};
jpgenc@1b030000 {
compatible = "mediatek,mt8195-jpgenc-hw";
reg = <0 0x1b030000 0 0x10000>;
iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
<&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
<&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
<&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>;
clock-names = "jpgenc";
power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
};
};
};
|
