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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-ddrmc-edac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Versal DDRMC (Integrated DDR Memory Controller)
maintainers:
- Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
- Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
description:
The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/
4X memory interfaces. Versal DDR memory controller has an optional ECC support
which correct single bit ECC errors and detect double bit ECC errors.
properties:
compatible:
const: xlnx,versal-ddrmc
reg:
items:
- description: DDR Memory Controller registers
- description: NOC registers corresponding to DDR Memory Controller
reg-names:
items:
- const: base
- const: noc
interrupts:
maxItems: 1
required:
- compatible
- reg
- reg-names
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
bus {
#address-cells = <2>;
#size-cells = <2>;
memory-controller@f6150000 {
compatible = "xlnx,versal-ddrmc";
reg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>;
reg-names = "base", "noc";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
};
};
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