summaryrefslogtreecommitdiffstats
path: root/Documentation/devicetree/bindings/net/microchip,lan966x-switch.yaml
blob: 306ef9ecf2b9199a55eb82a6cb2dd1c8fbb714a2 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/microchip,lan966x-switch.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip Lan966x Ethernet switch controller

maintainers:
  - Horatiu Vultur <horatiu.vultur@microchip.com>

description: |
  The lan966x switch is a multi-port Gigabit AVB/TSN Ethernet Switch with
  two integrated 10/100/1000Base-T PHYs. In addition to the integrated PHYs,
  it supports up to 2RGMII/RMII, up to 3BASE-X/SERDES/2.5GBASE-X and up to
  2 Quad-SGMII/Quad-USGMII interfaces.

properties:
  $nodename:
    pattern: "^switch@[0-9a-f]+$"

  compatible:
    const: microchip,lan966x-switch

  reg:
    items:
      - description: cpu target
      - description: general control block target

  reg-names:
    items:
      - const: cpu
      - const: gcb

  interrupts:
    minItems: 1
    items:
      - description: register based extraction
      - description: frame dma based extraction
      - description: analyzer interrupt
      - description: ptp interrupt
      - description: ptp external interrupt

  interrupt-names:
    minItems: 1
    items:
      - const: xtr
      - const: fdma
      - const: ana
      - const: ptp
      - const: ptp-ext

  resets:
    items:
      - description: Reset controller used for switch core reset (soft reset)

  reset-names:
    items:
      - const: switch

  ethernet-ports:
    type: object

    properties:
      '#address-cells':
        const: 1
      '#size-cells':
        const: 0

    additionalProperties: false

    patternProperties:
      "^port@[0-9a-f]+$":
        type: object

        $ref: /schemas/net/ethernet-controller.yaml#
        unevaluatedProperties: false

        properties:
          '#address-cells':
            const: 1
          '#size-cells':
            const: 0

          reg:
            description:
              Switch port number

          phys:
            description:
              Phandle of a Ethernet SerDes PHY

          phy-mode:
            description:
              This specifies the interface used by the Ethernet SerDes towards
              the PHY or SFP.
            enum:
              - gmii
              - sgmii
              - qsgmii
              - 1000base-x
              - 2500base-x

          phy-handle:
            description:
              Phandle of a Ethernet PHY.

          sfp:
            description:
              Phandle of an SFP.

          managed: true

        required:
          - reg
          - phys
          - phy-mode

        oneOf:
          - required:
              - phy-handle
          - required:
              - sfp
              - managed

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - interrupt-names
  - resets
  - reset-names
  - ethernet-ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    switch: switch@e0000000 {
      compatible = "microchip,lan966x-switch";
      reg =  <0xe0000000 0x0100000>,
             <0xe2000000 0x0800000>;
      reg-names = "cpu", "gcb";
      interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
      interrupt-names = "xtr";
      resets = <&switch_reset 0>;
      reset-names = "switch";
      ethernet-ports {
        #address-cells = <1>;
        #size-cells = <0>;

        port0: port@0 {
          reg = <0>;
          phy-handle = <&phy0>;
          phys = <&serdes 0 0>;
          phy-mode = "gmii";
        };

        port1: port@1 {
          reg = <1>;
          sfp = <&sfp_eth1>;
          managed = "in-band-status";
          phys = <&serdes 2 4>;
          phy-mode = "sgmii";
        };
      };
    };

...