blob: a65e6aa215a7f1c1ff1ebdef0cf1710e22317609 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/socionext,synquacer-netsec.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Socionext NetSec Ethernet Controller IP
maintainers:
- Jassi Brar <jaswinder.singh@linaro.org>
- Ilias Apalodimas <ilias.apalodimas@linaro.org>
allOf:
- $ref: ethernet-controller.yaml#
properties:
compatible:
const: socionext,synquacer-netsec
reg:
items:
- description: control register area
- description: EEPROM holding the MAC address and microengine firmware
clocks:
maxItems: 1
clock-names:
const: phy_ref_clk
dma-coherent: true
interrupts:
maxItems: 1
mdio:
$ref: mdio.yaml#
required:
- compatible
- reg
- clocks
- clock-names
- interrupts
- mdio
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
ethernet@522d0000 {
compatible = "socionext,synquacer-netsec";
reg = <0x522d0000 0x10000>, <0x10000000 0x10000>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_netsec>;
clock-names = "phy_ref_clk";
phy-mode = "rgmii";
max-speed = <1000>;
max-frame-size = <9000>;
phy-handle = <&phy1>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
};
...
|