Documentation/devicetree/bindings/perf/starfive,jh8100-starlink-pmu.yaml


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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/perf/starfive,jh8100-starlink-pmu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: StarFive JH8100 StarLink PMU

maintainers:
  - Ji Sheng Teoh <jisheng.teoh@starfivetech.com>

description:
  StarFive's JH8100 StarLink PMU integrates one or more CPU cores with a
  shared L3 memory system. The PMU support overflow interrupt, up to
  16 programmable 64bit event counters, and an independent 64bit cycle
  counter. StarFive's JH8100 StarLink PMU is accessed via MMIO.

properties:
  compatible:
    const: starfive,jh8100-starlink-pmu

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        pmu@12900000 {
            compatible = "starfive,jh8100-starlink-pmu";
            reg = <0x0 0x12900000 0x0 0x10000>;
            interrupts = <34>;
        };
    };