blob: 5ac994b3c0aa156bff9a49219f41a0dcc401855c (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/rockchip-inno-csi-dphy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip SoC MIPI RX0 D-PHY
maintainers:
- Heiko Stuebner <heiko@sntech.de>
description: |
The Rockchip SoC has a MIPI CSI D-PHY based on an Innosilicon IP which
connects to the ISP1 (Image Signal Processing unit v1.0) for CSI cameras.
properties:
compatible:
enum:
- rockchip,px30-csi-dphy
- rockchip,rk1808-csi-dphy
- rockchip,rk3326-csi-dphy
- rockchip,rk3368-csi-dphy
- rockchip,rk3568-csi-dphy
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
const: pclk
'#phy-cells':
const: 0
power-domains:
description: Video in/out power domain.
maxItems: 1
resets:
items:
- description: exclusive PHY reset line
reset-names:
items:
- const: apb
rockchip,grf:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Some additional phy settings are access through GRF regs.
required:
- compatible
- reg
- clocks
- clock-names
- '#phy-cells'
- power-domains
- resets
- reset-names
- rockchip,grf
additionalProperties: false
examples:
- |
csi_dphy: phy@ff2f0000 {
compatible = "rockchip,px30-csi-dphy";
reg = <0xff2f0000 0x4000>;
clocks = <&cru 1>;
clock-names = "pclk";
#phy-cells = <0>;
power-domains = <&power 1>;
resets = <&cru 1>;
reset-names = "apb";
rockchip,grf = <&grf>;
};
|
