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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/starfive,jh7110-pcie-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: StarFive JH7110 PCIe 2.0 PHY
maintainers:
- Minda Chen <minda.chen@starfivetech.com>
properties:
compatible:
const: starfive,jh7110-pcie-phy
reg:
maxItems: 1
"#phy-cells":
const: 0
starfive,sys-syscon:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: phandle to System Register Controller sys_syscon node.
- description: PHY connect offset of SYS_SYSCONSAIF__SYSCFG register for USB PHY.
description:
The phandle to System Register Controller syscon node and the PHY connect offset
of SYS_SYSCONSAIF__SYSCFG register. Connect PHY to USB3 controller.
starfive,stg-syscon:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: phandle to System Register Controller stg_syscon node.
- description: PHY mode offset of STG_SYSCONSAIF__SYSCFG register.
- description: PHY enable for USB offset of STG_SYSCONSAIF__SYSCFG register.
description:
The phandle to System Register Controller syscon node and the offset
of STG_SYSCONSAIF__SYSCFG register for PCIe PHY. Total 2 regsisters offset.
required:
- compatible
- reg
- "#phy-cells"
additionalProperties: false
examples:
- |
phy@10210000 {
compatible = "starfive,jh7110-pcie-phy";
reg = <0x10210000 0x10000>;
#phy-cells = <0>;
starfive,sys-syscon = <&sys_syscon 0x18>;
starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>;
};
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