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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,qdu1000-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. QDU1000/QRU1000 TLMM block
maintainers:
- Melody Olvera <quic_molvera@quicinc.com>
description: |
Top Level Mode Multiplexer pin controller found in the QDU1000 and
QRU1000 SoCs.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,qdu1000-tlmm
reg:
maxItems: 1
interrupts:
maxItems: 1
gpio-reserved-ranges:
minItems: 1
maxItems: 76
gpio-line-names:
maxItems: 151
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-qdu1000-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-qdu1000-tlmm-state"
additionalProperties: false
$defs:
qcom-qdu1000-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|150)$"
- enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ atest_char, atest_usb, char_exec, CMO_PRI, cmu_rng,
dbg_out_clk, ddr_bist, ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4,
ddr_pxi5, ddr_pxi6, ddr_pxi7, eth012_int_n, eth345_int_n,
gcc_gp1, gcc_gp2, gcc_gp3, gpio, gps_pps_in, hardsync_pps_in,
intr_c, jitter_bist_ref, pcie_clkreqn, phase_flag, pll_bist,
pll_clk, prng_rosc, qdss_cti, qdss_gpio, qlink0_enable,
qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request,
qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss,
qlink3_enable, qlink3_request, qlink3_wmss, qlink4_enable,
qlink4_request, qlink4_wmss, qlink5_enable, qlink5_request,
qlink5_wmss, qlink6_enable, qlink6_request, qlink6_wmss,
qlink7_enable, qlink7_request, qlink7_wmss, qspi_clk, qspi_cs,
qspi0, qspi1, qspi2, qspi3, qup00, qup01, qup02, qup03, qup04,
qup05, qup06, qup07, qup08, qup10, qup11, qup12, qup13, qup14,
qup15, qup16, qup17, qup20, qup21, qup22, SI5518_INT, smb_alert,
smb_clk, smb_dat, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3,
tgu_ch4, tgu_ch5, tgu_ch6, tgu_ch7, tmess_prng0, tmess_prng1,
tmess_prng2, tmess_prng3, tod_pps_in, tsense_pwm1, tsense_pwm2,
usb2phy_ac, usb_con_det, usb_dfp_en, usb_phy, vfr_0, vfr_1,
vsense_trigger ]
required:
- pins
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl@f000000 {
compatible = "qcom,qdu1000-tlmm";
reg = <0xf000000 0x1000000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 151>;
wakeup-parent = <&pdc>;
uart0-default-state {
pins = "gpio6", "gpio7", "gpio8", "gpio9";
function = "qup00";
};
};
|
