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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sdx75-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. SDX75 TLMM block
maintainers:
- Rohit Agarwal <quic_rohiagar@quicinc.com>
description:
Top Level Mode Multiplexer pin controller in Qualcomm SDX75 SoC.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,sdx75-tlmm
reg:
maxItems: 1
interrupts: true
interrupt-controller: true
"#interrupt-cells": true
gpio-controller: true
gpio-reserved-ranges:
minItems: 1
maxItems: 67
gpio-line-names:
maxItems: 133
"#gpio-cells": true
gpio-ranges: true
wakeup-parent: true
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-sdx75-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-sdx75-tlmm-state"
additionalProperties: false
$defs:
qcom-sdx75-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2])$"
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk, sdc2_cmd, sdc2_data ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ adsp_ext, atest_char, audio_ref_clk, bimc_dte, char_exec, coex_uart2,
coex_uart, cri_trng, cri_trng0, cri_trng1, dbg_out_clk, ddr_bist,
ddr_pxi0, ebi0_wrcdc, ebi2_a, ebi2_lcd, ebi2_lcd_te, emac0_mcg,
emac0_ptp, emac1_mcg, emac1_ptp, emac_cdc, emac_pps_in, eth0_mdc,
eth0_mdio, eth1_mdc, eth1_mdio, ext_dbg, gcc_125_clk, gcc_gp1_clk,
gcc_gp2_clk, gcc_gp3_clk, gcc_plltest, gpio, i2s_mclk, jitter_bist,
ldo_en, ldo_update, m_voc, mgpi_clk, native_char, native_tsens,
native_tsense, nav_dr_sync, nav_gpio, pa_indicator, pci_e,
pcie0_clkreq_n, pcie1_clkreq_n, pcie2_clkreq_n, pll_bist_sync,
pll_clk_aux, pll_ref_clk, pri_mi2s, prng_rosc, qdss_cti, qdss_gpio,
qlink0_b_en, qlink0_b_req, qlink0_l_en, qlink0_l_req, qlink0_wmss,
qlink1_l_en, qlink1_l_req, qlink1_wmss, qup_se0, qup_se1_l2_mira,
qup_se1_l2_mirb, qup_se1_l3_mira, qup_se1_l3_mirb, qup_se2, qup_se3,
qup_se4, qup_se5, qup_se6, qup_se7, qup_se8, rgmii_rx_ctl, rgmii_rxc,
rgmii_rxd, rgmii_tx_ctl, rgmii_txc, rgmii_txd, sd_card, sdc1_tb,
sdc2_tb_trig, sec_mi2s, sgmii_phy_intr0_n, sgmii_phy_intr1_n,
spmi_coex, spmi_vgi, tgu_ch0_trigout, tmess_prng0, tmess_prng1,
tmess_prng2, tmess_prng3, tri_mi2s, uim1_clk, uim1_data, uim1_present,
uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,
usb2phy_ac_en, vsense_trigger_mirnat]
required:
- pins
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@f100000 {
compatible = "qcom,sdx75-tlmm";
reg = <0x0f100000 0x300000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 133>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-wo-state {
pins = "gpio1";
function = "gpio";
};
uart-w-state {
rx-pins {
pins = "gpio12";
function = "qup_se1_l2_mira";
bias-disable;
};
tx-pins {
pins = "gpio13";
function = "qup_se1_l3_mira";
bias-disable;
};
};
};
...
|
