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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sm7150-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SM7150 TLMM pin controller
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Danila Tikhonov <danila@jiaxyga.com>
description:
Top Level Mode Multiplexer pin controller in Qualcomm SM7150 SoC.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,sm7150-tlmm
reg:
maxItems: 3
reg-names:
items:
- const: west
- const: north
- const: south
interrupts:
maxItems: 1
gpio-reserved-ranges:
minItems: 1
maxItems: 60
gpio-line-names:
maxItems: 119
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-sm7150-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-sm7150-tlmm-state"
additionalProperties: false
$defs:
qcom-sm7150-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-8])$"
- enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
sdc2_cmd, sdc2_data, ufs_reset ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ gpio, adsp_ext, agera_pll, aoss_cti, atest_char, atest_tsens,
atest_tsens2, atest_usb1, atest_usb2, cam_mclk, cci_async,
cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3,
cci_timer4, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2,
ddr_pxi3, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gp_pdm0,
gp_pdm1, gp_pdm2, gps_tx, jitter_bist, ldo_en, ldo_update,
m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
mdp_vsync3, mss_lte, nav_pps_in, nav_pps_out, pa_indicator,
pci_e, phase_flag, pll_bist, pll_bypassnl, pll_reset, pri_mi2s,
pri_mi2s_ws, prng_rosc, qdss, qdss_cti, qlink_enable,
qlink_request, qua_mi2s, qup00, qup01, qup02, qup03, qup04,
qup10, qup11, qup12, qup13, qup14, qup15, sd_write, sdc40,
sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, ter_mi2s,
tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsif1_clk, tsif1_data,
tsif1_en, tsif1_error, tsif1_sync, tsif2_clk, tsif2_data,
tsif2_en, tsif2_error, tsif2_sync, uim1_clk, uim1_data,
uim1_present, uim1_reset, uim2_clk, uim2_data, uim2_present,
uim2_reset, uim_batt, usb_phy, vfr_1, vsense_trigger,
wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1, wsa_clk,
wsa_data ]
required:
- pins
required:
- compatible
- reg
- reg-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@3500000 {
compatible = "qcom,sm7150-tlmm";
reg = <0x03500000 0x300000>,
<0x03900000 0x300000>,
<0x03d00000 0x300000>;
reg-names = "west", "north", "south";
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-ranges = <&tlmm 0 0 120>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
wakeup-parent = <&pdc>;
gpio-wo-state {
pins = "gpio1";
function = "gpio";
};
uart-w-state {
rx-pins {
pins = "gpio44";
function = "qup12";
bias-pull-up;
};
tx-pins {
pins = "gpio45";
function = "qup12";
bias-disable;
};
};
};
...
|
