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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SM8250 SoC LPASS LPI TLMM
maintainers:
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
description:
Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
(LPASS) Low Power Island (LPI) of Qualcomm SM8250 SoC.
properties:
compatible:
const: qcom,sm8250-lpass-lpi-pinctrl
reg:
maxItems: 2
clocks:
items:
- description: LPASS Core voting clock
- description: LPASS Audio voting clock
clock-names:
items:
- const: core
- const: audio
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-sm8250-lpass-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-sm8250-lpass-state"
additionalProperties: false
$defs:
qcom-sm8250-lpass-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|1[0-3])$"
minItems: 1
maxItems: 14
function:
enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws,
qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk,
dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data,
i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk,
dmic3_data, i2s2_data ]
description:
Specify the alternative function to be configured for the specified
pins.
allOf:
- $ref: qcom,lpass-lpi-common.yaml#
required:
- compatible
- reg
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/sound/qcom,q6afe.h>
lpi_tlmm: pinctrl@33c0000 {
compatible = "qcom,sm8250-lpass-lpi-pinctrl";
reg = <0x33c0000 0x20000>,
<0x3550000 0x10000>;
clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "core", "audio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&lpi_tlmm 0 0 14>;
wsa-swr-active-state {
clk-pins {
pins = "gpio10";
function = "wsa_swr_clk";
drive-strength = <2>;
slew-rate = <1>;
bias-disable;
};
data-pins {
pins = "gpio11";
function = "wsa_swr_data";
drive-strength = <2>;
slew-rate = <1>;
};
};
tx-swr-sleep-clk-state {
pins = "gpio0";
function = "swr_tx_clk";
drive-strength = <2>;
bias-pull-down;
};
};
|
