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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/reset/xlnx,zynqmp-reset.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Zynq UltraScale+ MPSoC and Versal reset
maintainers:
- Piyush Mehta <piyush.mehta@amd.com>
description: |
The Zynq UltraScale+ MPSoC and Versal has several different resets.
The PS reset subsystem is responsible for handling the external reset
input to the device and that all internal reset requirements are met
for the system (as a whole) and for the functional units.
Please also refer to reset.txt in this directory for common reset
controller binding usage. Device nodes that need access to reset
lines should specify them as a reset phandle in their corresponding
node as specified in reset.txt.
For list of all valid reset indices for Zynq UltraScale+ MPSoC
<dt-bindings/reset/xlnx-zynqmp-resets.h>
For list of all valid reset indices for Versal
<dt-bindings/reset/xlnx-versal-resets.h>
properties:
compatible:
enum:
- xlnx,zynqmp-reset
- xlnx,versal-reset
- xlnx,versal-net-reset
"#reset-cells":
const: 1
required:
- compatible
- "#reset-cells"
additionalProperties: false
examples:
- |
zynqmp_reset: reset-controller {
compatible = "xlnx,zynqmp-reset";
#reset-cells = <1>;
};
...
|
