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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-ahci-glue.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Socionext UniPhier SoC AHCI glue layer
maintainers:
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
description: |+
AHCI glue layer implemented on Socionext UniPhier SoCs is a sideband
logic handling signals to AHCI host controller inside AHCI component.
properties:
compatible:
items:
- enum:
- socionext,uniphier-pro4-ahci-glue
- socionext,uniphier-pxs2-ahci-glue
- socionext,uniphier-pxs3-ahci-glue
- const: simple-mfd
reg:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges: true
patternProperties:
"^reset-controller@[0-9a-f]+$":
$ref: /schemas/reset/socionext,uniphier-glue-reset.yaml#
"phy@[0-9a-f]+$":
$ref: /schemas/phy/socionext,uniphier-ahci-phy.yaml#
required:
- compatible
- reg
additionalProperties: false
examples:
- |
sata-controller@65700000 {
compatible = "socionext,uniphier-pxs3-ahci-glue", "simple-mfd";
reg = <0x65b00000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65700000 0x100>;
reset-controller@0 {
compatible = "socionext,uniphier-pxs3-ahci-reset";
reg = <0x0 0x4>;
clock-names = "link";
clocks = <&sys_clk 28>;
reset-names = "link";
resets = <&sys_rst 28>;
#reset-cells = <1>;
};
phy@10 {
compatible = "socionext,uniphier-pxs3-ahci-phy";
reg = <0x10 0x10>;
clock-names = "link", "phy";
clocks = <&sys_clk 28>, <&sys_clk 30>;
reset-names = "link", "phy";
resets = <&sys_rst 28>, <&sys_rst 30>;
#phy-cells = <0>;
};
};
|
