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# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/snps,dw-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Synopsys Designware Watchdog Timer
allOf:
- $ref: watchdog.yaml#
maintainers:
- Jamie Iles <jamie@jamieiles.com>
properties:
compatible:
oneOf:
- const: snps,dw-wdt
- items:
- enum:
- rockchip,px30-wdt
- rockchip,rk3066-wdt
- rockchip,rk3128-wdt
- rockchip,rk3188-wdt
- rockchip,rk3228-wdt
- rockchip,rk3288-wdt
- rockchip,rk3308-wdt
- rockchip,rk3328-wdt
- rockchip,rk3368-wdt
- rockchip,rk3399-wdt
- rockchip,rk3568-wdt
- rockchip,rk3588-wdt
- rockchip,rv1108-wdt
- const: snps,dw-wdt
reg:
maxItems: 1
interrupts:
description: DW Watchdog pre-timeout interrupt
maxItems: 1
clocks:
minItems: 1
items:
- description: Watchdog timer reference clock
- description: APB3 interface clock
clock-names:
minItems: 1
items:
- const: tclk
- const: pclk
resets:
description: Phandle to the DW Watchdog reset lane
maxItems: 1
snps,watchdog-tops:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: |
DW APB Watchdog custom timer intervals - Timeout Period ranges (TOPs).
Each TOP is a number loaded into the watchdog counter at the moment of
the timer restart. The counter decrementing happens each tick of the
reference clock. Therefore the TOPs array is equivalent to an array of
the timer expiration intervals supported by the DW APB Watchdog. Note
DW APB Watchdog IP-core might be synthesized with fixed TOP values,
in which case this property is unnecessary with default TOPs utilized.
default: [0x0001000 0x0002000 0x0004000 0x0008000
0x0010000 0x0020000 0x0040000 0x0080000
0x0100000 0x0200000 0x0400000 0x0800000
0x1000000 0x2000000 0x4000000 0x8000000]
minItems: 16
maxItems: 16
unevaluatedProperties: false
required:
- compatible
- reg
- clocks
examples:
- |
watchdog@ffd02000 {
compatible = "snps,dw-wdt";
reg = <0xffd02000 0x1000>;
interrupts = <0 171 4>;
clocks = <&per_base_clk>;
resets = <&wdt_rst>;
};
- |
watchdog@ffd02000 {
compatible = "snps,dw-wdt";
reg = <0xffd02000 0x1000>;
interrupts = <0 171 4>;
clocks = <&per_base_clk>;
clock-names = "tclk";
snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
0x000007FF 0x0000FFFF 0x0001FFFF
0x0003FFFF 0x0007FFFF 0x000FFFFF
0x001FFFFF 0x003FFFFF 0x007FFFFF
0x00FFFFFF 0x01FFFFFF 0x03FFFFFF
0x07FFFFFF>;
};
...
|
