1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019-2021 NXP
* Zhou Guoniu <guoniu.zhou@nxp.com>
*/
img_ipg_clk: clock-img-ipg {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
clock-output-names = "img_ipg_clk";
};
img_subsys: bus@58000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x58000000 0x0 0x58000000 0x1000000>;
jpegdec: jpegdec@58400000 {
reg = <0x58400000 0x00050000>;
interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
<&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
clock-names = "per", "ipg";
assigned-clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
<&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
assigned-clock-rates = <200000000>, <200000000>;
power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>,
<&pd IMX_SC_R_MJPEG_DEC_S0>;
slot = <0>;
};
jpegenc: jpegenc@58450000 {
reg = <0x58450000 0x00050000>;
interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
<&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
clock-names = "per", "ipg";
assigned-clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
<&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
assigned-clock-rates = <200000000>, <200000000>;
power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>,
<&pd IMX_SC_R_MJPEG_ENC_S0>;
slot = <0>;
};
img_jpeg_dec_lpcg: clock-controller@585d0000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x585d0000 0x10000>;
#clock-cells = <1>;
clocks = <&img_ipg_clk>, <&img_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>,
<IMX_LPCG_CLK_4>;
clock-output-names = "img_jpeg_dec_lpcg_clk",
"img_jpeg_dec_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>;
};
img_jpeg_enc_lpcg: clock-controller@585f0000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x585f0000 0x10000>;
#clock-cells = <1>;
clocks = <&img_ipg_clk>, <&img_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>,
<IMX_LPCG_CLK_4>;
clock-output-names = "img_jpeg_enc_lpcg_clk",
"img_jpeg_enc_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>;
};
};
|
