1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018-2019 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
/dts-v1/;
#include "imx8qm.dtsi"
/ {
model = "Freescale i.MX8QM MEK";
compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
chosen {
stdout-path = &lpuart0;
};
cpus {
/delete-node/ cpu-map;
/delete-node/ cpu@100;
/delete-node/ cpu@101;
};
thermal-zones {
/delete-node/ cpu1-thermal;
};
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x40000000>;
};
reg_usdhc2_vmmc: usdhc2-vmmc {
compatible = "regulator-fixed";
regulator-name = "SD1_SPWR";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_vref_1v8: regulator-adc-vref {
compatible = "regulator-fixed";
regulator-name = "vref_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
&adc0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc0>;
vref-supply = <®_vref_1v8>;
status = "okay";
};
&i2c1 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>;
sda-gpios = <&lsio_gpio0 15 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&lpuart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
status = "okay";
};
&lpuart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart2>;
status = "okay";
};
&lpuart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart3>;
status = "okay";
};
&lpspi2 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>;
cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>;
status = "okay";
spidev0: spi@0 {
reg = <0>;
compatible = "rohm,dh2228fv";
spi-max-frequency = <30000000>;
};
};
&flexspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi0>;
status = "okay";
flash0: flash@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <133000000>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <ðphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <8>;
no-sd;
no-sdio;
non-removable;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <4>;
vmmc-supply = <®_usdhc2_vmmc>;
cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>;
wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&iomuxc {
pinctrl_i2c1: i2c1grp {
fsl,pins = <
IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004c
IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x0600004c
>;
};
pinctrl_i2c1_gpio: i2c1gpio-grp {
fsl,pins = <
IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 0xc600004c
IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15 0xc600004c
>;
};
pinctrl_adc0: adc0grp {
fsl,pins = <
IMX8QM_ADC_IN0_DMA_ADC0_IN0 0xc0000060
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020
IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020
IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020
IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020
IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020
IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
>;
};
pinctrl_lpspi2: lpspi2grp {
fsl,pins = <
IMX8QM_SPI2_SCK_DMA_SPI2_SCK 0x06000040
IMX8QM_SPI2_SDO_DMA_SPI2_SDO 0x06000040
IMX8QM_SPI2_SDI_DMA_SPI2_SDI 0x06000040
>;
};
pinctrl_lpspi2_cs: lpspi2csgrp {
fsl,pins = <
IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 0x21
>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021
IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021
IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021
IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021
IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021
IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021
IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021
IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021
IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021
IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021
IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021
IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021
IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021
IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021
IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021
IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021
>;
};
pinctrl_lpuart0: lpuart0grp {
fsl,pins = <
IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020
IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020
>;
};
pinctrl_lpuart2: lpuart2grp {
fsl,pins = <
IMX8QM_UART0_RTS_B_DMA_UART2_RX 0x06000020
IMX8QM_UART0_CTS_B_DMA_UART2_TX 0x06000020
>;
};
pinctrl_lpuart3: lpuart3grp {
fsl,pins = <
IMX8QM_M41_GPIO0_00_DMA_UART3_RX 0x06000020
IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
>;
};
};
|
