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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "rk3568-fastrhino-r66s.dtsi"
/ {
model = "Lunzn FastRhino R68S";
compatible = "lunzn,fastrhino-r68s", "rockchip,rk3568";
aliases {
ethernet0 = &gmac0;
ethernet1 = &gmac1;
mmc0 = &sdhci;
};
adc-keys {
compatible = "adc-keys";
io-channels = <&saradc 0>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
button-recovery {
label = "Recovery";
linux,code = <KEY_VENDOR>;
press-threshold-microvolt = <1750>;
};
};
};
&gmac0 {
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
assigned-clock-rates = <0>, <125000000>;
clock_in_out = "output";
phy-handle = <&rgmii_phy0>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2
&gmac0_rx_bus2
&gmac0_rgmii_clk
&gmac0_rgmii_bus>;
snps,reset-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 15ms, 50ms for rtl8211f */
snps,reset-delays-us = <0 15000 50000>;
tx_delay = <0x3c>;
rx_delay = <0x2f>;
status = "okay";
};
&gmac1 {
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
assigned-clock-rates = <0>, <125000000>;
clock_in_out = "output";
phy-handle = <&rgmii_phy1>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&gmac1m1_miim
&gmac1m1_tx_bus2
&gmac1m1_rx_bus2
&gmac1m1_rgmii_clk
&gmac1m1_rgmii_bus>;
snps,reset-gpio = <&gpio0 RK_PB1 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 15ms, 50ms for rtl8211f */
snps,reset-delays-us = <0 15000 50000>;
tx_delay = <0x4f>;
rx_delay = <0x26>;
status = "okay";
};
&mdio0 {
rgmii_phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
pinctrl-0 = <ð_phy0_reset_pin>;
pinctrl-names = "default";
};
};
&mdio1 {
rgmii_phy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
pinctrl-0 = <ð_phy1_reset_pin>;
pinctrl-names = "default";
};
};
&pinctrl {
gmac0 {
eth_phy0_reset_pin: eth-phy0-reset-pin {
rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
gmac1 {
eth_phy1_reset_pin: eth-phy1-reset-pin {
rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&sdhci {
bus-width = <8>;
max-frequency = <200000000>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
status = "okay";
};
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