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|
// SPDX-License-Identifier: GPL-2.0
/*
* dts file for Xilinx ZynqMP SM-K26 rev1/B/A
*
* (C) Copyright 2020 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
/ {
model = "ZynqMP SM-K26 Rev1/B/A";
compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB",
"xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26",
"xlnx,zynqmp";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
nvmem0 = &eeprom;
nvmem1 = &eeprom_cc;
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &dcc;
spi0 = &qspi;
spi1 = &spi0;
spi2 = &spi1;
usb0 = &usb0;
usb1 = &usb1;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial1:115200n8";
};
memory@0 {
device_type = "memory"; /* 4GB */
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
pmu_region: pmu@7ff00000 {
reg = <0x0 0x7ff00000 0x0 0x100000>;
no-map;
};
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
key-fwuen {
label = "fwuen";
gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
linux,code = <BTN_MISC>;
wakeup-source;
autorepeat;
};
};
leds {
compatible = "gpio-leds";
ds35-led {
label = "heartbeat";
gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
ds36-led {
label = "vbus_det";
gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
};
ams {
compatible = "iio-hwmon";
io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
<&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,
<&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,
<&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,
<&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,
<&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,
<&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,
<&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,
<&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,
<&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;
};
};
&modepin_gpio {
label = "modepin";
};
&uart1 { /* MIO36/MIO37 */
status = "okay";
};
&pinctrl0 {
status = "okay";
pinctrl_sdhci0_default: sdhci0-default {
conf {
groups = "sdio0_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
mux {
groups = "sdio0_0_grp";
function = "sdio0";
};
};
};
&qspi { /* MIO 0-5 - U143 */
status = "okay";
spi_flash: flash@0 { /* MT25QU512A */
compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <40000000>; /* 40MHz */
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "Image Selector";
reg = <0x0 0x80000>; /* 512KB */
read-only;
lock;
};
partition@80000 {
label = "Image Selector Golden";
reg = <0x80000 0x80000>; /* 512KB */
read-only;
lock;
};
partition@100000 {
label = "Persistent Register";
reg = <0x100000 0x20000>; /* 128KB */
};
partition@120000 {
label = "Persistent Register Backup";
reg = <0x120000 0x20000>; /* 128KB */
};
partition@140000 {
label = "Open_1";
reg = <0x140000 0xC0000>; /* 768KB */
};
partition@200000 {
label = "Image A (FSBL, PMU, ATF, U-Boot)";
reg = <0x200000 0xD00000>; /* 13MB */
};
partition@f00000 {
label = "ImgSel Image A Catch";
reg = <0xF00000 0x80000>; /* 512KB */
read-only;
lock;
};
partition@f80000 {
label = "Image B (FSBL, PMU, ATF, U-Boot)";
reg = <0xF80000 0xD00000>; /* 13MB */
};
partition@1c80000 {
label = "ImgSel Image B Catch";
reg = <0x1C80000 0x80000>; /* 512KB */
read-only;
lock;
};
partition@1d00000 {
label = "Open_2";
reg = <0x1D00000 0x100000>; /* 1MB */
};
partition@1e00000 {
label = "Recovery Image";
reg = <0x1E00000 0x200000>; /* 2MB */
read-only;
lock;
};
partition@2000000 {
label = "Recovery Image Backup";
reg = <0x2000000 0x200000>; /* 2MB */
read-only;
lock;
};
partition@2200000 {
label = "U-Boot storage variables";
reg = <0x2200000 0x20000>; /* 128KB */
};
partition@2220000 {
label = "U-Boot storage variables backup";
reg = <0x2220000 0x20000>; /* 128KB */
};
partition@2240000 {
label = "SHA256";
reg = <0x2240000 0x40000>; /* 256B but 256KB sector */
read-only;
lock;
};
partition@2280000 {
label = "Secure OS Storage";
reg = <0x2280000 0x20000>; /* 128KB */
};
partition@22A0000 {
label = "User";
reg = <0x22A0000 0x1d60000>; /* 29.375 MB */
};
};
};
};
&sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci0_default>;
non-removable;
disable-wp;
bus-width = <8>;
xlnx,mio-bank = <0>;
assigned-clock-rates = <187498123>;
};
&spi1 { /* MIO6, 9-11 */
status = "okay";
label = "TPM";
num-cs = <1>;
tpm@0 { /* slm9670 - U144 */
compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
reg = <0>;
spi-max-frequency = <18500000>;
};
};
&i2c1 {
status = "okay";
bootph-all;
clock-frequency = <400000>;
scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
eeprom: eeprom@50 { /* u46 - also at address 0x58 */
bootph-all;
compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
reg = <0x50>;
/* WP pin EE_WP_EN connected to slg7x644092@68 */
};
eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */
bootph-all;
compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
reg = <0x51>;
};
/* da9062@30 - u170 - also at address 0x31 */
/* da9131@33 - u167 */
da9131: pmic@33 {
compatible = "dlg,da9131";
reg = <0x33>;
regulators {
da9131_buck1: buck1 {
regulator-name = "da9131_buck1";
regulator-boot-on;
regulator-always-on;
};
da9131_buck2: buck2 {
regulator-name = "da9131_buck2";
regulator-boot-on;
regulator-always-on;
};
};
};
/* da9130@32 - u166 */
da9130: pmic@32 {
compatible = "dlg,da9130";
reg = <0x32>;
regulators {
da9130_buck1: buck1 {
regulator-name = "da9130_buck1";
regulator-boot-on;
regulator-always-on;
};
};
};
/* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */
/*
* stdp4320 - u27 FW has below two issues to be fixed in next board revision.
* Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.
* Address conflict with slg7x644091@70 making both the devices NOT accessible.
* With the FW fix, stdp4320 should respond to address 0x73 only.
*/
/* slg7x644092@68 - u169 */
/* Also connected via JA1C as C23/C24 */
};
&gpio {
status = "okay";
gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
"QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */
"SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
"EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
"EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */
"I2C1_SDA", "", "", "", "", /* 25 - 29 */
"", "", "", "", "", /* 30 - 34 */
"", "", "", "", "", /* 35 - 39 */
"", "", "", "", "", /* 40 - 44 */
"", "", "", "", "", /* 45 - 49 */
"", "", "", "", "", /* 50 - 54 */
"", "", "", "", "", /* 55 - 59 */
"", "", "", "", "", /* 60 - 64 */
"", "", "", "", "", /* 65 - 69 */
"", "", "", "", "", /* 70 - 74 */
"", "", "", /* 75 - 77, MIO end and EMIO start */
"", "", /* 78 - 79 */
"", "", "", "", "", /* 80 - 84 */
"", "", "", "", "", /* 85 - 89 */
"", "", "", "", "", /* 90 - 94 */
"", "", "", "", "", /* 95 - 99 */
"", "", "", "", "", /* 100 - 104 */
"", "", "", "", "", /* 105 - 109 */
"", "", "", "", "", /* 110 - 114 */
"", "", "", "", "", /* 115 - 119 */
"", "", "", "", "", /* 120 - 124 */
"", "", "", "", "", /* 125 - 129 */
"", "", "", "", "", /* 130 - 134 */
"", "", "", "", "", /* 135 - 139 */
"", "", "", "", "", /* 140 - 144 */
"", "", "", "", "", /* 145 - 149 */
"", "", "", "", "", /* 150 - 154 */
"", "", "", "", "", /* 155 - 159 */
"", "", "", "", "", /* 160 - 164 */
"", "", "", "", "", /* 165 - 169 */
"", "", "", ""; /* 170 - 173 */
};
&xilinx_ams {
status = "okay";
};
&ams_ps {
status = "okay";
};
&ams_pl {
status = "okay";
};
&zynqmp_dpsub {
status = "okay";
};
&rtc {
status = "okay";
};
&lpd_dma_chan1 {
status = "okay";
};
&lpd_dma_chan2 {
status = "okay";
};
&lpd_dma_chan3 {
status = "okay";
};
&lpd_dma_chan4 {
status = "okay";
};
&lpd_dma_chan5 {
status = "okay";
};
&lpd_dma_chan6 {
status = "okay";
};
&lpd_dma_chan7 {
status = "okay";
};
&lpd_dma_chan8 {
status = "okay";
};
&fpd_dma_chan1 {
status = "okay";
};
&fpd_dma_chan2 {
status = "okay";
};
&fpd_dma_chan3 {
status = "okay";
};
&fpd_dma_chan4 {
status = "okay";
};
&fpd_dma_chan5 {
status = "okay";
};
&fpd_dma_chan6 {
status = "okay";
};
&fpd_dma_chan7 {
status = "okay";
};
&fpd_dma_chan8 {
status = "okay";
};
&gpu {
status = "okay";
};
&lpd_watchdog {
status = "okay";
};
&watchdog0 {
status = "okay";
};
&cpu_opp_table {
opp00 {
opp-hz = /bits/ 64 <1333333333>;
};
opp01 {
opp-hz = /bits/ 64 <666666666>;
};
opp02 {
opp-hz = /bits/ 64 <444444444>;
};
opp03 {
opp-hz = /bits/ 64 <333333333>;
};
};
|
