1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
|
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2022 Intel Corporation
*/
#ifndef __I915_REG_DEFS__
#define __I915_REG_DEFS__
#include <linux/bitfield.h>
#include <linux/bits.h>
/**
* REG_BIT() - Prepare a u32 bit value
* @__n: 0-based bit number
*
* Local wrapper for BIT() to force u32, with compile time checks.
*
* @return: Value with bit @__n set.
*/
#define REG_BIT(__n) \
((u32)(BIT(__n) + \
BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
((__n) < 0 || (__n) > 31))))
/**
* REG_BIT8() - Prepare a u8 bit value
* @__n: 0-based bit number
*
* Local wrapper for BIT() to force u8, with compile time checks.
*
* @return: Value with bit @__n set.
*/
#define REG_BIT8(__n) \
((u8)(BIT(__n) + \
BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
((__n) < 0 || (__n) > 7))))
/**
* REG_GENMASK() - Prepare a continuous u32 bitmask
* @__high: 0-based high bit
* @__low: 0-based low bit
*
* Local wrapper for GENMASK() to force u32, with compile time checks.
*
* @return: Continuous bitmask from @__high to @__low, inclusive.
*/
#define REG_GENMASK(__high, __low) \
((u32)(GENMASK(__high, __low) + \
BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
__is_constexpr(__low) && \
((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
/**
* REG_GENMASK64() - Prepare a continuous u64 bitmask
* @__high: 0-based high bit
* @__low: 0-based low bit
*
* Local wrapper for GENMASK_ULL() to force u64, with compile time checks.
*
* @return: Continuous bitmask from @__high to @__low, inclusive.
*/
#define REG_GENMASK64(__high, __low) \
((u64)(GENMASK_ULL(__high, __low) + \
BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
__is_constexpr(__low) && \
((__low) < 0 || (__high) > 63 || (__low) > (__high)))))
/**
* REG_GENMASK8() - Prepare a continuous u8 bitmask
* @__high: 0-based high bit
* @__low: 0-based low bit
*
* Local wrapper for GENMASK() to force u8, with compile time checks.
*
* @return: Continuous bitmask from @__high to @__low, inclusive.
*/
#define REG_GENMASK8(__high, __low) \
((u8)(GENMASK(__high, __low) + \
BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
__is_constexpr(__low) && \
((__low) < 0 || (__high) > 7 || (__low) > (__high)))))
/*
* Local integer constant expression version of is_power_of_2().
*/
#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
/**
* REG_FIELD_PREP() - Prepare a u32 bitfield value
* @__mask: shifted mask defining the field's length and position
* @__val: value to put in the field
*
* Local copy of FIELD_PREP() to generate an integer constant expression, force
* u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
*
* @return: @__val masked and shifted into the field defined by @__mask.
*/
#define REG_FIELD_PREP(__mask, __val) \
((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
/**
* REG_FIELD_PREP8() - Prepare a u8 bitfield value
* @__mask: shifted mask defining the field's length and position
* @__val: value to put in the field
*
* Local copy of FIELD_PREP() to generate an integer constant expression, force
* u8 and for consistency with REG_FIELD_GET8(), REG_BIT8() and REG_GENMASK8().
*
* @return: @__val masked and shifted into the field defined by @__mask.
*/
#define REG_FIELD_PREP8(__mask, __val) \
((u8)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U8_MAX) + \
BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
/**
* REG_FIELD_GET() - Extract a u32 bitfield value
* @__mask: shifted mask defining the field's length and position
* @__val: value to extract the bitfield value from
*
* Local wrapper for FIELD_GET() to force u32 and for consistency with
* REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
*
* @return: Masked and shifted value of the field defined by @__mask in @__val.
*/
#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))
/**
* REG_FIELD_GET64() - Extract a u64 bitfield value
* @__mask: shifted mask defining the field's length and position
* @__val: value to extract the bitfield value from
*
* Local wrapper for FIELD_GET() to force u64 and for consistency with
* REG_GENMASK64().
*
* @return: Masked and shifted value of the field defined by @__mask in @__val.
*/
#define REG_FIELD_GET64(__mask, __val) ((u64)FIELD_GET(__mask, __val))
/**
* REG_BIT16() - Prepare a u16 bit value
* @__n: 0-based bit number
*
* Local wrapper for BIT() to force u16, with compile time
* checks.
*
* @return: Value with bit @__n set.
*/
#define REG_BIT16(__n) \
((u16)(BIT(__n) + \
BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
((__n) < 0 || (__n) > 15))))
/**
* REG_GENMASK16() - Prepare a continuous u8 bitmask
* @__high: 0-based high bit
* @__low: 0-based low bit
*
* Local wrapper for GENMASK() to force u16, with compile time
* checks.
*
* @return: Continuous bitmask from @__high to @__low, inclusive.
*/
#define REG_GENMASK16(__high, __low) \
((u16)(GENMASK(__high, __low) + \
BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
__is_constexpr(__low) && \
((__low) < 0 || (__high) > 15 || (__low) > (__high)))))
/**
* REG_FIELD_PREP16() - Prepare a u16 bitfield value
* @__mask: shifted mask defining the field's length and position
* @__val: value to put in the field
*
* Local copy of FIELD_PREP16() to generate an integer constant
* expression, force u8 and for consistency with
* REG_FIELD_GET16(), REG_BIT16() and REG_GENMASK16().
*
* @return: @__val masked and shifted into the field defined by @__mask.
*/
#define REG_FIELD_PREP16(__mask, __val) \
((u16)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U16_MAX) + \
BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
#define _MASKED_FIELD(mask, value) ({ \
if (__builtin_constant_p(mask)) \
BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
if (__builtin_constant_p(value)) \
BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
BUILD_BUG_ON_MSG((value) & ~(mask), \
"Incorrect value for mask"); \
__MASKED_FIELD(mask, value); })
#define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
#define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
/*
* Given the first two numbers __a and __b of arbitrarily many evenly spaced
* numbers, pick the 0-based __index'th value.
*
* Always prefer this over _PICK() if the numbers are evenly spaced.
*/
#define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
/*
* Like _PICK_EVEN(), but supports 2 ranges of evenly spaced address offsets.
* @__c_index corresponds to the index in which the second range starts to be
* used. Using math interval notation, the first range is used for indexes [ 0,
* @__c_index), while the second range is used for [ @__c_index, ... ). Example:
*
* #define _FOO_A 0xf000
* #define _FOO_B 0xf004
* #define _FOO_C 0xf008
* #define _SUPER_FOO_A 0xa000
* #define _SUPER_FOO_B 0xa100
* #define FOO(x) _MMIO(_PICK_EVEN_2RANGES(x, 3, \
* _FOO_A, _FOO_B, \
* _SUPER_FOO_A, _SUPER_FOO_B))
*
* This expands to:
* 0: 0xf000,
* 1: 0xf004,
* 2: 0xf008,
* 3: 0xa000,
* 4: 0xa100,
* 5: 0xa200,
* ...
*/
#define _PICK_EVEN_2RANGES(__index, __c_index, __a, __b, __c, __d) \
(BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) + \
((__index) < (__c_index) ? _PICK_EVEN(__index, __a, __b) : \
_PICK_EVEN((__index) - (__c_index), __c, __d)))
/*
* Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
*
* Always prefer _PICK_EVEN() over this if the numbers are evenly spaced.
*/
#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
/**
* REG_FIELD_GET8() - Extract a u8 bitfield value
* @__mask: shifted mask defining the field's length and position
* @__val: value to extract the bitfield value from
*
* Local wrapper for FIELD_GET() to force u8 and for consistency with
* REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
*
* @return: Masked and shifted value of the field defined by @__mask in @__val.
*/
#define REG_FIELD_GET8(__mask, __val) ((u8)FIELD_GET(__mask, __val))
typedef struct {
u32 reg;
} i915_reg_t;
#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
typedef struct {
u32 reg;
} i915_mcr_reg_t;
#define MCR_REG(offset) ((const i915_mcr_reg_t){ .reg = (offset) })
#define INVALID_MMIO_REG _MMIO(0)
/*
* These macros can be used on either i915_reg_t or i915_mcr_reg_t since they're
* simply operations on the register's offset and don't care about the MCR vs
* non-MCR nature of the register.
*/
#define i915_mmio_reg_offset(r) \
_Generic((r), i915_reg_t: (r).reg, i915_mcr_reg_t: (r).reg)
#define i915_mmio_reg_equal(a, b) (i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b))
#define i915_mmio_reg_valid(r) (!i915_mmio_reg_equal(r, INVALID_MMIO_REG))
#endif /* __I915_REG_DEFS__ */
|
