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|
#ifndef MDP4_XML
#define MDP4_XML
/* Autogenerated file, DO NOT EDIT manually!
This file was generated by the rules-ng-ng headergen tool in this git repository:
http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
Copyright (C) 2013-2022 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
enum mdp4_pipe {
VG1 = 0,
VG2 = 1,
RGB1 = 2,
RGB2 = 3,
RGB3 = 4,
VG3 = 5,
VG4 = 6,
};
enum mdp4_mixer {
MIXER0 = 0,
MIXER1 = 1,
MIXER2 = 2,
};
enum mdp4_intf {
INTF_LCDC_DTV = 0,
INTF_DSI_VIDEO = 1,
INTF_DSI_CMD = 2,
INTF_EBI2_TV = 3,
};
enum mdp4_cursor_format {
CURSOR_ARGB = 1,
CURSOR_XRGB = 2,
};
enum mdp4_frame_format {
FRAME_LINEAR = 0,
FRAME_TILE_ARGB_4X4 = 1,
FRAME_TILE_YCBCR_420 = 2,
};
enum mdp4_scale_unit {
SCALE_FIR = 0,
SCALE_MN_PHASE = 1,
SCALE_PIXEL_RPT = 2,
};
enum mdp4_dma {
DMA_P = 0,
DMA_S = 1,
DMA_E = 2,
};
#define MDP4_IRQ_OVERLAY0_DONE 0x00000001
#define MDP4_IRQ_OVERLAY1_DONE 0x00000002
#define MDP4_IRQ_DMA_S_DONE 0x00000004
#define MDP4_IRQ_DMA_E_DONE 0x00000008
#define MDP4_IRQ_DMA_P_DONE 0x00000010
#define MDP4_IRQ_VG1_HISTOGRAM 0x00000020
#define MDP4_IRQ_VG2_HISTOGRAM 0x00000040
#define MDP4_IRQ_PRIMARY_VSYNC 0x00000080
#define MDP4_IRQ_PRIMARY_INTF_UDERRUN 0x00000100
#define MDP4_IRQ_EXTERNAL_VSYNC 0x00000200
#define MDP4_IRQ_EXTERNAL_INTF_UDERRUN 0x00000400
#define MDP4_IRQ_PRIMARY_RDPTR 0x00000800
#define MDP4_IRQ_DMA_P_HISTOGRAM 0x00020000
#define MDP4_IRQ_DMA_S_HISTOGRAM 0x04000000
#define MDP4_IRQ_OVERLAY2_DONE 0x40000000
#define REG_MDP4_VERSION 0x00000000
#define MDP4_VERSION_MINOR__MASK 0x00ff0000
#define MDP4_VERSION_MINOR__SHIFT 16
static inline uint32_t MDP4_VERSION_MINOR(uint32_t val)
{
return ((val) << MDP4_VERSION_MINOR__SHIFT) & MDP4_VERSION_MINOR__MASK;
}
#define MDP4_VERSION_MAJOR__MASK 0xff000000
#define MDP4_VERSION_MAJOR__SHIFT 24
static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val)
{
return ((val) << MDP4_VERSION_MAJOR__SHIFT) & MDP4_VERSION_MAJOR__MASK;
}
#define REG_MDP4_OVLP0_KICK 0x00000004
#define REG_MDP4_OVLP1_KICK 0x00000008
#define REG_MDP4_OVLP2_KICK 0x000000d0
#define REG_MDP4_DMA_P_KICK 0x0000000c
#define REG_MDP4_DMA_S_KICK 0x00000010
#define REG_MDP4_DMA_E_KICK 0x00000014
#define REG_MDP4_DISP_STATUS 0x00000018
#define REG_MDP4_DISP_INTF_SEL 0x00000038
#define MDP4_DISP_INTF_SEL_PRIM__MASK 0x00000003
#define MDP4_DISP_INTF_SEL_PRIM__SHIFT 0
static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val)
{
return ((val) << MDP4_DISP_INTF_SEL_PRIM__SHIFT) & MDP4_DISP_INTF_SEL_PRIM__MASK;
}
#define MDP4_DISP_INTF_SEL_SEC__MASK 0x0000000c
#define MDP4_DISP_INTF_SEL_SEC__SHIFT 2
static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val)
{
return ((val) << MDP4_DISP_INTF_SEL_SEC__SHIFT) & MDP4_DISP_INTF_SEL_SEC__MASK;
}
#define MDP4_DISP_INTF_SEL_EXT__MASK 0x00000030
#define MDP4_DISP_INTF_SEL_EXT__SHIFT 4
static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val)
{
return ((val) << MDP4_DISP_INTF_SEL_EXT__SHIFT) & MDP4_DISP_INTF_SEL_EXT__MASK;
}
#define MDP4_DISP_INTF_SEL_DSI_VIDEO 0x00000040
#define MDP4_DISP_INTF_SEL_DSI_CMD 0x00000080
#define REG_MDP4_RESET_STATUS 0x0000003c
#define REG_MDP4_READ_CNFG 0x0000004c
#define REG_MDP4_INTR_ENABLE 0x00000050
#define REG_MDP4_INTR_STATUS 0x00000054
#define REG_MDP4_INTR_CLEAR 0x00000058
#define REG_MDP4_EBI2_LCD0 0x00000060
#define REG_MDP4_EBI2_LCD1 0x00000064
#define REG_MDP4_PORTMAP_MODE 0x00000070
#define REG_MDP4_CS_CONTROLLER0 0x000000c0
#define REG_MDP4_CS_CONTROLLER1 0x000000c4
#define REG_MDP4_LAYERMIXER2_IN_CFG 0x000100f0
#define MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK 0x00000007
#define MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT 0
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)
{
return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK;
}
#define MDP4_LAYERMIXER2_IN_CFG_PIPE0_MIXER1 0x00000008
#define MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK 0x00000070
#define MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT 4
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)
{
return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK;
}
#define MDP4_LAYERMIXER2_IN_CFG_PIPE1_MIXER1 0x00000080
#define MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK 0x00000700
#define MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT 8
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)
{
return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK;
}
#define MDP4_LAYERMIXER2_IN_CFG_PIPE2_MIXER1 0x00000800
#define MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK 0x00007000
#define MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT 12
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)
{
return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK;
}
#define MDP4_LAYERMIXER2_IN_CFG_PIPE3_MIXER1 0x00008000
#define MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK 0x00070000
#define MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT 16
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)
{
return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK;
}
#define MDP4_LAYERMIXER2_IN_CFG_PIPE4_MIXER1 0x00080000
#define MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK 0x00700000
#define MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT 20
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)
{
return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK;
}
#define MDP4_LAYERMIXER2_IN_CFG_PIPE5_MIXER1 0x00800000
#define MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK 0x07000000
#define MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT 24
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)
{
return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK;
}
#define MDP4_LAYERMIXER2_IN_CFG_PIPE6_MIXER1 0x08000000
#define MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK 0x70000000
#define MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT 28
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)
{
return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK;
}
#define MDP4_LAYERMIXER2_IN_CFG_PIPE7_MIXER1 0x80000000
#define REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD 0x000100fc
#define REG_MDP4_LAYERMIXER_IN_CFG 0x00010100
#define MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK 0x00000007
#define MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT 0
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)
{
return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK;
}
#define MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1 0x00000008
#define MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK 0x00000070
#define MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT 4
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)
{
return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK;
}
#define MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1 0x00000080
#define MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK 0x00000700
#define MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT 8
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)
{
return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK;
}
#define MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1 0x00000800
#define MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK 0x00007000
#define MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT 12
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)
{
return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK;
}
#define MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1 0x00008000
#define MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK 0x00070000
#define MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT 16
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)
{
return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK;
}
#define MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1 0x00080000
#define MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK 0x00700000
#define MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT 20
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)
{
return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK;
}
#define MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1 0x00800000
#define MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK 0x07000000
#define MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT 24
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)
{
return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK;
}
#define MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1 0x08000000
#define MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK 0x70000000
#define MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT 28
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)
{
return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK;
}
#define MDP4_LAYERMIXER_IN_CFG_PIPE7_MIXER1 0x80000000
#define REG_MDP4_VG2_SRC_FORMAT 0x00030050
#define REG_MDP4_VG2_CONST_COLOR 0x00031008
#define REG_MDP4_OVERLAY_FLUSH 0x00018000
#define MDP4_OVERLAY_FLUSH_OVLP0 0x00000001
#define MDP4_OVERLAY_FLUSH_OVLP1 0x00000002
#define MDP4_OVERLAY_FLUSH_VG1 0x00000004
#define MDP4_OVERLAY_FLUSH_VG2 0x00000008
#define MDP4_OVERLAY_FLUSH_RGB1 0x00000010
#define MDP4_OVERLAY_FLUSH_RGB2 0x00000020
static inline uint32_t __offset_OVLP(uint32_t idx)
{
switch (idx) {
case 0: return 0x00010000;
case 1: return 0x00018000;
case 2: return 0x00088000;
default: return INVALID_IDX(idx);
}
}
static inline uint32_t REG_MDP4_OVLP(uint32_t i0) { return 0x00000000 + __offset_OVLP(i0); }
static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { return 0x00000004 + __offset_OVLP(i0); }
static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { return 0x00000008 + __offset_OVLP(i0); }
#define MDP4_OVLP_SIZE_HEIGHT__MASK 0xffff0000
#define MDP4_OVLP_SIZE_HEIGHT__SHIFT 16
static inline uint32_t MDP4_OVLP_SIZE_HEIGHT(uint32_t val)
{
return ((val) << MDP4_OVLP_SIZE_HEIGHT__SHIFT) & MDP4_OVLP_SIZE_HEIGHT__MASK;
}
#define MDP4_OVLP_SIZE_WIDTH__MASK 0x0000ffff
#define MDP4_OVLP_SIZE_WIDTH__SHIFT 0
static inline uint32_t MDP4_OVLP_SIZE_WIDTH(uint32_t val)
{
return ((val) << MDP4_OVLP_SIZE_WIDTH__SHIFT) & MDP4_OVLP_SIZE_WIDTH__MASK;
}
static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { return 0x0000000c + __offset_OVLP(i0); }
static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0) { return 0x00000010 + __offset_OVLP(i0); }
static inline uint32_t REG_MDP4_OVLP_OPMODE(uint32_t i0) { return 0x00000014 + __offset_OVLP(i0); }
static inline uint32_t __offset_STAGE(uint32_t idx)
{
switch (idx) {
case 0: return 0x00000104;
case 1: return 0x00000124;
case 2: return 0x00000144;
case 3: return 0x00000160;
default: return INVALID_IDX(idx);
}
}
static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); }
static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); }
#define MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK 0x00000003
#define MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT 0
static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp_alpha_type val)
{
return ((val) << MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK;
}
#define MDP4_OVLP_STAGE_OP_FG_INV_ALPHA 0x00000004
#define MDP4_OVLP_STAGE_OP_FG_MOD_ALPHA 0x00000008
#define MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK 0x00000030
#define MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT 4
static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp_alpha_type val)
{
return ((val) << MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK;
}
#define MDP4_OVLP_STAGE_OP_BG_INV_ALPHA 0x00000040
#define MDP4_OVLP_STAGE_OP_BG_MOD_ALPHA 0x00000080
#define MDP4_OVLP_STAGE_OP_FG_TRANSP 0x00000100
#define MDP4_OVLP_STAGE_OP_BG_TRANSP 0x00000200
static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_OVLP(i0) + __offset_STAGE(i1); }
static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_OVLP(i0) + __offset_STAGE(i1); }
static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_OVLP(i0) + __offset_STAGE(i1); }
static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_OVLP(i0) + __offset_STAGE(i1); }
static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_OVLP(i0) + __offset_STAGE(i1); }
static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_OVLP(i0) + __offset_STAGE(i1); }
static inline uint32_t __offset_STAGE_CO3(uint32_t idx)
{
switch (idx) {
case 0: return 0x00001004;
case 1: return 0x00001404;
case 2: return 0x00001804;
case 3: return 0x00001b84;
default: return INVALID_IDX(idx);
}
}
static inline uint32_t REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); }
static inline uint32_t REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); }
#define MDP4_OVLP_STAGE_CO3_SEL_FG_ALPHA 0x00000001
static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW0(uint32_t i0) { return 0x00000180 + __offset_OVLP(i0); }
static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW1(uint32_t i0) { return 0x00000184 + __offset_OVLP(i0); }
static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH0(uint32_t i0) { return 0x00000188 + __offset_OVLP(i0); }
static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH1(uint32_t i0) { return 0x0000018c + __offset_OVLP(i0); }
static inline uint32_t REG_MDP4_OVLP_CSC_CONFIG(uint32_t i0) { return 0x00000200 + __offset_OVLP(i0); }
static inline uint32_t REG_MDP4_OVLP_CSC(uint32_t i0) { return 0x00002000 + __offset_OVLP(i0); }
static inline uint32_t REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; }
#define REG_MDP4_DMA_P_OP_MODE 0x00090070
static inline uint32_t REG_MDP4_LUTN(uint32_t i0) { return 0x00094800 + 0x400*i0; }
static inline uint32_t REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; }
static inline uint32_t REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; }
#define REG_MDP4_DMA_S_OP_MODE 0x000a0028
static inline uint32_t REG_MDP4_DMA_E_QUANT(uint32_t i0) { return 0x000b0070 + 0x4*i0; }
static inline uint32_t __offset_DMA(enum mdp4_dma idx)
{
switch (idx) {
case DMA_P: return 0x00090000;
case DMA_S: return 0x000a0000;
case DMA_E: return 0x000b0000;
default: return INVALID_IDX(idx);
}
}
static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); }
static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); }
#define MDP4_DMA_CONFIG_G_BPC__MASK 0x00000003
#define MDP4_DMA_CONFIG_G_BPC__SHIFT 0
static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp_bpc val)
{
return ((val) << MDP4_DMA_CONFIG_G_BPC__SHIFT) & MDP4_DMA_CONFIG_G_BPC__MASK;
}
#define MDP4_DMA_CONFIG_B_BPC__MASK 0x0000000c
#define MDP4_DMA_CONFIG_B_BPC__SHIFT 2
static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp_bpc val)
{
return ((val) << MDP4_DMA_CONFIG_B_BPC__SHIFT) & MDP4_DMA_CONFIG_B_BPC__MASK;
}
#define MDP4_DMA_CONFIG_R_BPC__MASK 0x00000030
#define MDP4_DMA_CONFIG_R_BPC__SHIFT 4
static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp_bpc val)
{
return ((val) << MDP4_DMA_CONFIG_R_BPC__SHIFT) & MDP4_DMA_CONFIG_R_BPC__MASK;
}
#define MDP4_DMA_CONFIG_PACK_ALIGN_MSB 0x00000080
#define MDP4_DMA_CONFIG_PACK__MASK 0x0000ff00
#define MDP4_DMA_CONFIG_PACK__SHIFT 8
static inline uint32_t MDP4_DMA_CONFIG_PACK(uint32_t val)
{
return ((val) << MDP4_DMA_CONFIG_PACK__SHIFT) & MDP4_DMA_CONFIG_PACK__MASK;
}
#define MDP4_DMA_CONFIG_DEFLKR_EN 0x01000000
#define MDP4_DMA_CONFIG_DITHER_EN 0x01000000
static inline uint32_t REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0) { return 0x00000004 + __offset_DMA(i0); }
#define MDP4_DMA_SRC_SIZE_HEIGHT__MASK 0xffff0000
#define MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT 16
static inline uint32_t MDP4_DMA_SRC_SIZE_HEIGHT(uint32_t val)
{
return ((val) << MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT) & MDP4_DMA_SRC_SIZE_HEIGHT__MASK;
}
#define MDP4_DMA_SRC_SIZE_WIDTH__MASK 0x0000ffff
#define MDP4_DMA_SRC_SIZE_WIDTH__SHIFT 0
static inline uint32_t MDP4_DMA_SRC_SIZE_WIDTH(uint32_t val)
{
return ((val) << MDP4_DMA_SRC_SIZE_WIDTH__SHIFT) & MDP4_DMA_SRC_SIZE_WIDTH__MASK;
}
static inline uint32_t REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0) { return 0x00000008 + __offset_DMA(i0); }
static inline uint32_t REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0) { return 0x0000000c + __offset_DMA(i0); }
static inline uint32_t REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0) { return 0x00000010 + __offset_DMA(i0); }
#define MDP4_DMA_DST_SIZE_HEIGHT__MASK 0xffff0000
#define MDP4_DMA_DST_SIZE_HEIGHT__SHIFT 16
static inline uint32_t MDP4_DMA_DST_SIZE_HEIGHT(uint32_t val)
{
return ((val) << MDP4_DMA_DST_SIZE_HEIGHT__SHIFT) & MDP4_DMA_DST_SIZE_HEIGHT__MASK;
}
#define MDP4_DMA_DST_SIZE_WIDTH__MASK 0x0000ffff
#define MDP4_DMA_DST_SIZE_WIDTH__SHIFT 0
static inline uint32_t MDP4_DMA_DST_SIZE_WIDTH(uint32_t val)
{
return ((val) << MDP4_DMA_DST_SIZE_WIDTH__SHIFT) & MDP4_DMA_DST_SIZE_WIDTH__MASK;
}
static inline uint32_t REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0) { return 0x00000044 + __offset_DMA(i0); }
#define MDP4_DMA_CURSOR_SIZE_WIDTH__MASK 0x0000007f
#define MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT 0
static inline uint32_t MDP4_DMA_CURSOR_SIZE_WIDTH(uint32_t val)
{
return ((val) << MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT) & MDP4_DMA_CURSOR_SIZE_WIDTH__MASK;
}
#define MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK 0x007f0000
#define MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT 16
static inline uint32_t MDP4_DMA_CURSOR_SIZE_HEIGHT(uint32_t val)
{
return ((val) << MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT) & MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK;
}
static inline uint32_t REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i0) { return 0x00000048 + __offset_DMA(i0); }
static inline uint32_t REG_MDP4_DMA_CURSOR_POS(enum mdp4_dma i0) { return 0x0000004c + __offset_DMA(i0); }
#define MDP4_DMA_CURSOR_POS_X__MASK 0x0000ffff
#define MDP4_DMA_CURSOR_POS_X__SHIFT 0
static inline uint32_t MDP4_DMA_CURSOR_POS_X(uint32_t val)
{
return ((val) << MDP4_DMA_CURSOR_POS_X__SHIFT) & MDP4_DMA_CURSOR_POS_X__MASK;
}
#define MDP4_DMA_CURSOR_POS_Y__MASK 0xffff0000
#define MDP4_DMA_CURSOR_POS_Y__SHIFT 16
static inline uint32_t MDP4_DMA_CURSOR_POS_Y(uint32_t val)
{
return ((val) << MDP4_DMA_CURSOR_POS_Y__SHIFT) & MDP4_DMA_CURSOR_POS_Y__MASK;
}
static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_CONFIG(enum mdp4_dma i0) { return 0x00000060 + __offset_DMA(i0); }
#define MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN 0x00000001
#define MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__MASK 0x00000006
#define MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT 1
static inline uint32_t MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(enum mdp4_cursor_format val)
{
return ((val) << MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT) & MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__MASK;
}
#define MDP4_DMA_CURSOR_BLEND_CONFIG_TRANSP_EN 0x00000008
static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_PARAM(enum mdp4_dma i0) { return 0x00000064 + __offset_DMA(i0); }
static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_LOW(enum mdp4_dma i0) { return 0x00000068 + __offset_DMA(i0); }
static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_HIGH(enum mdp4_dma i0) { return 0x0000006c + __offset_DMA(i0); }
static inline uint32_t REG_MDP4_DMA_FETCH_CONFIG(enum mdp4_dma i0) { return 0x00001004 + __offset_DMA(i0); }
static inline uint32_t REG_MDP4_DMA_CSC(enum mdp4_dma i0) { return 0x00003000 + __offset_DMA(i0); }
static inline uint32_t REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; }
static inline uint32_t REG_MDP4_PIPE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; }
static inline uint32_t REG_MDP4_PIPE_SRC_SIZE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; }
#define MDP4_PIPE_SRC_SIZE_HEIGHT__MASK 0xffff0000
#define MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT 16
static inline uint32_t MDP4_PIPE_SRC_SIZE_HEIGHT(uint32_t val)
{
return ((val) << MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SRC_SIZE_HEIGHT__MASK;
}
#define MDP4_PIPE_SRC_SIZE_WIDTH__MASK 0x0000ffff
#define MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT 0
static inline uint32_t MDP4_PIPE_SRC_SIZE_WIDTH(uint32_t val)
{
return ((val) << MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SRC_SIZE_WIDTH__MASK;
}
static inline uint32_t REG_MDP4_PIPE_SRC_XY(enum mdp4_pipe i0) { return 0x00020004 + 0x10000*i0; }
#define MDP4_PIPE_SRC_XY_Y__MASK 0xffff0000
#define MDP4_PIPE_SRC_XY_Y__SHIFT 16
static inline uint32_t MDP4_PIPE_SRC_XY_Y(uint32_t val)
{
return ((val) << MDP4_PIPE_SRC_XY_Y__SHIFT) & MDP4_PIPE_SRC_XY_Y__MASK;
}
#define MDP4_PIPE_SRC_XY_X__MASK 0x0000ffff
#define MDP4_PIPE_SRC_XY_X__SHIFT 0
static inline uint32_t MDP4_PIPE_SRC_XY_X(uint32_t val)
{
return ((val) << MDP4_PIPE_SRC_XY_X__SHIFT) & MDP4_PIPE_SRC_XY_X__MASK;
}
static inline uint32_t REG_MDP4_PIPE_DST_SIZE(enum mdp4_pipe i0) { return 0x00020008 + 0x10000*i0; }
#define MDP4_PIPE_DST_SIZE_HEIGHT__MASK 0xffff0000
#define MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT 16
static inline uint32_t MDP4_PIPE_DST_SIZE_HEIGHT(uint32_t val)
{
return ((val) << MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_DST_SIZE_HEIGHT__MASK;
}
#define MDP4_PIPE_DST_SIZE_WIDTH__MASK 0x0000ffff
#define MDP4_PIPE_DST_SIZE_WIDTH__SHIFT 0
static inline uint32_t MDP4_PIPE_DST_SIZE_WIDTH(uint32_t val)
{
return ((val) << MDP4_PIPE_DST_SIZE_WIDTH__SHIFT) & MDP4_PIPE_DST_SIZE_WIDTH__MASK;
}
static inline uint32_t REG_MDP4_PIPE_DST_XY(enum mdp4_pipe i0) { return 0x0002000c + 0x10000*i0; }
#define MDP4_PIPE_DST_XY_Y__MASK 0xffff0000
#define MDP4_PIPE_DST_XY_Y__SHIFT 16
static inline uint32_t MDP4_PIPE_DST_XY_Y(uint32_t val)
{
return ((val) << MDP4_PIPE_DST_XY_Y__SHIFT) & MDP4_PIPE_DST_XY_Y__MASK;
}
#define MDP4_PIPE_DST_XY_X__MASK 0x0000ffff
#define MDP4_PIPE_DST_XY_X__SHIFT 0
static inline uint32_t MDP4_PIPE_DST_XY_X(uint32_t val)
{
return ((val) << MDP4_PIPE_DST_XY_X__SHIFT) & MDP4_PIPE_DST_XY_X__MASK;
}
static inline uint32_t REG_MDP4_PIPE_SRCP0_BASE(enum mdp4_pipe i0) { return 0x00020010 + 0x10000*i0; }
static inline uint32_t REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0) { return 0x00020014 + 0x10000*i0; }
static inline uint32_t REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0) { return 0x00020018 + 0x10000*i0; }
static inline uint32_t REG_MDP4_PIPE_SRCP3_BASE(enum mdp4_pipe i0) { return 0x0002001c + 0x10000*i0; }
static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0) { return 0x00020040 + 0x10000*i0; }
#define MDP4_PIPE_SRC_STRIDE_A_P0__MASK 0x0000ffff
#define MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT 0
static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P0(uint32_t val)
{
return ((val) << MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P0__MASK;
}
#define MDP4_PIPE_SRC_STRIDE_A_P1__MASK 0xffff0000
#define MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT 16
static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P1(uint32_t val)
{
return ((val) << MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P1__MASK;
}
static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_B(enum mdp4_pipe i0) { return 0x00020044 + 0x10000*i0; }
#define MDP4_PIPE_SRC_STRIDE_B_P2__MASK 0x0000ffff
#define MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT 0
static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P2(uint32_t val)
{
return ((val) << MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P2__MASK;
}
#define MDP4_PIPE_SRC_STRIDE_B_P3__MASK 0xffff0000
#define MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT 16
static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val)
{
return ((val) << MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P3__MASK;
}
static inline uint32_t REG_MDP4_PIPE_SSTILE_FRAME_SIZE(enum mdp4_pipe i0) { return 0x00020048 + 0x10000*i0; }
#define MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__MASK 0xffff0000
#define MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__SHIFT 16
static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT(uint32_t val)
{
return ((val) << MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__MASK;
}
#define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MASK 0x0000ffff
#define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT 0
static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH(uint32_t val)
{
return ((val) << MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MASK;
}
static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0; }
#define MDP4_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003
#define MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT 0
static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)
{
return ((val) << MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_G_BPC__MASK;
}
#define MDP4_PIPE_SRC_FORMAT_B_BPC__MASK 0x0000000c
#define MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT 2
static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)
{
return ((val) << MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_B_BPC__MASK;
}
#define MDP4_PIPE_SRC_FORMAT_R_BPC__MASK 0x00000030
#define MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT 4
static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)
{
return ((val) << MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_R_BPC__MASK;
}
#define MDP4_PIPE_SRC_FORMAT_A_BPC__MASK 0x000000c0
#define MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT 6
static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)
{
return ((val) << MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_A_BPC__MASK;
}
#define MDP4_PIPE_SRC_FORMAT_ALPHA_ENABLE 0x00000100
#define MDP4_PIPE_SRC_FORMAT_CPP__MASK 0x00000600
#define MDP4_PIPE_SRC_FORMAT_CPP__SHIFT 9
static inline uint32_t MDP4_PIPE_SRC_FORMAT_CPP(uint32_t val)
{
return ((val) << MDP4_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CPP__MASK;
}
#define MDP4_PIPE_SRC_FORMAT_ROTATED_90 0x00001000
#define MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK 0x00006000
#define MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT 13
static inline uint32_t MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)
{
return ((val) << MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK;
}
#define MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT 0x00020000
#define MDP4_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB 0x00040000
#define MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__MASK 0x00180000
#define MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__SHIFT 19
static inline uint32_t MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(uint32_t val)
{
return ((val) << MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__SHIFT) & MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__MASK;
}
#define MDP4_PIPE_SRC_FORMAT_SOLID_FILL 0x00400000
#define MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK 0x0c000000
#define MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT 26
static inline uint32_t MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)
{
return ((val) << MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK;
}
#define MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__MASK 0x60000000
#define MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__SHIFT 29
static inline uint32_t MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(enum mdp4_frame_format val)
{
return ((val) << MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__SHIFT) & MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__MASK;
}
static inline uint32_t REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0) { return 0x00020054 + 0x10000*i0; }
#define MDP4_PIPE_SRC_UNPACK_ELEM0__MASK 0x000000ff
#define MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT 0
static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM0(uint32_t val)
{
return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM0__MASK;
}
#define MDP4_PIPE_SRC_UNPACK_ELEM1__MASK 0x0000ff00
#define MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT 8
static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM1(uint32_t val)
{
return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM1__MASK;
}
#define MDP4_PIPE_SRC_UNPACK_ELEM2__MASK 0x00ff0000
#define MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT 16
static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM2(uint32_t val)
{
return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM2__MASK;
}
#define MDP4_PIPE_SRC_UNPACK_ELEM3__MASK 0xff000000
#define MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT 24
static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM3(uint32_t val)
{
return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM3__MASK;
}
static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0) { return 0x00020058 + 0x10000*i0; }
#define MDP4_PIPE_OP_MODE_SCALEX_EN 0x00000001
#define MDP4_PIPE_OP_MODE_SCALEY_EN 0x00000002
#define MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__MASK 0x0000000c
#define MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__SHIFT 2
static inline uint32_t MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL(enum mdp4_scale_unit val)
{
return ((val) << MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__SHIFT) & MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__MASK;
}
#define MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__MASK 0x00000030
#define MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__SHIFT 4
static inline uint32_t MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL(enum mdp4_scale_unit val)
{
return ((val) << MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__SHIFT) & MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__MASK;
}
#define MDP4_PIPE_OP_MODE_SRC_YCBCR 0x00000200
#define MDP4_PIPE_OP_MODE_DST_YCBCR 0x00000400
#define MDP4_PIPE_OP_MODE_CSC_EN 0x00000800
#define MDP4_PIPE_OP_MODE_FLIP_LR 0x00002000
#define MDP4_PIPE_OP_MODE_FLIP_UD 0x00004000
#define MDP4_PIPE_OP_MODE_DITHER_EN 0x00008000
#define MDP4_PIPE_OP_MODE_IGC_LUT_EN 0x00010000
#define MDP4_PIPE_OP_MODE_DEINT_EN 0x00040000
#define MDP4_PIPE_OP_MODE_DEINT_ODD_REF 0x00080000
static inline uint32_t REG_MDP4_PIPE_PHASEX_STEP(enum mdp4_pipe i0) { return 0x0002005c + 0x10000*i0; }
static inline uint32_t REG_MDP4_PIPE_PHASEY_STEP(enum mdp4_pipe i0) { return 0x00020060 + 0x10000*i0; }
static inline uint32_t REG_MDP4_PIPE_FETCH_CONFIG(enum mdp4_pipe i0) { return 0x00021004 + 0x10000*i0; }
static inline uint32_t REG_MDP4_PIPE_SOLID_COLOR(enum mdp4_pipe i0) { return 0x00021008 + 0x10000*i0; }
static inline uint32_t REG_MDP4_PIPE_CSC(enum mdp4_pipe i0) { return 0x00024000 + 0x10000*i0; }
static inline uint32_t REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; }
static inline uint32_t REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; }
static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; }
static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; }
static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; }
static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; }
static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; }
static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; }
static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; }
static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; }
#define REG_MDP4_LCDC 0x000c0000
#define REG_MDP4_LCDC_ENABLE 0x000c0000
#define REG_MDP4_LCDC_HSYNC_CTRL 0x000c0004
#define MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK 0x0000ffff
#define MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT 0
static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PULSEW(uint32_t val)
{
return ((val) << MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK;
}
#define MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK 0xffff0000
#define MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT 16
static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PERIOD(uint32_t val)
{
return ((val) << MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK;
}
#define REG_MDP4_LCDC_VSYNC_PERIOD 0x000c0008
#define REG_MDP4_LCDC_VSYNC_LEN 0x000c000c
#define REG_MDP4_LCDC_DISPLAY_HCTRL 0x000c0010
#define MDP4_LCDC_DISPLAY_HCTRL_START__MASK 0x0000ffff
#define MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT 0
static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_START(uint32_t val)
{
return ((val) << MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_START__MASK;
}
#define MDP4_LCDC_DISPLAY_HCTRL_END__MASK 0xffff0000
#define MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT 16
static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_END(uint32_t val)
{
return ((val) << MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_END__MASK;
}
#define REG_MDP4_LCDC_DISPLAY_VSTART 0x000c0014
#define REG_MDP4_LCDC_DISPLAY_VEND 0x000c0018
#define REG_MDP4_LCDC_ACTIVE_HCTL 0x000c001c
#define MDP4_LCDC_ACTIVE_HCTL_START__MASK 0x00007fff
#define MDP4_LCDC_ACTIVE_HCTL_START__SHIFT 0
static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_START(uint32_t val)
{
return ((val) << MDP4_LCDC_ACTIVE_HCTL_START__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_START__MASK;
}
#define MDP4_LCDC_ACTIVE_HCTL_END__MASK 0x7fff0000
#define MDP4_LCDC_ACTIVE_HCTL_END__SHIFT 16
static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_END(uint32_t val)
{
return ((val) << MDP4_LCDC_ACTIVE_HCTL_END__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_END__MASK;
}
#define MDP4_LCDC_ACTIVE_HCTL_ACTIVE_START_X 0x80000000
#define REG_MDP4_LCDC_ACTIVE_VSTART 0x000c0020
#define REG_MDP4_LCDC_ACTIVE_VEND 0x000c0024
#define REG_MDP4_LCDC_BORDER_CLR 0x000c0028
#define REG_MDP4_LCDC_UNDERFLOW_CLR 0x000c002c
#define MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff
#define MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT 0
static inline uint32_t MDP4_LCDC_UNDERFLOW_CLR_COLOR(uint32_t val)
{
return ((val) << MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK;
}
#define MDP4_LCDC_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000
#define REG_MDP4_LCDC_HSYNC_SKEW 0x000c0030
#define REG_MDP4_LCDC_TEST_CNTL 0x000c0034
#define REG_MDP4_LCDC_CTRL_POLARITY 0x000c0038
#define MDP4_LCDC_CTRL_POLARITY_HSYNC_LOW 0x00000001
#define MDP4_LCDC_CTRL_POLARITY_VSYNC_LOW 0x00000002
#define MDP4_LCDC_CTRL_POLARITY_DATA_EN_LOW 0x00000004
#define REG_MDP4_LCDC_LVDS_INTF_CTL 0x000c2000
#define MDP4_LCDC_LVDS_INTF_CTL_MODE_SEL 0x00000004
#define MDP4_LCDC_LVDS_INTF_CTL_RGB_OUT 0x00000008
#define MDP4_LCDC_LVDS_INTF_CTL_CH_SWAP 0x00000010
#define MDP4_LCDC_LVDS_INTF_CTL_CH1_RES_BIT 0x00000020
#define MDP4_LCDC_LVDS_INTF_CTL_CH2_RES_BIT 0x00000040
#define MDP4_LCDC_LVDS_INTF_CTL_ENABLE 0x00000080
#define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE0_EN 0x00000100
#define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE1_EN 0x00000200
#define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE2_EN 0x00000400
#define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE3_EN 0x00000800
#define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE0_EN 0x00001000
#define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE1_EN 0x00002000
#define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE2_EN 0x00004000
#define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE3_EN 0x00008000
#define MDP4_LCDC_LVDS_INTF_CTL_CH1_CLK_LANE_EN 0x00010000
#define MDP4_LCDC_LVDS_INTF_CTL_CH2_CLK_LANE_EN 0x00020000
static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL(uint32_t i0) { return 0x000c2014 + 0x8*i0; }
static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(uint32_t i0) { return 0x000c2014 + 0x8*i0; }
#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__MASK 0x000000ff
#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__SHIFT 0
static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(uint32_t val)
{
return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__MASK;
}
#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__MASK 0x0000ff00
#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__SHIFT 8
static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(uint32_t val)
{
return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__MASK;
}
#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__MASK 0x00ff0000
#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__SHIFT 16
static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(uint32_t val)
{
return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__MASK;
}
#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__MASK 0xff000000
#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__SHIFT 24
static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(uint32_t val)
{
return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__MASK;
}
static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(uint32_t i0) { return 0x000c2018 + 0x8*i0; }
#define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__MASK 0x000000ff
#define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__SHIFT 0
static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(uint32_t val)
{
return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__MASK;
}
#define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__MASK 0x0000ff00
#define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__SHIFT 8
static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(uint32_t val)
{
return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__MASK;
}
#define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__MASK 0x00ff0000
#define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__SHIFT 16
static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(uint32_t val)
{
return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__MASK;
}
#define REG_MDP4_LCDC_LVDS_PHY_RESET 0x000c2034
#define REG_MDP4_LVDS_PHY_PLL_CTRL_0 0x000c3000
#define REG_MDP4_LVDS_PHY_PLL_CTRL_1 0x000c3004
#define REG_MDP4_LVDS_PHY_PLL_CTRL_2 0x000c3008
#define REG_MDP4_LVDS_PHY_PLL_CTRL_3 0x000c300c
#define REG_MDP4_LVDS_PHY_PLL_CTRL_5 0x000c3014
#define REG_MDP4_LVDS_PHY_PLL_CTRL_6 0x000c3018
#define REG_MDP4_LVDS_PHY_PLL_CTRL_7 0x000c301c
#define REG_MDP4_LVDS_PHY_PLL_CTRL_8 0x000c3020
#define REG_MDP4_LVDS_PHY_PLL_CTRL_9 0x000c3024
#define REG_MDP4_LVDS_PHY_PLL_LOCKED 0x000c3080
#define REG_MDP4_LVDS_PHY_CFG2 0x000c3108
#define REG_MDP4_LVDS_PHY_CFG0 0x000c3100
#define MDP4_LVDS_PHY_CFG0_SERIALIZATION_ENBLE 0x00000010
#define MDP4_LVDS_PHY_CFG0_CHANNEL0 0x00000040
#define MDP4_LVDS_PHY_CFG0_CHANNEL1 0x00000080
#define REG_MDP4_DTV 0x000d0000
#define REG_MDP4_DTV_ENABLE 0x000d0000
#define REG_MDP4_DTV_HSYNC_CTRL 0x000d0004
#define MDP4_DTV_HSYNC_CTRL_PULSEW__MASK 0x0000ffff
#define MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT 0
static inline uint32_t MDP4_DTV_HSYNC_CTRL_PULSEW(uint32_t val)
{
return ((val) << MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DTV_HSYNC_CTRL_PULSEW__MASK;
}
#define MDP4_DTV_HSYNC_CTRL_PERIOD__MASK 0xffff0000
#define MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT 16
static inline uint32_t MDP4_DTV_HSYNC_CTRL_PERIOD(uint32_t val)
{
return ((val) << MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DTV_HSYNC_CTRL_PERIOD__MASK;
}
#define REG_MDP4_DTV_VSYNC_PERIOD 0x000d0008
#define REG_MDP4_DTV_VSYNC_LEN 0x000d000c
#define REG_MDP4_DTV_DISPLAY_HCTRL 0x000d0018
#define MDP4_DTV_DISPLAY_HCTRL_START__MASK 0x0000ffff
#define MDP4_DTV_DISPLAY_HCTRL_START__SHIFT 0
static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_START(uint32_t val)
{
return ((val) << MDP4_DTV_DISPLAY_HCTRL_START__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_START__MASK;
}
#define MDP4_DTV_DISPLAY_HCTRL_END__MASK 0xffff0000
#define MDP4_DTV_DISPLAY_HCTRL_END__SHIFT 16
static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_END(uint32_t val)
{
return ((val) << MDP4_DTV_DISPLAY_HCTRL_END__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_END__MASK;
}
#define REG_MDP4_DTV_DISPLAY_VSTART 0x000d001c
#define REG_MDP4_DTV_DISPLAY_VEND 0x000d0020
#define REG_MDP4_DTV_ACTIVE_HCTL 0x000d002c
#define MDP4_DTV_ACTIVE_HCTL_START__MASK 0x00007fff
#define MDP4_DTV_ACTIVE_HCTL_START__SHIFT 0
static inline uint32_t MDP4_DTV_ACTIVE_HCTL_START(uint32_t val)
{
return ((val) << MDP4_DTV_ACTIVE_HCTL_START__SHIFT) & MDP4_DTV_ACTIVE_HCTL_START__MASK;
}
#define MDP4_DTV_ACTIVE_HCTL_END__MASK 0x7fff0000
#define MDP4_DTV_ACTIVE_HCTL_END__SHIFT 16
static inline uint32_t MDP4_DTV_ACTIVE_HCTL_END(uint32_t val)
{
return ((val) << MDP4_DTV_ACTIVE_HCTL_END__SHIFT) & MDP4_DTV_ACTIVE_HCTL_END__MASK;
}
#define MDP4_DTV_ACTIVE_HCTL_ACTIVE_START_X 0x80000000
#define REG_MDP4_DTV_ACTIVE_VSTART 0x000d0030
#define REG_MDP4_DTV_ACTIVE_VEND 0x000d0038
#define REG_MDP4_DTV_BORDER_CLR 0x000d0040
#define REG_MDP4_DTV_UNDERFLOW_CLR 0x000d0044
#define MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff
#define MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT 0
static inline uint32_t MDP4_DTV_UNDERFLOW_CLR_COLOR(uint32_t val)
{
return ((val) << MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK;
}
#define MDP4_DTV_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000
#define REG_MDP4_DTV_HSYNC_SKEW 0x000d0048
#define REG_MDP4_DTV_TEST_CNTL 0x000d004c
#define REG_MDP4_DTV_CTRL_POLARITY 0x000d0050
#define MDP4_DTV_CTRL_POLARITY_HSYNC_LOW 0x00000001
#define MDP4_DTV_CTRL_POLARITY_VSYNC_LOW 0x00000002
#define MDP4_DTV_CTRL_POLARITY_DATA_EN_LOW 0x00000004
#define REG_MDP4_DSI 0x000e0000
#define REG_MDP4_DSI_ENABLE 0x000e0000
#define REG_MDP4_DSI_HSYNC_CTRL 0x000e0004
#define MDP4_DSI_HSYNC_CTRL_PULSEW__MASK 0x0000ffff
#define MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT 0
static inline uint32_t MDP4_DSI_HSYNC_CTRL_PULSEW(uint32_t val)
{
return ((val) << MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DSI_HSYNC_CTRL_PULSEW__MASK;
}
#define MDP4_DSI_HSYNC_CTRL_PERIOD__MASK 0xffff0000
#define MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT 16
static inline uint32_t MDP4_DSI_HSYNC_CTRL_PERIOD(uint32_t val)
{
return ((val) << MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DSI_HSYNC_CTRL_PERIOD__MASK;
}
#define REG_MDP4_DSI_VSYNC_PERIOD 0x000e0008
#define REG_MDP4_DSI_VSYNC_LEN 0x000e000c
#define REG_MDP4_DSI_DISPLAY_HCTRL 0x000e0010
#define MDP4_DSI_DISPLAY_HCTRL_START__MASK 0x0000ffff
#define MDP4_DSI_DISPLAY_HCTRL_START__SHIFT 0
static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_START(uint32_t val)
{
return ((val) << MDP4_DSI_DISPLAY_HCTRL_START__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_START__MASK;
}
#define MDP4_DSI_DISPLAY_HCTRL_END__MASK 0xffff0000
#define MDP4_DSI_DISPLAY_HCTRL_END__SHIFT 16
static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_END(uint32_t val)
{
return ((val) << MDP4_DSI_DISPLAY_HCTRL_END__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_END__MASK;
}
#define REG_MDP4_DSI_DISPLAY_VSTART 0x000e0014
#define REG_MDP4_DSI_DISPLAY_VEND 0x000e0018
#define REG_MDP4_DSI_ACTIVE_HCTL 0x000e001c
#define MDP4_DSI_ACTIVE_HCTL_START__MASK 0x00007fff
#define MDP4_DSI_ACTIVE_HCTL_START__SHIFT 0
static inline uint32_t MDP4_DSI_ACTIVE_HCTL_START(uint32_t val)
{
return ((val) << MDP4_DSI_ACTIVE_HCTL_START__SHIFT) & MDP4_DSI_ACTIVE_HCTL_START__MASK;
}
#define MDP4_DSI_ACTIVE_HCTL_END__MASK 0x7fff0000
#define MDP4_DSI_ACTIVE_HCTL_END__SHIFT 16
static inline uint32_t MDP4_DSI_ACTIVE_HCTL_END(uint32_t val)
{
return ((val) << MDP4_DSI_ACTIVE_HCTL_END__SHIFT) & MDP4_DSI_ACTIVE_HCTL_END__MASK;
}
#define MDP4_DSI_ACTIVE_HCTL_ACTIVE_START_X 0x80000000
#define REG_MDP4_DSI_ACTIVE_VSTART 0x000e0020
#define REG_MDP4_DSI_ACTIVE_VEND 0x000e0024
#define REG_MDP4_DSI_BORDER_CLR 0x000e0028
#define REG_MDP4_DSI_UNDERFLOW_CLR 0x000e002c
#define MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff
#define MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT 0
static inline uint32_t MDP4_DSI_UNDERFLOW_CLR_COLOR(uint32_t val)
{
return ((val) << MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK;
}
#define MDP4_DSI_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000
#define REG_MDP4_DSI_HSYNC_SKEW 0x000e0030
#define REG_MDP4_DSI_TEST_CNTL 0x000e0034
#define REG_MDP4_DSI_CTRL_POLARITY 0x000e0038
#define MDP4_DSI_CTRL_POLARITY_HSYNC_LOW 0x00000001
#define MDP4_DSI_CTRL_POLARITY_VSYNC_LOW 0x00000002
#define MDP4_DSI_CTRL_POLARITY_DATA_EN_LOW 0x00000004
#endif /* MDP4_XML */
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