summaryrefslogtreecommitdiffstats
path: root/drivers/phy/microchip/sparx5_serdes_regs.h
blob: d0543fd3dc94d268f510b50d04adf5abebfb544b (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
/* SPDX-License-Identifier: GPL-2.0+
 * Microchip Sparx5 SerDes driver
 *
 * Copyright (c) 2020 Microchip Technology Inc.
 */

/* This file is autogenerated by cml-utils 2020-11-16 13:11:27 +0100.
 * Commit ID: 13bdf073131d8bf40c54901df6988ae4e9c8f29f
 */

#ifndef _SPARX5_SERDES_REGS_H_
#define _SPARX5_SERDES_REGS_H_

#include <linux/bitfield.h>
#include <linux/types.h>
#include <linux/bug.h>

enum sparx5_serdes_target {
	TARGET_SD10G_LANE = 200,
	TARGET_SD25G_LANE = 212,
	TARGET_SD6G_LANE = 233,
	TARGET_SD_CMU = 248,
	TARGET_SD_CMU_CFG = 262,
	TARGET_SD_LANE = 276,
	TARGET_SD_LANE_25G = 301,
	NUM_TARGETS = 332
};

#define __REG(...)    __VA_ARGS__

/*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_01 */
#define SD10G_LANE_LANE_01(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 4, 0, 1, 4)

#define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0 GENMASK(2, 0)
#define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
#define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x)

#define SD10G_LANE_LANE_01_CFG_RXDET_EN          BIT(4)
#define SD10G_LANE_LANE_01_CFG_RXDET_EN_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_EN, x)
#define SD10G_LANE_LANE_01_CFG_RXDET_EN_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_01_CFG_RXDET_EN, x)

#define SD10G_LANE_LANE_01_CFG_RXDET_STR         BIT(5)
#define SD10G_LANE_LANE_01_CFG_RXDET_STR_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_STR, x)
#define SD10G_LANE_LANE_01_CFG_RXDET_STR_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_01_CFG_RXDET_STR, x)

/*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_02 */
#define SD10G_LANE_LANE_02(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 8, 0, 1, 4)

#define SD10G_LANE_LANE_02_CFG_EN_ADV            BIT(0)
#define SD10G_LANE_LANE_02_CFG_EN_ADV_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_ADV, x)
#define SD10G_LANE_LANE_02_CFG_EN_ADV_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_ADV, x)

#define SD10G_LANE_LANE_02_CFG_EN_MAIN           BIT(1)
#define SD10G_LANE_LANE_02_CFG_EN_MAIN_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_MAIN, x)
#define SD10G_LANE_LANE_02_CFG_EN_MAIN_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_MAIN, x)

#define SD10G_LANE_LANE_02_CFG_EN_DLY            BIT(2)
#define SD10G_LANE_LANE_02_CFG_EN_DLY_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_DLY, x)
#define SD10G_LANE_LANE_02_CFG_EN_DLY_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_DLY, x)

#define SD10G_LANE_LANE_02_CFG_EN_DLY2           BIT(3)
#define SD10G_LANE_LANE_02_CFG_EN_DLY2_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_DLY2, x)
#define SD10G_LANE_LANE_02_CFG_EN_DLY2_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_DLY2, x)

#define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0       GENMASK(7, 4)
#define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0, x)
#define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0, x)

/*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_03 */
#define SD10G_LANE_LANE_03(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 12, 0, 1, 4)

#define SD10G_LANE_LANE_03_CFG_TAP_MAIN          BIT(0)
#define SD10G_LANE_LANE_03_CFG_TAP_MAIN_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_03_CFG_TAP_MAIN, x)
#define SD10G_LANE_LANE_03_CFG_TAP_MAIN_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_03_CFG_TAP_MAIN, x)

/*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_04 */
#define SD10G_LANE_LANE_04(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 16, 0, 1, 4)

#define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0       GENMASK(4, 0)
#define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0, x)
#define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0, x)

/*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_06 */
#define SD10G_LANE_LANE_06(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 24, 0, 1, 4)

#define SD10G_LANE_LANE_06_CFG_PD_DRIVER         BIT(0)
#define SD10G_LANE_LANE_06_CFG_PD_DRIVER_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_06_CFG_PD_DRIVER, x)
#define SD10G_LANE_LANE_06_CFG_PD_DRIVER_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_06_CFG_PD_DRIVER, x)

#define SD10G_LANE_LANE_06_CFG_PD_CLK            BIT(1)
#define SD10G_LANE_LANE_06_CFG_PD_CLK_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_06_CFG_PD_CLK, x)
#define SD10G_LANE_LANE_06_CFG_PD_CLK_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_06_CFG_PD_CLK, x)

#define SD10G_LANE_LANE_06_CFG_PD_CML            BIT(2)
#define SD10G_LANE_LANE_06_CFG_PD_CML_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_06_CFG_PD_CML, x)
#define SD10G_LANE_LANE_06_CFG_PD_CML_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_06_CFG_PD_CML, x)

#define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN       BIT(3)
#define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN, x)
#define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN, x)

#define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN       BIT(4)
#define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN, x)
#define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN, x)

#define SD10G_LANE_LANE_06_CFG_EN_PREEMPH        BIT(5)
#define SD10G_LANE_LANE_06_CFG_EN_PREEMPH_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_06_CFG_EN_PREEMPH, x)
#define SD10G_LANE_LANE_06_CFG_EN_PREEMPH_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_06_CFG_EN_PREEMPH, x)

/*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_0B */
#define SD10G_LANE_LANE_0B(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 44, 0, 1, 4)

#define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0        GENMASK(3, 0)
#define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0, x)
#define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0, x)

#define SD10G_LANE_LANE_0B_CFG_PD_CTLE           BIT(4)
#define SD10G_LANE_LANE_0B_CFG_PD_CTLE_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_0B_CFG_PD_CTLE, x)
#define SD10G_LANE_LANE_0B_CFG_PD_CTLE_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_0B_CFG_PD_CTLE, x)

#define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN        BIT(5)
#define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN, x)
#define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN, x)

#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE  BIT(6)
#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE, x)
#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE, x)

#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ   BIT(7)
#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ, x)
#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ, x)

/*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_0C */
#define SD10G_LANE_LANE_0C(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 48, 0, 1, 4)

#define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE         BIT(0)
#define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSCAL_AFE, x)
#define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSCAL_AFE, x)

#define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ          BIT(1)
#define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSCAL_SQ, x)
#define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSCAL_SQ, x)

#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE      BIT(2)
#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE, x)
#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE, x)

#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ       BIT(3)
#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ, x)
#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ, x)

#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE      BIT(4)
#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE, x)
#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE, x)

#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ       BIT(5)
#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ, x)
#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ, x)

#define SD10G_LANE_LANE_0C_CFG_PD_RX_LS          BIT(6)
#define SD10G_LANE_LANE_0C_CFG_PD_RX_LS_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_0C_CFG_PD_RX_LS, x)
#define SD10G_LANE_LANE_0C_CFG_PD_RX_LS_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_0C_CFG_PD_RX_LS, x)

#define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12     BIT(7)
#define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12, x)
#define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12, x)

/*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_0D */
#define SD10G_LANE_LANE_0D(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 52, 0, 1, 4)

#define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0    GENMASK(1, 0)
#define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0, x)
#define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0, x)

#define SD10G_LANE_LANE_0D_CFG_EQR_BYP           BIT(4)
#define SD10G_LANE_LANE_0D_CFG_EQR_BYP_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_0D_CFG_EQR_BYP, x)
#define SD10G_LANE_LANE_0D_CFG_EQR_BYP_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_0D_CFG_EQR_BYP, x)

/*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_0E */
#define SD10G_LANE_LANE_0E(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 56, 0, 1, 4)

#define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0     GENMASK(3, 0)
#define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0, x)
#define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0, x)

#define SD10G_LANE_LANE_0E_CFG_RXLB_EN           BIT(4)
#define SD10G_LANE_LANE_0E_CFG_RXLB_EN_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_0E_CFG_RXLB_EN, x)
#define SD10G_LANE_LANE_0E_CFG_RXLB_EN_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_0E_CFG_RXLB_EN, x)

#define SD10G_LANE_LANE_0E_CFG_TXLB_EN           BIT(5)
#define SD10G_LANE_LANE_0E_CFG_TXLB_EN_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_0E_CFG_TXLB_EN, x)
#define SD10G_LANE_LANE_0E_CFG_TXLB_EN_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_0E_CFG_TXLB_EN, x)

#define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN      BIT(6)
#define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN, x)
#define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN, x)

/*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_0F */
#define SD10G_LANE_LANE_0F(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 60, 0, 1, 4)

#define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0      GENMASK(7, 0)
#define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0, x)
#define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0, x)

/*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_13 */
#define SD10G_LANE_LANE_13(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 76, 0, 1, 4)

#define SD10G_LANE_LANE_13_CFG_DCDR_PD           BIT(0)
#define SD10G_LANE_LANE_13_CFG_DCDR_PD_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_13_CFG_DCDR_PD, x)
#define SD10G_LANE_LANE_13_CFG_DCDR_PD_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_13_CFG_DCDR_PD, x)

#define SD10G_LANE_LANE_13_CFG_PHID_1T           BIT(1)
#define SD10G_LANE_LANE_13_CFG_PHID_1T_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_13_CFG_PHID_1T, x)
#define SD10G_LANE_LANE_13_CFG_PHID_1T_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_13_CFG_PHID_1T, x)

#define SD10G_LANE_LANE_13_CFG_CDRCK_EN          BIT(2)
#define SD10G_LANE_LANE_13_CFG_CDRCK_EN_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_13_CFG_CDRCK_EN, x)
#define SD10G_LANE_LANE_13_CFG_CDRCK_EN_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_13_CFG_CDRCK_EN, x)

/*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_14 */
#define SD10G_LANE_LANE_14(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 80, 0, 1, 4)

#define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0    GENMASK(7, 0)
#define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0, x)
#define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0, x)

/*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_15 */
#define SD10G_LANE_LANE_15(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 84, 0, 1, 4)

#define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8   GENMASK(7, 0)
#define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8, x)
#define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8, x)

/*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_16 */
#define SD10G_LANE_LANE_16(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 88, 0, 1, 4)

#define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16  GENMASK(7, 0)
#define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16, x)
#define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16, x)

/*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_1A */
#define SD10G_LANE_LANE_1A(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 104, 0, 1, 4)

#define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN      BIT(0)
#define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN, x)
#define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN, x)

#define SD10G_LANE_LANE_1A_CFG_PI_EN             BIT(1)
#define SD10G_LANE_LANE_1A_CFG_PI_EN_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_EN, x)
#define SD10G_LANE_LANE_1A_CFG_PI_EN_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_EN, x)

#define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN         BIT(2)
#define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_DFE_EN, x)
#define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_DFE_EN, x)

#define SD10G_LANE_LANE_1A_CFG_PI_STEPS          BIT(3)
#define SD10G_LANE_LANE_1A_CFG_PI_STEPS_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_STEPS, x)
#define SD10G_LANE_LANE_1A_CFG_PI_STEPS_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_STEPS, x)

#define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0 GENMASK(5, 4)
#define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0, x)
#define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0, x)

/*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_22 */
#define SD10G_LANE_LANE_22(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 136, 0, 1, 4)

#define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1     GENMASK(4, 0)
#define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1, x)
#define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1, x)

/*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_23 */
#define SD10G_LANE_LANE_23(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 140, 0, 1, 4)

#define SD10G_LANE_LANE_23_CFG_DFE_PD            BIT(0)
#define SD10G_LANE_LANE_23_CFG_DFE_PD_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_23_CFG_DFE_PD, x)
#define SD10G_LANE_LANE_23_CFG_DFE_PD_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_23_CFG_DFE_PD, x)

#define SD10G_LANE_LANE_23_CFG_EN_DFEDIG         BIT(1)
#define SD10G_LANE_LANE_23_CFG_EN_DFEDIG_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_23_CFG_EN_DFEDIG, x)
#define SD10G_LANE_LANE_23_CFG_EN_DFEDIG_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_23_CFG_EN_DFEDIG, x)

#define SD10G_LANE_LANE_23_CFG_DFECK_EN          BIT(2)
#define SD10G_LANE_LANE_23_CFG_DFECK_EN_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_23_CFG_DFECK_EN, x)
#define SD10G_LANE_LANE_23_CFG_DFECK_EN_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_23_CFG_DFECK_EN, x)

#define SD10G_LANE_LANE_23_CFG_ERRAMP_PD         BIT(3)
#define SD10G_LANE_LANE_23_CFG_ERRAMP_PD_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_23_CFG_ERRAMP_PD, x)
#define SD10G_LANE_LANE_23_CFG_ERRAMP_PD_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_23_CFG_ERRAMP_PD, x)

#define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0      GENMASK(6, 4)
#define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0, x)
#define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0, x)

/*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_24 */
#define SD10G_LANE_LANE_24(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 144, 0, 1, 4)

#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0    GENMASK(3, 0)
#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0, x)
#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0, x)

#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0    GENMASK(7, 4)
#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0, x)
#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0, x)

/*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_26 */
#define SD10G_LANE_LANE_26(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 152, 0, 1, 4)

#define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0 GENMASK(7, 0)
#define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0, x)
#define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0, x)

/*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_2F */
#define SD10G_LANE_LANE_2F(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 188, 0, 1, 4)

#define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0        GENMASK(2, 0)
#define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0, x)
#define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0, x)

#define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0      GENMASK(7, 4)
#define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0, x)
#define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0, x)

/*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_30 */
#define SD10G_LANE_LANE_30(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 192, 0, 1, 4)

#define SD10G_LANE_LANE_30_CFG_SUMMER_EN         BIT(0)
#define SD10G_LANE_LANE_30_CFG_SUMMER_EN_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_30_CFG_SUMMER_EN, x)
#define SD10G_LANE_LANE_30_CFG_SUMMER_EN_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_30_CFG_SUMMER_EN, x)

#define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0     GENMASK(6, 4)
#define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0, x)
#define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0, x)

/*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_31 */
#define SD10G_LANE_LANE_31(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 196, 0, 1, 4)

#define SD10G_LANE_LANE_31_CFG_PI_RSTN           BIT(0)
#define SD10G_LANE_LANE_31_CFG_PI_RSTN_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_31_CFG_PI_RSTN, x)
#define SD10G_LANE_LANE_31_CFG_PI_RSTN_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_31_CFG_PI_RSTN, x)

#define SD10G_LANE_LANE_31_CFG_CDR_RSTN          BIT(1)
#define SD10G_LANE_LANE_31_CFG_CDR_RSTN_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_31_CFG_CDR_RSTN, x)
#define SD10G_LANE_LANE_31_CFG_CDR_RSTN_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_31_CFG_CDR_RSTN, x)

#define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG       BIT(2)
#define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG, x)
#define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG, x)

#define SD10G_LANE_LANE_31_CFG_CTLE_RSTN         BIT(3)
#define SD10G_LANE_LANE_31_CFG_CTLE_RSTN_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_31_CFG_CTLE_RSTN, x)
#define SD10G_LANE_LANE_31_CFG_CTLE_RSTN_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_31_CFG_CTLE_RSTN, x)

#define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8       BIT(4)
#define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8, x)
#define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8, x)

#define SD10G_LANE_LANE_31_CFG_R50_EN            BIT(5)
#define SD10G_LANE_LANE_31_CFG_R50_EN_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_31_CFG_R50_EN, x)
#define SD10G_LANE_LANE_31_CFG_R50_EN_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_31_CFG_R50_EN, x)

/*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_32 */
#define SD10G_LANE_LANE_32(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 200, 0, 1, 4)

#define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0 GENMASK(1, 0)
#define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0, x)
#define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0, x)

#define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0 GENMASK(5, 4)
#define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0, x)
#define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0, x)

/*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_33 */
#define SD10G_LANE_LANE_33(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 204, 0, 1, 4)

#define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0 GENMASK(2, 0)
#define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0, x)
#define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0, x)

#define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0 GENMASK(5, 4)
#define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0, x)
#define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0, x)

/*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_35 */
#define SD10G_LANE_LANE_35(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 212, 0, 1, 4)

#define SD10G_LANE_LANE_35_CFG_TXRATE_1_0        GENMASK(1, 0)
#define SD10G_LANE_LANE_35_CFG_TXRATE_1_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_35_CFG_TXRATE_1_0, x)
#define SD10G_LANE_LANE_35_CFG_TXRATE_1_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_35_CFG_TXRATE_1_0, x)

#define SD10G_LANE_LANE_35_CFG_RXRATE_1_0        GENMASK(5, 4)
#define SD10G_LANE_LANE_35_CFG_RXRATE_1_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_35_CFG_RXRATE_1_0, x)
#define SD10G_LANE_LANE_35_CFG_RXRATE_1_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_35_CFG_RXRATE_1_0, x)

/*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_36 */
#define SD10G_LANE_LANE_36(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 216, 0, 1, 4)

#define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0 GENMASK(1, 0)
#define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0, x)
#define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0, x)

#define SD10G_LANE_LANE_36_CFG_EID_LP            BIT(4)
#define SD10G_LANE_LANE_36_CFG_EID_LP_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_36_CFG_EID_LP, x)
#define SD10G_LANE_LANE_36_CFG_EID_LP_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_36_CFG_EID_LP, x)

#define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH    BIT(5)
#define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH, x)
#define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH, x)

#define SD10G_LANE_LANE_36_CFG_PRBS_SEL          BIT(6)
#define SD10G_LANE_LANE_36_CFG_PRBS_SEL_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_36_CFG_PRBS_SEL, x)
#define SD10G_LANE_LANE_36_CFG_PRBS_SEL_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_36_CFG_PRBS_SEL, x)

#define SD10G_LANE_LANE_36_CFG_PRBS_SETB         BIT(7)
#define SD10G_LANE_LANE_36_CFG_PRBS_SETB_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_36_CFG_PRBS_SETB, x)
#define SD10G_LANE_LANE_36_CFG_PRBS_SETB_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_36_CFG_PRBS_SETB, x)

/*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_37 */
#define SD10G_LANE_LANE_37(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 220, 0, 1, 4)

#define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD     BIT(0)
#define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD, x)
#define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD, x)

#define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE      BIT(1)
#define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE, x)
#define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE, x)

#define SD10G_LANE_LANE_37_CFG_TXSWING_HALF      BIT(2)
#define SD10G_LANE_LANE_37_CFG_TXSWING_HALF_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_37_CFG_TXSWING_HALF, x)
#define SD10G_LANE_LANE_37_CFG_TXSWING_HALF_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_37_CFG_TXSWING_HALF, x)

#define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0   GENMASK(5, 4)
#define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0, x)
#define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0, x)

/*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_39 */
#define SD10G_LANE_LANE_39(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 228, 0, 1, 4)

#define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0      GENMASK(2, 0)
#define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0, x)
#define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0, x)

#define SD10G_LANE_LANE_39_CFG_RX_SSC_LH         BIT(4)
#define SD10G_LANE_LANE_39_CFG_RX_SSC_LH_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_39_CFG_RX_SSC_LH, x)
#define SD10G_LANE_LANE_39_CFG_RX_SSC_LH_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_39_CFG_RX_SSC_LH, x)

/*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_3A */
#define SD10G_LANE_LANE_3A(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 232, 0, 1, 4)

#define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0        GENMASK(3, 0)
#define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0, x)
#define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0, x)

#define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0        GENMASK(7, 4)
#define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0, x)
#define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0, x)

/*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_3C */
#define SD10G_LANE_LANE_3C(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 240, 0, 1, 4)

#define SD10G_LANE_LANE_3C_CFG_DIS_ACC           BIT(0)
#define SD10G_LANE_LANE_3C_CFG_DIS_ACC_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_3C_CFG_DIS_ACC, x)
#define SD10G_LANE_LANE_3C_CFG_DIS_ACC_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_3C_CFG_DIS_ACC, x)

#define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER      BIT(1)
#define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER, x)
#define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER, x)

/*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_40 */
#define SD10G_LANE_LANE_40(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 256, 0, 1, 4)

#define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0  GENMASK(7, 0)
#define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0, x)
#define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0, x)

/*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_41 */
#define SD10G_LANE_LANE_41(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 260, 0, 1, 4)

#define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8 GENMASK(7, 0)
#define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8, x)
#define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8, x)

/*      SD10G_LANE_TARGET:LANE_GRP_0:LANE_42 */
#define SD10G_LANE_LANE_42(t)     __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 264, 0, 1, 4)

#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0   GENMASK(2, 0)
#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0, x)
#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0, x)

#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0   GENMASK(6, 4)
#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0, x)
#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0, x)

/*      SD10G_LANE_TARGET:LANE_GRP_1:LANE_48 */
#define SD10G_LANE_LANE_48(t)     __REG(TARGET_SD10G_LANE, t, 12, 288, 0, 1, 40, 0, 0, 1, 4)

#define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0      GENMASK(3, 0)
#define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0, x)
#define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0, x)

#define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL      BIT(4)
#define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL, x)
#define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL, x)

#define SD10G_LANE_LANE_48_CFG_CLK_ENQ           BIT(5)
#define SD10G_LANE_LANE_48_CFG_CLK_ENQ_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_48_CFG_CLK_ENQ, x)
#define SD10G_LANE_LANE_48_CFG_CLK_ENQ_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_48_CFG_CLK_ENQ, x)

/*      SD10G_LANE_TARGET:LANE_GRP_1:LANE_50 */
#define SD10G_LANE_LANE_50(t)     __REG(TARGET_SD10G_LANE, t, 12, 288, 0, 1, 40, 32, 0, 1, 4)

#define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0   GENMASK(1, 0)
#define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0, x)
#define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0, x)

#define SD10G_LANE_LANE_50_CFG_SSC_RESETB        BIT(4)
#define SD10G_LANE_LANE_50_CFG_SSC_RESETB_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_50_CFG_SSC_RESETB, x)
#define SD10G_LANE_LANE_50_CFG_SSC_RESETB_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_50_CFG_SSC_RESETB, x)

#define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL   BIT(5)
#define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL, x)
#define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL, x)

#define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL      BIT(6)
#define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL, x)
#define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL, x)

#define SD10G_LANE_LANE_50_CFG_JT_EN             BIT(7)
#define SD10G_LANE_LANE_50_CFG_JT_EN_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_50_CFG_JT_EN, x)
#define SD10G_LANE_LANE_50_CFG_JT_EN_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_50_CFG_JT_EN, x)

/*      SD10G_LANE_TARGET:LANE_GRP_2:LANE_52 */
#define SD10G_LANE_LANE_52(t)     __REG(TARGET_SD10G_LANE, t, 12, 328, 0, 1, 24, 0, 0, 1, 4)

#define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0 GENMASK(5, 0)
#define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0, x)
#define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0, x)

/*      SD10G_LANE_TARGET:LANE_GRP_4:LANE_83 */
#define SD10G_LANE_LANE_83(t)     __REG(TARGET_SD10G_LANE, t, 12, 464, 0, 1, 112, 60, 0, 1, 4)

#define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE      BIT(0)
#define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_83_R_TX_BIT_REVERSE, x)
#define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_83_R_TX_BIT_REVERSE, x)

#define SD10G_LANE_LANE_83_R_TX_POL_INV          BIT(1)
#define SD10G_LANE_LANE_83_R_TX_POL_INV_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_83_R_TX_POL_INV, x)
#define SD10G_LANE_LANE_83_R_TX_POL_INV_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_83_R_TX_POL_INV, x)

#define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE      BIT(2)
#define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_83_R_RX_BIT_REVERSE, x)
#define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_83_R_RX_BIT_REVERSE, x)

#define SD10G_LANE_LANE_83_R_RX_POL_INV          BIT(3)
#define SD10G_LANE_LANE_83_R_RX_POL_INV_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_83_R_RX_POL_INV, x)
#define SD10G_LANE_LANE_83_R_RX_POL_INV_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_83_R_RX_POL_INV, x)

#define SD10G_LANE_LANE_83_R_DFE_RSTN            BIT(4)
#define SD10G_LANE_LANE_83_R_DFE_RSTN_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_83_R_DFE_RSTN, x)
#define SD10G_LANE_LANE_83_R_DFE_RSTN_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_83_R_DFE_RSTN, x)

#define SD10G_LANE_LANE_83_R_CDR_RSTN            BIT(5)
#define SD10G_LANE_LANE_83_R_CDR_RSTN_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_83_R_CDR_RSTN, x)
#define SD10G_LANE_LANE_83_R_CDR_RSTN_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_83_R_CDR_RSTN, x)

#define SD10G_LANE_LANE_83_R_CTLE_RSTN           BIT(6)
#define SD10G_LANE_LANE_83_R_CTLE_RSTN_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_83_R_CTLE_RSTN, x)
#define SD10G_LANE_LANE_83_R_CTLE_RSTN_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_83_R_CTLE_RSTN, x)

/*      SD10G_LANE_TARGET:LANE_GRP_5:LANE_93 */
#define SD10G_LANE_LANE_93(t)     __REG(TARGET_SD10G_LANE, t, 12, 576, 0, 1, 64, 12, 0, 1, 4)

#define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN    BIT(0)
#define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN, x)
#define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN, x)

#define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT BIT(1)
#define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT, x)
#define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT, x)

#define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE     BIT(2)
#define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE, x)
#define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE, x)

#define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL     BIT(3)
#define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL, x)
#define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL, x)

#define SD10G_LANE_LANE_93_R_REG_MANUAL          BIT(4)
#define SD10G_LANE_LANE_93_R_REG_MANUAL_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_93_R_REG_MANUAL, x)
#define SD10G_LANE_LANE_93_R_REG_MANUAL_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_93_R_REG_MANUAL, x)

#define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT   BIT(5)
#define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT, x)
#define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT, x)

#define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT    BIT(6)
#define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT, x)
#define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT, x)

#define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT BIT(7)
#define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT, x)
#define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT, x)

/*      SD10G_LANE_TARGET:LANE_GRP_5:LANE_94 */
#define SD10G_LANE_LANE_94(t)     __REG(TARGET_SD10G_LANE, t, 12, 576, 0, 1, 64, 16, 0, 1, 4)

#define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0      GENMASK(2, 0)
#define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0, x)
#define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0, x)

#define SD10G_LANE_LANE_94_R_ISCAN_REG           BIT(4)
#define SD10G_LANE_LANE_94_R_ISCAN_REG_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_94_R_ISCAN_REG, x)
#define SD10G_LANE_LANE_94_R_ISCAN_REG_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_94_R_ISCAN_REG, x)

#define SD10G_LANE_LANE_94_R_TXEQ_REG            BIT(5)
#define SD10G_LANE_LANE_94_R_TXEQ_REG_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_94_R_TXEQ_REG, x)
#define SD10G_LANE_LANE_94_R_TXEQ_REG_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_94_R_TXEQ_REG, x)

#define SD10G_LANE_LANE_94_R_MISC_REG            BIT(6)
#define SD10G_LANE_LANE_94_R_MISC_REG_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_94_R_MISC_REG, x)
#define SD10G_LANE_LANE_94_R_MISC_REG_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_94_R_MISC_REG, x)

#define SD10G_LANE_LANE_94_R_SWING_REG           BIT(7)
#define SD10G_LANE_LANE_94_R_SWING_REG_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_94_R_SWING_REG, x)
#define SD10G_LANE_LANE_94_R_SWING_REG_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_94_R_SWING_REG, x)

/*      SD10G_LANE_TARGET:LANE_GRP_5:LANE_9E */
#define SD10G_LANE_LANE_9E(t)     __REG(TARGET_SD10G_LANE, t, 12, 576, 0, 1, 64, 56, 0, 1, 4)

#define SD10G_LANE_LANE_9E_R_RXEQ_REG            BIT(0)
#define SD10G_LANE_LANE_9E_R_RXEQ_REG_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_9E_R_RXEQ_REG, x)
#define SD10G_LANE_LANE_9E_R_RXEQ_REG_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_9E_R_RXEQ_REG, x)

#define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN BIT(1)
#define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN, x)
#define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN, x)

#define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN    BIT(2)
#define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN, x)
#define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN, x)

/*      SD10G_LANE_TARGET:LANE_GRP_6:LANE_A1 */
#define SD10G_LANE_LANE_A1(t)     __REG(TARGET_SD10G_LANE, t, 12, 640, 0, 1, 128, 4, 0, 1, 4)

#define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0 GENMASK(1, 0)
#define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0, x)
#define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0, x)

#define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT        BIT(4)
#define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_A1_R_SSC_FROM_HWT, x)
#define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_A1_R_SSC_FROM_HWT, x)

#define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT        BIT(5)
#define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_A1_R_CDR_FROM_HWT, x)
#define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_A1_R_CDR_FROM_HWT, x)

#define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT BIT(6)
#define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT, x)
#define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT, x)

#define SD10G_LANE_LANE_A1_R_PCLK_GATING         BIT(7)
#define SD10G_LANE_LANE_A1_R_PCLK_GATING_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_A1_R_PCLK_GATING, x)
#define SD10G_LANE_LANE_A1_R_PCLK_GATING_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_A1_R_PCLK_GATING, x)

/*      SD10G_LANE_TARGET:LANE_GRP_6:LANE_A2 */
#define SD10G_LANE_LANE_A2(t)     __REG(TARGET_SD10G_LANE, t, 12, 640, 0, 1, 128, 8, 0, 1, 4)

#define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0 GENMASK(4, 0)
#define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0, x)
#define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0, x)

/*      SD10G_LANE_TARGET:LANE_GRP_8:LANE_DF */
#define SD10G_LANE_LANE_DF(t)     __REG(TARGET_SD10G_LANE, t, 12, 832, 0, 1, 84, 60, 0, 1, 4)

#define SD10G_LANE_LANE_DF_LOL_UDL               BIT(0)
#define SD10G_LANE_LANE_DF_LOL_UDL_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_DF_LOL_UDL, x)
#define SD10G_LANE_LANE_DF_LOL_UDL_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_DF_LOL_UDL, x)

#define SD10G_LANE_LANE_DF_LOL                   BIT(1)
#define SD10G_LANE_LANE_DF_LOL_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_DF_LOL, x)
#define SD10G_LANE_LANE_DF_LOL_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_DF_LOL, x)

#define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED BIT(2)
#define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x)
#define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x)

#define SD10G_LANE_LANE_DF_SQUELCH               BIT(3)
#define SD10G_LANE_LANE_DF_SQUELCH_SET(x)\
	FIELD_PREP(SD10G_LANE_LANE_DF_SQUELCH, x)
#define SD10G_LANE_LANE_DF_SQUELCH_GET(x)\
	FIELD_GET(SD10G_LANE_LANE_DF_SQUELCH, x)

/*      SD25G_TARGET:CMU_GRP_0:CMU_09 */
#define SD25G_LANE_CMU_09(t)      __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 36, 0, 1, 4)

#define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN      BIT(0)
#define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN, x)
#define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN, x)

#define SD25G_LANE_CMU_09_CFG_EN_DUMMY           BIT(1)
#define SD25G_LANE_CMU_09_CFG_EN_DUMMY_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_09_CFG_EN_DUMMY, x)
#define SD25G_LANE_CMU_09_CFG_EN_DUMMY_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_09_CFG_EN_DUMMY, x)

#define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET        BIT(2)
#define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_09_CFG_PLL_LOS_SET, x)
#define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_09_CFG_PLL_LOS_SET, x)

#define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD      BIT(3)
#define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD, x)
#define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD, x)

#define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0     GENMASK(5, 4)
#define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0, x)
#define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0, x)

/*      SD25G_TARGET:CMU_GRP_0:CMU_0B */
#define SD25G_LANE_CMU_0B(t)      __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 44, 0, 1, 4)

#define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT      BIT(0)
#define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT, x)
#define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT, x)

#define SD25G_LANE_CMU_0B_CFG_DISLOL             BIT(1)
#define SD25G_LANE_CMU_0B_CFG_DISLOL_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_0B_CFG_DISLOL, x)
#define SD25G_LANE_CMU_0B_CFG_DISLOL_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_0B_CFG_DISLOL, x)

#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN BIT(2)
#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN, x)
#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN, x)

#define SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN     BIT(3)
#define SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN, x)
#define SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN, x)

#define SD25G_LANE_CMU_0B_CFG_VFILT2PAD          BIT(4)
#define SD25G_LANE_CMU_0B_CFG_VFILT2PAD_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_0B_CFG_VFILT2PAD, x)
#define SD25G_LANE_CMU_0B_CFG_VFILT2PAD_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_0B_CFG_VFILT2PAD, x)

#define SD25G_LANE_CMU_0B_CFG_DISLOS             BIT(5)
#define SD25G_LANE_CMU_0B_CFG_DISLOS_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_0B_CFG_DISLOS, x)
#define SD25G_LANE_CMU_0B_CFG_DISLOS_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_0B_CFG_DISLOS, x)

#define SD25G_LANE_CMU_0B_CFG_DCLOL              BIT(6)
#define SD25G_LANE_CMU_0B_CFG_DCLOL_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_0B_CFG_DCLOL, x)
#define SD25G_LANE_CMU_0B_CFG_DCLOL_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_0B_CFG_DCLOL, x)

#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN    BIT(7)
#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN, x)
#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN, x)

/*      SD25G_TARGET:CMU_GRP_0:CMU_0C */
#define SD25G_LANE_CMU_0C(t)      __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 48, 0, 1, 4)

#define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET        BIT(0)
#define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET, x)
#define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET, x)

#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN        BIT(1)
#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN, x)
#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN, x)

#define SD25G_LANE_CMU_0C_CFG_VCO_PD             BIT(2)
#define SD25G_LANE_CMU_0C_CFG_VCO_PD_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_0C_CFG_VCO_PD, x)
#define SD25G_LANE_CMU_0C_CFG_VCO_PD_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_0C_CFG_VCO_PD, x)

#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP        BIT(3)
#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP, x)
#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP, x)

#define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0   GENMASK(5, 4)
#define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0, x)
#define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0, x)

/*      SD25G_TARGET:CMU_GRP_0:CMU_0D */
#define SD25G_LANE_CMU_0D(t)      __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 52, 0, 1, 4)

#define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD         BIT(0)
#define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_0D_CFG_CK_TREE_PD, x)
#define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_0D_CFG_CK_TREE_PD, x)

#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN        BIT(1)
#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN, x)
#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN, x)

#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP        BIT(2)
#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP, x)
#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP, x)

#define SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP        BIT(3)
#define SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP, x)
#define SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP, x)

#define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0     GENMASK(5, 4)
#define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0, x)
#define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0, x)

/*      SD25G_TARGET:CMU_GRP_0:CMU_0E */
#define SD25G_LANE_CMU_0E(t)      __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 56, 0, 1, 4)

#define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0        GENMASK(3, 0)
#define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0, x)
#define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0, x)

#define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD   BIT(4)
#define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD, x)
#define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD, x)

/*      SD25G_TARGET:CMU_GRP_0:CMU_13 */
#define SD25G_LANE_CMU_13(t)      __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 76, 0, 1, 4)

#define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0    GENMASK(3, 0)
#define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0, x)
#define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0, x)

#define SD25G_LANE_CMU_13_CFG_JT_EN              BIT(4)
#define SD25G_LANE_CMU_13_CFG_JT_EN_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_13_CFG_JT_EN, x)
#define SD25G_LANE_CMU_13_CFG_JT_EN_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_13_CFG_JT_EN, x)

/*      SD25G_TARGET:CMU_GRP_0:CMU_18 */
#define SD25G_LANE_CMU_18(t)      __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 96, 0, 1, 4)

#define SD25G_LANE_CMU_18_R_PLL_RSTN             BIT(0)
#define SD25G_LANE_CMU_18_R_PLL_RSTN_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_18_R_PLL_RSTN, x)
#define SD25G_LANE_CMU_18_R_PLL_RSTN_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_18_R_PLL_RSTN, x)

#define SD25G_LANE_CMU_18_R_PLL_LOL_SET          BIT(1)
#define SD25G_LANE_CMU_18_R_PLL_LOL_SET_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_18_R_PLL_LOL_SET, x)
#define SD25G_LANE_CMU_18_R_PLL_LOL_SET_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_18_R_PLL_LOL_SET, x)

#define SD25G_LANE_CMU_18_R_PLL_LOS_SET          BIT(2)
#define SD25G_LANE_CMU_18_R_PLL_LOS_SET_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_18_R_PLL_LOS_SET, x)
#define SD25G_LANE_CMU_18_R_PLL_LOS_SET_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_18_R_PLL_LOS_SET, x)

#define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0       GENMASK(5, 4)
#define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0, x)
#define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0, x)

/*      SD25G_TARGET:CMU_GRP_0:CMU_19 */
#define SD25G_LANE_CMU_19(t)      __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 100, 0, 1, 4)

#define SD25G_LANE_CMU_19_R_CK_RESETB            BIT(0)
#define SD25G_LANE_CMU_19_R_CK_RESETB_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_19_R_CK_RESETB, x)
#define SD25G_LANE_CMU_19_R_CK_RESETB_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_19_R_CK_RESETB, x)

#define SD25G_LANE_CMU_19_R_PLL_DLOL_EN          BIT(1)
#define SD25G_LANE_CMU_19_R_PLL_DLOL_EN_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_19_R_PLL_DLOL_EN, x)
#define SD25G_LANE_CMU_19_R_PLL_DLOL_EN_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_19_R_PLL_DLOL_EN, x)

/*      SD25G_TARGET:CMU_GRP_0:CMU_1A */
#define SD25G_LANE_CMU_1A(t)      __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 104, 0, 1, 4)

#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0       GENMASK(2, 0)
#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0, x)
#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0, x)

#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT  BIT(4)
#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT, x)
#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT, x)

#define SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE       BIT(5)
#define SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE, x)
#define SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE, x)

#define SD25G_LANE_CMU_1A_R_REG_MANUAL           BIT(6)
#define SD25G_LANE_CMU_1A_R_REG_MANUAL_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_1A_R_REG_MANUAL, x)
#define SD25G_LANE_CMU_1A_R_REG_MANUAL_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_1A_R_REG_MANUAL, x)

/*      SD25G_TARGET:CMU_GRP_1:CMU_2A */
#define SD25G_LANE_CMU_2A(t)      __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 36, 0, 1, 4)

#define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0          GENMASK(1, 0)
#define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_2A_R_DBG_SEL_1_0, x)
#define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_2A_R_DBG_SEL_1_0, x)

#define SD25G_LANE_CMU_2A_R_DBG_LINK_LANE        BIT(4)
#define SD25G_LANE_CMU_2A_R_DBG_LINK_LANE_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_2A_R_DBG_LINK_LANE, x)
#define SD25G_LANE_CMU_2A_R_DBG_LINK_LANE_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_2A_R_DBG_LINK_LANE, x)

#define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS       BIT(5)
#define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS, x)
#define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS, x)

/*      SD25G_TARGET:CMU_GRP_1:CMU_30 */
#define SD25G_LANE_CMU_30(t)      __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 60, 0, 1, 4)

#define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0 GENMASK(2, 0)
#define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0, x)
#define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0, x)

#define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0 GENMASK(6, 4)
#define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0, x)
#define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0, x)

/*      SD25G_TARGET:CMU_GRP_1:CMU_31 */
#define SD25G_LANE_CMU_31(t)      __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 64, 0, 1, 4)

#define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0 GENMASK(7, 0)
#define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0, x)
#define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0, x)

/*      SD25G_TARGET:CMU_GRP_2:CMU_40 */
#define SD25G_LANE_CMU_40(t)      __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 0, 0, 1, 4)

#define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL     BIT(0)
#define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL, x)
#define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL, x)

#define SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD      BIT(1)
#define SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD, x)
#define SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD, x)

#define SD25G_LANE_CMU_40_L0_CFG_PD_CLK          BIT(2)
#define SD25G_LANE_CMU_40_L0_CFG_PD_CLK_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_PD_CLK, x)
#define SD25G_LANE_CMU_40_L0_CFG_PD_CLK_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_PD_CLK, x)

#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN        BIT(3)
#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN, x)
#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN, x)

#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN    BIT(4)
#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN, x)
#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN, x)

#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST       BIT(5)
#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST, x)
#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST, x)

/*      SD25G_TARGET:CMU_GRP_2:CMU_45 */
#define SD25G_LANE_CMU_45(t)      __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 20, 0, 1, 4)

#define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0  GENMASK(7, 0)
#define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0, x)
#define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0, x)

/*      SD25G_TARGET:CMU_GRP_2:CMU_46 */
#define SD25G_LANE_CMU_46(t)      __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 24, 0, 1, 4)

#define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8 GENMASK(7, 0)
#define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8, x)
#define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8, x)

/*      SD25G_TARGET:CMU_GRP_3:CMU_C0 */
#define SD25G_LANE_CMU_C0(t)      __REG(TARGET_SD25G_LANE, t, 8, 768, 0, 1, 252, 0, 0, 1, 4)

#define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0     GENMASK(3, 0)
#define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0, x)
#define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0, x)

#define SD25G_LANE_CMU_C0_PLL_LOL_UDL            BIT(4)
#define SD25G_LANE_CMU_C0_PLL_LOL_UDL_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_C0_PLL_LOL_UDL, x)
#define SD25G_LANE_CMU_C0_PLL_LOL_UDL_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_C0_PLL_LOL_UDL, x)

/*      SD25G_TARGET:CMU_GRP_4:CMU_FF */
#define SD25G_LANE_CMU_FF(t)      __REG(TARGET_SD25G_LANE, t, 8, 1020, 0, 1, 4, 0, 0, 1, 4)

#define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX   GENMASK(7, 0)
#define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(x)\
	FIELD_PREP(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX, x)
#define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_GET(x)\
	FIELD_GET(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_00 */
#define SD25G_LANE_LANE_00(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 0, 0, 1, 4)

#define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0 GENMASK(3, 0)
#define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0, x)
#define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0, x)

#define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0 GENMASK(5, 4)
#define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0, x)
#define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_01 */
#define SD25G_LANE_LANE_01(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 4, 0, 1, 4)

#define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0 GENMASK(2, 0)
#define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0, x)
#define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0, x)

#define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0  GENMASK(5, 4)
#define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0, x)
#define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_03 */
#define SD25G_LANE_LANE_03(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 12, 0, 1, 4)

#define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0    GENMASK(4, 0)
#define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0, x)
#define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_04 */
#define SD25G_LANE_LANE_04(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 16, 0, 1, 4)

#define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN    BIT(0)
#define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN, x)
#define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN, x)

#define SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN    BIT(1)
#define SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN, x)
#define SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN, x)

#define SD25G_LANE_LANE_04_LN_CFG_PD_CML         BIT(2)
#define SD25G_LANE_LANE_04_LN_CFG_PD_CML_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_PD_CML, x)
#define SD25G_LANE_LANE_04_LN_CFG_PD_CML_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_PD_CML, x)

#define SD25G_LANE_LANE_04_LN_CFG_PD_CLK         BIT(3)
#define SD25G_LANE_LANE_04_LN_CFG_PD_CLK_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_PD_CLK, x)
#define SD25G_LANE_LANE_04_LN_CFG_PD_CLK_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_PD_CLK, x)

#define SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER      BIT(4)
#define SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER, x)
#define SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER, x)

#define SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN       BIT(5)
#define SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN, x)
#define SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_05 */
#define SD25G_LANE_LANE_05(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 20, 0, 1, 4)

#define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0   GENMASK(3, 0)
#define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0, x)
#define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0, x)

#define SD25G_LANE_LANE_05_LN_CFG_BW_1_0         GENMASK(5, 4)
#define SD25G_LANE_LANE_05_LN_CFG_BW_1_0_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_05_LN_CFG_BW_1_0, x)
#define SD25G_LANE_LANE_05_LN_CFG_BW_1_0_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_05_LN_CFG_BW_1_0, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_06 */
#define SD25G_LANE_LANE_06(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 24, 0, 1, 4)

#define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN        BIT(0)
#define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_06_LN_CFG_EN_MAIN, x)
#define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_06_LN_CFG_EN_MAIN, x)

#define SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0    GENMASK(7, 4)
#define SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0, x)
#define SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_07 */
#define SD25G_LANE_LANE_07(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 28, 0, 1, 4)

#define SD25G_LANE_LANE_07_LN_CFG_EN_ADV         BIT(0)
#define SD25G_LANE_LANE_07_LN_CFG_EN_ADV_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_07_LN_CFG_EN_ADV, x)
#define SD25G_LANE_LANE_07_LN_CFG_EN_ADV_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_07_LN_CFG_EN_ADV, x)

#define SD25G_LANE_LANE_07_LN_CFG_EN_DLY2        BIT(1)
#define SD25G_LANE_LANE_07_LN_CFG_EN_DLY2_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_07_LN_CFG_EN_DLY2, x)
#define SD25G_LANE_LANE_07_LN_CFG_EN_DLY2_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_07_LN_CFG_EN_DLY2, x)

#define SD25G_LANE_LANE_07_LN_CFG_EN_DLY         BIT(2)
#define SD25G_LANE_LANE_07_LN_CFG_EN_DLY_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_07_LN_CFG_EN_DLY, x)
#define SD25G_LANE_LANE_07_LN_CFG_EN_DLY_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_07_LN_CFG_EN_DLY, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_09 */
#define SD25G_LANE_LANE_09(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 36, 0, 1, 4)

#define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0 GENMASK(3, 0)
#define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0, x)
#define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_0A */
#define SD25G_LANE_LANE_0A(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 40, 0, 1, 4)

#define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0 GENMASK(5, 0)
#define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0, x)
#define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_0B */
#define SD25G_LANE_LANE_0B(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 44, 0, 1, 4)

#define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN   BIT(0)
#define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN, x)
#define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN, x)

#define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST      BIT(1)
#define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST, x)
#define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST, x)

#define SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0   GENMASK(5, 4)
#define SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0, x)
#define SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_0C */
#define SD25G_LANE_LANE_0C(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 48, 0, 1, 4)

#define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0 GENMASK(2, 0)
#define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
#define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0, x)

#define SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN       BIT(4)
#define SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN, x)
#define SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN, x)

#define SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD      BIT(5)
#define SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD, x)
#define SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_0D */
#define SD25G_LANE_LANE_0D(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 52, 0, 1, 4)

#define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0     GENMASK(2, 0)
#define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0, x)
#define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0, x)

#define SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8    BIT(4)
#define SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8, x)
#define SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8, x)

#define SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN      BIT(5)
#define SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN, x)
#define SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN, x)

#define SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD        BIT(6)
#define SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD, x)
#define SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD, x)

#define SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN       BIT(7)
#define SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN, x)
#define SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_0E */
#define SD25G_LANE_LANE_0E(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 56, 0, 1, 4)

#define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN       BIT(0)
#define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN, x)
#define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN, x)

#define SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD    BIT(1)
#define SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD, x)
#define SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD, x)

#define SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG      BIT(2)
#define SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG, x)
#define SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG, x)

#define SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0   GENMASK(6, 4)
#define SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0, x)
#define SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_0F */
#define SD25G_LANE_LANE_0F(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 60, 0, 1, 4)

#define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1  GENMASK(4, 0)
#define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1, x)
#define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_18 */
#define SD25G_LANE_LANE_18(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 96, 0, 1, 4)

#define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN       BIT(0)
#define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN, x)
#define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN, x)

#define SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT       BIT(1)
#define SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT, x)
#define SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT, x)

#define SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN    BIT(2)
#define SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN, x)
#define SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN, x)

#define SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD      BIT(3)
#define SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD, x)
#define SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD, x)

#define SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0  GENMASK(6, 4)
#define SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0, x)
#define SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_19 */
#define SD25G_LANE_LANE_19(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 100, 0, 1, 4)

#define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD        BIT(0)
#define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_DCDR_PD, x)
#define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_DCDR_PD, x)

#define SD25G_LANE_LANE_19_LN_CFG_ECDR_PD        BIT(1)
#define SD25G_LANE_LANE_19_LN_CFG_ECDR_PD_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_ECDR_PD, x)
#define SD25G_LANE_LANE_19_LN_CFG_ECDR_PD_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_ECDR_PD, x)

#define SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL      BIT(2)
#define SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL, x)
#define SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL, x)

#define SD25G_LANE_LANE_19_LN_CFG_TXLB_EN        BIT(3)
#define SD25G_LANE_LANE_19_LN_CFG_TXLB_EN_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_TXLB_EN, x)
#define SD25G_LANE_LANE_19_LN_CFG_TXLB_EN_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_TXLB_EN, x)

#define SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU      BIT(4)
#define SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU, x)
#define SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU, x)

#define SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP     BIT(5)
#define SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP, x)
#define SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP, x)

#define SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET     BIT(6)
#define SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET, x)
#define SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET, x)

#define SD25G_LANE_LANE_19_LN_CFG_PD_CTLE        BIT(7)
#define SD25G_LANE_LANE_19_LN_CFG_PD_CTLE_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_PD_CTLE, x)
#define SD25G_LANE_LANE_19_LN_CFG_PD_CTLE_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_PD_CTLE, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_1A */
#define SD25G_LANE_LANE_1A(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 104, 0, 1, 4)

#define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN     BIT(0)
#define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN, x)
#define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN, x)

#define SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0     GENMASK(6, 4)
#define SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0, x)
#define SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_1B */
#define SD25G_LANE_LANE_1B(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 108, 0, 1, 4)

#define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0      GENMASK(7, 0)
#define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0, x)
#define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_1C */
#define SD25G_LANE_LANE_1C(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 112, 0, 1, 4)

#define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN       BIT(0)
#define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN, x)
#define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN, x)

#define SD25G_LANE_LANE_1C_LN_CFG_DFE_PD         BIT(1)
#define SD25G_LANE_LANE_1C_LN_CFG_DFE_PD_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_DFE_PD, x)
#define SD25G_LANE_LANE_1C_LN_CFG_DFE_PD_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_DFE_PD, x)

#define SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD      BIT(2)
#define SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD, x)
#define SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD, x)

#define SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0  GENMASK(7, 4)
#define SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0, x)
#define SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_1D */
#define SD25G_LANE_LANE_1D(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 116, 0, 1, 4)

#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR  BIT(0)
#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR, x)
#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR, x)

#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD     BIT(1)
#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD, x)
#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD, x)

#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN     BIT(2)
#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN, x)
#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN, x)

#define SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP   BIT(3)
#define SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP, x)
#define SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP, x)

#define SD25G_LANE_LANE_1D_LN_CFG_PHID_1T        BIT(4)
#define SD25G_LANE_LANE_1D_LN_CFG_PHID_1T_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PHID_1T, x)
#define SD25G_LANE_LANE_1D_LN_CFG_PHID_1T_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PHID_1T, x)

#define SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN      BIT(5)
#define SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN, x)
#define SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN, x)

#define SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR     BIT(6)
#define SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR, x)
#define SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR, x)

#define SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD        BIT(7)
#define SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD, x)
#define SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_1E */
#define SD25G_LANE_LANE_1E(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 120, 0, 1, 4)

#define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0   GENMASK(1, 0)
#define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0, x)
#define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0, x)

#define SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN        BIT(4)
#define SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN, x)
#define SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN, x)

#define SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN   BIT(5)
#define SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN, x)
#define SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN, x)

#define SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR   BIT(6)
#define SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR, x)
#define SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR, x)

#define SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD     BIT(7)
#define SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD, x)
#define SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_21 */
#define SD25G_LANE_LANE_21(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 132, 0, 1, 4)

#define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0 GENMASK(4, 0)
#define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0, x)
#define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_22 */
#define SD25G_LANE_LANE_22(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 136, 0, 1, 4)

#define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0  GENMASK(3, 0)
#define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0, x)
#define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_25 */
#define SD25G_LANE_LANE_25(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 148, 0, 1, 4)

#define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0 GENMASK(6, 0)
#define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0, x)
#define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_26 */
#define SD25G_LANE_LANE_26(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 152, 0, 1, 4)

#define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0 GENMASK(6, 0)
#define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0, x)
#define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_28 */
#define SD25G_LANE_LANE_28(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 160, 0, 1, 4)

#define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN  BIT(0)
#define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN, x)
#define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN, x)

#define SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH      BIT(1)
#define SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH, x)
#define SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH, x)

#define SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL   BIT(2)
#define SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL, x)
#define SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL, x)

#define SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0 GENMASK(6, 4)
#define SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0, x)
#define SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_2B */
#define SD25G_LANE_LANE_2B(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 172, 0, 1, 4)

#define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0      GENMASK(3, 0)
#define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0, x)
#define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0, x)

#define SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR BIT(4)
#define SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR, x)
#define SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR, x)

#define SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU    BIT(5)
#define SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU, x)
#define SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_2C */
#define SD25G_LANE_LANE_2C(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 176, 0, 1, 4)

#define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0 GENMASK(2, 0)
#define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0, x)
#define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0, x)

#define SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER   BIT(4)
#define SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER, x)
#define SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_2D */
#define SD25G_LANE_LANE_2D(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 180, 0, 1, 4)

#define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0   GENMASK(2, 0)
#define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0, x)
#define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0, x)

#define SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0 GENMASK(6, 4)
#define SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0, x)
#define SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_2E */
#define SD25G_LANE_LANE_2E(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 184, 0, 1, 4)

#define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN  BIT(0)
#define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN, x)
#define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN, x)

#define SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ         BIT(1)
#define SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ, x)
#define SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ, x)

#define SD25G_LANE_LANE_2E_LN_CFG_PD_SQ          BIT(2)
#define SD25G_LANE_LANE_2E_LN_CFG_PD_SQ_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_PD_SQ, x)
#define SD25G_LANE_LANE_2E_LN_CFG_PD_SQ_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_PD_SQ, x)

#define SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS       BIT(3)
#define SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS, x)
#define SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS, x)

#define SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC     BIT(4)
#define SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC, x)
#define SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC, x)

#define SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG    BIT(5)
#define SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG, x)
#define SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG, x)

#define SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN        BIT(6)
#define SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN, x)
#define SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN, x)

#define SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN      BIT(7)
#define SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN, x)
#define SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_40 */
#define SD25G_LANE_LANE_40(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 256, 0, 1, 4)

#define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE   BIT(0)
#define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE, x)
#define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE, x)

#define SD25G_LANE_LANE_40_LN_R_TX_POL_INV       BIT(1)
#define SD25G_LANE_LANE_40_LN_R_TX_POL_INV_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_40_LN_R_TX_POL_INV, x)
#define SD25G_LANE_LANE_40_LN_R_TX_POL_INV_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_40_LN_R_TX_POL_INV, x)

#define SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE   BIT(2)
#define SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE, x)
#define SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE, x)

#define SD25G_LANE_LANE_40_LN_R_RX_POL_INV       BIT(3)
#define SD25G_LANE_LANE_40_LN_R_RX_POL_INV_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_40_LN_R_RX_POL_INV, x)
#define SD25G_LANE_LANE_40_LN_R_RX_POL_INV_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_40_LN_R_RX_POL_INV, x)

#define SD25G_LANE_LANE_40_LN_R_CDR_RSTN         BIT(4)
#define SD25G_LANE_LANE_40_LN_R_CDR_RSTN_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_40_LN_R_CDR_RSTN, x)
#define SD25G_LANE_LANE_40_LN_R_CDR_RSTN_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_40_LN_R_CDR_RSTN, x)

#define SD25G_LANE_LANE_40_LN_R_DFE_RSTN         BIT(5)
#define SD25G_LANE_LANE_40_LN_R_DFE_RSTN_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_40_LN_R_DFE_RSTN, x)
#define SD25G_LANE_LANE_40_LN_R_DFE_RSTN_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_40_LN_R_DFE_RSTN, x)

#define SD25G_LANE_LANE_40_LN_R_CTLE_RSTN        BIT(6)
#define SD25G_LANE_LANE_40_LN_R_CTLE_RSTN_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_40_LN_R_CTLE_RSTN, x)
#define SD25G_LANE_LANE_40_LN_R_CTLE_RSTN_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_40_LN_R_CTLE_RSTN, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_42 */
#define SD25G_LANE_LANE_42(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 264, 0, 1, 4)

#define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0 GENMASK(7, 0)
#define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0, x)
#define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_43 */
#define SD25G_LANE_LANE_43(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 268, 0, 1, 4)

#define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8 GENMASK(7, 0)
#define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8, x)
#define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_44 */
#define SD25G_LANE_LANE_44(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 272, 0, 1, 4)

#define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0 GENMASK(7, 0)
#define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0, x)
#define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0, x)

/*      SD25G_TARGET:LANE_GRP_0:LANE_45 */
#define SD25G_LANE_LANE_45(t)     __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 276, 0, 1, 4)

#define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8 GENMASK(7, 0)
#define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8, x)
#define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8, x)

/*      SD25G_TARGET:LANE_GRP_1:LANE_DE */
#define SD25G_LANE_LANE_DE(t)     __REG(TARGET_SD25G_LANE, t, 8, 1792, 0, 1, 128, 120, 0, 1, 4)

#define SD25G_LANE_LANE_DE_LN_LOL_UDL            BIT(0)
#define SD25G_LANE_LANE_DE_LN_LOL_UDL_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_DE_LN_LOL_UDL, x)
#define SD25G_LANE_LANE_DE_LN_LOL_UDL_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_DE_LN_LOL_UDL, x)

#define SD25G_LANE_LANE_DE_LN_LOL                BIT(1)
#define SD25G_LANE_LANE_DE_LN_LOL_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_DE_LN_LOL, x)
#define SD25G_LANE_LANE_DE_LN_LOL_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_DE_LN_LOL, x)

#define SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED BIT(2)
#define SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED, x)
#define SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED, x)

#define SD25G_LANE_LANE_DE_LN_PMA_RXEI           BIT(3)
#define SD25G_LANE_LANE_DE_LN_PMA_RXEI_SET(x)\
	FIELD_PREP(SD25G_LANE_LANE_DE_LN_PMA_RXEI, x)
#define SD25G_LANE_LANE_DE_LN_PMA_RXEI_GET(x)\
	FIELD_GET(SD25G_LANE_LANE_DE_LN_PMA_RXEI, x)

/*      SD10G_LANE_TARGET:LANE_GRP_8:LANE_DF */
#define SD6G_LANE_LANE_DF(t)      __REG(TARGET_SD6G_LANE, t, 13, 832, 0, 1, 84, 60, 0, 1, 4)

#define SD6G_LANE_LANE_DF_LOL_UDL                BIT(0)
#define SD6G_LANE_LANE_DF_LOL_UDL_SET(x)\
	FIELD_PREP(SD6G_LANE_LANE_DF_LOL_UDL, x)
#define SD6G_LANE_LANE_DF_LOL_UDL_GET(x)\
	FIELD_GET(SD6G_LANE_LANE_DF_LOL_UDL, x)

#define SD6G_LANE_LANE_DF_LOL                    BIT(1)
#define SD6G_LANE_LANE_DF_LOL_SET(x)\
	FIELD_PREP(SD6G_LANE_LANE_DF_LOL, x)
#define SD6G_LANE_LANE_DF_LOL_GET(x)\
	FIELD_GET(SD6G_LANE_LANE_DF_LOL, x)

#define SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED  BIT(2)
#define SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_SET(x)\
	FIELD_PREP(SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x)
#define SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_GET(x)\
	FIELD_GET(SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x)

#define SD6G_LANE_LANE_DF_SQUELCH                BIT(3)
#define SD6G_LANE_LANE_DF_SQUELCH_SET(x)\
	FIELD_PREP(SD6G_LANE_LANE_DF_SQUELCH, x)
#define SD6G_LANE_LANE_DF_SQUELCH_GET(x)\
	FIELD_GET(SD6G_LANE_LANE_DF_SQUELCH, x)

/*      SD10G_CMU_TARGET:CMU_GRP_0:CMU_00 */
#define SD_CMU_CMU_00(t)          __REG(TARGET_SD_CMU, t, 14, 0, 0, 1, 20, 0, 0, 1, 4)

#define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE      BIT(0)
#define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE_SET(x)\
	FIELD_PREP(SD_CMU_CMU_00_R_HWT_SIMULATION_MODE, x)
#define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE_GET(x)\
	FIELD_GET(SD_CMU_CMU_00_R_HWT_SIMULATION_MODE, x)

#define SD_CMU_CMU_00_CFG_PLL_LOL_SET            BIT(1)
#define SD_CMU_CMU_00_CFG_PLL_LOL_SET_SET(x)\
	FIELD_PREP(SD_CMU_CMU_00_CFG_PLL_LOL_SET, x)
#define SD_CMU_CMU_00_CFG_PLL_LOL_SET_GET(x)\
	FIELD_GET(SD_CMU_CMU_00_CFG_PLL_LOL_SET, x)

#define SD_CMU_CMU_00_CFG_PLL_LOS_SET            BIT(2)
#define SD_CMU_CMU_00_CFG_PLL_LOS_SET_SET(x)\
	FIELD_PREP(SD_CMU_CMU_00_CFG_PLL_LOS_SET, x)
#define SD_CMU_CMU_00_CFG_PLL_LOS_SET_GET(x)\
	FIELD_GET(SD_CMU_CMU_00_CFG_PLL_LOS_SET, x)

#define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0         GENMASK(5, 4)
#define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_SET(x)\
	FIELD_PREP(SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0, x)
#define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_GET(x)\
	FIELD_GET(SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0, x)

/*      SD10G_CMU_TARGET:CMU_GRP_1:CMU_05 */
#define SD_CMU_CMU_05(t)          __REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 0, 0, 1, 4)

#define SD_CMU_CMU_05_CFG_REFCK_TERM_EN          BIT(0)
#define SD_CMU_CMU_05_CFG_REFCK_TERM_EN_SET(x)\
	FIELD_PREP(SD_CMU_CMU_05_CFG_REFCK_TERM_EN, x)
#define SD_CMU_CMU_05_CFG_REFCK_TERM_EN_GET(x)\
	FIELD_GET(SD_CMU_CMU_05_CFG_REFCK_TERM_EN, x)

#define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0        GENMASK(5, 4)
#define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_SET(x)\
	FIELD_PREP(SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0, x)
#define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_GET(x)\
	FIELD_GET(SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0, x)

/*      SD10G_CMU_TARGET:CMU_GRP_1:CMU_06 */
#define SD_CMU_CMU_06(t) \
	__REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 4, 0, 1, 4)

#define SD_CMU_CMU_06_CFG_DISLOS                 BIT(0)
#define SD_CMU_CMU_06_CFG_DISLOS_SET(x)\
	FIELD_PREP(SD_CMU_CMU_06_CFG_DISLOS, x)
#define SD_CMU_CMU_06_CFG_DISLOS_GET(x)\
	FIELD_GET(SD_CMU_CMU_06_CFG_DISLOS, x)

#define SD_CMU_CMU_06_CFG_DISLOL                 BIT(1)
#define SD_CMU_CMU_06_CFG_DISLOL_SET(x)\
	FIELD_PREP(SD_CMU_CMU_06_CFG_DISLOL, x)
#define SD_CMU_CMU_06_CFG_DISLOL_GET(x)\
	FIELD_GET(SD_CMU_CMU_06_CFG_DISLOL, x)

#define SD_CMU_CMU_06_CFG_DCLOL                  BIT(2)
#define SD_CMU_CMU_06_CFG_DCLOL_SET(x)\
	FIELD_PREP(SD_CMU_CMU_06_CFG_DCLOL, x)
#define SD_CMU_CMU_06_CFG_DCLOL_GET(x)\
	FIELD_GET(SD_CMU_CMU_06_CFG_DCLOL, x)

#define SD_CMU_CMU_06_CFG_FORCE_RX_FILT          BIT(3)
#define SD_CMU_CMU_06_CFG_FORCE_RX_FILT_SET(x)\
	FIELD_PREP(SD_CMU_CMU_06_CFG_FORCE_RX_FILT, x)
#define SD_CMU_CMU_06_CFG_FORCE_RX_FILT_GET(x)\
	FIELD_GET(SD_CMU_CMU_06_CFG_FORCE_RX_FILT, x)

#define SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD          BIT(4)
#define SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD_SET(x)\
	FIELD_PREP(SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD, x)
#define SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD_GET(x)\
	FIELD_GET(SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD, x)

#define SD_CMU_CMU_06_CFG_VCO_PD                 BIT(5)
#define SD_CMU_CMU_06_CFG_VCO_PD_SET(x)\
	FIELD_PREP(SD_CMU_CMU_06_CFG_VCO_PD, x)
#define SD_CMU_CMU_06_CFG_VCO_PD_GET(x)\
	FIELD_GET(SD_CMU_CMU_06_CFG_VCO_PD, x)

#define SD_CMU_CMU_06_CFG_VCO_CAL_RESETN         BIT(6)
#define SD_CMU_CMU_06_CFG_VCO_CAL_RESETN_SET(x)\
	FIELD_PREP(SD_CMU_CMU_06_CFG_VCO_CAL_RESETN, x)
#define SD_CMU_CMU_06_CFG_VCO_CAL_RESETN_GET(x)\
	FIELD_GET(SD_CMU_CMU_06_CFG_VCO_CAL_RESETN, x)

#define SD_CMU_CMU_06_CFG_VCO_CAL_BYP            BIT(7)
#define SD_CMU_CMU_06_CFG_VCO_CAL_BYP_SET(x)\
	FIELD_PREP(SD_CMU_CMU_06_CFG_VCO_CAL_BYP, x)
#define SD_CMU_CMU_06_CFG_VCO_CAL_BYP_GET(x)\
	FIELD_GET(SD_CMU_CMU_06_CFG_VCO_CAL_BYP, x)

/*      SD10G_CMU_TARGET:CMU_GRP_1:CMU_08 */
#define SD_CMU_CMU_08(t) \
	__REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 12, 0, 1, 4)

#define SD_CMU_CMU_08_CFG_VFILT2PAD              BIT(0)
#define SD_CMU_CMU_08_CFG_VFILT2PAD_SET(x)\
	FIELD_PREP(SD_CMU_CMU_08_CFG_VFILT2PAD, x)
#define SD_CMU_CMU_08_CFG_VFILT2PAD_GET(x)\
	FIELD_GET(SD_CMU_CMU_08_CFG_VFILT2PAD, x)

#define SD_CMU_CMU_08_CFG_EN_DUMMY               BIT(1)
#define SD_CMU_CMU_08_CFG_EN_DUMMY_SET(x)\
	FIELD_PREP(SD_CMU_CMU_08_CFG_EN_DUMMY, x)
#define SD_CMU_CMU_08_CFG_EN_DUMMY_GET(x)\
	FIELD_GET(SD_CMU_CMU_08_CFG_EN_DUMMY, x)

#define SD_CMU_CMU_08_CFG_CK_TREE_PD             BIT(2)
#define SD_CMU_CMU_08_CFG_CK_TREE_PD_SET(x)\
	FIELD_PREP(SD_CMU_CMU_08_CFG_CK_TREE_PD, x)
#define SD_CMU_CMU_08_CFG_CK_TREE_PD_GET(x)\
	FIELD_GET(SD_CMU_CMU_08_CFG_CK_TREE_PD, x)

#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN        BIT(3)
#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_SET(x)\
	FIELD_PREP(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN, x)
#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_GET(x)\
	FIELD_GET(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN, x)

#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN     BIT(4)
#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN_SET(x)\
	FIELD_PREP(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN, x)
#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN_GET(x)\
	FIELD_GET(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN, x)

/*      SD10G_CMU_TARGET:CMU_GRP_1:CMU_09 */
#define SD_CMU_CMU_09(t)          __REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 16, 0, 1, 4)

#define SD_CMU_CMU_09_CFG_EN_TX_CK_UP            BIT(0)
#define SD_CMU_CMU_09_CFG_EN_TX_CK_UP_SET(x)\
	FIELD_PREP(SD_CMU_CMU_09_CFG_EN_TX_CK_UP, x)
#define SD_CMU_CMU_09_CFG_EN_TX_CK_UP_GET(x)\
	FIELD_GET(SD_CMU_CMU_09_CFG_EN_TX_CK_UP, x)

#define SD_CMU_CMU_09_CFG_EN_TX_CK_DN            BIT(1)
#define SD_CMU_CMU_09_CFG_EN_TX_CK_DN_SET(x)\
	FIELD_PREP(SD_CMU_CMU_09_CFG_EN_TX_CK_DN, x)
#define SD_CMU_CMU_09_CFG_EN_TX_CK_DN_GET(x)\
	FIELD_GET(SD_CMU_CMU_09_CFG_EN_TX_CK_DN, x)

#define SD_CMU_CMU_09_CFG_SW_8G                  BIT(4)
#define SD_CMU_CMU_09_CFG_SW_8G_SET(x)\
	FIELD_PREP(SD_CMU_CMU_09_CFG_SW_8G, x)
#define SD_CMU_CMU_09_CFG_SW_8G_GET(x)\
	FIELD_GET(SD_CMU_CMU_09_CFG_SW_8G, x)

#define SD_CMU_CMU_09_CFG_SW_10G                 BIT(5)
#define SD_CMU_CMU_09_CFG_SW_10G_SET(x)\
	FIELD_PREP(SD_CMU_CMU_09_CFG_SW_10G, x)
#define SD_CMU_CMU_09_CFG_SW_10G_GET(x)\
	FIELD_GET(SD_CMU_CMU_09_CFG_SW_10G, x)

/*      SD10G_CMU_TARGET:CMU_GRP_1:CMU_0D */
#define SD_CMU_CMU_0D(t)          __REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 32, 0, 1, 4)

#define SD_CMU_CMU_0D_CFG_PD_DIV64               BIT(0)
#define SD_CMU_CMU_0D_CFG_PD_DIV64_SET(x)\
	FIELD_PREP(SD_CMU_CMU_0D_CFG_PD_DIV64, x)
#define SD_CMU_CMU_0D_CFG_PD_DIV64_GET(x)\
	FIELD_GET(SD_CMU_CMU_0D_CFG_PD_DIV64, x)

#define SD_CMU_CMU_0D_CFG_PD_DIV66               BIT(1)
#define SD_CMU_CMU_0D_CFG_PD_DIV66_SET(x)\
	FIELD_PREP(SD_CMU_CMU_0D_CFG_PD_DIV66, x)
#define SD_CMU_CMU_0D_CFG_PD_DIV66_GET(x)\
	FIELD_GET(SD_CMU_CMU_0D_CFG_PD_DIV66, x)

#define SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD           BIT(2)
#define SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_SET(x)\
	FIELD_PREP(SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD, x)
#define SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_GET(x)\
	FIELD_GET(SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD, x)

#define SD_CMU_CMU_0D_CFG_JC_BYP                 BIT(3)
#define SD_CMU_CMU_0D_CFG_JC_BYP_SET(x)\
	FIELD_PREP(SD_CMU_CMU_0D_CFG_JC_BYP, x)
#define SD_CMU_CMU_0D_CFG_JC_BYP_GET(x)\
	FIELD_GET(SD_CMU_CMU_0D_CFG_JC_BYP, x)

#define SD_CMU_CMU_0D_CFG_REFCK_PD               BIT(4)
#define SD_CMU_CMU_0D_CFG_REFCK_PD_SET(x)\
	FIELD_PREP(SD_CMU_CMU_0D_CFG_REFCK_PD, x)
#define SD_CMU_CMU_0D_CFG_REFCK_PD_GET(x)\
	FIELD_GET(SD_CMU_CMU_0D_CFG_REFCK_PD, x)

/*      SD10G_CMU_TARGET:CMU_GRP_3:CMU_1B */
#define SD_CMU_CMU_1B(t)          __REG(TARGET_SD_CMU, t, 14, 104, 0, 1, 20, 4, 0, 1, 4)

#define SD_CMU_CMU_1B_CFG_RESERVE_7_0            GENMASK(7, 0)
#define SD_CMU_CMU_1B_CFG_RESERVE_7_0_SET(x)\
	FIELD_PREP(SD_CMU_CMU_1B_CFG_RESERVE_7_0, x)
#define SD_CMU_CMU_1B_CFG_RESERVE_7_0_GET(x)\
	FIELD_GET(SD_CMU_CMU_1B_CFG_RESERVE_7_0, x)

/*      SD10G_CMU_TARGET:CMU_GRP_4:CMU_1F */
#define SD_CMU_CMU_1F(t)          __REG(TARGET_SD_CMU, t, 14, 124, 0, 1, 68, 0, 0, 1, 4)

#define SD_CMU_CMU_1F_CFG_BIAS_DN_EN             BIT(0)
#define SD_CMU_CMU_1F_CFG_BIAS_DN_EN_SET(x)\
	FIELD_PREP(SD_CMU_CMU_1F_CFG_BIAS_DN_EN, x)
#define SD_CMU_CMU_1F_CFG_BIAS_DN_EN_GET(x)\
	FIELD_GET(SD_CMU_CMU_1F_CFG_BIAS_DN_EN, x)

#define SD_CMU_CMU_1F_CFG_BIAS_UP_EN             BIT(1)
#define SD_CMU_CMU_1F_CFG_BIAS_UP_EN_SET(x)\
	FIELD_PREP(SD_CMU_CMU_1F_CFG_BIAS_UP_EN, x)
#define SD_CMU_CMU_1F_CFG_BIAS_UP_EN_GET(x)\
	FIELD_GET(SD_CMU_CMU_1F_CFG_BIAS_UP_EN, x)

#define SD_CMU_CMU_1F_CFG_IC2IP_N                BIT(2)
#define SD_CMU_CMU_1F_CFG_IC2IP_N_SET(x)\
	FIELD_PREP(SD_CMU_CMU_1F_CFG_IC2IP_N, x)
#define SD_CMU_CMU_1F_CFG_IC2IP_N_GET(x)\
	FIELD_GET(SD_CMU_CMU_1F_CFG_IC2IP_N, x)

#define SD_CMU_CMU_1F_CFG_VTUNE_SEL              BIT(3)
#define SD_CMU_CMU_1F_CFG_VTUNE_SEL_SET(x)\
	FIELD_PREP(SD_CMU_CMU_1F_CFG_VTUNE_SEL, x)
#define SD_CMU_CMU_1F_CFG_VTUNE_SEL_GET(x)\
	FIELD_GET(SD_CMU_CMU_1F_CFG_VTUNE_SEL, x)

/*      SD10G_CMU_TARGET:CMU_GRP_5:CMU_30 */
#define SD_CMU_CMU_30(t)          __REG(TARGET_SD_CMU, t, 14, 192, 0, 1, 72, 0, 0, 1, 4)

#define SD_CMU_CMU_30_R_PLL_DLOL_EN              BIT(0)
#define SD_CMU_CMU_30_R_PLL_DLOL_EN_SET(x)\
	FIELD_PREP(SD_CMU_CMU_30_R_PLL_DLOL_EN, x)
#define SD_CMU_CMU_30_R_PLL_DLOL_EN_GET(x)\
	FIELD_GET(SD_CMU_CMU_30_R_PLL_DLOL_EN, x)

/*      SD10G_CMU_TARGET:CMU_GRP_6:CMU_44 */
#define SD_CMU_CMU_44(t)          __REG(TARGET_SD_CMU, t, 14, 264, 0, 1, 632, 8, 0, 1, 4)

#define SD_CMU_CMU_44_R_PLL_RSTN                 BIT(0)
#define SD_CMU_CMU_44_R_PLL_RSTN_SET(x)\
	FIELD_PREP(SD_CMU_CMU_44_R_PLL_RSTN, x)
#define SD_CMU_CMU_44_R_PLL_RSTN_GET(x)\
	FIELD_GET(SD_CMU_CMU_44_R_PLL_RSTN, x)

#define SD_CMU_CMU_44_R_CK_RESETB                BIT(1)
#define SD_CMU_CMU_44_R_CK_RESETB_SET(x)\
	FIELD_PREP(SD_CMU_CMU_44_R_CK_RESETB, x)
#define SD_CMU_CMU_44_R_CK_RESETB_GET(x)\
	FIELD_GET(SD_CMU_CMU_44_R_CK_RESETB, x)

/*      SD10G_CMU_TARGET:CMU_GRP_6:CMU_45 */
#define SD_CMU_CMU_45(t)          __REG(TARGET_SD_CMU, t, 14, 264, 0, 1, 632, 12, 0, 1, 4)

#define SD_CMU_CMU_45_R_EN_RATECHG_CTRL          BIT(0)
#define SD_CMU_CMU_45_R_EN_RATECHG_CTRL_SET(x)\
	FIELD_PREP(SD_CMU_CMU_45_R_EN_RATECHG_CTRL, x)
#define SD_CMU_CMU_45_R_EN_RATECHG_CTRL_GET(x)\
	FIELD_GET(SD_CMU_CMU_45_R_EN_RATECHG_CTRL, x)

#define SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT      BIT(1)
#define SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_SET(x)\
	FIELD_PREP(SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT, x)
#define SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_GET(x)\
	FIELD_GET(SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT, x)

#define SD_CMU_CMU_45_RESERVED                   BIT(2)
#define SD_CMU_CMU_45_RESERVED_SET(x)\
	FIELD_PREP(SD_CMU_CMU_45_RESERVED, x)
#define SD_CMU_CMU_45_RESERVED_GET(x)\
	FIELD_GET(SD_CMU_CMU_45_RESERVED, x)

#define SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT    BIT(3)
#define SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_SET(x)\
	FIELD_PREP(SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT, x)
#define SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_GET(x)\
	FIELD_GET(SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT, x)

#define SD_CMU_CMU_45_RESERVED_2                 BIT(4)
#define SD_CMU_CMU_45_RESERVED_2_SET(x)\
	FIELD_PREP(SD_CMU_CMU_45_RESERVED_2, x)
#define SD_CMU_CMU_45_RESERVED_2_GET(x)\
	FIELD_GET(SD_CMU_CMU_45_RESERVED_2, x)

#define SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT     BIT(5)
#define SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_SET(x)\
	FIELD_PREP(SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT, x)
#define SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_GET(x)\
	FIELD_GET(SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT, x)

#define SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT         BIT(6)
#define SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_SET(x)\
	FIELD_PREP(SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT, x)
#define SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_GET(x)\
	FIELD_GET(SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT, x)

#define SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN     BIT(7)
#define SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN_SET(x)\
	FIELD_PREP(SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN, x)
#define SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN_GET(x)\
	FIELD_GET(SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN, x)

/*      SD10G_CMU_TARGET:CMU_GRP_6:CMU_47 */
#define SD_CMU_CMU_47(t)          __REG(TARGET_SD_CMU, t, 14, 264, 0, 1, 632, 20, 0, 1, 4)

#define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0      GENMASK(4, 0)
#define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_SET(x)\
	FIELD_PREP(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0, x)
#define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_GET(x)\
	FIELD_GET(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0, x)

/*      SD10G_CMU_TARGET:CMU_GRP_7:CMU_E0 */
#define SD_CMU_CMU_E0(t)          __REG(TARGET_SD_CMU, t, 14, 896, 0, 1, 8, 0, 0, 1, 4)

#define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0         GENMASK(3, 0)
#define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0_SET(x)\
	FIELD_PREP(SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0, x)
#define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0_GET(x)\
	FIELD_GET(SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0, x)

#define SD_CMU_CMU_E0_PLL_LOL_UDL                BIT(4)
#define SD_CMU_CMU_E0_PLL_LOL_UDL_SET(x)\
	FIELD_PREP(SD_CMU_CMU_E0_PLL_LOL_UDL, x)
#define SD_CMU_CMU_E0_PLL_LOL_UDL_GET(x)\
	FIELD_GET(SD_CMU_CMU_E0_PLL_LOL_UDL, x)

/*      SD_CMU_TARGET:SD_CMU_CFG:SD_CMU_CFG */
#define SD_CMU_CFG_SD_CMU_CFG(t)  __REG(TARGET_SD_CMU_CFG, t, 14, 0, 0, 1, 8, 0, 0, 1, 4)

#define SD_CMU_CFG_SD_CMU_CFG_CMU_RST            BIT(0)
#define SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(x)\
	FIELD_PREP(SD_CMU_CFG_SD_CMU_CFG_CMU_RST, x)
#define SD_CMU_CFG_SD_CMU_CFG_CMU_RST_GET(x)\
	FIELD_GET(SD_CMU_CFG_SD_CMU_CFG_CMU_RST, x)

#define SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST        BIT(1)
#define SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(x)\
	FIELD_PREP(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, x)
#define SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_GET(x)\
	FIELD_GET(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, x)

/*      SD_LANE_TARGET:SD_RESET:SD_SER_RST */
#define SD_LANE_SD_SER_RST(t)     __REG(TARGET_SD_LANE, t, 25, 0, 0, 1, 8, 0, 0, 1, 4)

#define SD_LANE_SD_SER_RST_SER_RST               BIT(0)
#define SD_LANE_SD_SER_RST_SER_RST_SET(x)\
	FIELD_PREP(SD_LANE_SD_SER_RST_SER_RST, x)
#define SD_LANE_SD_SER_RST_SER_RST_GET(x)\
	FIELD_GET(SD_LANE_SD_SER_RST_SER_RST, x)

/*      SD_LANE_TARGET:SD_RESET:SD_DES_RST */
#define SD_LANE_SD_DES_RST(t)     __REG(TARGET_SD_LANE, t, 25, 0, 0, 1, 8, 4, 0, 1, 4)

#define SD_LANE_SD_DES_RST_DES_RST               BIT(0)
#define SD_LANE_SD_DES_RST_DES_RST_SET(x)\
	FIELD_PREP(SD_LANE_SD_DES_RST_DES_RST, x)
#define SD_LANE_SD_DES_RST_DES_RST_GET(x)\
	FIELD_GET(SD_LANE_SD_DES_RST_DES_RST, x)

/*      SD_LANE_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG */
#define SD_LANE_SD_LANE_CFG(t)    __REG(TARGET_SD_LANE, t, 25, 8, 0, 1, 8, 0, 0, 1, 4)

#define SD_LANE_SD_LANE_CFG_MACRO_RST            BIT(0)
#define SD_LANE_SD_LANE_CFG_MACRO_RST_SET(x)\
	FIELD_PREP(SD_LANE_SD_LANE_CFG_MACRO_RST, x)
#define SD_LANE_SD_LANE_CFG_MACRO_RST_GET(x)\
	FIELD_GET(SD_LANE_SD_LANE_CFG_MACRO_RST, x)

#define SD_LANE_SD_LANE_CFG_EXT_CFG_RST          BIT(1)
#define SD_LANE_SD_LANE_CFG_EXT_CFG_RST_SET(x)\
	FIELD_PREP(SD_LANE_SD_LANE_CFG_EXT_CFG_RST, x)
#define SD_LANE_SD_LANE_CFG_EXT_CFG_RST_GET(x)\
	FIELD_GET(SD_LANE_SD_LANE_CFG_EXT_CFG_RST, x)

#define SD_LANE_SD_LANE_CFG_TX_REF_SEL           GENMASK(5, 4)
#define SD_LANE_SD_LANE_CFG_TX_REF_SEL_SET(x)\
	FIELD_PREP(SD_LANE_SD_LANE_CFG_TX_REF_SEL, x)
#define SD_LANE_SD_LANE_CFG_TX_REF_SEL_GET(x)\
	FIELD_GET(SD_LANE_SD_LANE_CFG_TX_REF_SEL, x)

#define SD_LANE_SD_LANE_CFG_RX_REF_SEL           GENMASK(7, 6)
#define SD_LANE_SD_LANE_CFG_RX_REF_SEL_SET(x)\
	FIELD_PREP(SD_LANE_SD_LANE_CFG_RX_REF_SEL, x)
#define SD_LANE_SD_LANE_CFG_RX_REF_SEL_GET(x)\
	FIELD_GET(SD_LANE_SD_LANE_CFG_RX_REF_SEL, x)

#define SD_LANE_SD_LANE_CFG_LANE_RST             BIT(8)
#define SD_LANE_SD_LANE_CFG_LANE_RST_SET(x)\
	FIELD_PREP(SD_LANE_SD_LANE_CFG_LANE_RST, x)
#define SD_LANE_SD_LANE_CFG_LANE_RST_GET(x)\
	FIELD_GET(SD_LANE_SD_LANE_CFG_LANE_RST, x)

#define SD_LANE_SD_LANE_CFG_LANE_TX_RST          BIT(9)
#define SD_LANE_SD_LANE_CFG_LANE_TX_RST_SET(x)\
	FIELD_PREP(SD_LANE_SD_LANE_CFG_LANE_TX_RST, x)
#define SD_LANE_SD_LANE_CFG_LANE_TX_RST_GET(x)\
	FIELD_GET(SD_LANE_SD_LANE_CFG_LANE_TX_RST, x)

#define SD_LANE_SD_LANE_CFG_LANE_RX_RST          BIT(10)
#define SD_LANE_SD_LANE_CFG_LANE_RX_RST_SET(x)\
	FIELD_PREP(SD_LANE_SD_LANE_CFG_LANE_RX_RST, x)
#define SD_LANE_SD_LANE_CFG_LANE_RX_RST_GET(x)\
	FIELD_GET(SD_LANE_SD_LANE_CFG_LANE_RX_RST, x)

/*      SD_LANE_TARGET:SD_LANE_CFG_STAT:SD_LANE_STAT */
#define SD_LANE_SD_LANE_STAT(t)   __REG(TARGET_SD_LANE, t, 25, 8, 0, 1, 8, 4, 0, 1, 4)

#define SD_LANE_SD_LANE_STAT_PMA_RST_DONE        BIT(0)
#define SD_LANE_SD_LANE_STAT_PMA_RST_DONE_SET(x)\
	FIELD_PREP(SD_LANE_SD_LANE_STAT_PMA_RST_DONE, x)
#define SD_LANE_SD_LANE_STAT_PMA_RST_DONE_GET(x)\
	FIELD_GET(SD_LANE_SD_LANE_STAT_PMA_RST_DONE, x)

#define SD_LANE_SD_LANE_STAT_DFE_RST_DONE        BIT(1)
#define SD_LANE_SD_LANE_STAT_DFE_RST_DONE_SET(x)\
	FIELD_PREP(SD_LANE_SD_LANE_STAT_DFE_RST_DONE, x)
#define SD_LANE_SD_LANE_STAT_DFE_RST_DONE_GET(x)\
	FIELD_GET(SD_LANE_SD_LANE_STAT_DFE_RST_DONE, x)

#define SD_LANE_SD_LANE_STAT_DBG_OBS             GENMASK(31, 16)
#define SD_LANE_SD_LANE_STAT_DBG_OBS_SET(x)\
	FIELD_PREP(SD_LANE_SD_LANE_STAT_DBG_OBS, x)
#define SD_LANE_SD_LANE_STAT_DBG_OBS_GET(x)\
	FIELD_GET(SD_LANE_SD_LANE_STAT_DBG_OBS, x)

/*      SD_LANE_TARGET:SD_PWR_CFG:QUIET_MODE_6G */
#define SD_LANE_QUIET_MODE_6G(t) \
	__REG(TARGET_SD_LANE, t, 25, 24, 0, 1, 8, 4, 0, 1, 4)

#define SD_LANE_QUIET_MODE_6G_QUIET_MODE         GENMASK(24, 0)
#define SD_LANE_QUIET_MODE_6G_QUIET_MODE_SET(x)\
	FIELD_PREP(SD_LANE_QUIET_MODE_6G_QUIET_MODE, x)
#define SD_LANE_QUIET_MODE_6G_QUIET_MODE_GET(x)\
	FIELD_GET(SD_LANE_QUIET_MODE_6G_QUIET_MODE, x)

/*      SD_LANE_TARGET:CFG_STAT_FX100:MISC */
#define SD_LANE_MISC(t)           __REG(TARGET_SD_LANE, t, 25, 56, 0, 1, 56, 0, 0, 1, 4)

#define SD_LANE_MISC_SD_125_RST_DIS              BIT(0)
#define SD_LANE_MISC_SD_125_RST_DIS_SET(x)\
	FIELD_PREP(SD_LANE_MISC_SD_125_RST_DIS, x)
#define SD_LANE_MISC_SD_125_RST_DIS_GET(x)\
	FIELD_GET(SD_LANE_MISC_SD_125_RST_DIS, x)

#define SD_LANE_MISC_RX_ENA                      BIT(1)
#define SD_LANE_MISC_RX_ENA_SET(x)\
	FIELD_PREP(SD_LANE_MISC_RX_ENA, x)
#define SD_LANE_MISC_RX_ENA_GET(x)\
	FIELD_GET(SD_LANE_MISC_RX_ENA, x)

#define SD_LANE_MISC_MUX_ENA                     BIT(2)
#define SD_LANE_MISC_MUX_ENA_SET(x)\
	FIELD_PREP(SD_LANE_MISC_MUX_ENA, x)
#define SD_LANE_MISC_MUX_ENA_GET(x)\
	FIELD_GET(SD_LANE_MISC_MUX_ENA, x)

#define SD_LANE_MISC_CORE_CLK_FREQ               GENMASK(5, 4)
#define SD_LANE_MISC_CORE_CLK_FREQ_SET(x)\
	FIELD_PREP(SD_LANE_MISC_CORE_CLK_FREQ, x)
#define SD_LANE_MISC_CORE_CLK_FREQ_GET(x)\
	FIELD_GET(SD_LANE_MISC_CORE_CLK_FREQ, x)

/*      SD_LANE_TARGET:CFG_STAT_FX100:M_STAT_MISC */
#define SD_LANE_M_STAT_MISC(t)    __REG(TARGET_SD_LANE, t, 25, 56, 0, 1, 56, 36, 0, 1, 4)

#define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM GENMASK(21, 0)
#define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM_SET(x)\
	FIELD_PREP(SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM, x)
#define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM_GET(x)\
	FIELD_GET(SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM, x)

#define SD_LANE_M_STAT_MISC_M_LOCK_CNT           GENMASK(31, 24)
#define SD_LANE_M_STAT_MISC_M_LOCK_CNT_SET(x)\
	FIELD_PREP(SD_LANE_M_STAT_MISC_M_LOCK_CNT, x)
#define SD_LANE_M_STAT_MISC_M_LOCK_CNT_GET(x)\
	FIELD_GET(SD_LANE_M_STAT_MISC_M_LOCK_CNT, x)

/*      SD25G_CFG_TARGET:SD_RESET:SD_SER_RST */
#define SD_LANE_25G_SD_SER_RST(t) __REG(TARGET_SD_LANE_25G, t, 8, 0, 0, 1, 8, 0, 0, 1, 4)

#define SD_LANE_25G_SD_SER_RST_SER_RST           BIT(0)
#define SD_LANE_25G_SD_SER_RST_SER_RST_SET(x)\
	FIELD_PREP(SD_LANE_25G_SD_SER_RST_SER_RST, x)
#define SD_LANE_25G_SD_SER_RST_SER_RST_GET(x)\
	FIELD_GET(SD_LANE_25G_SD_SER_RST_SER_RST, x)

/*      SD25G_CFG_TARGET:SD_RESET:SD_DES_RST */
#define SD_LANE_25G_SD_DES_RST(t) __REG(TARGET_SD_LANE_25G, t, 8, 0, 0, 1, 8, 4, 0, 1, 4)

#define SD_LANE_25G_SD_DES_RST_DES_RST           BIT(0)
#define SD_LANE_25G_SD_DES_RST_DES_RST_SET(x)\
	FIELD_PREP(SD_LANE_25G_SD_DES_RST_DES_RST, x)
#define SD_LANE_25G_SD_DES_RST_DES_RST_GET(x)\
	FIELD_GET(SD_LANE_25G_SD_DES_RST_DES_RST, x)

/*      SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG */
#define SD_LANE_25G_SD_LANE_CFG(t) __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 0, 0, 1, 4)

#define SD_LANE_25G_SD_LANE_CFG_MACRO_RST        BIT(0)
#define SD_LANE_25G_SD_LANE_CFG_MACRO_RST_SET(x)\
	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_MACRO_RST, x)
#define SD_LANE_25G_SD_LANE_CFG_MACRO_RST_GET(x)\
	FIELD_GET(SD_LANE_25G_SD_LANE_CFG_MACRO_RST, x)

#define SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST      BIT(1)
#define SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(x)\
	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST, x)
#define SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_GET(x)\
	FIELD_GET(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST, x)

#define SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE BIT(4)
#define SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE_SET(x)\
	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE, x)
#define SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE_GET(x)\
	FIELD_GET(SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE, x)

#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE  GENMASK(7, 5)
#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE_SET(x)\
	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE, x)
#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE_GET(x)\
	FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE, x)

#define SD_LANE_25G_SD_LANE_CFG_LANE_RST         BIT(8)
#define SD_LANE_25G_SD_LANE_CFG_LANE_RST_SET(x)\
	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_LANE_RST, x)
#define SD_LANE_25G_SD_LANE_CFG_LANE_RST_GET(x)\
	FIELD_GET(SD_LANE_25G_SD_LANE_CFG_LANE_RST, x)

#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV       BIT(9)
#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV_SET(x)\
	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV, x)
#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV_GET(x)\
	FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV, x)

#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN      BIT(10)
#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN_SET(x)\
	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN, x)
#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN_GET(x)\
	FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN, x)

#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY       BIT(11)
#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY_SET(x)\
	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY, x)
#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY_GET(x)\
	FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY, x)

#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV      GENMASK(15, 12)
#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV_SET(x)\
	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV, x)
#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV_GET(x)\
	FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV, x)

#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN     BIT(16)
#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN_SET(x)\
	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN, x)
#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN_GET(x)\
	FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN, x)

#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY      GENMASK(21, 17)
#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY_SET(x)\
	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY, x)
#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY_GET(x)\
	FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY, x)

#define SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN     BIT(22)
#define SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN_SET(x)\
	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN, x)
#define SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN_GET(x)\
	FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN, x)

#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN BIT(23)
#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN_SET(x)\
	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN, x)
#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN_GET(x)\
	FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN, x)

#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING  BIT(24)
#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING_SET(x)\
	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING, x)
#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING_GET(x)\
	FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING, x)

#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI     BIT(25)
#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI_SET(x)\
	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI, x)
#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI_GET(x)\
	FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI, x)

#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN GENMASK(28, 26)
#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN_SET(x)\
	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN, x)
#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN_GET(x)\
	FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN, x)

/*      SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG2 */
#define SD_LANE_25G_SD_LANE_CFG2(t) __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 4, 0, 1, 4)

#define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL  GENMASK(2, 0)
#define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL_SET(x)\
	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL, x)
#define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL_GET(x)\
	FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL, x)

#define SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL    GENMASK(5, 3)
#define SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL_SET(x)\
	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL, x)
#define SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL_GET(x)\
	FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL, x)

#define SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL   GENMASK(8, 6)
#define SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL_SET(x)\
	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL, x)
#define SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL_GET(x)\
	FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL, x)

#define SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED GENMASK(10, 9)
#define SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED_SET(x)\
	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED, x)
#define SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED_GET(x)\
	FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED, x)

#define SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV   GENMASK(13, 11)
#define SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV_SET(x)\
	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV, x)
#define SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV_GET(x)\
	FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV, x)

#define SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV   GENMASK(16, 14)
#define SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV_SET(x)\
	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV, x)
#define SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV_GET(x)\
	FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV, x)

#define SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL GENMASK(19, 17)
#define SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL_SET(x)\
	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL, x)
#define SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL_GET(x)\
	FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL, x)

#define SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV GENMASK(23, 20)
#define SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV_SET(x)\
	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV, x)
#define SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV_GET(x)\
	FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV, x)

#define SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL  GENMASK(25, 24)
#define SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL_SET(x)\
	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL, x)
#define SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL_GET(x)\
	FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL, x)

#define SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL      GENMASK(28, 26)
#define SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL_SET(x)\
	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL, x)
#define SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL_GET(x)\
	FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL, x)

#define SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL      GENMASK(31, 29)
#define SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL_SET(x)\
	FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL, x)
#define SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL_GET(x)\
	FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL, x)

/*      SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_STAT */
#define SD_LANE_25G_SD_LANE_STAT(t) __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 8, 0, 1, 4)

#define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE    BIT(0)
#define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE_SET(x)\
	FIELD_PREP(SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE, x)
#define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE_GET(x)\
	FIELD_GET(SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE, x)

#define SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE   BIT(1)
#define SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE_SET(x)\
	FIELD_PREP(SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE, x)
#define SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE_GET(x)\
	FIELD_GET(SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE, x)

#define SD_LANE_25G_SD_LANE_STAT_DBG_OBS         GENMASK(31, 16)
#define SD_LANE_25G_SD_LANE_STAT_DBG_OBS_SET(x)\
	FIELD_PREP(SD_LANE_25G_SD_LANE_STAT_DBG_OBS, x)
#define SD_LANE_25G_SD_LANE_STAT_DBG_OBS_GET(x)\
	FIELD_GET(SD_LANE_25G_SD_LANE_STAT_DBG_OBS, x)

/*      SD25G_CFG_TARGET:SD_PWR_CFG:QUIET_MODE_6G */
#define SD_LANE_25G_QUIET_MODE_6G(t) \
	__REG(TARGET_SD_LANE_25G, t, 8, 28, 0, 1, 8, 4, 0, 1, 4)

#define SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE     GENMASK(24, 0)
#define SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE_SET(x)\
	FIELD_PREP(SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE, x)
#define SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE_GET(x)\
	FIELD_GET(SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE, x)

#endif /* _SPARX5_SERDES_REGS_H_ */