1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
|
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
// Copyright (c) 2017-2018, Linaro Limited
#include <linux/slab.h>
#include <sound/soc.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include "wcd9335.h"
#include "wcd-clsh-v2.h"
struct wcd_clsh_ctrl {
int state;
int mode;
int flyback_users;
int buck_users;
int clsh_users;
int codec_version;
struct snd_soc_component *comp;
};
/* Class-H registers for codecs from and above WCD9335 */
#define WCD9XXX_A_CDC_RX0_RX_PATH_CFG0 WCD9335_REG(0xB, 0x42)
#define WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK BIT(6)
#define WCD9XXX_A_CDC_RX_PATH_CLSH_ENABLE BIT(6)
#define WCD9XXX_A_CDC_RX_PATH_CLSH_DISABLE 0
#define WCD9XXX_A_CDC_RX1_RX_PATH_CFG0 WCD9335_REG(0xB, 0x56)
#define WCD9XXX_A_CDC_RX2_RX_PATH_CFG0 WCD9335_REG(0xB, 0x6A)
#define WCD9XXX_A_CDC_CLSH_K1_MSB WCD9335_REG(0xC, 0x08)
#define WCD9XXX_A_CDC_CLSH_K1_MSB_COEF_MASK GENMASK(3, 0)
#define WCD9XXX_A_CDC_CLSH_K1_LSB WCD9335_REG(0xC, 0x09)
#define WCD9XXX_A_CDC_CLSH_K1_LSB_COEF_MASK GENMASK(7, 0)
#define WCD9XXX_A_ANA_RX_SUPPLIES WCD9335_REG(0x6, 0x08)
#define WCD9XXX_A_ANA_RX_REGULATOR_MODE_MASK BIT(1)
#define WCD9XXX_A_ANA_RX_REGULATOR_MODE_CLS_H 0
#define WCD9XXX_A_ANA_RX_REGULATOR_MODE_CLS_AB BIT(1)
#define WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_MASK BIT(2)
#define WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_UHQA BIT(2)
#define WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_DEFAULT 0
#define WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_MASK BIT(3)
#define WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_UHQA BIT(3)
#define WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_DEFAULT 0
#define WCD9XXX_A_ANA_RX_VNEG_EN_MASK BIT(6)
#define WCD9XXX_A_ANA_RX_VNEG_EN_SHIFT 6
#define WCD9XXX_A_ANA_RX_VNEG_ENABLE BIT(6)
#define WCD9XXX_A_ANA_RX_VNEG_DISABLE 0
#define WCD9XXX_A_ANA_RX_VPOS_EN_MASK BIT(7)
#define WCD9XXX_A_ANA_RX_VPOS_EN_SHIFT 7
#define WCD9XXX_A_ANA_RX_VPOS_ENABLE BIT(7)
#define WCD9XXX_A_ANA_RX_VPOS_DISABLE 0
#define WCD9XXX_A_ANA_HPH WCD9335_REG(0x6, 0x09)
#define WCD9XXX_A_ANA_HPH_PWR_LEVEL_MASK GENMASK(3, 2)
#define WCD9XXX_A_ANA_HPH_PWR_LEVEL_UHQA 0x08
#define WCD9XXX_A_ANA_HPH_PWR_LEVEL_LP 0x04
#define WCD9XXX_A_ANA_HPH_PWR_LEVEL_NORMAL 0x0
#define WCD9XXX_A_CDC_CLSH_CRC WCD9335_REG(0xC, 0x01)
#define WCD9XXX_A_CDC_CLSH_CRC_CLK_EN_MASK BIT(0)
#define WCD9XXX_A_CDC_CLSH_CRC_CLK_ENABLE BIT(0)
#define WCD9XXX_A_CDC_CLSH_CRC_CLK_DISABLE 0
#define WCD9XXX_FLYBACK_EN WCD9335_REG(0x6, 0xA4)
#define WCD9XXX_FLYBACK_EN_DELAY_SEL_MASK GENMASK(6, 5)
#define WCD9XXX_FLYBACK_EN_DELAY_26P25_US 0x40
#define WCD9XXX_FLYBACK_EN_RESET_BY_EXT_MASK BIT(4)
#define WCD9XXX_FLYBACK_EN_PWDN_WITHOUT_DELAY BIT(4)
#define WCD9XXX_FLYBACK_EN_PWDN_WITH_DELAY 0
#define WCD9XXX_RX_BIAS_FLYB_BUFF WCD9335_REG(0x6, 0xC7)
#define WCD9XXX_RX_BIAS_FLYB_VNEG_5_UA_MASK GENMASK(7, 4)
#define WCD9XXX_RX_BIAS_FLYB_VPOS_5_UA_MASK GENMASK(3, 0)
#define WCD9XXX_HPH_L_EN WCD9335_REG(0x6, 0xD3)
#define WCD9XXX_HPH_CONST_SEL_L_MASK GENMASK(7, 3)
#define WCD9XXX_HPH_CONST_SEL_BYPASS 0
#define WCD9XXX_HPH_CONST_SEL_LP_PATH 0x40
#define WCD9XXX_HPH_CONST_SEL_HQ_PATH 0x80
#define WCD9XXX_HPH_R_EN WCD9335_REG(0x6, 0xD6)
#define WCD9XXX_HPH_REFBUFF_UHQA_CTL WCD9335_REG(0x6, 0xDD)
#define WCD9XXX_HPH_REFBUFF_UHQA_GAIN_MASK GENMASK(2, 0)
#define WCD9XXX_CLASSH_CTRL_VCL_2 WCD9335_REG(0x6, 0x9B)
#define WCD9XXX_CLASSH_CTRL_VCL_2_VREF_FILT_1_MASK GENMASK(5, 4)
#define WCD9XXX_CLASSH_CTRL_VCL_VREF_FILT_R_50KOHM 0x20
#define WCD9XXX_CLASSH_CTRL_VCL_VREF_FILT_R_0KOHM 0x0
#define WCD9XXX_CDC_RX1_RX_PATH_CTL WCD9335_REG(0xB, 0x55)
#define WCD9XXX_CDC_RX2_RX_PATH_CTL WCD9335_REG(0xB, 0x69)
#define WCD9XXX_CDC_CLK_RST_CTRL_MCLK_CONTROL WCD9335_REG(0xD, 0x41)
#define WCD9XXX_CDC_CLK_RST_CTRL_MCLK_EN_MASK BIT(0)
#define WCD9XXX_CDC_CLK_RST_CTRL_MCLK_11P3_EN_MASK BIT(1)
#define WCD9XXX_CLASSH_CTRL_CCL_1 WCD9335_REG(0x6, 0x9C)
#define WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_MASK GENMASK(7, 4)
#define WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_50MA 0x50
#define WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_30MA 0x30
#define WCD9XXX_BASE_ADDRESS 0x3000
#define WCD9XXX_ANA_RX_SUPPLIES (WCD9XXX_BASE_ADDRESS+0x008)
#define WCD9XXX_ANA_HPH (WCD9XXX_BASE_ADDRESS+0x009)
#define WCD9XXX_CLASSH_MODE_2 (WCD9XXX_BASE_ADDRESS+0x098)
#define WCD9XXX_CLASSH_MODE_3 (WCD9XXX_BASE_ADDRESS+0x099)
#define WCD9XXX_FLYBACK_VNEG_CTRL_1 (WCD9XXX_BASE_ADDRESS+0x0A5)
#define WCD9XXX_FLYBACK_VNEG_CTRL_4 (WCD9XXX_BASE_ADDRESS+0x0A8)
#define WCD9XXX_FLYBACK_VNEGDAC_CTRL_2 (WCD9XXX_BASE_ADDRESS+0x0AF)
#define WCD9XXX_RX_BIAS_HPH_LOWPOWER (WCD9XXX_BASE_ADDRESS+0x0BF)
#define WCD9XXX_V3_RX_BIAS_FLYB_BUFF (WCD9XXX_BASE_ADDRESS+0x0C7)
#define WCD9XXX_HPH_PA_CTL1 (WCD9XXX_BASE_ADDRESS+0x0D1)
#define WCD9XXX_HPH_NEW_INT_PA_MISC2 (WCD9XXX_BASE_ADDRESS+0x138)
#define CLSH_REQ_ENABLE true
#define CLSH_REQ_DISABLE false
#define WCD_USLEEP_RANGE 50
enum {
DAC_GAIN_0DB = 0,
DAC_GAIN_0P2DB,
DAC_GAIN_0P4DB,
DAC_GAIN_0P6DB,
DAC_GAIN_0P8DB,
DAC_GAIN_M0P2DB,
DAC_GAIN_M0P4DB,
DAC_GAIN_M0P6DB,
};
static inline void wcd_enable_clsh_block(struct wcd_clsh_ctrl *ctrl,
bool enable)
{
struct snd_soc_component *comp = ctrl->comp;
if ((enable && ++ctrl->clsh_users == 1) ||
(!enable && --ctrl->clsh_users == 0))
snd_soc_component_update_bits(comp, WCD9XXX_A_CDC_CLSH_CRC,
WCD9XXX_A_CDC_CLSH_CRC_CLK_EN_MASK,
enable);
if (ctrl->clsh_users < 0)
ctrl->clsh_users = 0;
}
static inline void wcd_clsh_set_buck_mode(struct snd_soc_component *comp,
int mode)
{
/* set to HIFI */
if (mode == CLS_H_HIFI)
snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES,
WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_MASK,
WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_UHQA);
else
snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES,
WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_MASK,
WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_DEFAULT);
}
static void wcd_clsh_v3_set_buck_mode(struct snd_soc_component *component,
int mode)
{
if (mode == CLS_H_HIFI || mode == CLS_H_LOHIFI ||
mode == CLS_AB_HIFI || mode == CLS_AB_LOHIFI)
snd_soc_component_update_bits(component,
WCD9XXX_ANA_RX_SUPPLIES,
0x08, 0x08); /* set to HIFI */
else
snd_soc_component_update_bits(component,
WCD9XXX_ANA_RX_SUPPLIES,
0x08, 0x00); /* set to default */
}
static inline void wcd_clsh_set_flyback_mode(struct snd_soc_component *comp,
int mode)
{
/* set to HIFI */
if (mode == CLS_H_HIFI)
snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES,
WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_MASK,
WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_UHQA);
else
snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES,
WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_MASK,
WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_DEFAULT);
}
static void wcd_clsh_buck_ctrl(struct wcd_clsh_ctrl *ctrl,
int mode,
bool enable)
{
struct snd_soc_component *comp = ctrl->comp;
/* enable/disable buck */
if ((enable && (++ctrl->buck_users == 1)) ||
(!enable && (--ctrl->buck_users == 0)))
snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES,
WCD9XXX_A_ANA_RX_VPOS_EN_MASK,
enable << WCD9XXX_A_ANA_RX_VPOS_EN_SHIFT);
/*
* 500us sleep is required after buck enable/disable
* as per HW requirement
*/
usleep_range(500, 500 + WCD_USLEEP_RANGE);
}
static void wcd_clsh_v3_buck_ctrl(struct snd_soc_component *component,
struct wcd_clsh_ctrl *ctrl,
int mode,
bool enable)
{
/* enable/disable buck */
if ((enable && (++ctrl->buck_users == 1)) ||
(!enable && (--ctrl->buck_users == 0))) {
snd_soc_component_update_bits(component,
WCD9XXX_ANA_RX_SUPPLIES,
(1 << 7), (enable << 7));
/*
* 500us sleep is required after buck enable/disable
* as per HW requirement
*/
usleep_range(500, 510);
if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
mode == CLS_H_HIFI || mode == CLS_H_LP)
snd_soc_component_update_bits(component,
WCD9XXX_CLASSH_MODE_3,
0x02, 0x00);
snd_soc_component_update_bits(component,
WCD9XXX_CLASSH_MODE_2,
0xFF, 0x3A);
/* 500usec delay is needed as per HW requirement */
usleep_range(500, 500 + WCD_USLEEP_RANGE);
}
}
static void wcd_clsh_flyback_ctrl(struct wcd_clsh_ctrl *ctrl,
int mode,
bool enable)
{
struct snd_soc_component *comp = ctrl->comp;
/* enable/disable flyback */
if ((enable && (++ctrl->flyback_users == 1)) ||
(!enable && (--ctrl->flyback_users == 0))) {
snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES,
WCD9XXX_A_ANA_RX_VNEG_EN_MASK,
enable << WCD9XXX_A_ANA_RX_VNEG_EN_SHIFT);
/* 100usec delay is needed as per HW requirement */
usleep_range(100, 110);
}
/*
* 500us sleep is required after flyback enable/disable
* as per HW requirement
*/
usleep_range(500, 500 + WCD_USLEEP_RANGE);
}
static void wcd_clsh_set_gain_path(struct wcd_clsh_ctrl *ctrl, int mode)
{
struct snd_soc_component *comp = ctrl->comp;
int val = 0;
switch (mode) {
case CLS_H_NORMAL:
case CLS_AB:
val = WCD9XXX_HPH_CONST_SEL_BYPASS;
break;
case CLS_H_HIFI:
val = WCD9XXX_HPH_CONST_SEL_HQ_PATH;
break;
case CLS_H_LP:
val = WCD9XXX_HPH_CONST_SEL_LP_PATH;
break;
}
snd_soc_component_update_bits(comp, WCD9XXX_HPH_L_EN,
WCD9XXX_HPH_CONST_SEL_L_MASK,
val);
snd_soc_component_update_bits(comp, WCD9XXX_HPH_R_EN,
WCD9XXX_HPH_CONST_SEL_L_MASK,
val);
}
static void wcd_clsh_v2_set_hph_mode(struct snd_soc_component *comp, int mode)
{
int val = 0, gain = 0, res_val;
int ipeak = WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_50MA;
res_val = WCD9XXX_CLASSH_CTRL_VCL_VREF_FILT_R_0KOHM;
switch (mode) {
case CLS_H_NORMAL:
res_val = WCD9XXX_CLASSH_CTRL_VCL_VREF_FILT_R_50KOHM;
val = WCD9XXX_A_ANA_HPH_PWR_LEVEL_NORMAL;
gain = DAC_GAIN_0DB;
ipeak = WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_50MA;
break;
case CLS_AB:
val = WCD9XXX_A_ANA_HPH_PWR_LEVEL_NORMAL;
gain = DAC_GAIN_0DB;
ipeak = WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_50MA;
break;
case CLS_H_HIFI:
val = WCD9XXX_A_ANA_HPH_PWR_LEVEL_UHQA;
gain = DAC_GAIN_M0P2DB;
ipeak = WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_50MA;
break;
case CLS_H_LP:
val = WCD9XXX_A_ANA_HPH_PWR_LEVEL_LP;
ipeak = WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_30MA;
break;
}
snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_HPH,
WCD9XXX_A_ANA_HPH_PWR_LEVEL_MASK, val);
snd_soc_component_update_bits(comp, WCD9XXX_CLASSH_CTRL_VCL_2,
WCD9XXX_CLASSH_CTRL_VCL_2_VREF_FILT_1_MASK,
res_val);
if (mode != CLS_H_LP)
snd_soc_component_update_bits(comp,
WCD9XXX_HPH_REFBUFF_UHQA_CTL,
WCD9XXX_HPH_REFBUFF_UHQA_GAIN_MASK,
gain);
snd_soc_component_update_bits(comp, WCD9XXX_CLASSH_CTRL_CCL_1,
WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_MASK,
ipeak);
}
static void wcd_clsh_v3_set_hph_mode(struct snd_soc_component *component,
int mode)
{
u8 val;
switch (mode) {
case CLS_H_NORMAL:
val = 0x00;
break;
case CLS_AB:
case CLS_H_ULP:
val = 0x0C;
break;
case CLS_AB_HIFI:
case CLS_H_HIFI:
val = 0x08;
break;
case CLS_H_LP:
case CLS_H_LOHIFI:
case CLS_AB_LP:
case CLS_AB_LOHIFI:
val = 0x04;
break;
default:
dev_err(component->dev, "%s:Invalid mode %d\n", __func__, mode);
return;
}
snd_soc_component_update_bits(component, WCD9XXX_ANA_HPH, 0x0C, val);
}
void wcd_clsh_set_hph_mode(struct wcd_clsh_ctrl *ctrl, int mode)
{
struct snd_soc_component *comp = ctrl->comp;
if (ctrl->codec_version >= WCD937X)
wcd_clsh_v3_set_hph_mode(comp, mode);
else
wcd_clsh_v2_set_hph_mode(comp, mode);
}
EXPORT_SYMBOL_GPL(wcd_clsh_set_hph_mode);
static void wcd_clsh_set_flyback_current(struct snd_soc_component *comp,
int mode)
{
snd_soc_component_update_bits(comp, WCD9XXX_RX_BIAS_FLYB_BUFF,
WCD9XXX_RX_BIAS_FLYB_VPOS_5_UA_MASK, 0x0A);
snd_soc_component_update_bits(comp, WCD9XXX_RX_BIAS_FLYB_BUFF,
WCD9XXX_RX_BIAS_FLYB_VNEG_5_UA_MASK, 0x0A);
/* Sleep needed to avoid click and pop as per HW requirement */
usleep_range(100, 110);
}
static void wcd_clsh_set_buck_regulator_mode(struct snd_soc_component *comp,
int mode)
{
if (mode == CLS_AB)
snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES,
WCD9XXX_A_ANA_RX_REGULATOR_MODE_MASK,
WCD9XXX_A_ANA_RX_REGULATOR_MODE_CLS_AB);
else
snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES,
WCD9XXX_A_ANA_RX_REGULATOR_MODE_MASK,
WCD9XXX_A_ANA_RX_REGULATOR_MODE_CLS_H);
}
static void wcd_clsh_v3_set_buck_regulator_mode(struct snd_soc_component *component,
int mode)
{
snd_soc_component_update_bits(component, WCD9XXX_ANA_RX_SUPPLIES,
0x02, 0x00);
}
static void wcd_clsh_v3_set_flyback_mode(struct snd_soc_component *component,
int mode)
{
if (mode == CLS_H_HIFI || mode == CLS_H_LOHIFI ||
mode == CLS_AB_HIFI || mode == CLS_AB_LOHIFI) {
snd_soc_component_update_bits(component,
WCD9XXX_ANA_RX_SUPPLIES,
0x04, 0x04);
snd_soc_component_update_bits(component,
WCD9XXX_FLYBACK_VNEG_CTRL_4,
0xF0, 0x80);
} else {
snd_soc_component_update_bits(component,
WCD9XXX_ANA_RX_SUPPLIES,
0x04, 0x00); /* set to Default */
snd_soc_component_update_bits(component,
WCD9XXX_FLYBACK_VNEG_CTRL_4,
0xF0, 0x70);
}
}
static void wcd_clsh_v3_force_iq_ctl(struct snd_soc_component *component,
int mode, bool enable)
{
if (enable) {
snd_soc_component_update_bits(component,
WCD9XXX_FLYBACK_VNEGDAC_CTRL_2,
0xE0, 0xA0);
/* 100usec delay is needed as per HW requirement */
usleep_range(100, 110);
snd_soc_component_update_bits(component,
WCD9XXX_CLASSH_MODE_3,
0x02, 0x02);
snd_soc_component_update_bits(component,
WCD9XXX_CLASSH_MODE_2,
0xFF, 0x1C);
if (mode == CLS_H_LOHIFI || mode == CLS_AB_LOHIFI) {
snd_soc_component_update_bits(component,
WCD9XXX_HPH_NEW_INT_PA_MISC2,
0x20, 0x20);
snd_soc_component_update_bits(component,
WCD9XXX_RX_BIAS_HPH_LOWPOWER,
0xF0, 0xC0);
snd_soc_component_update_bits(component,
WCD9XXX_HPH_PA_CTL1,
0x0E, 0x02);
}
} else {
snd_soc_component_update_bits(component,
WCD9XXX_HPH_NEW_INT_PA_MISC2,
0x20, 0x00);
snd_soc_component_update_bits(component,
WCD9XXX_RX_BIAS_HPH_LOWPOWER,
0xF0, 0x80);
snd_soc_component_update_bits(component,
WCD9XXX_HPH_PA_CTL1,
0x0E, 0x06);
}
}
static void wcd_clsh_v3_flyback_ctrl(struct snd_soc_component *component,
struct wcd_clsh_ctrl *ctrl,
int mode,
bool enable)
{
/* enable/disable flyback */
if ((enable && (++ctrl->flyback_users == 1)) ||
(!enable && (--ctrl->flyback_users == 0))) {
snd_soc_component_update_bits(component,
WCD9XXX_FLYBACK_VNEG_CTRL_1,
0xE0, 0xE0);
snd_soc_component_update_bits(component,
WCD9XXX_ANA_RX_SUPPLIES,
(1 << 6), (enable << 6));
/*
* 100us sleep is required after flyback enable/disable
* as per HW requirement
*/
usleep_range(100, 110);
snd_soc_component_update_bits(component,
WCD9XXX_FLYBACK_VNEGDAC_CTRL_2,
0xE0, 0xE0);
/* 500usec delay is needed as per HW requirement */
usleep_range(500, 500 + WCD_USLEEP_RANGE);
}
}
static void wcd_clsh_v3_set_flyback_current(struct snd_soc_component *component,
int mode)
{
snd_soc_component_update_bits(component, WCD9XXX_V3_RX_BIAS_FLYB_BUFF,
0x0F, 0x0A);
snd_soc_component_update_bits(component, WCD9XXX_V3_RX_BIAS_FLYB_BUFF,
0xF0, 0xA0);
/* Sleep needed to avoid click and pop as per HW requirement */
usleep_range(100, 110);
}
static void wcd_clsh_v3_state_aux(struct wcd_clsh_ctrl *ctrl, int req_state,
bool is_enable, int mode)
{
struct snd_soc_component *component = ctrl->comp;
if (is_enable) {
wcd_clsh_v3_set_buck_mode(component, mode);
wcd_clsh_v3_set_flyback_mode(component, mode);
wcd_clsh_v3_flyback_ctrl(component, ctrl, mode, true);
wcd_clsh_v3_set_flyback_current(component, mode);
wcd_clsh_v3_buck_ctrl(component, ctrl, mode, true);
} else {
wcd_clsh_v3_buck_ctrl(component, ctrl, mode, false);
wcd_clsh_v3_flyback_ctrl(component, ctrl, mode, false);
wcd_clsh_v3_set_flyback_mode(component, CLS_H_NORMAL);
wcd_clsh_v3_set_buck_mode(component, CLS_H_NORMAL);
}
}
static void wcd_clsh_state_lo(struct wcd_clsh_ctrl *ctrl, int req_state,
bool is_enable, int mode)
{
struct snd_soc_component *comp = ctrl->comp;
if (mode != CLS_AB) {
dev_err(comp->dev, "%s: LO cannot be in this mode: %d\n",
__func__, mode);
return;
}
if (is_enable) {
wcd_clsh_set_buck_regulator_mode(comp, mode);
wcd_clsh_set_buck_mode(comp, mode);
wcd_clsh_set_flyback_mode(comp, mode);
wcd_clsh_flyback_ctrl(ctrl, mode, true);
wcd_clsh_set_flyback_current(comp, mode);
wcd_clsh_buck_ctrl(ctrl, mode, true);
} else {
wcd_clsh_buck_ctrl(ctrl, mode, false);
wcd_clsh_flyback_ctrl(ctrl, mode, false);
wcd_clsh_set_flyback_mode(comp, CLS_H_NORMAL);
wcd_clsh_set_buck_mode(comp, CLS_H_NORMAL);
wcd_clsh_set_buck_regulator_mode(comp, CLS_H_NORMAL);
}
}
static void wcd_clsh_v3_state_hph_r(struct wcd_clsh_ctrl *ctrl, int req_state,
bool is_enable, int mode)
{
struct snd_soc_component *component = ctrl->comp;
if (mode == CLS_H_NORMAL) {
dev_dbg(component->dev, "%s: Normal mode not applicable for hph_r\n",
__func__);
return;
}
if (is_enable) {
wcd_clsh_v3_set_buck_regulator_mode(component, mode);
wcd_clsh_v3_set_flyback_mode(component, mode);
wcd_clsh_v3_force_iq_ctl(component, mode, true);
wcd_clsh_v3_flyback_ctrl(component, ctrl, mode, true);
wcd_clsh_v3_set_flyback_current(component, mode);
wcd_clsh_v3_set_buck_mode(component, mode);
wcd_clsh_v3_buck_ctrl(component, ctrl, mode, true);
wcd_clsh_v3_set_hph_mode(component, mode);
} else {
wcd_clsh_v3_set_hph_mode(component, CLS_H_NORMAL);
/* buck and flyback set to default mode and disable */
wcd_clsh_v3_flyback_ctrl(component, ctrl, CLS_H_NORMAL, false);
wcd_clsh_v3_buck_ctrl(component, ctrl, CLS_H_NORMAL, false);
wcd_clsh_v3_force_iq_ctl(component, CLS_H_NORMAL, false);
wcd_clsh_v3_set_flyback_mode(component, CLS_H_NORMAL);
wcd_clsh_v3_set_buck_mode(component, CLS_H_NORMAL);
}
}
static void wcd_clsh_state_hph_r(struct wcd_clsh_ctrl *ctrl, int req_state,
bool is_enable, int mode)
{
struct snd_soc_component *comp = ctrl->comp;
if (mode == CLS_H_NORMAL) {
dev_err(comp->dev, "%s: Normal mode not applicable for hph_r\n",
__func__);
return;
}
if (is_enable) {
if (mode != CLS_AB) {
wcd_enable_clsh_block(ctrl, true);
/*
* These K1 values depend on the Headphone Impedance
* For now it is assumed to be 16 ohm
*/
snd_soc_component_update_bits(comp,
WCD9XXX_A_CDC_CLSH_K1_MSB,
WCD9XXX_A_CDC_CLSH_K1_MSB_COEF_MASK,
0x00);
snd_soc_component_update_bits(comp,
WCD9XXX_A_CDC_CLSH_K1_LSB,
WCD9XXX_A_CDC_CLSH_K1_LSB_COEF_MASK,
0xC0);
snd_soc_component_update_bits(comp,
WCD9XXX_A_CDC_RX2_RX_PATH_CFG0,
WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK,
WCD9XXX_A_CDC_RX_PATH_CLSH_ENABLE);
}
wcd_clsh_set_buck_regulator_mode(comp, mode);
wcd_clsh_set_flyback_mode(comp, mode);
wcd_clsh_flyback_ctrl(ctrl, mode, true);
wcd_clsh_set_flyback_current(comp, mode);
wcd_clsh_set_buck_mode(comp, mode);
wcd_clsh_buck_ctrl(ctrl, mode, true);
wcd_clsh_v2_set_hph_mode(comp, mode);
wcd_clsh_set_gain_path(ctrl, mode);
} else {
wcd_clsh_v2_set_hph_mode(comp, CLS_H_NORMAL);
if (mode != CLS_AB) {
snd_soc_component_update_bits(comp,
WCD9XXX_A_CDC_RX2_RX_PATH_CFG0,
WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK,
WCD9XXX_A_CDC_RX_PATH_CLSH_DISABLE);
wcd_enable_clsh_block(ctrl, false);
}
/* buck and flyback set to default mode and disable */
wcd_clsh_buck_ctrl(ctrl, CLS_H_NORMAL, false);
wcd_clsh_flyback_ctrl(ctrl, CLS_H_NORMAL, false);
wcd_clsh_set_flyback_mode(comp, CLS_H_NORMAL);
wcd_clsh_set_buck_mode(comp, CLS_H_NORMAL);
wcd_clsh_set_buck_regulator_mode(comp, CLS_H_NORMAL);
}
}
static void wcd_clsh_v3_state_hph_l(struct wcd_clsh_ctrl *ctrl, int req_state,
bool is_enable, int mode)
{
struct snd_soc_component *component = ctrl->comp;
if (mode == CLS_H_NORMAL) {
dev_dbg(component->dev, "%s: Normal mode not applicable for hph_l\n",
__func__);
return;
}
if (is_enable) {
wcd_clsh_v3_set_buck_regulator_mode(component, mode);
wcd_clsh_v3_set_flyback_mode(component, mode);
wcd_clsh_v3_force_iq_ctl(component, mode, true);
wcd_clsh_v3_flyback_ctrl(component, ctrl, mode, true);
wcd_clsh_v3_set_flyback_current(component, mode);
wcd_clsh_v3_set_buck_mode(component, mode);
wcd_clsh_v3_buck_ctrl(component, ctrl, mode, true);
wcd_clsh_v3_set_hph_mode(component, mode);
} else {
wcd_clsh_v3_set_hph_mode(component, CLS_H_NORMAL);
/* set buck and flyback to Default Mode */
wcd_clsh_v3_flyback_ctrl(component, ctrl, CLS_H_NORMAL, false);
wcd_clsh_v3_buck_ctrl(component, ctrl, CLS_H_NORMAL, false);
wcd_clsh_v3_force_iq_ctl(component, CLS_H_NORMAL, false);
wcd_clsh_v3_set_flyback_mode(component, CLS_H_NORMAL);
wcd_clsh_v3_set_buck_mode(component, CLS_H_NORMAL);
}
}
static void wcd_clsh_state_hph_l(struct wcd_clsh_ctrl *ctrl, int req_state,
bool is_enable, int mode)
{
struct snd_soc_component *comp = ctrl->comp;
if (mode == CLS_H_NORMAL) {
dev_err(comp->dev, "%s: Normal mode not applicable for hph_l\n",
__func__);
return;
}
if (is_enable) {
if (mode != CLS_AB) {
wcd_enable_clsh_block(ctrl, true);
/*
* These K1 values depend on the Headphone Impedance
* For now it is assumed to be 16 ohm
*/
snd_soc_component_update_bits(comp,
WCD9XXX_A_CDC_CLSH_K1_MSB,
WCD9XXX_A_CDC_CLSH_K1_MSB_COEF_MASK,
0x00);
snd_soc_component_update_bits(comp,
WCD9XXX_A_CDC_CLSH_K1_LSB,
WCD9XXX_A_CDC_CLSH_K1_LSB_COEF_MASK,
0xC0);
snd_soc_component_update_bits(comp,
WCD9XXX_A_CDC_RX1_RX_PATH_CFG0,
WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK,
WCD9XXX_A_CDC_RX_PATH_CLSH_ENABLE);
}
wcd_clsh_set_buck_regulator_mode(comp, mode);
wcd_clsh_set_flyback_mode(comp, mode);
wcd_clsh_flyback_ctrl(ctrl, mode, true);
wcd_clsh_set_flyback_current(comp, mode);
wcd_clsh_set_buck_mode(comp, mode);
wcd_clsh_buck_ctrl(ctrl, mode, true);
wcd_clsh_v2_set_hph_mode(comp, mode);
wcd_clsh_set_gain_path(ctrl, mode);
} else {
wcd_clsh_v2_set_hph_mode(comp, CLS_H_NORMAL);
if (mode != CLS_AB) {
snd_soc_component_update_bits(comp,
WCD9XXX_A_CDC_RX1_RX_PATH_CFG0,
WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK,
WCD9XXX_A_CDC_RX_PATH_CLSH_DISABLE);
wcd_enable_clsh_block(ctrl, false);
}
/* set buck and flyback to Default Mode */
wcd_clsh_buck_ctrl(ctrl, CLS_H_NORMAL, false);
wcd_clsh_flyback_ctrl(ctrl, CLS_H_NORMAL, false);
wcd_clsh_set_flyback_mode(comp, CLS_H_NORMAL);
wcd_clsh_set_buck_mode(comp, CLS_H_NORMAL);
wcd_clsh_set_buck_regulator_mode(comp, CLS_H_NORMAL);
}
}
static void wcd_clsh_v3_state_ear(struct wcd_clsh_ctrl *ctrl, int req_state,
bool is_enable, int mode)
{
struct snd_soc_component *component = ctrl->comp;
if (is_enable) {
wcd_clsh_v3_set_buck_regulator_mode(component, mode);
wcd_clsh_v3_set_flyback_mode(component, mode);
wcd_clsh_v3_force_iq_ctl(component, mode, true);
wcd_clsh_v3_flyback_ctrl(component, ctrl, mode, true);
wcd_clsh_v3_set_flyback_current(component, mode);
wcd_clsh_v3_set_buck_mode(component, mode);
wcd_clsh_v3_buck_ctrl(component, ctrl, mode, true);
wcd_clsh_v3_set_hph_mode(component, mode);
} else {
wcd_clsh_v3_set_hph_mode(component, CLS_H_NORMAL);
/* set buck and flyback to Default Mode */
wcd_clsh_v3_flyback_ctrl(component, ctrl, CLS_H_NORMAL, false);
wcd_clsh_v3_buck_ctrl(component, ctrl, CLS_H_NORMAL, false);
wcd_clsh_v3_force_iq_ctl(component, CLS_H_NORMAL, false);
wcd_clsh_v3_set_flyback_mode(component, CLS_H_NORMAL);
wcd_clsh_v3_set_buck_mode(component, CLS_H_NORMAL);
}
}
static void wcd_clsh_state_ear(struct wcd_clsh_ctrl *ctrl, int req_state,
bool is_enable, int mode)
{
struct snd_soc_component *comp = ctrl->comp;
if (mode != CLS_H_NORMAL) {
dev_err(comp->dev, "%s: mode: %d cannot be used for EAR\n",
__func__, mode);
return;
}
if (is_enable) {
wcd_enable_clsh_block(ctrl, true);
snd_soc_component_update_bits(comp,
WCD9XXX_A_CDC_RX0_RX_PATH_CFG0,
WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK,
WCD9XXX_A_CDC_RX_PATH_CLSH_ENABLE);
wcd_clsh_set_buck_mode(comp, mode);
wcd_clsh_set_flyback_mode(comp, mode);
wcd_clsh_flyback_ctrl(ctrl, mode, true);
wcd_clsh_set_flyback_current(comp, mode);
wcd_clsh_buck_ctrl(ctrl, mode, true);
} else {
snd_soc_component_update_bits(comp,
WCD9XXX_A_CDC_RX0_RX_PATH_CFG0,
WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK,
WCD9XXX_A_CDC_RX_PATH_CLSH_DISABLE);
wcd_enable_clsh_block(ctrl, false);
wcd_clsh_buck_ctrl(ctrl, mode, false);
wcd_clsh_flyback_ctrl(ctrl, mode, false);
wcd_clsh_set_flyback_mode(comp, CLS_H_NORMAL);
wcd_clsh_set_buck_mode(comp, CLS_H_NORMAL);
}
}
static int _wcd_clsh_ctrl_set_state(struct wcd_clsh_ctrl *ctrl, int req_state,
bool is_enable, int mode)
{
switch (req_state) {
case WCD_CLSH_STATE_EAR:
if (ctrl->codec_version >= WCD937X)
wcd_clsh_v3_state_ear(ctrl, req_state, is_enable, mode);
else
wcd_clsh_state_ear(ctrl, req_state, is_enable, mode);
break;
case WCD_CLSH_STATE_HPHL:
if (ctrl->codec_version >= WCD937X)
wcd_clsh_v3_state_hph_l(ctrl, req_state, is_enable, mode);
else
wcd_clsh_state_hph_l(ctrl, req_state, is_enable, mode);
break;
case WCD_CLSH_STATE_HPHR:
if (ctrl->codec_version >= WCD937X)
wcd_clsh_v3_state_hph_r(ctrl, req_state, is_enable, mode);
else
wcd_clsh_state_hph_r(ctrl, req_state, is_enable, mode);
break;
case WCD_CLSH_STATE_LO:
if (ctrl->codec_version < WCD937X)
wcd_clsh_state_lo(ctrl, req_state, is_enable, mode);
break;
case WCD_CLSH_STATE_AUX:
if (ctrl->codec_version >= WCD937X)
wcd_clsh_v3_state_aux(ctrl, req_state, is_enable, mode);
break;
default:
break;
}
return 0;
}
/*
* Function: wcd_clsh_is_state_valid
* Params: state
* Description:
* Provides information on valid states of Class H configuration
*/
static bool wcd_clsh_is_state_valid(int state)
{
switch (state) {
case WCD_CLSH_STATE_IDLE:
case WCD_CLSH_STATE_EAR:
case WCD_CLSH_STATE_HPHL:
case WCD_CLSH_STATE_HPHR:
case WCD_CLSH_STATE_LO:
case WCD_CLSH_STATE_AUX:
return true;
default:
return false;
};
}
/*
* Function: wcd_clsh_fsm
* Params: ctrl, req_state, req_type, clsh_event
* Description:
* This function handles PRE DAC and POST DAC conditions of different devices
* and updates class H configuration of different combination of devices
* based on validity of their states. ctrl will contain current
* class h state information
*/
int wcd_clsh_ctrl_set_state(struct wcd_clsh_ctrl *ctrl,
enum wcd_clsh_event clsh_event,
int nstate,
enum wcd_clsh_mode mode)
{
struct snd_soc_component *comp = ctrl->comp;
if (nstate == ctrl->state)
return 0;
if (!wcd_clsh_is_state_valid(nstate)) {
dev_err(comp->dev, "Class-H not a valid new state:\n");
return -EINVAL;
}
switch (clsh_event) {
case WCD_CLSH_EVENT_PRE_DAC:
_wcd_clsh_ctrl_set_state(ctrl, nstate, CLSH_REQ_ENABLE, mode);
break;
case WCD_CLSH_EVENT_POST_PA:
_wcd_clsh_ctrl_set_state(ctrl, nstate, CLSH_REQ_DISABLE, mode);
break;
}
ctrl->state = nstate;
ctrl->mode = mode;
return 0;
}
EXPORT_SYMBOL_GPL(wcd_clsh_ctrl_set_state);
int wcd_clsh_ctrl_get_state(struct wcd_clsh_ctrl *ctrl)
{
return ctrl->state;
}
EXPORT_SYMBOL_GPL(wcd_clsh_ctrl_get_state);
struct wcd_clsh_ctrl *wcd_clsh_ctrl_alloc(struct snd_soc_component *comp,
int version)
{
struct wcd_clsh_ctrl *ctrl;
ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
if (!ctrl)
return ERR_PTR(-ENOMEM);
ctrl->state = WCD_CLSH_STATE_IDLE;
ctrl->comp = comp;
ctrl->codec_version = version;
return ctrl;
}
EXPORT_SYMBOL_GPL(wcd_clsh_ctrl_alloc);
void wcd_clsh_ctrl_free(struct wcd_clsh_ctrl *ctrl)
{
kfree(ctrl);
}
EXPORT_SYMBOL_GPL(wcd_clsh_ctrl_free);
MODULE_DESCRIPTION("WCD93XX Class-H driver");
MODULE_LICENSE("GPL");
|
