1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Ptrace test TM SPR registers
*
* Copyright (C) 2015 Anshuman Khandual, IBM Corporation.
*/
#include "ptrace.h"
#include "tm.h"
/* Tracee and tracer shared data */
struct shared {
int flag;
struct tm_spr_regs regs;
};
unsigned long tfhar;
int shm_id;
struct shared *cptr, *pptr;
int shm_id1;
int *cptr1, *pptr1;
#define TM_KVM_SCHED 0xe0000001ac000001
int validate_tm_spr(struct tm_spr_regs *regs)
{
FAIL_IF(regs->tm_tfhar != tfhar);
FAIL_IF((regs->tm_texasr == TM_KVM_SCHED) && (regs->tm_tfiar != 0));
return TEST_PASS;
}
void tm_spr(void)
{
unsigned long result, texasr;
int ret;
cptr = (struct shared *)shmat(shm_id, NULL, 0);
cptr1 = (int *)shmat(shm_id1, NULL, 0);
trans:
cptr1[0] = 0;
asm __volatile__(
"1: ;"
/* TM failover handler should follow "tbegin.;" */
"mflr 31;"
"bl 4f;" /* $ = TFHAR - 12 */
"4: ;"
"mflr %[tfhar];"
"mtlr 31;"
"tbegin.;"
"beq 2f;"
"tsuspend.;"
"li 8, 1;"
"sth 8, 0(%[cptr1]);"
"tresume.;"
"b .;"
"tend.;"
"li 0, 0;"
"ori %[res], 0, 0;"
"b 3f;"
"2: ;"
"li 0, 1;"
"ori %[res], 0, 0;"
"mfspr %[texasr], %[sprn_texasr];"
"3: ;"
: [tfhar] "=r" (tfhar), [res] "=r" (result),
[texasr] "=r" (texasr), [cptr1] "=b" (cptr1)
: [sprn_texasr] "i" (SPRN_TEXASR)
: "memory", "r0", "r8", "r31"
);
/* There are 2 32bit instructions before tbegin. */
tfhar += 12;
if (result) {
if (!cptr->flag)
goto trans;
ret = validate_tm_spr((struct tm_spr_regs *)&cptr->regs);
shmdt((void *)cptr);
shmdt((void *)cptr1);
if (ret)
exit(1);
exit(0);
}
shmdt((void *)cptr);
shmdt((void *)cptr1);
exit(1);
}
int trace_tm_spr(pid_t child)
{
FAIL_IF(start_trace(child));
FAIL_IF(show_tm_spr(child, (struct tm_spr_regs *)&pptr->regs));
printf("TFHAR: %lx TEXASR: %lx TFIAR: %lx\n", pptr->regs.tm_tfhar,
pptr->regs.tm_texasr, pptr->regs.tm_tfiar);
pptr->flag = 1;
FAIL_IF(stop_trace(child));
return TEST_PASS;
}
int ptrace_tm_spr(void)
{
pid_t pid;
int ret, status;
SKIP_IF_MSG(!have_htm(), "Don't have transactional memory");
SKIP_IF_MSG(htm_is_synthetic(), "Transactional memory is synthetic");
shm_id = shmget(IPC_PRIVATE, sizeof(struct shared), 0777|IPC_CREAT);
shm_id1 = shmget(IPC_PRIVATE, sizeof(int), 0777|IPC_CREAT);
pid = fork();
if (pid < 0) {
perror("fork() failed");
return TEST_FAIL;
}
if (pid == 0)
tm_spr();
if (pid) {
pptr = (struct shared *)shmat(shm_id, NULL, 0);
pptr1 = (int *)shmat(shm_id1, NULL, 0);
while (!pptr1[0])
asm volatile("" : : : "memory");
ret = trace_tm_spr(pid);
if (ret) {
kill(pid, SIGKILL);
shmdt((void *)pptr);
shmdt((void *)pptr1);
shmctl(shm_id, IPC_RMID, NULL);
shmctl(shm_id1, IPC_RMID, NULL);
return TEST_FAIL;
}
shmdt((void *)pptr);
shmdt((void *)pptr1);
ret = wait(&status);
shmctl(shm_id, IPC_RMID, NULL);
shmctl(shm_id1, IPC_RMID, NULL);
if (ret != pid) {
printf("Child's exit status not captured\n");
return TEST_FAIL;
}
return (WIFEXITED(status) && WEXITSTATUS(status)) ? TEST_FAIL :
TEST_PASS;
}
return TEST_PASS;
}
int main(int argc, char *argv[])
{
return test_harness(ptrace_tm_spr, "ptrace_tm_spr");
}
|