diff options
Diffstat (limited to 'upstream/mageia-cauldron/man1/as.1')
| -rw-r--r-- | upstream/mageia-cauldron/man1/as.1 | 1603 |
1 files changed, 792 insertions, 811 deletions
diff --git a/upstream/mageia-cauldron/man1/as.1 b/upstream/mageia-cauldron/man1/as.1 index c7c2a85a..5477f0e3 100644 --- a/upstream/mageia-cauldron/man1/as.1 +++ b/upstream/mageia-cauldron/man1/as.1 @@ -1,4 +1,5 @@ -.\" Automatically generated by Pod::Man 4.14 (Pod::Simple 3.43) +.\" -*- mode: troff; coding: utf-8 -*- +.\" Automatically generated by Pod::Man 5.01 (Pod::Simple 3.43) .\" .\" Standard preamble: .\" ======================================================================== @@ -15,29 +16,12 @@ .ft R .fi .. -.\" Set up some character translations and predefined strings. \*(-- will -.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left -.\" double quote, and \*(R" will give a right double quote. \*(C+ will -.\" give a nicer C++. Capital omega is used to do unbreakable dashes and -.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, -.\" nothing in troff, for use with C<>. -.tr \(*W- -.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.\" \*(C` and \*(C' are quotes in nroff, nothing in troff, for use with C<>. .ie n \{\ -. ds -- \(*W- -. ds PI pi -. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch -. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch -. ds L" "" -. ds R" "" . ds C` "" . ds C' "" 'br\} .el\{\ -. ds -- \|\(em\| -. ds PI \(*p -. ds L" `` -. ds R" '' . ds C` . ds C' 'br\} @@ -68,81 +52,19 @@ . \} .\} .rr rF -.\" -.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). -.\" Fear. Run. Save yourself. No user-serviceable parts. -. \" fudge factors for nroff and troff -.if n \{\ -. ds #H 0 -. ds #V .8m -. ds #F .3m -. ds #[ \f1 -. ds #] \fP -.\} -.if t \{\ -. ds #H ((1u-(\\\\n(.fu%2u))*.13m) -. ds #V .6m -. ds #F 0 -. ds #[ \& -. ds #] \& -.\} -. \" simple accents for nroff and troff -.if n \{\ -. ds ' \& -. ds ` \& -. ds ^ \& -. ds , \& -. ds ~ ~ -. ds / -.\} -.if t \{\ -. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" -. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' -. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' -. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' -. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' -. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' -.\} -. \" troff and (daisy-wheel) nroff accents -.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' -.ds 8 \h'\*(#H'\(*b\h'-\*(#H' -.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] -.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' -.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' -.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] -.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] -.ds ae a\h'-(\w'a'u*4/10)'e -.ds Ae A\h'-(\w'A'u*4/10)'E -. \" corrections for vroff -.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' -.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' -. \" for low resolution devices (crt and lpr) -.if \n(.H>23 .if \n(.V>19 \ -\{\ -. ds : e -. ds 8 ss -. ds o a -. ds d- d\h'-1'\(ga -. ds D- D\h'-1'\(hy -. ds th \o'bp' -. ds Th \o'LP' -. ds ae ae -. ds Ae AE -.\} -.rm #[ #] #H #V #F C .\" ======================================================================== .\" .IX Title "AS 1" -.TH AS 1 "2023-06-27" "binutils-2.40" "GNU Development Tools" +.TH AS 1 2024-04-08 binutils-2.42 "GNU Development Tools" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l .nh -.SH "NAME" +.SH NAME AS \- the portable GNU assembler. -.SH "SYNOPSIS" +.SH SYNOPSIS .IX Header "SYNOPSIS" -as [\fB\-a\fR[\fBcdghlns\fR][=\fIfile\fR]] +as [\fB\-a\fR[\fBcdghilns\fR][=\fIfile\fR]] [\fB\-\-alternate\fR] [\fB\-\-compress\-debug\-sections\fR] [\fB\-\-nocompress\-debug\-sections\fR] [\fB\-D\fR] @@ -154,7 +76,7 @@ as [\fB\-a\fR[\fBcdghlns\fR][=\fIfile\fR]] [\fB\-f\fR] [\fB\-g\fR] [\fB\-\-gstabs\fR] [\fB\-\-gstabs+\fR] [\fB\-\-gdwarf\-<N>\fR] [\fB\-\-gdwarf\-sections\fR] - [\fB\-\-gdwarf\-cie\-version\fR=\fI\s-1VERSION\s0\fR] + [\fB\-\-gdwarf\-cie\-version\fR=\fIVERSION\fR] [\fB\-\-generate\-missing\-build\-notes=[no|yes]\fR] [\fB\-\-gsframe\fR] [\fB\-\-hash\-size\fR=\fIN\fR] @@ -164,26 +86,27 @@ as [\fB\-a\fR[\fBcdghlns\fR][=\fIfile\fR]] [\fB\-K\fR] [\fB\-\-keep\-locals\fR] [\fB\-L\fR] - [\fB\-\-listing\-lhs\-width\fR=\fI\s-1NUM\s0\fR] - [\fB\-\-listing\-lhs\-width2\fR=\fI\s-1NUM\s0\fR] - [\fB\-\-listing\-rhs\-width\fR=\fI\s-1NUM\s0\fR] - [\fB\-\-listing\-cont\-lines\fR=\fI\s-1NUM\s0\fR] + [\fB\-\-listing\-lhs\-width\fR=\fINUM\fR] + [\fB\-\-listing\-lhs\-width2\fR=\fINUM\fR] + [\fB\-\-listing\-rhs\-width\fR=\fINUM\fR] + [\fB\-\-listing\-cont\-lines\fR=\fINUM\fR] [\fB\-\-multibyte\-handling=[allow|warn|warn\-sym\-only]\fR] [\fB\-\-no\-pad\-sections\fR] [\fB\-o\fR \fIobjfile\fR] [\fB\-R\fR] + [\fB\-\-scfi=experimental\fR] [\fB\-\-sectname\-subst\fR] [\fB\-\-size\-check=[error|warning]\fR] [\fB\-\-statistics\fR] [\fB\-v\fR] [\fB\-version\fR] [\fB\-\-version\fR] [\fB\-W\fR] [\fB\-\-warn\fR] [\fB\-\-fatal\-warnings\fR] [\fB\-w\fR] [\fB\-x\fR] - [\fB\-Z\fR] [\fB@\fR\fI\s-1FILE\s0\fR] + [\fB\-Z\fR] [\fB@\fR\fIFILE\fR] [\fItarget-options\fR] [\fB\-\-\fR|\fIfiles\fR ...] -.SH "TARGET" +.SH TARGET .IX Header "TARGET" \&\fITarget AArch64 options:\fR [\fB\-EB\fR|\fB\-EL\fR] - [\fB\-mabi\fR=\fI\s-1ABI\s0\fR] + [\fB\-mabi\fR=\fIABI\fR] .PP \&\fITarget Alpha options:\fR [\fB\-m\fR\fIcpu\fR] @@ -192,14 +115,14 @@ as [\fB\-a\fR[\fBcdghlns\fR][=\fIfile\fR]] [\fB\-relax\fR] [\fB\-g\fR] [\fB\-G\fR\fIsize\fR] [\fB\-F\fR] [\fB\-32addr\fR] .PP -\&\fITarget \s-1ARC\s0 options:\fR +\&\fITarget ARC options:\fR [\fB\-mcpu=\fR\fIcpu\fR] [\fB\-mA6\fR|\fB\-mARC600\fR|\fB\-mARC601\fR|\fB\-mA7\fR|\fB\-mARC700\fR|\fB\-mEM\fR|\fB\-mHS\fR] [\fB\-mcode\-density\fR] [\fB\-mrelax\fR] [\fB\-EB\fR|\fB\-EL\fR] .PP -\&\fITarget \s-1ARM\s0 options:\fR +\&\fITarget ARM options:\fR [\fB\-mcpu\fR=\fIprocessor\fR[+\fIextension\fR...]] [\fB\-march\fR=\fIarchitecture\fR[+\fIextension\fR...]] [\fB\-mfpu\fR=\fIfloating-point-format\fR] @@ -217,10 +140,10 @@ as [\fB\-a\fR[\fBcdghlns\fR][=\fIfile\fR]] [\fB\-mno\-fdpic\fR] [\fB\-mnopic\fR] .PP -\&\fITarget \s-1BPF\s0 options:\fR +\&\fITarget BPF options:\fR [\fB\-EL\fR] [\fB\-EB\fR] .PP -\&\fITarget \s-1CRIS\s0 options:\fR +\&\fITarget CRIS options:\fR [\fB\-\-underscore\fR | \fB\-\-no\-underscore\fR] [\fB\-\-pic\fR] [\fB\-N\fR] [\fB\-\-emulation=criself\fR | \fB\-\-emulation=crisaout\fR] @@ -250,7 +173,7 @@ as [\fB\-a\fR[\fBcdghlns\fR][=\fIfile\fR]] \&\fITarget D30V options:\fR [\fB\-O\fR|\fB\-n\fR|\fB\-N\fR] .PP -\&\fITarget \s-1EPIPHANY\s0 options:\fR +\&\fITarget EPIPHANY options:\fR [\fB\-mepiphany\fR|\fB\-mepiphany16\fR] .PP \&\fITarget H8/300 options:\fR @@ -258,9 +181,9 @@ as [\fB\-a\fR[\fBcdghlns\fR][=\fIfile\fR]] .PP \&\fITarget i386 options:\fR [\fB\-\-32\fR|\fB\-\-x32\fR|\fB\-\-64\fR] [\fB\-n\fR] - [\fB\-march\fR=\fI\s-1CPU\s0\fR[+\fI\s-1EXTENSION\s0\fR...]] [\fB\-mtune\fR=\fI\s-1CPU\s0\fR] + [\fB\-march\fR=\fICPU\fR[+\fIEXTENSION\fR...]] [\fB\-mtune\fR=\fICPU\fR] .PP -\&\fITarget \s-1IA\-64\s0 options:\fR +\&\fITarget IA\-64 options:\fR [\fB\-mconstant\-gp\fR|\fB\-mauto\-pic\fR] [\fB\-milp32\fR|\fB\-milp64\fR|\fB\-mlp64\fR|\fB\-mp64\fR] [\fB\-mle\fR|\fBmbe\fR] @@ -269,7 +192,7 @@ as [\fB\-a\fR[\fBcdghlns\fR][=\fIfile\fR]] [\fB\-mhint.b=ok\fR|\fB\-mhint.b=warning\fR|\fB\-mhint.b=error\fR] [\fB\-x\fR|\fB\-xexplicit\fR] [\fB\-xauto\fR] [\fB\-xdebug\fR] .PP -\&\fITarget \s-1IP2K\s0 options:\fR +\&\fITarget IP2K options:\fR [\fB\-mip2022\fR|\fB\-mip2022ext\fR] .PP \&\fITarget M32C options:\fR @@ -290,22 +213,23 @@ as [\fB\-a\fR[\fBcdghlns\fR][=\fIfile\fR]] [\fB\-\-strict\-direct\-mode\fR] [\fB\-\-print\-insn\-syntax\fR] [\fB\-\-print\-opcodes\fR] [\fB\-\-generate\-example\fR] .PP -\&\fITarget \s-1MCORE\s0 options:\fR +\&\fITarget MCORE options:\fR [\fB\-jsri2bsr\fR] [\fB\-sifilter\fR] [\fB\-relax\fR] [\fB\-mcpu=[210|340]\fR] .PP \&\fITarget Meta options:\fR [\fB\-mcpu=\fR\fIcpu\fR] [\fB\-mfpu=\fR\fIcpu\fR] [\fB\-mdsp=\fR\fIcpu\fR] -\&\fITarget \s-1MICROBLAZE\s0 options:\fR +\&\fITarget MICROBLAZE options:\fR + [\fB\-mlittle\-endian\fR] [\fB\-mbig\-endian\fR] .PP -\&\fITarget \s-1MIPS\s0 options:\fR +\&\fITarget MIPS options:\fR [\fB\-nocpp\fR] [\fB\-EL\fR] [\fB\-EB\fR] [\fB\-O\fR[\fIoptimization level\fR]] [\fB\-g\fR[\fIdebug level\fR]] [\fB\-G\fR \fInum\fR] [\fB\-KPIC\fR] [\fB\-call_shared\fR] [\fB\-non_shared\fR] [\fB\-xgot\fR [\fB\-mvxworks\-pic\fR] - [\fB\-mabi\fR=\fI\s-1ABI\s0\fR] [\fB\-32\fR] [\fB\-n32\fR] [\fB\-64\fR] [\fB\-mfp32\fR] [\fB\-mgp32\fR] + [\fB\-mabi\fR=\fIABI\fR] [\fB\-32\fR] [\fB\-n32\fR] [\fB\-64\fR] [\fB\-mfp32\fR] [\fB\-mgp32\fR] [\fB\-mfp64\fR] [\fB\-mgp64\fR] [\fB\-mfpxx\fR] [\fB\-modd\-spreg\fR] [\fB\-mno\-odd\-spreg\fR] - [\fB\-march\fR=\fI\s-1CPU\s0\fR] [\fB\-mtune\fR=\fI\s-1CPU\s0\fR] [\fB\-mips1\fR] [\fB\-mips2\fR] + [\fB\-march\fR=\fICPU\fR] [\fB\-mtune\fR=\fICPU\fR] [\fB\-mips1\fR] [\fB\-mips2\fR] [\fB\-mips3\fR] [\fB\-mips4\fR] [\fB\-mips5\fR] [\fB\-mips32\fR] [\fB\-mips32r2\fR] [\fB\-mips32r3\fR] [\fB\-mips32r5\fR] [\fB\-mips32r6\fR] [\fB\-mips64\fR] [\fB\-mips64r2\fR] [\fB\-mips64r3\fR] [\fB\-mips64r5\fR] [\fB\-mips64r6\fR] @@ -341,27 +265,27 @@ as [\fB\-a\fR[\fBcdghlns\fR][=\fIfile\fR]] [\fB\-mdebug\fR] [\fB\-no\-mdebug\fR] [\fB\-mpdr\fR] [\fB\-mno\-pdr\fR] .PP -\&\fITarget \s-1MMIX\s0 options:\fR +\&\fITarget MMIX options:\fR [\fB\-\-fixed\-special\-register\-names\fR] [\fB\-\-globalize\-symbols\fR] [\fB\-\-gnu\-syntax\fR] [\fB\-\-relax\fR] [\fB\-\-no\-predefined\-symbols\fR] [\fB\-\-no\-expand\fR] [\fB\-\-no\-merge\-gregs\fR] [\fB\-x\fR] [\fB\-\-linker\-allocated\-gregs\fR] .PP -\&\fITarget Nios \s-1II\s0 options:\fR +\&\fITarget Nios II options:\fR [\fB\-relax\-all\fR] [\fB\-relax\-section\fR] [\fB\-no\-relax\fR] [\fB\-EB\fR] [\fB\-EL\fR] .PP -\&\fITarget \s-1NDS32\s0 options:\fR +\&\fITarget NDS32 options:\fR [\fB\-EL\fR] [\fB\-EB\fR] [\fB\-O\fR] [\fB\-Os\fR] [\fB\-mcpu=\fR\fIcpu\fR] [\fB\-misa=\fR\fIisa\fR] [\fB\-mabi=\fR\fIabi\fR] [\fB\-mall\-ext\fR] [\fB\-m[no\-]16\-bit\fR] [\fB\-m[no\-]perf\-ext\fR] [\fB\-m[no\-]perf2\-ext\fR] [\fB\-m[no\-]string\-ext\fR] [\fB\-m[no\-]dsp\-ext\fR] [\fB\-m[no\-]mac\fR] [\fB\-m[no\-]div\fR] [\fB\-m[no\-]audio\-isa\-ext\fR] [\fB\-m[no\-]fpu\-sp\-ext\fR] [\fB\-m[no\-]fpu\-dp\-ext\fR] - [\fB\-m[no\-]fpu\-fma\fR] [\fB\-mfpu\-freg=\fR\fI\s-1FREG\s0\fR] [\fB\-mreduced\-regs\fR] + [\fB\-m[no\-]fpu\-fma\fR] [\fB\-mfpu\-freg=\fR\fIFREG\fR] [\fB\-mreduced\-regs\fR] [\fB\-mfull\-regs\fR] [\fB\-m[no\-]dx\-regs\fR] [\fB\-mpic\fR] [\fB\-mno\-relax\fR] [\fB\-mb2bb\fR] .PP -\&\fITarget \s-1PDP11\s0 options:\fR +\&\fITarget PDP11 options:\fR [\fB\-mpic\fR|\fB\-mno\-pic\fR] [\fB\-mall\fR] [\fB\-mno\-extensions\fR] [\fB\-m\fR\fIextension\fR|\fB\-mno\-\fR\fIextension\fR] [\fB\-m\fR\fIcpu\fR] [\fB\-m\fR\fImachine\fR] @@ -379,27 +303,27 @@ as [\fB\-a\fR[\fBcdghlns\fR][=\fIfile\fR]] \fB\-mcell\fR|\fB\-mspe\fR|\fB\-mspe2\fR|\fB\-mtitan\fR|\fB\-me300\fR|\fB\-mcom\fR] [\fB\-many\fR] [\fB\-maltivec\fR|\fB\-mvsx\fR|\fB\-mhtm\fR|\fB\-mvle\fR] [\fB\-mregnames\fR|\fB\-mno\-regnames\fR] - [\fB\-mrelocatable\fR|\fB\-mrelocatable\-lib\fR|\fB\-K \s-1PIC\s0\fR] [\fB\-memb\fR] + [\fB\-mrelocatable\fR|\fB\-mrelocatable\-lib\fR|\fB\-K PIC\fR] [\fB\-memb\fR] [\fB\-mlittle\fR|\fB\-mlittle\-endian\fR|\fB\-le\fR|\fB\-mbig\fR|\fB\-mbig\-endian\fR|\fB\-be\fR] [\fB\-msolaris\fR|\fB\-mno\-solaris\fR] [\fB\-nops=\fR\fIcount\fR] .PP -\&\fITarget \s-1PRU\s0 options:\fR +\&\fITarget PRU options:\fR [\fB\-link\-relax\fR] [\fB\-mnolink\-relax\fR] [\fB\-mno\-warn\-regname\-label\fR] .PP \&\fITarget RISC-V options:\fR [\fB\-fpic\fR|\fB\-fPIC\fR|\fB\-fno\-pic\fR] - [\fB\-march\fR=\fI\s-1ISA\s0\fR] - [\fB\-mabi\fR=\fI\s-1ABI\s0\fR] + [\fB\-march\fR=\fIISA\fR] + [\fB\-mabi\fR=\fIABI\fR] [\fB\-mlittle\-endian\fR|\fB\-mbig\-endian\fR] .PP -\&\fITarget \s-1RL78\s0 options:\fR +\&\fITarget RL78 options:\fR [\fB\-mg10\fR] [\fB\-m32bit\-doubles\fR|\fB\-m64bit\-doubles\fR] .PP -\&\fITarget \s-1RX\s0 options:\fR +\&\fITarget RX options:\fR [\fB\-mlittle\-endian\fR|\fB\-mbig\-endian\fR] [\fB\-m32bit\-doubles\fR|\fB\-m64bit\-doubles\fR] [\fB\-muse\-conventional\-section\-names\fR] @@ -410,17 +334,17 @@ as [\fB\-a\fR[\fBcdghlns\fR][=\fIfile\fR]] [\fB\-mgcc\-abi\fR|\fB\-mrx\-abi\fR] .PP \&\fITarget s390 options:\fR - [\fB\-m31\fR|\fB\-m64\fR] [\fB\-mesa\fR|\fB\-mzarch\fR] [\fB\-march\fR=\fI\s-1CPU\s0\fR] + [\fB\-m31\fR|\fB\-m64\fR] [\fB\-mesa\fR|\fB\-mzarch\fR] [\fB\-march\fR=\fICPU\fR] [\fB\-mregnames\fR|\fB\-mno\-regnames\fR] [\fB\-mwarn\-areg\-zero\fR] .PP -\&\fITarget \s-1SCORE\s0 options:\fR +\&\fITarget SCORE options:\fR [\fB\-EB\fR][\fB\-EL\fR][\fB\-FIXDD\fR][\fB\-NWARN\fR] [\fB\-SCORE5\fR][\fB\-SCORE5U\fR][\fB\-SCORE7\fR][\fB\-SCORE3\fR] [\fB\-march=score7\fR][\fB\-march=score3\fR] [\fB\-USE_R1\fR][\fB\-KPIC\fR][\fB\-O0\fR][\fB\-G\fR \fInum\fR][\fB\-V\fR] .PP -\&\fITarget \s-1SPARC\s0 options:\fR +\&\fITarget SPARC options:\fR [\fB\-Av6\fR|\fB\-Av7\fR|\fB\-Av8\fR|\fB\-Aleon\fR|\fB\-Asparclet\fR|\fB\-Asparclite\fR \fB\-Av8plus\fR|\fB\-Av8plusa\fR|\fB\-Av8plusb\fR|\fB\-Av8plusc\fR|\fB\-Av8plusd\fR \fB\-Av8plusv\fR|\fB\-Av8plusm\fR|\fB\-Av9\fR|\fB\-Av9a\fR|\fB\-Av9b\fR|\fB\-Av9c\fR @@ -437,11 +361,11 @@ as [\fB\-a\fR[\fBcdghlns\fR][=\fIfile\fR]] [\fB\-32\fR|\fB\-64\fR] [\fB\-\-enforce\-aligned\-data\fR][\fB\-\-dcti\-couples\-detect\fR] .PP -\&\fITarget \s-1TIC54X\s0 options:\fR +\&\fITarget TIC54X options:\fR [\fB\-mcpu=54[123589]\fR|\fB\-mcpu=54[56]lp\fR] [\fB\-mfar\-mode\fR|\fB\-mf\fR] [\fB\-merrors\-to\-file\fR \fI<filename>\fR|\fB\-me\fR \fI<filename>\fR] .PP -\&\fITarget \s-1TIC6X\s0 options:\fR +\&\fITarget TIC6X options:\fR [\fB\-march=\fR\fIarch\fR] [\fB\-mbig\-endian\fR|\fB\-mlittle\-endian\fR] [\fB\-mdsbt\fR|\fB\-mno\-dsbt\fR] [\fB\-mpid=no\fR|\fB\-mpid=near\fR|\fB\-mpid=far\fR] [\fB\-mpic\fR|\fB\-mno\-pic\fR] @@ -462,23 +386,23 @@ as [\fB\-a\fR[\fBcdghlns\fR][=\fIfile\fR]] [\fB\-\-abi\-windowed\fR|\fB\-\-abi\-call0\fR] .PP \&\fITarget Z80 options:\fR - [\fB\-march=\fR\fI\s-1CPU\s0\fR\fI[\-EXT]\fR\fI[+EXT]\fR] - [\fB\-local\-prefix=\fR\fI\s-1PREFIX\s0\fR] + [\fB\-march=\fR\fICPU\fR\fI[\-EXT]\fR\fI[+EXT]\fR] + [\fB\-local\-prefix=\fR\fIPREFIX\fR] [\fB\-colonless\fR] [\fB\-sdcc\fR] - [\fB\-fp\-s=\fR\fI\s-1FORMAT\s0\fR] - [\fB\-fp\-d=\fR\fI\s-1FORMAT\s0\fR] -.SH "DESCRIPTION" + [\fB\-fp\-s=\fR\fIFORMAT\fR] + [\fB\-fp\-d=\fR\fIFORMAT\fR] +.SH DESCRIPTION .IX Header "DESCRIPTION" -\&\s-1GNU\s0 \fBas\fR is really a family of assemblers. -If you use (or have used) the \s-1GNU\s0 assembler on one architecture, you +GNU \fBas\fR is really a family of assemblers. +If you use (or have used) the GNU assembler on one architecture, you should find a fairly similar environment when you use it on another architecture. Each version has much in common with the others, including object file formats, most assembler directives (often called \&\fIpseudo-ops\fR) and assembler syntax. .PP \&\fBas\fR is primarily intended to assemble the output of the -\&\s-1GNU C\s0 compiler \f(CW\*(C`gcc\*(C'\fR for use by the linker +GNU C compiler \f(CW\*(C`gcc\*(C'\fR for use by the linker \&\f(CW\*(C`ld\*(C'\fR. Nevertheless, we've tried to make \fBas\fR assemble correctly everything that other assemblers for the same machine would assemble. @@ -513,7 +437,7 @@ runs \fBas\fR automatically. Warnings report an assumption made so that \fBas\fR could keep assembling a flawed program; errors report a grave problem that stops the assembly. .PP -If you are invoking \fBas\fR via the \s-1GNU C\s0 compiler, +If you are invoking \fBas\fR via the GNU C compiler, you can use the \fB\-Wa\fR option to pass arguments through to the assembler. The assembler arguments must be separated from each other (and the \fB\-Wa\fR) by commas. For example: @@ -528,12 +452,12 @@ local symbols in the symbol table). .PP Usually you do not need to use this \fB\-Wa\fR mechanism, since many compiler command-line options are automatically passed to the assembler by the compiler. -(You can call the \s-1GNU\s0 compiler driver with the \fB\-v\fR option to see +(You can call the GNU compiler driver with the \fB\-v\fR option to see precisely what options it passes to each compilation pass, including the assembler.) -.SH "OPTIONS" +.SH OPTIONS .IX Header "OPTIONS" -.IP "\fB@\fR\fIfile\fR" 4 +.IP \fB@\fR\fIfile\fR 4 .IX Item "@file" Read command-line options from \fIfile\fR. The options read are inserted in place of the original @\fIfile\fR option. If \fIfile\fR @@ -546,35 +470,38 @@ option in either single or double quotes. Any character (including a backslash) may be included by prefixing the character to be included with a backslash. The \fIfile\fR may itself contain additional @\fIfile\fR options; any such options will be processed recursively. -.IP "\fB\-a[cdghlmns]\fR" 4 -.IX Item "-a[cdghlmns]" +.IP \fB\-a[cdghilmns]\fR 4 +.IX Item "-a[cdghilmns]" Turn on listings, in any of a variety of ways: .RS 4 -.IP "\fB\-ac\fR" 4 +.IP \fB\-ac\fR 4 .IX Item "-ac" omit false conditionals -.IP "\fB\-ad\fR" 4 +.IP \fB\-ad\fR 4 .IX Item "-ad" omit debugging directives -.IP "\fB\-ag\fR" 4 +.IP \fB\-ag\fR 4 .IX Item "-ag" include general information, like as version and options passed -.IP "\fB\-ah\fR" 4 +.IP \fB\-ah\fR 4 .IX Item "-ah" include high-level source -.IP "\fB\-al\fR" 4 +.IP \fB\-al\fR 4 .IX Item "-al" include assembly -.IP "\fB\-am\fR" 4 +.IP \fB\-ali\fR 4 +.IX Item "-ali" +include assembly with ginsn +.IP \fB\-am\fR 4 .IX Item "-am" include macro expansions -.IP "\fB\-an\fR" 4 +.IP \fB\-an\fR 4 .IX Item "-an" omit forms processing -.IP "\fB\-as\fR" 4 +.IP \fB\-as\fR 4 .IX Item "-as" include symbols -.IP "\fB=file\fR" 4 +.IP \fB=file\fR 4 .IX Item "=file" set the name of the listing file .RE @@ -584,53 +511,53 @@ You may combine these options; for example, use \fB\-aln\fR for assembly listing without forms processing. The \fB=file\fR option, if used, must be the last one. By itself, \fB\-a\fR defaults to \fB\-ahls\fR. .RE -.IP "\fB\-\-alternate\fR" 4 +.IP \fB\-\-alternate\fR 4 .IX Item "--alternate" Begin in alternate macro mode. -.IP "\fB\-\-compress\-debug\-sections\fR" 4 +.IP \fB\-\-compress\-debug\-sections\fR 4 .IX Item "--compress-debug-sections" -Compress \s-1DWARF\s0 debug sections using zlib with \s-1SHF_COMPRESSED\s0 from the -\&\s-1ELF ABI.\s0 The resulting object file may not be compatible with older +Compress DWARF debug sections using zlib with SHF_COMPRESSED from the +ELF ABI. The resulting object file may not be compatible with older linkers and object file utilities. Note if compression would make a given section \fIlarger\fR then it is not compressed. -.IP "\fB\-\-compress\-debug\-sections=none\fR" 4 +.IP \fB\-\-compress\-debug\-sections=none\fR 4 .IX Item "--compress-debug-sections=none" .PD 0 -.IP "\fB\-\-compress\-debug\-sections=zlib\fR" 4 +.IP \fB\-\-compress\-debug\-sections=zlib\fR 4 .IX Item "--compress-debug-sections=zlib" -.IP "\fB\-\-compress\-debug\-sections=zlib\-gnu\fR" 4 +.IP \fB\-\-compress\-debug\-sections=zlib\-gnu\fR 4 .IX Item "--compress-debug-sections=zlib-gnu" -.IP "\fB\-\-compress\-debug\-sections=zlib\-gabi\fR" 4 +.IP \fB\-\-compress\-debug\-sections=zlib\-gabi\fR 4 .IX Item "--compress-debug-sections=zlib-gabi" -.IP "\fB\-\-compress\-debug\-sections=zstd\fR" 4 +.IP \fB\-\-compress\-debug\-sections=zstd\fR 4 .IX Item "--compress-debug-sections=zstd" .PD -These options control how \s-1DWARF\s0 debug sections are compressed. +These options control how DWARF debug sections are compressed. \&\fB\-\-compress\-debug\-sections=none\fR is equivalent to \&\fB\-\-nocompress\-debug\-sections\fR. \&\fB\-\-compress\-debug\-sections=zlib\fR and \&\fB\-\-compress\-debug\-sections=zlib\-gabi\fR are equivalent to \&\fB\-\-compress\-debug\-sections\fR. -\&\fB\-\-compress\-debug\-sections=zlib\-gnu\fR compresses \s-1DWARF\s0 debug sections +\&\fB\-\-compress\-debug\-sections=zlib\-gnu\fR compresses DWARF debug sections using the obsoleted zlib-gnu format. The debug sections are renamed to begin with \fB.zdebug\fR. -\&\fB\-\-compress\-debug\-sections=zstd\fR compresses \s-1DWARF\s0 debug +\&\fB\-\-compress\-debug\-sections=zstd\fR compresses DWARF debug sections using zstd. Note \- if compression would actually make a section \&\fIlarger\fR, then it is not compressed nor renamed. -.IP "\fB\-\-nocompress\-debug\-sections\fR" 4 +.IP \fB\-\-nocompress\-debug\-sections\fR 4 .IX Item "--nocompress-debug-sections" -Do not compress \s-1DWARF\s0 debug sections. This is usually the default for all +Do not compress DWARF debug sections. This is usually the default for all targets except the x86/x86_64, but a configure time option can be used to override this. -.IP "\fB\-D\fR" 4 +.IP \fB\-D\fR 4 .IX Item "-D" -Enable denugging in target specific backends, if supported. Otherwise ignored. +Enable debugging in target specific backends, if supported. Otherwise ignored. Even if ignored, this option is accepted for script compatibility with calls to other assemblers. .IP "\fB\-\-debug\-prefix\-map\fR \fIold\fR\fB=\fR\fInew\fR" 4 .IX Item "--debug-prefix-map old=new" -When assembling files in directory \fI\fIold\fI\fR, record debugging -information describing them as in \fI\fInew\fI\fR instead. +When assembling files in directory \fIold\fR, record debugging +information describing them as in \fInew\fR instead. .IP "\fB\-\-defsym\fR \fIsym\fR\fB=\fR\fIvalue\fR" 4 .IX Item "--defsym sym=value" Define the symbol \fIsym\fR to be \fIvalue\fR before assembling the input file. @@ -638,75 +565,75 @@ Define the symbol \fIsym\fR to be \fIvalue\fR before assembling the input file. indicates a hexadecimal value, and a leading \fB0\fR indicates an octal value. The value of the symbol can be overridden inside a source file via the use of a \f(CW\*(C`.set\*(C'\fR pseudo-op. -.IP "\fB\-\-dump\-config\fR" 4 +.IP \fB\-\-dump\-config\fR 4 .IX Item "--dump-config" Displays how the assembler is configured and then exits. -.IP "\fB\-\-elf\-stt\-common=no\fR" 4 +.IP \fB\-\-elf\-stt\-common=no\fR 4 .IX Item "--elf-stt-common=no" .PD 0 -.IP "\fB\-\-elf\-stt\-common=yes\fR" 4 +.IP \fB\-\-elf\-stt\-common=yes\fR 4 .IX Item "--elf-stt-common=yes" .PD -These options control whether the \s-1ELF\s0 assembler should generate common +These options control whether the ELF assembler should generate common symbols with the \f(CW\*(C`STT_COMMON\*(C'\fR type. The default can be controlled by a configure option \fB\-\-enable\-elf\-stt\-common\fR. -.IP "\fB\-\-emulation=\fR\fIname\fR" 4 +.IP \fB\-\-emulation=\fR\fIname\fR 4 .IX Item "--emulation=name" If the assembler is configured to support multiple different target configurations then this option can be used to select the desired form. -.IP "\fB\-f\fR" 4 +.IP \fB\-f\fR 4 .IX Item "-f" -\&\*(L"fast\*(R"\-\-\-skip whitespace and comment preprocessing (assume source is +"fast"\-\-\-skip whitespace and comment preprocessing (assume source is compiler output). -.IP "\fB\-g\fR" 4 +.IP \fB\-g\fR 4 .IX Item "-g" .PD 0 -.IP "\fB\-\-gen\-debug\fR" 4 +.IP \fB\-\-gen\-debug\fR 4 .IX Item "--gen-debug" .PD Generate debugging information for each assembler source line using whichever -debug format is preferred by the target. This currently means either \s-1STABS, -ECOFF\s0 or \s-1DWARF2.\s0 When the debug format is \s-1DWARF\s0 then a \f(CW\*(C`.debug_info\*(C'\fR and +debug format is preferred by the target. This currently means either STABS, +ECOFF or DWARF2. When the debug format is DWARF then a \f(CW\*(C`.debug_info\*(C'\fR and \&\f(CW\*(C`.debug_line\*(C'\fR section is only emitted when the assembly file doesn't generate one itself. -.IP "\fB\-\-gstabs\fR" 4 +.IP \fB\-\-gstabs\fR 4 .IX Item "--gstabs" Generate stabs debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it. -.IP "\fB\-\-gstabs+\fR" 4 +.IP \fB\-\-gstabs+\fR 4 .IX Item "--gstabs+" -Generate stabs debugging information for each assembler line, with \s-1GNU\s0 +Generate stabs debugging information for each assembler line, with GNU extensions that probably only gdb can handle, and that could make other debuggers crash or refuse to read your program. This -may help debugging assembler code. Currently the only \s-1GNU\s0 extension is +may help debugging assembler code. Currently the only GNU extension is the location of the current working directory at assembling time. -.IP "\fB\-\-gdwarf\-2\fR" 4 +.IP \fB\-\-gdwarf\-2\fR 4 .IX Item "--gdwarf-2" -Generate \s-1DWARF2\s0 debugging information for each assembler line. This +Generate DWARF2 debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it. Note\-\-\-this option is only supported by some targets, not all of them. -.IP "\fB\-\-gdwarf\-3\fR" 4 +.IP \fB\-\-gdwarf\-3\fR 4 .IX Item "--gdwarf-3" This option is the same as the \fB\-\-gdwarf\-2\fR option, except that it allows for the possibility of the generation of extra debug information as per -version 3 of the \s-1DWARF\s0 specification. Note \- enabling this option does not +version 3 of the DWARF specification. Note \- enabling this option does not guarantee the generation of any extra information, the choice to do so is on a per target basis. -.IP "\fB\-\-gdwarf\-4\fR" 4 +.IP \fB\-\-gdwarf\-4\fR 4 .IX Item "--gdwarf-4" This option is the same as the \fB\-\-gdwarf\-2\fR option, except that it allows for the possibility of the generation of extra debug information as per -version 4 of the \s-1DWARF\s0 specification. Note \- enabling this option does not +version 4 of the DWARF specification. Note \- enabling this option does not guarantee the generation of any extra information, the choice to do so is on a per target basis. -.IP "\fB\-\-gdwarf\-5\fR" 4 +.IP \fB\-\-gdwarf\-5\fR 4 .IX Item "--gdwarf-5" This option is the same as the \fB\-\-gdwarf\-2\fR option, except that it allows for the possibility of the generation of extra debug information as per -version 5 of the \s-1DWARF\s0 specification. Note \- enabling this option does not +version 5 of the DWARF specification. Note \- enabling this option does not guarantee the generation of any extra information, the choice to do so is on a per target basis. -.IP "\fB\-\-gdwarf\-sections\fR" 4 +.IP \fB\-\-gdwarf\-sections\fR 4 .IX Item "--gdwarf-sections" Instead of creating a .debug_line section, create a series of \&.debug_line.\fIfoo\fR sections where \fIfoo\fR is the name of the @@ -715,79 +642,79 @@ will have its dwarf line number information placed into a section called \&\fI.debug_line.text.func\fR. If the code section is just called \fI.text\fR then debug line section will still be called just \fI.debug_line\fR without any suffix. -.IP "\fB\-\-gdwarf\-cie\-version=\fR\fIversion\fR" 4 +.IP \fB\-\-gdwarf\-cie\-version=\fR\fIversion\fR 4 .IX Item "--gdwarf-cie-version=version" -Control which version of \s-1DWARF\s0 Common Information Entries (CIEs) are produced. -When this flag is not specificed the default is version 1, though some targets +Control which version of DWARF Common Information Entries (CIEs) are produced. +When this flag is not specified the default is version 1, though some targets can modify this default. Other possible values for \fIversion\fR are 3 or 4. -.IP "\fB\-\-generate\-missing\-build\-notes=yes\fR" 4 +.IP \fB\-\-generate\-missing\-build\-notes=yes\fR 4 .IX Item "--generate-missing-build-notes=yes" .PD 0 -.IP "\fB\-\-generate\-missing\-build\-notes=no\fR" 4 +.IP \fB\-\-generate\-missing\-build\-notes=no\fR 4 .IX Item "--generate-missing-build-notes=no" .PD -These options control whether the \s-1ELF\s0 assembler should generate \s-1GNU\s0 Build +These options control whether the ELF assembler should generate GNU Build attribute notes if none are present in the input sources. The default can be controlled by the \fB\-\-enable\-generate\-build\-notes\fR configure option. -.IP "\fB\-\-gsframe\fR" 4 +.IP \fB\-\-gsframe\fR 4 .IX Item "--gsframe" .PD 0 -.IP "\fB\-\-gsframe\fR" 4 +.IP \fB\-\-gsframe\fR 4 .IX Item "--gsframe" .PD -Create \fI.sframe\fR section from \s-1CFI\s0 directives. +Create \fI.sframe\fR section from CFI directives. .IP "\fB\-\-hash\-size\fR \fIN\fR" 4 .IX Item "--hash-size N" Ignored. Supported for command line compatibility with other assemblers. -.IP "\fB\-\-help\fR" 4 +.IP \fB\-\-help\fR 4 .IX Item "--help" Print a summary of the command-line options and exit. -.IP "\fB\-\-target\-help\fR" 4 +.IP \fB\-\-target\-help\fR 4 .IX Item "--target-help" Print a summary of all target specific options and exit. .IP "\fB\-I\fR \fIdir\fR" 4 .IX Item "-I dir" Add directory \fIdir\fR to the search list for \f(CW\*(C`.include\*(C'\fR directives. -.IP "\fB\-J\fR" 4 +.IP \fB\-J\fR 4 .IX Item "-J" Don't warn about signed overflow. -.IP "\fB\-K\fR" 4 +.IP \fB\-K\fR 4 .IX Item "-K" Issue warnings when difference tables altered for long displacements. -.IP "\fB\-L\fR" 4 +.IP \fB\-L\fR 4 .IX Item "-L" .PD 0 -.IP "\fB\-\-keep\-locals\fR" 4 +.IP \fB\-\-keep\-locals\fR 4 .IX Item "--keep-locals" .PD Keep (in the symbol table) local symbols. These symbols start with -system-specific local label prefixes, typically \fB.L\fR for \s-1ELF\s0 systems +system-specific local label prefixes, typically \fB.L\fR for ELF systems or \fBL\fR for traditional a.out systems. -.IP "\fB\-\-listing\-lhs\-width=\fR\fInumber\fR" 4 +.IP \fB\-\-listing\-lhs\-width=\fR\fInumber\fR 4 .IX Item "--listing-lhs-width=number" Set the maximum width, in words, of the output data column for an assembler listing to \fInumber\fR. -.IP "\fB\-\-listing\-lhs\-width2=\fR\fInumber\fR" 4 +.IP \fB\-\-listing\-lhs\-width2=\fR\fInumber\fR 4 .IX Item "--listing-lhs-width2=number" Set the maximum width, in words, of the output data column for continuation lines in an assembler listing to \fInumber\fR. -.IP "\fB\-\-listing\-rhs\-width=\fR\fInumber\fR" 4 +.IP \fB\-\-listing\-rhs\-width=\fR\fInumber\fR 4 .IX Item "--listing-rhs-width=number" Set the maximum width of an input source line, as displayed in a listing, to \&\fInumber\fR bytes. -.IP "\fB\-\-listing\-cont\-lines=\fR\fInumber\fR" 4 +.IP \fB\-\-listing\-cont\-lines=\fR\fInumber\fR 4 .IX Item "--listing-cont-lines=number" Set the maximum number of lines printed in a listing for a single line of input to \fInumber\fR + 1. -.IP "\fB\-\-multibyte\-handling=allow\fR" 4 +.IP \fB\-\-multibyte\-handling=allow\fR 4 .IX Item "--multibyte-handling=allow" .PD 0 -.IP "\fB\-\-multibyte\-handling=warn\fR" 4 +.IP \fB\-\-multibyte\-handling=warn\fR 4 .IX Item "--multibyte-handling=warn" -.IP "\fB\-\-multibyte\-handling=warn\-sym\-only\fR" 4 +.IP \fB\-\-multibyte\-handling=warn\-sym\-only\fR 4 .IX Item "--multibyte-handling=warn-sym-only" -.IP "\fB\-\-multibyte\-handling=warn_sym_only\fR" 4 +.IP \fB\-\-multibyte\-handling=warn_sym_only\fR 4 .IX Item "--multibyte-handling=warn_sym_only" .PD Controls how the assembler handles multibyte characters in the input. The @@ -798,7 +725,7 @@ is encountered. Using the \fBwarn-sym-only\fR argument will only cause a warning to be generated when a symbol is defined with a name that contains multibyte characters. (References to undefined symbols will not generate a warning). -.IP "\fB\-\-no\-pad\-sections\fR" 4 +.IP \fB\-\-no\-pad\-sections\fR 4 .IX Item "--no-pad-sections" Stop the assembler for padding the ends of output sections to the alignment of that section. The default is to pad the sections, but this can waste space @@ -806,60 +733,74 @@ which might be needed on targets which have tight memory constraints. .IP "\fB\-o\fR \fIobjfile\fR" 4 .IX Item "-o objfile" Name the object-file output from \fBas\fR \fIobjfile\fR. -.IP "\fB\-R\fR" 4 +.IP \fB\-R\fR 4 .IX Item "-R" Fold the data section into the text section. -.IP "\fB\-\-reduce\-memory\-overheads\fR" 4 +.IP \fB\-\-reduce\-memory\-overheads\fR 4 .IX Item "--reduce-memory-overheads" Ignored. Supported for compatibility with tools that apss the same option to both the assembler and the linker. -.IP "\fB\-\-sectname\-subst\fR" 4 +.IP \fB\-\-scfi=experimental\fR 4 +.IX Item "--scfi=experimental" +This option controls whether the assembler should synthesize CFI for +hand-written input. If the input already contains some synthesizable CFI +directives, the assembler ignores them and emits a warning. Note that +\&\f(CW\*(C`\-\-scfi=experimental\*(C'\fR is not intended to be used for compiler-generated +code, including inline assembly. This experimental support is work in +progress. Only System V AMD64 ABI is supported. +.Sp +Each input function in assembly must begin with the \f(CW\*(C`.type\*(C'\fR directive, and +should ideally be closed off using a \f(CW\*(C`.size\*(C'\fR directive. When using SCFI, +each \f(CW\*(C`.type\*(C'\fR directive prompts GAS to start a new FDE (a.k.a., Function +Descriptor Entry). This implies that with each \f(CW\*(C`.type\*(C'\fR directive, a +previous block of instructions, if any, is finalised as a distinct FDE. +.IP \fB\-\-sectname\-subst\fR 4 .IX Item "--sectname-subst" Honor substitution sequences in section names. -.IP "\fB\-\-size\-check=error\fR" 4 +.IP \fB\-\-size\-check=error\fR 4 .IX Item "--size-check=error" .PD 0 -.IP "\fB\-\-size\-check=warning\fR" 4 +.IP \fB\-\-size\-check=warning\fR 4 .IX Item "--size-check=warning" .PD -Issue an error or warning for invalid \s-1ELF\s0 .size directive. -.IP "\fB\-\-statistics\fR" 4 +Issue an error or warning for invalid ELF .size directive. +.IP \fB\-\-statistics\fR 4 .IX Item "--statistics" Print the maximum space (in bytes) and total time (in seconds) used by assembly. -.IP "\fB\-\-strip\-local\-absolute\fR" 4 +.IP \fB\-\-strip\-local\-absolute\fR 4 .IX Item "--strip-local-absolute" Remove local absolute symbols from the outgoing symbol table. -.IP "\fB\-v\fR" 4 +.IP \fB\-v\fR 4 .IX Item "-v" .PD 0 -.IP "\fB\-version\fR" 4 +.IP \fB\-version\fR 4 .IX Item "-version" .PD Print the \fBas\fR version. -.IP "\fB\-\-version\fR" 4 +.IP \fB\-\-version\fR 4 .IX Item "--version" Print the \fBas\fR version and exit. -.IP "\fB\-W\fR" 4 +.IP \fB\-W\fR 4 .IX Item "-W" .PD 0 -.IP "\fB\-\-no\-warn\fR" 4 +.IP \fB\-\-no\-warn\fR 4 .IX Item "--no-warn" .PD Suppress warning messages. -.IP "\fB\-\-fatal\-warnings\fR" 4 +.IP \fB\-\-fatal\-warnings\fR 4 .IX Item "--fatal-warnings" Treat warnings as errors. -.IP "\fB\-\-warn\fR" 4 +.IP \fB\-\-warn\fR 4 .IX Item "--warn" Don't suppress warning messages or treat them as errors. -.IP "\fB\-w\fR" 4 +.IP \fB\-w\fR 4 .IX Item "-w" Ignored. -.IP "\fB\-x\fR" 4 +.IP \fB\-x\fR 4 .IX Item "-x" Ignored. -.IP "\fB\-Z\fR" 4 +.IP \fB\-Z\fR 4 .IX Item "-Z" Generate an object file even after errors. .IP "\fB\-\- |\fR \fIfiles\fR \fB...\fR" 4 @@ -867,21 +808,21 @@ Generate an object file even after errors. Standard input, or source files to assemble. .PP The following options are available when as is configured for the -64\-bit mode of the \s-1ARM\s0 Architecture (AArch64). -.IP "\fB\-EB\fR" 4 +64\-bit mode of the ARM Architecture (AArch64). +.IP \fB\-EB\fR 4 .IX Item "-EB" This option specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor. -.IP "\fB\-EL\fR" 4 +.IP \fB\-EL\fR 4 .IX Item "-EL" This option specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor. -.IP "\fB\-mabi=\fR\fIabi\fR" 4 +.IP \fB\-mabi=\fR\fIabi\fR 4 .IX Item "-mabi=abi" -Specify which \s-1ABI\s0 the source code uses. The recognized arguments +Specify which ABI the source code uses. The recognized arguments are: \f(CW\*(C`ilp32\*(C'\fR and \f(CW\*(C`lp64\*(C'\fR, which decides the generated object -file in \s-1ELF32\s0 and \s-1ELF64\s0 format respectively. The default is \f(CW\*(C`lp64\*(C'\fR. -.IP "\fB\-mcpu=\fR\fIprocessor\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4 +file in ELF32 and ELF64 format respectively. The default is \f(CW\*(C`lp64\*(C'\fR. +.IP \fB\-mcpu=\fR\fIprocessor\fR\fB[+\fR\fIextension\fR\fB...]\fR 4 .IX Item "-mcpu=processor[+extension...]" This option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute @@ -903,7 +844,9 @@ on the target processor. The following processor names are recognized: \&\f(CW\*(C`cortex\-a78ae\*(C'\fR, \&\f(CW\*(C`cortex\-a78c\*(C'\fR, \&\f(CW\*(C`cortex\-a510\*(C'\fR, +\&\f(CW\*(C`cortex\-a520\*(C'\fR, \&\f(CW\*(C`cortex\-a710\*(C'\fR, +\&\f(CW\*(C`cortex\-a720\*(C'\fR, \&\f(CW\*(C`ares\*(C'\fR, \&\f(CW\*(C`exynos\-m1\*(C'\fR, \&\f(CW\*(C`falkor\*(C'\fR, @@ -919,8 +862,10 @@ on the target processor. The following processor names are recognized: \&\f(CW\*(C`xgene2\*(C'\fR, \&\f(CW\*(C`cortex\-r82\*(C'\fR, \&\f(CW\*(C`cortex\-x1\*(C'\fR, +\&\f(CW\*(C`cortex\-x2\*(C'\fR, +\&\f(CW\*(C`cortex\-x3\*(C'\fR, and -\&\f(CW\*(C`cortex\-x2\*(C'\fR. +\&\f(CW\*(C`cortex\-x4\*(C'\fR. The special name \f(CW\*(C`all\*(C'\fR may be used to allow the assembler to accept instructions valid for any supported processor, including all optional extensions. @@ -933,7 +878,7 @@ If some implementations of a particular processor can have an extension, then then those extensions are automatically enabled. Consequently, you will not normally have to specify any additional extensions. -.IP "\fB\-march=\fR\fIarchitecture\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4 +.IP \fB\-march=\fR\fIarchitecture\fR\fB[+\fR\fIextension\fR\fB...]\fR 4 .IX Item "-march=architecture[+extension...]" This option specifies the target architecture. The assembler will issue an error message if an attempt is made to assemble an @@ -941,8 +886,8 @@ instruction which will not execute on the target architecture. The following architecture names are recognized: \f(CW\*(C`armv8\-a\*(C'\fR, \&\f(CW\*(C`armv8.1\-a\*(C'\fR, \f(CW\*(C`armv8.2\-a\*(C'\fR, \f(CW\*(C`armv8.3\-a\*(C'\fR, \f(CW\*(C`armv8.4\-a\*(C'\fR \&\f(CW\*(C`armv8.5\-a\*(C'\fR, \f(CW\*(C`armv8.6\-a\*(C'\fR, \f(CW\*(C`armv8.7\-a\*(C'\fR, \f(CW\*(C`armv8.8\-a\*(C'\fR, -\&\f(CW\*(C`armv8\-r\*(C'\fR, \f(CW\*(C`armv9\-a\*(C'\fR, \f(CW\*(C`armv9.1\-a\*(C'\fR, \f(CW\*(C`armv9.2\-a\*(C'\fR, -and \f(CW\*(C`armv9.3\-a\*(C'\fR. +\&\f(CW\*(C`armv8.9\-a\*(C'\fR, \f(CW\*(C`armv8\-r\*(C'\fR, \f(CW\*(C`armv9\-a\*(C'\fR, \f(CW\*(C`armv9.1\-a\*(C'\fR, +\&\f(CW\*(C`armv9.2\-a\*(C'\fR, \f(CW\*(C`armv9.3\-a\*(C'\fR and \f(CW\*(C`armv9.4\-a\*(C'\fR. .Sp If both \fB\-mcpu\fR and \fB\-march\fR are specified, the assembler will use the setting for \fB\-mcpu\fR. If neither are @@ -950,18 +895,18 @@ specified, the assembler will default to \fB\-mcpu=all\fR. .Sp The architecture option can be extended with the same instruction set extension options as the \fB\-mcpu\fR option. Unlike -\&\fB\-mcpu\fR, extensions are not always enabled by default, -.IP "\fB\-mverbose\-error\fR" 4 +\&\fB\-mcpu\fR, extensions are not always enabled by default. +.IP \fB\-mverbose\-error\fR 4 .IX Item "-mverbose-error" This option enables verbose error messages for AArch64 gas. This option is enabled by default. -.IP "\fB\-mno\-verbose\-error\fR" 4 +.IP \fB\-mno\-verbose\-error\fR 4 .IX Item "-mno-verbose-error" This option disables verbose error messages in AArch64 gas. .PP The following options are available when as is configured for an Alpha processor. -.IP "\fB\-m\fR\fIcpu\fR" 4 +.IP \fB\-m\fR\fIcpu\fR 4 .IX Item "-mcpu" This option specifies the target processor. If an attempt is made to assemble an instruction which will not execute on the target processor, @@ -991,81 +936,81 @@ The following processor names are recognized: The special name \f(CW\*(C`all\*(C'\fR may be used to allow the assembler to accept instructions valid for any Alpha processor. .Sp -In order to support existing practice in \s-1OSF/1\s0 with respect to \f(CW\*(C`.arch\*(C'\fR, -and existing practice within \fB\s-1MILO\s0\fR (the Linux \s-1ARC\s0 bootloader), the +In order to support existing practice in OSF/1 with respect to \f(CW\*(C`.arch\*(C'\fR, +and existing practice within \fBMILO\fR (the Linux ARC bootloader), the numbered processor names (e.g. 21064) enable the processor-specific PALcode -instructions, while the \*(L"electro-vlasic\*(R" names (e.g. \f(CW\*(C`ev4\*(C'\fR) do not. -.IP "\fB\-mdebug\fR" 4 +instructions, while the "electro-vlasic" names (e.g. \f(CW\*(C`ev4\*(C'\fR) do not. +.IP \fB\-mdebug\fR 4 .IX Item "-mdebug" .PD 0 -.IP "\fB\-no\-mdebug\fR" 4 +.IP \fB\-no\-mdebug\fR 4 .IX Item "-no-mdebug" .PD Enables or disables the generation of \f(CW\*(C`.mdebug\*(C'\fR encapsulation for stabs directives and procedure descriptors. The default is to automatically enable \f(CW\*(C`.mdebug\*(C'\fR when the first stabs directive is seen. -.IP "\fB\-relax\fR" 4 +.IP \fB\-relax\fR 4 .IX Item "-relax" This option forces all relocations to be put into the object file, instead of saving space and resolving some relocations at assembly time. Note that this option does not propagate all symbol arithmetic into the object file, because not all symbol arithmetic can be represented. However, the option can still be useful in specific applications. -.IP "\fB\-replace\fR" 4 +.IP \fB\-replace\fR 4 .IX Item "-replace" .PD 0 -.IP "\fB\-noreplace\fR" 4 +.IP \fB\-noreplace\fR 4 .IX Item "-noreplace" .PD Enables or disables the optimization of procedure calls, both at assemblage -and at link time. These options are only available for \s-1VMS\s0 targets and +and at link time. These options are only available for VMS targets and \&\f(CW\*(C`\-replace\*(C'\fR is the default. See section 1.4.1 of the OpenVMS Linker Utility Manual. -.IP "\fB\-g\fR" 4 +.IP \fB\-g\fR 4 .IX Item "-g" This option is used when the compiler generates debug information. When \&\fBgcc\fR is using \fBmips-tfile\fR to generate debug -information for \s-1ECOFF,\s0 local labels must be passed through to the object +information for ECOFF, local labels must be passed through to the object file. Otherwise this option has no effect. -.IP "\fB\-G\fR\fIsize\fR" 4 +.IP \fB\-G\fR\fIsize\fR 4 .IX Item "-Gsize" A local common symbol larger than \fIsize\fR is placed in \f(CW\*(C`.bss\*(C'\fR, while smaller symbols are placed in \f(CW\*(C`.sbss\*(C'\fR. -.IP "\fB\-F\fR" 4 +.IP \fB\-F\fR 4 .IX Item "-F" .PD 0 -.IP "\fB\-32addr\fR" 4 +.IP \fB\-32addr\fR 4 .IX Item "-32addr" .PD These options are ignored for backward compatibility. .PP -The following options are available when as is configured for an \s-1ARC\s0 +The following options are available when as is configured for an ARC processor. -.IP "\fB\-mcpu=\fR\fIcpu\fR" 4 +.IP \fB\-mcpu=\fR\fIcpu\fR 4 .IX Item "-mcpu=cpu" This option selects the core processor variant. .IP "\fB\-EB | \-EL\fR" 4 .IX Item "-EB | -EL" Select either big-endian (\-EB) or little-endian (\-EL) output. -.IP "\fB\-mcode\-density\fR" 4 +.IP \fB\-mcode\-density\fR 4 .IX Item "-mcode-density" Enable Code Density extension instructions. .PP -The following options are available when as is configured for the \s-1ARM\s0 +The following options are available when as is configured for the ARM processor family. -.IP "\fB\-mcpu=\fR\fIprocessor\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4 +.IP \fB\-mcpu=\fR\fIprocessor\fR\fB[+\fR\fIextension\fR\fB...]\fR 4 .IX Item "-mcpu=processor[+extension...]" -Specify which \s-1ARM\s0 processor variant is the target. -.IP "\fB\-march=\fR\fIarchitecture\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4 +Specify which ARM processor variant is the target. +.IP \fB\-march=\fR\fIarchitecture\fR\fB[+\fR\fIextension\fR\fB...]\fR 4 .IX Item "-march=architecture[+extension...]" -Specify which \s-1ARM\s0 architecture variant is used by the target. -.IP "\fB\-mfpu=\fR\fIfloating-point-format\fR" 4 +Specify which ARM architecture variant is used by the target. +.IP \fB\-mfpu=\fR\fIfloating-point-format\fR 4 .IX Item "-mfpu=floating-point-format" Select which Floating Point architecture is the target. -.IP "\fB\-mfloat\-abi=\fR\fIabi\fR" 4 +.IP \fB\-mfloat\-abi=\fR\fIabi\fR 4 .IX Item "-mfloat-abi=abi" -Select which floating point \s-1ABI\s0 is in use. -.IP "\fB\-mthumb\fR" 4 +Select which floating point ABI is in use. +.IP \fB\-mthumb\fR 4 .IX Item "-mthumb" Enable Thumb only instruction decoding. .IP "\fB\-mapcs\-32 | \-mapcs\-26 | \-mapcs\-float | \-mapcs\-reentrant\fR" 4 @@ -1074,23 +1019,23 @@ Select which procedure calling convention is in use. .IP "\fB\-EB | \-EL\fR" 4 .IX Item "-EB | -EL" Select either big-endian (\-EB) or little-endian (\-EL) output. -.IP "\fB\-mthumb\-interwork\fR" 4 +.IP \fB\-mthumb\-interwork\fR 4 .IX Item "-mthumb-interwork" Specify that the code has been generated with interworking between Thumb and -\&\s-1ARM\s0 code in mind. -.IP "\fB\-mccs\fR" 4 +ARM code in mind. +.IP \fB\-mccs\fR 4 .IX Item "-mccs" Turns on CodeComposer Studio assembly syntax compatibility mode. -.IP "\fB\-k\fR" 4 +.IP \fB\-k\fR 4 .IX Item "-k" -Specify that \s-1PIC\s0 code has been generated. +Specify that PIC code has been generated. .PP The following options are available when as is configured for the Blackfin processor family. -.IP "\fB\-mcpu=\fR\fIprocessor\fR[\fB\-\fR\fIsirevision\fR]" 4 +.IP \fB\-mcpu=\fR\fIprocessor\fR[\fB\-\fR\fIsirevision\fR] 4 .IX Item "-mcpu=processor[-sirevision]" This option specifies the target processor. The optional \fIsirevision\fR -is not used in assembler. It's here such that \s-1GCC\s0 can easily pass down its +is not used in assembler. It's here such that GCC can easily pass down its \&\f(CW\*(C`\-mcpu=\*(C'\fR option. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are @@ -1129,30 +1074,46 @@ recognized: \&\f(CW\*(C`bf561\*(C'\fR, and \&\f(CW\*(C`bf592\*(C'\fR. -.IP "\fB\-mfdpic\fR" 4 +.IP \fB\-mfdpic\fR 4 .IX Item "-mfdpic" -Assemble for the \s-1FDPIC ABI.\s0 -.IP "\fB\-mno\-fdpic\fR" 4 +Assemble for the FDPIC ABI. +.IP \fB\-mno\-fdpic\fR 4 .IX Item "-mno-fdpic" .PD 0 -.IP "\fB\-mnopic\fR" 4 +.IP \fB\-mnopic\fR 4 .IX Item "-mnopic" .PD Disable \-mfdpic. .PP The following options are available when as is configured for -the Linux kernel \s-1BPF\s0 processor family. +the Linux kernel BPF processor family. .PP -\&\f(CW@chapter\fR \s-1BPF\s0 Dependent Features -.SS "Options" -.IX Subsection "Options" -.IP "\fB\-EB\fR" 4 +\&\f(CW@chapter\fR BPF Dependent Features +.SS "BPF Options" +.IX Subsection "BPF Options" +.IP \fB\-EB\fR 4 .IX Item "-EB" This option specifies that the assembler should emit big-endian eBPF. -.IP "\fB\-EL\fR" 4 +.IP \fB\-EL\fR 4 .IX Item "-EL" This option specifies that the assembler should emit little-endian eBPF. +.IP \fB\-mdialect=\fR\fIdialect\fR 4 +.IX Item "-mdialect=dialect" +This option specifies the assembly language dialect to recognize while +assembling. The assembler supports \fBnormal\fR and +\&\fBpseudoc\fR. +.IP \fB\-misa\-spec=\fR\fIspec\fR 4 +.IX Item "-misa-spec=spec" +This option specifies the version of the BPF instruction set to use +when assembling. The BPF ISA versions supported are \fBv1\fR \fBv2\fR, \fBv3\fR and \fBv4\fR. +.Sp +The value \fBxbpf\fR can be specified to recognize extra +instructions that are used by GCC for testing purposes. But beware +this is not valid BPF. +.IP \fB\-mno\-relax\fR 4 +.IX Item "-mno-relax" +This option tells the assembler to not relax instructions. .PP Note that if no endianness option is specified in the command line, the host endianness is used. @@ -1160,184 +1121,184 @@ See the info pages for documentation of the CRIS-specific options. .PP The following options are available when as is configured for the C\-SKY processor family. -.IP "\fB\-march=\fR\fIarchname\fR" 4 +.IP \fB\-march=\fR\fIarchname\fR 4 .IX Item "-march=archname" Assemble for architecture \fIarchname\fR. The \fB\-\-help\fR option lists valid values for \fIarchname\fR. -.IP "\fB\-mcpu=\fR\fIcpuname\fR" 4 +.IP \fB\-mcpu=\fR\fIcpuname\fR 4 .IX Item "-mcpu=cpuname" Assemble for architecture \fIcpuname\fR. The \fB\-\-help\fR option lists valid values for \fIcpuname\fR. -.IP "\fB\-EL\fR" 4 +.IP \fB\-EL\fR 4 .IX Item "-EL" .PD 0 -.IP "\fB\-mlittle\-endian\fR" 4 +.IP \fB\-mlittle\-endian\fR 4 .IX Item "-mlittle-endian" .PD Generate little-endian output. -.IP "\fB\-EB\fR" 4 +.IP \fB\-EB\fR 4 .IX Item "-EB" .PD 0 -.IP "\fB\-mbig\-endian\fR" 4 +.IP \fB\-mbig\-endian\fR 4 .IX Item "-mbig-endian" .PD Generate big-endian output. -.IP "\fB\-fpic\fR" 4 +.IP \fB\-fpic\fR 4 .IX Item "-fpic" .PD 0 -.IP "\fB\-pic\fR" 4 +.IP \fB\-pic\fR 4 .IX Item "-pic" .PD Generate position-independent code. -.IP "\fB\-mljump\fR" 4 +.IP \fB\-mljump\fR 4 .IX Item "-mljump" .PD 0 -.IP "\fB\-mno\-ljump\fR" 4 +.IP \fB\-mno\-ljump\fR 4 .IX Item "-mno-ljump" .PD Enable/disable transformation of the short branch instructions \&\f(CW\*(C`jbf\*(C'\fR, \f(CW\*(C`jbt\*(C'\fR, and \f(CW\*(C`jbr\*(C'\fR to \f(CW\*(C`jmpi\*(C'\fR. This option is for V2 processors only. -It is ignored on \s-1CK801\s0 and \s-1CK802\s0 targets, which do not support the \f(CW\*(C`jmpi\*(C'\fR +It is ignored on CK801 and CK802 targets, which do not support the \f(CW\*(C`jmpi\*(C'\fR instruction, and is enabled by default for other processors. -.IP "\fB\-mbranch\-stub\fR" 4 +.IP \fB\-mbranch\-stub\fR 4 .IX Item "-mbranch-stub" .PD 0 -.IP "\fB\-mno\-branch\-stub\fR" 4 +.IP \fB\-mno\-branch\-stub\fR 4 .IX Item "-mno-branch-stub" .PD Pass through \f(CW\*(C`R_CKCORE_PCREL_IMM26BY2\*(C'\fR relocations for \f(CW\*(C`bsr\*(C'\fR instructions to the linker. .Sp -This option is only available for bare-metal C\-SKY V2 \s-1ELF\s0 targets, +This option is only available for bare-metal C\-SKY V2 ELF targets, where it is enabled by default. It cannot be used in code that will be dynamically linked against shared libraries. -.IP "\fB\-force2bsr\fR" 4 +.IP \fB\-force2bsr\fR 4 .IX Item "-force2bsr" .PD 0 -.IP "\fB\-mforce2bsr\fR" 4 +.IP \fB\-mforce2bsr\fR 4 .IX Item "-mforce2bsr" -.IP "\fB\-no\-force2bsr\fR" 4 +.IP \fB\-no\-force2bsr\fR 4 .IX Item "-no-force2bsr" -.IP "\fB\-mno\-force2bsr\fR" 4 +.IP \fB\-mno\-force2bsr\fR 4 .IX Item "-mno-force2bsr" .PD Enable/disable transformation of \f(CW\*(C`jbsr\*(C'\fR instructions to \f(CW\*(C`bsr\*(C'\fR. This option is always enabled (and \fB\-mno\-force2bsr\fR is ignored) -for \s-1CK801/CK802\s0 targets. It is also always enabled when +for CK801/CK802 targets. It is also always enabled when \&\fB\-mbranch\-stub\fR is in effect. -.IP "\fB\-jsri2bsr\fR" 4 +.IP \fB\-jsri2bsr\fR 4 .IX Item "-jsri2bsr" .PD 0 -.IP "\fB\-mjsri2bsr\fR" 4 +.IP \fB\-mjsri2bsr\fR 4 .IX Item "-mjsri2bsr" -.IP "\fB\-no\-jsri2bsr\fR" 4 +.IP \fB\-no\-jsri2bsr\fR 4 .IX Item "-no-jsri2bsr" -.IP "\fB\-mno\-jsri2bsr\fR" 4 +.IP \fB\-mno\-jsri2bsr\fR 4 .IX Item "-mno-jsri2bsr" .PD Enable/disable transformation of \f(CW\*(C`jsri\*(C'\fR instructions to \f(CW\*(C`bsr\*(C'\fR. This option is enabled by default. -.IP "\fB\-mnolrw\fR" 4 +.IP \fB\-mnolrw\fR 4 .IX Item "-mnolrw" .PD 0 -.IP "\fB\-mno\-lrw\fR" 4 +.IP \fB\-mno\-lrw\fR 4 .IX Item "-mno-lrw" .PD Enable/disable transformation of \f(CW\*(C`lrw\*(C'\fR instructions into a \&\f(CW\*(C`movih\*(C'\fR/\f(CW\*(C`ori\*(C'\fR pair. -.IP "\fB\-melrw\fR" 4 +.IP \fB\-melrw\fR 4 .IX Item "-melrw" .PD 0 -.IP "\fB\-mno\-elrw\fR" 4 +.IP \fB\-mno\-elrw\fR 4 .IX Item "-mno-elrw" .PD Enable/disable extended \f(CW\*(C`lrw\*(C'\fR instructions. This option is enabled by default for CK800\-series processors. -.IP "\fB\-mlaf\fR" 4 +.IP \fB\-mlaf\fR 4 .IX Item "-mlaf" .PD 0 -.IP "\fB\-mliterals\-after\-func\fR" 4 +.IP \fB\-mliterals\-after\-func\fR 4 .IX Item "-mliterals-after-func" -.IP "\fB\-mno\-laf\fR" 4 +.IP \fB\-mno\-laf\fR 4 .IX Item "-mno-laf" -.IP "\fB\-mno\-literals\-after\-func\fR" 4 +.IP \fB\-mno\-literals\-after\-func\fR 4 .IX Item "-mno-literals-after-func" .PD Enable/disable placement of literal pools after each function. -.IP "\fB\-mlabr\fR" 4 +.IP \fB\-mlabr\fR 4 .IX Item "-mlabr" .PD 0 -.IP "\fB\-mliterals\-after\-br\fR" 4 +.IP \fB\-mliterals\-after\-br\fR 4 .IX Item "-mliterals-after-br" -.IP "\fB\-mno\-labr\fR" 4 +.IP \fB\-mno\-labr\fR 4 .IX Item "-mno-labr" -.IP "\fB\-mnoliterals\-after\-br\fR" 4 +.IP \fB\-mnoliterals\-after\-br\fR 4 .IX Item "-mnoliterals-after-br" .PD Enable/disable placement of literal pools after unconditional branches. This option is enabled by default. -.IP "\fB\-mistack\fR" 4 +.IP \fB\-mistack\fR 4 .IX Item "-mistack" .PD 0 -.IP "\fB\-mno\-istack\fR" 4 +.IP \fB\-mno\-istack\fR 4 .IX Item "-mno-istack" .PD Enable/disable interrupt stack instructions. This option is enabled by -default on \s-1CK801, CK802,\s0 and \s-1CK802\s0 processors. +default on CK801, CK802, and CK802 processors. .PP The following options explicitly enable certain optional instructions. These features are also enabled implicitly by using \f(CW\*(C`\-mcpu=\*(C'\fR to specify a processor that supports it. -.IP "\fB\-mhard\-float\fR" 4 +.IP \fB\-mhard\-float\fR 4 .IX Item "-mhard-float" Enable hard float instructions. -.IP "\fB\-mmp\fR" 4 +.IP \fB\-mmp\fR 4 .IX Item "-mmp" Enable multiprocessor instructions. -.IP "\fB\-mcp\fR" 4 +.IP \fB\-mcp\fR 4 .IX Item "-mcp" Enable coprocessor instructions. -.IP "\fB\-mcache\fR" 4 +.IP \fB\-mcache\fR 4 .IX Item "-mcache" Enable cache prefetch instruction. -.IP "\fB\-msecurity\fR" 4 +.IP \fB\-msecurity\fR 4 .IX Item "-msecurity" Enable C\-SKY security instructions. -.IP "\fB\-mtrust\fR" 4 +.IP \fB\-mtrust\fR 4 .IX Item "-mtrust" Enable C\-SKY trust instructions. -.IP "\fB\-mdsp\fR" 4 +.IP \fB\-mdsp\fR 4 .IX Item "-mdsp" -Enable \s-1DSP\s0 instructions. -.IP "\fB\-medsp\fR" 4 +Enable DSP instructions. +.IP \fB\-medsp\fR 4 .IX Item "-medsp" -Enable enhanced \s-1DSP\s0 instructions. -.IP "\fB\-mvdsp\fR" 4 +Enable enhanced DSP instructions. +.IP \fB\-mvdsp\fR 4 .IX Item "-mvdsp" -Enable vector \s-1DSP\s0 instructions. +Enable vector DSP instructions. .PP The following options are available when as is configured for an Epiphany processor. -.IP "\fB\-mepiphany\fR" 4 +.IP \fB\-mepiphany\fR 4 .IX Item "-mepiphany" Specifies that the both 32 and 16 bit instructions are allowed. This is the default behavior. -.IP "\fB\-mepiphany16\fR" 4 +.IP \fB\-mepiphany16\fR 4 .IX Item "-mepiphany16" Restricts the permitted instructions to just the 16 bit set. .PP The following options are available when as is configured for an H8/300 processor. \&\f(CW@chapter\fR H8/300 Dependent Features -.SS "Options" +.SS Options .IX Subsection "Options" The Renesas H8/300 version of \f(CW\*(C`as\*(C'\fR has one machine-dependent option: -.IP "\fB\-h\-tick\-hex\fR" 4 +.IP \fB\-h\-tick\-hex\fR 4 .IX Item "-h-tick-hex" Support H'00 style hex constants in addition to 0x00 style. -.IP "\fB\-mach=\fR\fIname\fR" 4 +.IP \fB\-mach=\fR\fIname\fR 4 .IX Item "-mach=name" Sets the H8300 machine variant. The following machine names are recognised: @@ -1354,27 +1315,27 @@ an i386 processor. .IX Item "--32 | --x32 | --64" Select the word size, either 32 bits or 64 bits. \fB\-\-32\fR implies Intel i386 architecture, while \fB\-\-x32\fR and \fB\-\-64\fR -imply \s-1AMD\s0 x86\-64 architecture with 32\-bit or 64\-bit word-size +imply AMD x86\-64 architecture with 32\-bit or 64\-bit word-size respectively. .Sp -These options are only available with the \s-1ELF\s0 object file format, and -require that the necessary \s-1BFD\s0 support has been included (on a 32\-bit +These options are only available with the ELF object file format, and +require that the necessary BFD support has been included (on a 32\-bit platform you have to add \-\-enable\-64\-bit\-bfd to configure enable 64\-bit usage and use x86\-64 as target platform). -.IP "\fB\-n\fR" 4 +.IP \fB\-n\fR 4 .IX Item "-n" -By default, x86 \s-1GAS\s0 replaces multiple nop instructions used for +By default, x86 GAS replaces multiple nop instructions used for alignment within code sections with multi-byte nop instructions such as leal 0(%esi,1),%esi. This switch disables the optimization if a single byte nop (0x90) is explicitly specified as the fill byte for alignment. -.IP "\fB\-\-divide\fR" 4 +.IP \fB\-\-divide\fR 4 .IX Item "--divide" On SVR4\-derived platforms, the character \fB/\fR is treated as a comment character, which means that it cannot be used in expressions. The \&\fB\-\-divide\fR option turns \fB/\fR into a normal character. This does not disable \fB/\fR at the beginning of a line starting a comment, or affect using \fB#\fR for starting a comment. -.IP "\fB\-march=\fR\fI\s-1CPU\s0\fR\fB[+\fR\fI\s-1EXTENSION\s0\fR\fB...]\fR" 4 +.IP \fB\-march=\fR\fICPU\fR\fB[+\fR\fIEXTENSION\fR\fB...]\fR 4 .IX Item "-march=CPU[+EXTENSION...]" This option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction @@ -1412,6 +1373,7 @@ processor names are recognized: \&\f(CW\*(C`znver2\*(C'\fR, \&\f(CW\*(C`znver3\*(C'\fR, \&\f(CW\*(C`znver4\*(C'\fR, +\&\f(CW\*(C`znver5\*(C'\fR, \&\f(CW\*(C`btver1\*(C'\fR, \&\f(CW\*(C`btver2\*(C'\fR, \&\f(CW\*(C`generic32\*(C'\fR and @@ -1438,6 +1400,8 @@ accept various extension mnemonics. For example, \&\f(CW\*(C`sse4\*(C'\fR, \&\f(CW\*(C`avx\*(C'\fR, \&\f(CW\*(C`avx2\*(C'\fR, +\&\f(CW\*(C`lahf_sahf\*(C'\fR, +\&\f(CW\*(C`monitor\*(C'\fR, \&\f(CW\*(C`adx\*(C'\fR, \&\f(CW\*(C`rdseed\*(C'\fR, \&\f(CW\*(C`prfchw\*(C'\fR, @@ -1490,9 +1454,23 @@ accept various extension mnemonics. For example, \&\f(CW\*(C`msrlist\*(C'\fR, \&\f(CW\*(C`avx_ne_convert\*(C'\fR, \&\f(CW\*(C`rao_int\*(C'\fR, +\&\f(CW\*(C`fred\*(C'\fR, +\&\f(CW\*(C`lkgs\*(C'\fR, +\&\f(CW\*(C`avx_vnni_int16\*(C'\fR, +\&\f(CW\*(C`sha512\*(C'\fR, +\&\f(CW\*(C`sm3\*(C'\fR, +\&\f(CW\*(C`sm4\*(C'\fR, +\&\f(CW\*(C`pbndkb\*(C'\fR, +\&\f(CW\*(C`avx10.1\*(C'\fR, +\&\f(CW\*(C`avx10.1/512\*(C'\fR, +\&\f(CW\*(C`avx10.1/256\*(C'\fR, +\&\f(CW\*(C`avx10.1/128\*(C'\fR, +\&\f(CW\*(C`user_msr\*(C'\fR, +\&\f(CW\*(C`apx_f\*(C'\fR, \&\f(CW\*(C`amx_int8\*(C'\fR, \&\f(CW\*(C`amx_bf16\*(C'\fR, \&\f(CW\*(C`amx_fp16\*(C'\fR, +\&\f(CW\*(C`amx_complex\*(C'\fR, \&\f(CW\*(C`amx_tile\*(C'\fR, \&\f(CW\*(C`vmx\*(C'\fR, \&\f(CW\*(C`vmfunc\*(C'\fR, @@ -1543,137 +1521,141 @@ accept various extension mnemonics. For example, \&\f(CW\*(C`svme\*(C'\fR and \&\f(CW\*(C`padlock\*(C'\fR. Note that these extension mnemonics can be prefixed with \f(CW\*(C`no\*(C'\fR to revoke -the respective (and any dependent) functionality. +the respective (and any dependent) functionality. Note further that the +suffixes permitted on \f(CW\*(C`\-march=avx10.<N>\*(C'\fR enforce a vector length +restriction, i.e. despite these otherwise being "enabling" options, using +these suffixes will disable all insns with wider vector or mask register +operands. .Sp When the \f(CW\*(C`.arch\*(C'\fR directive is used with \fB\-march\fR, the \&\f(CW\*(C`.arch\*(C'\fR directive will take precedent. -.IP "\fB\-mtune=\fR\fI\s-1CPU\s0\fR" 4 +.IP \fB\-mtune=\fR\fICPU\fR 4 .IX Item "-mtune=CPU" This option specifies a processor to optimize for. When used in conjunction with the \fB\-march\fR option, only instructions of the processor specified by the \fB\-march\fR option will be generated. .Sp -Valid \fI\s-1CPU\s0\fR values are identical to the processor list of -\&\fB\-march=\fR\fI\s-1CPU\s0\fR. -.IP "\fB\-msse2avx\fR" 4 +Valid \fICPU\fR values are identical to the processor list of +\&\fB\-march=\fR\fICPU\fR. +.IP \fB\-msse2avx\fR 4 .IX Item "-msse2avx" -This option specifies that the assembler should encode \s-1SSE\s0 instructions -with \s-1VEX\s0 prefix. -.IP "\fB\-muse\-unaligned\-vector\-move\fR" 4 +This option specifies that the assembler should encode SSE instructions +with VEX prefix. +.IP \fB\-muse\-unaligned\-vector\-move\fR 4 .IX Item "-muse-unaligned-vector-move" This option specifies that the assembler should encode aligned vector move as unaligned vector move. -.IP "\fB\-msse\-check=\fR\fInone\fR" 4 +.IP \fB\-msse\-check=\fR\fInone\fR 4 .IX Item "-msse-check=none" .PD 0 -.IP "\fB\-msse\-check=\fR\fIwarning\fR" 4 +.IP \fB\-msse\-check=\fR\fIwarning\fR 4 .IX Item "-msse-check=warning" -.IP "\fB\-msse\-check=\fR\fIerror\fR" 4 +.IP \fB\-msse\-check=\fR\fIerror\fR 4 .IX Item "-msse-check=error" .PD -These options control if the assembler should check \s-1SSE\s0 instructions. -\&\fB\-msse\-check=\fR\fInone\fR will make the assembler not to check \s-1SSE\s0 +These options control if the assembler should check SSE instructions. +\&\fB\-msse\-check=\fR\fInone\fR will make the assembler not to check SSE instructions, which is the default. \fB\-msse\-check=\fR\fIwarning\fR -will make the assembler issue a warning for any \s-1SSE\s0 instruction. +will make the assembler issue a warning for any SSE instruction. \&\fB\-msse\-check=\fR\fIerror\fR will make the assembler issue an error -for any \s-1SSE\s0 instruction. -.IP "\fB\-mavxscalar=\fR\fI128\fR" 4 +for any SSE instruction. +.IP \fB\-mavxscalar=\fR\fI128\fR 4 .IX Item "-mavxscalar=128" .PD 0 -.IP "\fB\-mavxscalar=\fR\fI256\fR" 4 +.IP \fB\-mavxscalar=\fR\fI256\fR 4 .IX Item "-mavxscalar=256" .PD -These options control how the assembler should encode scalar \s-1AVX\s0 +These options control how the assembler should encode scalar AVX instructions. \fB\-mavxscalar=\fR\fI128\fR will encode scalar -\&\s-1AVX\s0 instructions with 128bit vector length, which is the default. -\&\fB\-mavxscalar=\fR\fI256\fR will encode scalar \s-1AVX\s0 instructions +AVX instructions with 128bit vector length, which is the default. +\&\fB\-mavxscalar=\fR\fI256\fR will encode scalar AVX instructions with 256bit vector length. .Sp -\&\s-1WARNING:\s0 Don't use this for production code \- due to \s-1CPU\s0 errata the +WARNING: Don't use this for production code \- due to CPU errata the resulting code may not work on certain models. -.IP "\fB\-mvexwig=\fR\fI0\fR" 4 +.IP \fB\-mvexwig=\fR\fI0\fR 4 .IX Item "-mvexwig=0" .PD 0 -.IP "\fB\-mvexwig=\fR\fI1\fR" 4 +.IP \fB\-mvexwig=\fR\fI1\fR 4 .IX Item "-mvexwig=1" .PD -These options control how the assembler should encode \s-1VEX\s0.W\-ignored (\s-1WIG\s0) -\&\s-1VEX\s0 instructions. \fB\-mvexwig=\fR\fI0\fR will encode \s-1WIG VEX\s0 +These options control how the assembler should encode VEX.W\-ignored (WIG) +VEX instructions. \fB\-mvexwig=\fR\fI0\fR will encode WIG VEX instructions with vex.w = 0, which is the default. -\&\fB\-mvexwig=\fR\fI1\fR will encode \s-1WIG EVEX\s0 instructions with +\&\fB\-mvexwig=\fR\fI1\fR will encode WIG EVEX instructions with vex.w = 1. .Sp -\&\s-1WARNING:\s0 Don't use this for production code \- due to \s-1CPU\s0 errata the +WARNING: Don't use this for production code \- due to CPU errata the resulting code may not work on certain models. -.IP "\fB\-mevexlig=\fR\fI128\fR" 4 +.IP \fB\-mevexlig=\fR\fI128\fR 4 .IX Item "-mevexlig=128" .PD 0 -.IP "\fB\-mevexlig=\fR\fI256\fR" 4 +.IP \fB\-mevexlig=\fR\fI256\fR 4 .IX Item "-mevexlig=256" -.IP "\fB\-mevexlig=\fR\fI512\fR" 4 +.IP \fB\-mevexlig=\fR\fI512\fR 4 .IX Item "-mevexlig=512" .PD These options control how the assembler should encode length-ignored -(\s-1LIG\s0) \s-1EVEX\s0 instructions. \fB\-mevexlig=\fR\fI128\fR will encode \s-1LIG -EVEX\s0 instructions with 128bit vector length, which is the default. +(LIG) EVEX instructions. \fB\-mevexlig=\fR\fI128\fR will encode LIG +EVEX instructions with 128bit vector length, which is the default. \&\fB\-mevexlig=\fR\fI256\fR and \fB\-mevexlig=\fR\fI512\fR will -encode \s-1LIG EVEX\s0 instructions with 256bit and 512bit vector length, +encode LIG EVEX instructions with 256bit and 512bit vector length, respectively. -.IP "\fB\-mevexwig=\fR\fI0\fR" 4 +.IP \fB\-mevexwig=\fR\fI0\fR 4 .IX Item "-mevexwig=0" .PD 0 -.IP "\fB\-mevexwig=\fR\fI1\fR" 4 +.IP \fB\-mevexwig=\fR\fI1\fR 4 .IX Item "-mevexwig=1" .PD -These options control how the assembler should encode w\-ignored (\s-1WIG\s0) -\&\s-1EVEX\s0 instructions. \fB\-mevexwig=\fR\fI0\fR will encode \s-1WIG -EVEX\s0 instructions with evex.w = 0, which is the default. -\&\fB\-mevexwig=\fR\fI1\fR will encode \s-1WIG EVEX\s0 instructions with +These options control how the assembler should encode w\-ignored (WIG) +EVEX instructions. \fB\-mevexwig=\fR\fI0\fR will encode WIG +EVEX instructions with evex.w = 0, which is the default. +\&\fB\-mevexwig=\fR\fI1\fR will encode WIG EVEX instructions with evex.w = 1. -.IP "\fB\-mmnemonic=\fR\fIatt\fR" 4 +.IP \fB\-mmnemonic=\fR\fIatt\fR 4 .IX Item "-mmnemonic=att" .PD 0 -.IP "\fB\-mmnemonic=\fR\fIintel\fR" 4 +.IP \fB\-mmnemonic=\fR\fIintel\fR 4 .IX Item "-mmnemonic=intel" .PD This option specifies instruction mnemonic for matching instructions. The \f(CW\*(C`.att_mnemonic\*(C'\fR and \f(CW\*(C`.intel_mnemonic\*(C'\fR directives will take precedent. -.IP "\fB\-msyntax=\fR\fIatt\fR" 4 +.IP \fB\-msyntax=\fR\fIatt\fR 4 .IX Item "-msyntax=att" .PD 0 -.IP "\fB\-msyntax=\fR\fIintel\fR" 4 +.IP \fB\-msyntax=\fR\fIintel\fR 4 .IX Item "-msyntax=intel" .PD This option specifies instruction syntax when processing instructions. The \f(CW\*(C`.att_syntax\*(C'\fR and \f(CW\*(C`.intel_syntax\*(C'\fR directives will take precedent. -.IP "\fB\-mnaked\-reg\fR" 4 +.IP \fB\-mnaked\-reg\fR 4 .IX Item "-mnaked-reg" This option specifies that registers don't require a \fB%\fR prefix. The \f(CW\*(C`.att_syntax\*(C'\fR and \f(CW\*(C`.intel_syntax\*(C'\fR directives will take precedent. -.IP "\fB\-madd\-bnd\-prefix\fR" 4 +.IP \fB\-madd\-bnd\-prefix\fR 4 .IX Item "-madd-bnd-prefix" -This option forces the assembler to add \s-1BND\s0 prefix to all branches, even +This option forces the assembler to add BND prefix to all branches, even if such prefix was not explicitly specified in the source code. -.IP "\fB\-mno\-shared\fR" 4 +.IP \fB\-mno\-shared\fR 4 .IX Item "-mno-shared" -On \s-1ELF\s0 target, the assembler normally optimizes out non-PLT relocations +On ELF target, the assembler normally optimizes out non-PLT relocations against defined non-weak global branch targets with default visibility. The \fB\-mshared\fR option tells the assembler to generate code which may go into a shared library where all non-weak global branch targets with default visibility can be preempted. The resulting code is slightly bigger. This option only affects the handling of branch instructions. -.IP "\fB\-mbig\-obj\fR" 4 +.IP \fB\-mbig\-obj\fR 4 .IX Item "-mbig-obj" -On \s-1PE/COFF\s0 target this option forces the use of big object file +On PE/COFF target this option forces the use of big object file format, which allows more than 32768 sections. -.IP "\fB\-momit\-lock\-prefix=\fR\fIno\fR" 4 +.IP \fB\-momit\-lock\-prefix=\fR\fIno\fR 4 .IX Item "-momit-lock-prefix=no" .PD 0 -.IP "\fB\-momit\-lock\-prefix=\fR\fIyes\fR" 4 +.IP \fB\-momit\-lock\-prefix=\fR\fIyes\fR 4 .IX Item "-momit-lock-prefix=yes" .PD These options control how the assembler should encode lock prefix. @@ -1683,23 +1665,23 @@ single-thread computers \&\fB\-momit\-lock\-prefix=\fR\fIyes\fR will omit all lock prefixes. \&\fB\-momit\-lock\-prefix=\fR\fIno\fR will encode lock prefix as usual, which is the default. -.IP "\fB\-mfence\-as\-lock\-add=\fR\fIno\fR" 4 +.IP \fB\-mfence\-as\-lock\-add=\fR\fIno\fR 4 .IX Item "-mfence-as-lock-add=no" .PD 0 -.IP "\fB\-mfence\-as\-lock\-add=\fR\fIyes\fR" 4 +.IP \fB\-mfence\-as\-lock\-add=\fR\fIyes\fR 4 .IX Item "-mfence-as-lock-add=yes" .PD These options control how the assembler should encode lfence, mfence and sfence. \&\fB\-mfence\-as\-lock\-add=\fR\fIyes\fR will encode lfence, mfence and -sfence as \fBlock addl \f(CB$0x0\fB, (%rsp)\fR in 64\-bit mode and -\&\fBlock addl \f(CB$0x0\fB, (%esp)\fR in 32\-bit mode. +sfence as \fBlock addl \fR\f(CB$0x0\fR\fB, (%rsp)\fR in 64\-bit mode and +\&\fBlock addl \fR\f(CB$0x0\fR\fB, (%esp)\fR in 32\-bit mode. \&\fB\-mfence\-as\-lock\-add=\fR\fIno\fR will encode lfence, mfence and sfence as usual, which is the default. -.IP "\fB\-mrelax\-relocations=\fR\fIno\fR" 4 +.IP \fB\-mrelax\-relocations=\fR\fIno\fR 4 .IX Item "-mrelax-relocations=no" .PD 0 -.IP "\fB\-mrelax\-relocations=\fR\fIyes\fR" 4 +.IP \fB\-mrelax\-relocations=\fR\fIyes\fR 4 .IX Item "-mrelax-relocations=yes" .PD These options control whether the assembler should generate relax @@ -1709,27 +1691,27 @@ R_X86_64_REX_GOTPCRELX, in 64\-bit mode. \&\fB\-mrelax\-relocations=\fR\fIno\fR will not generate relax relocations. The default can be controlled by a configure option \&\fB\-\-enable\-x86\-relax\-relocations\fR. -.IP "\fB\-malign\-branch\-boundary=\fR\fI\s-1NUM\s0\fR" 4 +.IP \fB\-malign\-branch\-boundary=\fR\fINUM\fR 4 .IX Item "-malign-branch-boundary=NUM" This option controls how the assembler should align branches with segment -prefixes or \s-1NOP.\s0 \fI\s-1NUM\s0\fR must be a power of 2. It should be 0 or -no less than 16. Branches will be aligned within \fI\s-1NUM\s0\fR byte +prefixes or NOP. \fINUM\fR must be a power of 2. It should be 0 or +no less than 16. Branches will be aligned within \fINUM\fR byte boundary. \fB\-malign\-branch\-boundary=0\fR, which is the default, doesn't align branches. -.IP "\fB\-malign\-branch=\fR\fI\s-1TYPE\s0\fR\fB[+\fR\fI\s-1TYPE\s0\fR\fB...]\fR" 4 +.IP \fB\-malign\-branch=\fR\fITYPE\fR\fB[+\fR\fITYPE\fR\fB...]\fR 4 .IX Item "-malign-branch=TYPE[+TYPE...]" -This option specifies types of branches to align. \fI\s-1TYPE\s0\fR is +This option specifies types of branches to align. \fITYPE\fR is combination of \fBjcc\fR, which aligns conditional jumps, \&\fBfused\fR, which aligns fused conditional jumps, \fBjmp\fR, which aligns unconditional jumps, \fBcall\fR which aligns calls, \&\fBret\fR, which aligns rets, \fBindirect\fR, which aligns indirect jumps and calls. The default is \fB\-malign\-branch=jcc+fused+jmp\fR. -.IP "\fB\-malign\-branch\-prefix\-size=\fR\fI\s-1NUM\s0\fR" 4 +.IP \fB\-malign\-branch\-prefix\-size=\fR\fINUM\fR 4 .IX Item "-malign-branch-prefix-size=NUM" This option specifies the maximum number of prefixes on an instruction -to align branches. \fI\s-1NUM\s0\fR should be between 0 and 5. The default -\&\fI\s-1NUM\s0\fR is 5. -.IP "\fB\-mbranches\-within\-32B\-boundaries\fR" 4 +to align branches. \fINUM\fR should be between 0 and 5. The default +\&\fINUM\fR is 5. +.IP \fB\-mbranches\-within\-32B\-boundaries\fR 4 .IX Item "-mbranches-within-32B-boundaries" This option aligns conditional jumps, fused conditional jumps and unconditional jumps within 32 byte boundary with up to 5 segment prefixes @@ -1738,24 +1720,24 @@ on an instruction. It is equivalent to \&\fB\-malign\-branch=jcc+fused+jmp\fR \&\fB\-malign\-branch\-prefix\-size=5\fR. The default doesn't align branches. -.IP "\fB\-mlfence\-after\-load=\fR\fIno\fR" 4 +.IP \fB\-mlfence\-after\-load=\fR\fIno\fR 4 .IX Item "-mlfence-after-load=no" .PD 0 -.IP "\fB\-mlfence\-after\-load=\fR\fIyes\fR" 4 +.IP \fB\-mlfence\-after\-load=\fR\fIyes\fR 4 .IX Item "-mlfence-after-load=yes" .PD These options control whether the assembler should generate lfence after load instructions. \fB\-mlfence\-after\-load=\fR\fIyes\fR will generate lfence. \fB\-mlfence\-after\-load=\fR\fIno\fR will not generate lfence, which is the default. -.IP "\fB\-mlfence\-before\-indirect\-branch=\fR\fInone\fR" 4 +.IP \fB\-mlfence\-before\-indirect\-branch=\fR\fInone\fR 4 .IX Item "-mlfence-before-indirect-branch=none" .PD 0 -.IP "\fB\-mlfence\-before\-indirect\-branch=\fR\fIall\fR" 4 +.IP \fB\-mlfence\-before\-indirect\-branch=\fR\fIall\fR 4 .IX Item "-mlfence-before-indirect-branch=all" -.IP "\fB\-mlfence\-before\-indirect\-branch=\fR\fIregister\fR" 4 +.IP \fB\-mlfence\-before\-indirect\-branch=\fR\fIregister\fR 4 .IX Item "-mlfence-before-indirect-branch=register" -.IP "\fB\-mlfence\-before\-indirect\-branch=\fR\fImemory\fR" 4 +.IP \fB\-mlfence\-before\-indirect\-branch=\fR\fImemory\fR 4 .IX Item "-mlfence-before-indirect-branch=memory" .PD These options control whether the assembler should generate lfence @@ -1774,16 +1756,16 @@ lfence nor issue warning, which is the default. Note that lfence won't be generated before indirect near branch via register with \&\fB\-mlfence\-after\-load=\fR\fIyes\fR since lfence will be generated after loading branch target register. -.IP "\fB\-mlfence\-before\-ret=\fR\fInone\fR" 4 +.IP \fB\-mlfence\-before\-ret=\fR\fInone\fR 4 .IX Item "-mlfence-before-ret=none" .PD 0 -.IP "\fB\-mlfence\-before\-ret=\fR\fIshl\fR" 4 +.IP \fB\-mlfence\-before\-ret=\fR\fIshl\fR 4 .IX Item "-mlfence-before-ret=shl" -.IP "\fB\-mlfence\-before\-ret=\fR\fIor\fR" 4 +.IP \fB\-mlfence\-before\-ret=\fR\fIor\fR 4 .IX Item "-mlfence-before-ret=or" -.IP "\fB\-mlfence\-before\-ret=\fR\fIyes\fR" 4 +.IP \fB\-mlfence\-before\-ret=\fR\fIyes\fR 4 .IX Item "-mlfence-before-ret=yes" -.IP "\fB\-mlfence\-before\-ret=\fR\fInot\fR" 4 +.IP \fB\-mlfence\-before\-ret=\fR\fInot\fR 4 .IX Item "-mlfence-before-ret=not" .PD These options control whether the assembler should generate lfence @@ -1793,94 +1775,94 @@ generate or instruction with lfence. with lfence. \fB\-mlfence\-before\-ret=\fR\fInot\fR will generate not instruction with lfence. \fB\-mlfence\-before\-ret=\fR\fInone\fR will not generate lfence, which is the default. -.IP "\fB\-mx86\-used\-note=\fR\fIno\fR" 4 +.IP \fB\-mx86\-used\-note=\fR\fIno\fR 4 .IX Item "-mx86-used-note=no" .PD 0 -.IP "\fB\-mx86\-used\-note=\fR\fIyes\fR" 4 +.IP \fB\-mx86\-used\-note=\fR\fIyes\fR 4 .IX Item "-mx86-used-note=yes" .PD These options control whether the assembler should generate -\&\s-1GNU_PROPERTY_X86_ISA_1_USED\s0 and \s-1GNU_PROPERTY_X86_FEATURE_2_USED -GNU\s0 property notes. The default can be controlled by the +GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED +GNU property notes. The default can be controlled by the \&\fB\-\-enable\-x86\-used\-note\fR configure option. -.IP "\fB\-mevexrcig=\fR\fIrne\fR" 4 +.IP \fB\-mevexrcig=\fR\fIrne\fR 4 .IX Item "-mevexrcig=rne" .PD 0 -.IP "\fB\-mevexrcig=\fR\fIrd\fR" 4 +.IP \fB\-mevexrcig=\fR\fIrd\fR 4 .IX Item "-mevexrcig=rd" -.IP "\fB\-mevexrcig=\fR\fIru\fR" 4 +.IP \fB\-mevexrcig=\fR\fIru\fR 4 .IX Item "-mevexrcig=ru" -.IP "\fB\-mevexrcig=\fR\fIrz\fR" 4 +.IP \fB\-mevexrcig=\fR\fIrz\fR 4 .IX Item "-mevexrcig=rz" .PD These options control how the assembler should encode SAE-only -\&\s-1EVEX\s0 instructions. \fB\-mevexrcig=\fR\fIrne\fR will encode \s-1RC\s0 bits -of \s-1EVEX\s0 instruction with 00, which is the default. +EVEX instructions. \fB\-mevexrcig=\fR\fIrne\fR will encode RC bits +of EVEX instruction with 00, which is the default. \&\fB\-mevexrcig=\fR\fIrd\fR, \fB\-mevexrcig=\fR\fIru\fR -and \fB\-mevexrcig=\fR\fIrz\fR will encode SAE-only \s-1EVEX\s0 instructions -with 01, 10 and 11 \s-1RC\s0 bits, respectively. -.IP "\fB\-mamd64\fR" 4 +and \fB\-mevexrcig=\fR\fIrz\fR will encode SAE-only EVEX instructions +with 01, 10 and 11 RC bits, respectively. +.IP \fB\-mamd64\fR 4 .IX Item "-mamd64" .PD 0 -.IP "\fB\-mintel64\fR" 4 +.IP \fB\-mintel64\fR 4 .IX Item "-mintel64" .PD -This option specifies that the assembler should accept only \s-1AMD64\s0 or -Intel64 \s-1ISA\s0 in 64\-bit mode. The default is to accept common, Intel64 -only and \s-1AMD64\s0 ISAs. +This option specifies that the assembler should accept only AMD64 or +Intel64 ISA in 64\-bit mode. The default is to accept common, Intel64 +only and AMD64 ISAs. .IP "\fB\-O0 | \-O | \-O1 | \-O2 | \-Os\fR" 4 .IX Item "-O0 | -O | -O1 | -O2 | -Os" Optimize instruction encoding with smaller instruction size. \fB\-O\fR and \fB\-O1\fR encode 64\-bit register load instructions with 64\-bit immediate as 32\-bit register load instructions with 31\-bit or 32\-bits immediates, encode 64\-bit register clearing instructions with 32\-bit -register clearing instructions, encode 256\-bit/512\-bit \s-1VEX/EVEX\s0 vector -register clearing instructions with 128\-bit \s-1VEX\s0 vector register -clearing instructions, encode 128\-bit/256\-bit \s-1EVEX\s0 vector -register load/store instructions with \s-1VEX\s0 vector register load/store -instructions, and encode 128\-bit/256\-bit \s-1EVEX\s0 packed integer logical -instructions with 128\-bit/256\-bit \s-1VEX\s0 packed integer logical. +register clearing instructions, encode 256\-bit/512\-bit VEX/EVEX vector +register clearing instructions with 128\-bit VEX vector register +clearing instructions, encode 128\-bit/256\-bit EVEX vector +register load/store instructions with VEX vector register load/store +instructions, and encode 128\-bit/256\-bit EVEX packed integer logical +instructions with 128\-bit/256\-bit VEX packed integer logical. .Sp \&\fB\-O2\fR includes \fB\-O1\fR optimization plus encodes -256\-bit/512\-bit \s-1EVEX\s0 vector register clearing instructions with 128\-bit -\&\s-1EVEX\s0 vector register clearing instructions. In 64\-bit mode \s-1VEX\s0 encoded +256\-bit/512\-bit EVEX vector register clearing instructions with 128\-bit +EVEX vector register clearing instructions. In 64\-bit mode VEX encoded instructions with commutative source operands will also have their -source operands swapped if this allows using the 2\-byte \s-1VEX\s0 prefix form -instead of the 3\-byte one. Certain forms of \s-1AND\s0 as well as \s-1OR\s0 with the -same (register) operand specified twice will also be changed to \s-1TEST.\s0 +source operands swapped if this allows using the 2\-byte VEX prefix form +instead of the 3\-byte one. Certain forms of AND as well as OR with the +same (register) operand specified twice will also be changed to TEST. .Sp \&\fB\-Os\fR includes \fB\-O2\fR optimization plus encodes 16\-bit, 32\-bit and 64\-bit register tests with immediate as 8\-bit register test with immediate. \fB\-O0\fR turns off this optimization. .PP The following options are available when as is configured for the -Ubicom \s-1IP2K\s0 series. -.IP "\fB\-mip2022ext\fR" 4 +Ubicom IP2K series. +.IP \fB\-mip2022ext\fR 4 .IX Item "-mip2022ext" -Specifies that the extended \s-1IP2022\s0 instructions are allowed. -.IP "\fB\-mip2022\fR" 4 +Specifies that the extended IP2022 instructions are allowed. +.IP \fB\-mip2022\fR 4 .IX Item "-mip2022" Restores the default behaviour, which restricts the permitted instructions to -just the basic \s-1IP2022\s0 ones. +just the basic IP2022 ones. .PP The following options are available when as is configured for the Renesas M32C and M16C processors. -.IP "\fB\-m32c\fR" 4 +.IP \fB\-m32c\fR 4 .IX Item "-m32c" Assemble M32C instructions. -.IP "\fB\-m16c\fR" 4 +.IP \fB\-m16c\fR 4 .IX Item "-m16c" Assemble M16C instructions (the default). -.IP "\fB\-relax\fR" 4 +.IP \fB\-relax\fR 4 .IX Item "-relax" Enable support for link-time relaxations. -.IP "\fB\-h\-tick\-hex\fR" 4 +.IP \fB\-h\-tick\-hex\fR 4 .IX Item "-h-tick-hex" Support H'00 style hex constants in addition to 0x00 style. .PP The following options are available when as is configured for the Renesas M32R (formerly Mitsubishi M32R) series. -.IP "\fB\-\-m32rx\fR" 4 +.IP \fB\-\-m32rx\fR 4 .IX Item "--m32rx" Specify which processor in the M32R family is the target. The default is normally the M32R, but this option changes it to the M32RX. @@ -1895,7 +1877,7 @@ encountered. .PP The following options are available when as is configured for the Motorola 68000 series. -.IP "\fB\-l\fR" 4 +.IP \fB\-l\fR 4 .IX Item "-l" Shorten references to undefined symbols, to one word instead of two. .IP "\fB\-m68000 | \-m68008 | \-m68010 | \-m68020 | \-m68030\fR" 4 @@ -1918,33 +1900,33 @@ coprocessor instructions with the main processor. .IP "\fB\-m68851 | \-mno\-68851\fR" 4 .IX Item "-m68851 | -mno-68851" The target machine does (or does not) have a memory-management -unit coprocessor. The default is to assume an \s-1MMU\s0 for 68020 and up. +unit coprocessor. The default is to assume an MMU for 68020 and up. .PP The following options are available when as is configured for an -Altera Nios \s-1II\s0 processor. -.IP "\fB\-relax\-section\fR" 4 +Altera Nios II processor. +.IP \fB\-relax\-section\fR 4 .IX Item "-relax-section" Replace identified out-of-range branches with PC-relative \f(CW\*(C`jmp\*(C'\fR sequences when possible. The generated code sequences are suitable for use in position-independent code, but there is a practical limit on the extended branch range because of the length of the sequences. This option is the default. -.IP "\fB\-relax\-all\fR" 4 +.IP \fB\-relax\-all\fR 4 .IX Item "-relax-all" Replace branch instructions not determinable to be in range and all call instructions with \f(CW\*(C`jmp\*(C'\fR and \f(CW\*(C`callr\*(C'\fR sequences (respectively). This option generates absolute relocations against the target symbols and is not appropriate for position-independent code. -.IP "\fB\-no\-relax\fR" 4 +.IP \fB\-no\-relax\fR 4 .IX Item "-no-relax" Do not replace any branches or calls. -.IP "\fB\-EB\fR" 4 +.IP \fB\-EB\fR 4 .IX Item "-EB" Generate big-endian output. -.IP "\fB\-EL\fR" 4 +.IP \fB\-EL\fR 4 .IX Item "-EL" Generate little-endian output. This is the default. -.IP "\fB\-march=\fR\fIarchitecture\fR" 4 +.IP \fB\-march=\fR\fIarchitecture\fR 4 .IX Item "-march=architecture" This option specifies the target architecture. The assembler issues an error message if an attempt is made to assemble an instruction which @@ -1955,104 +1937,104 @@ names are recognized: The default is \f(CW\*(C`r1\*(C'\fR. .PP The following options are available when as is configured for a -\&\s-1PRU\s0 processor. -.IP "\fB\-mlink\-relax\fR" 4 +PRU processor. +.IP \fB\-mlink\-relax\fR 4 .IX Item "-mlink-relax" -Assume that \s-1LD\s0 would optimize \s-1LDI32\s0 instructions by checking the upper -16 bits of the \fIexpression\fR. If they are all zeros, then \s-1LD\s0 would -shorten the \s-1LDI32\s0 instruction to a single \s-1LDI.\s0 In such case \f(CW\*(C`as\*(C'\fR -will output \s-1DIFF\s0 relocations for diff expressions. -.IP "\fB\-mno\-link\-relax\fR" 4 +Assume that LD would optimize LDI32 instructions by checking the upper +16 bits of the \fIexpression\fR. If they are all zeros, then LD would +shorten the LDI32 instruction to a single LDI. In such case \f(CW\*(C`as\*(C'\fR +will output DIFF relocations for diff expressions. +.IP \fB\-mno\-link\-relax\fR 4 .IX Item "-mno-link-relax" -Assume that \s-1LD\s0 would not optimize \s-1LDI32\s0 instructions. As a consequence, -\&\s-1DIFF\s0 relocations will not be emitted. -.IP "\fB\-mno\-warn\-regname\-label\fR" 4 +Assume that LD would not optimize LDI32 instructions. As a consequence, +DIFF relocations will not be emitted. +.IP \fB\-mno\-warn\-regname\-label\fR 4 .IX Item "-mno-warn-regname-label" Do not warn if a label name matches a register name. Usually assembler programmers will want this warning to be emitted. C compilers may want to turn this off. .PP The following options are available when as is configured for -a \s-1MIPS\s0 processor. +a MIPS processor. .IP "\fB\-G\fR \fInum\fR" 4 .IX Item "-G num" This option sets the largest size of an object that can be referenced implicitly with the \f(CW\*(C`gp\*(C'\fR register. It is only accepted for targets that -use \s-1ECOFF\s0 format, such as a DECstation running Ultrix. The default value is 8. -.IP "\fB\-EB\fR" 4 +use ECOFF format, such as a DECstation running Ultrix. The default value is 8. +.IP \fB\-EB\fR 4 .IX Item "-EB" -Generate \*(L"big endian\*(R" format output. -.IP "\fB\-EL\fR" 4 +Generate "big endian" format output. +.IP \fB\-EL\fR 4 .IX Item "-EL" -Generate \*(L"little endian\*(R" format output. -.IP "\fB\-mips1\fR" 4 +Generate "little endian" format output. +.IP \fB\-mips1\fR 4 .IX Item "-mips1" .PD 0 -.IP "\fB\-mips2\fR" 4 +.IP \fB\-mips2\fR 4 .IX Item "-mips2" -.IP "\fB\-mips3\fR" 4 +.IP \fB\-mips3\fR 4 .IX Item "-mips3" -.IP "\fB\-mips4\fR" 4 +.IP \fB\-mips4\fR 4 .IX Item "-mips4" -.IP "\fB\-mips5\fR" 4 +.IP \fB\-mips5\fR 4 .IX Item "-mips5" -.IP "\fB\-mips32\fR" 4 +.IP \fB\-mips32\fR 4 .IX Item "-mips32" -.IP "\fB\-mips32r2\fR" 4 +.IP \fB\-mips32r2\fR 4 .IX Item "-mips32r2" -.IP "\fB\-mips32r3\fR" 4 +.IP \fB\-mips32r3\fR 4 .IX Item "-mips32r3" -.IP "\fB\-mips32r5\fR" 4 +.IP \fB\-mips32r5\fR 4 .IX Item "-mips32r5" -.IP "\fB\-mips32r6\fR" 4 +.IP \fB\-mips32r6\fR 4 .IX Item "-mips32r6" -.IP "\fB\-mips64\fR" 4 +.IP \fB\-mips64\fR 4 .IX Item "-mips64" -.IP "\fB\-mips64r2\fR" 4 +.IP \fB\-mips64r2\fR 4 .IX Item "-mips64r2" -.IP "\fB\-mips64r3\fR" 4 +.IP \fB\-mips64r3\fR 4 .IX Item "-mips64r3" -.IP "\fB\-mips64r5\fR" 4 +.IP \fB\-mips64r5\fR 4 .IX Item "-mips64r5" -.IP "\fB\-mips64r6\fR" 4 +.IP \fB\-mips64r6\fR 4 .IX Item "-mips64r6" .PD -Generate code for a particular \s-1MIPS\s0 Instruction Set Architecture level. +Generate code for a particular MIPS Instruction Set Architecture level. \&\fB\-mips1\fR is an alias for \fB\-march=r3000\fR, \fB\-mips2\fR is an alias for \fB\-march=r6000\fR, \fB\-mips3\fR is an alias for \&\fB\-march=r4000\fR and \fB\-mips4\fR is an alias for \fB\-march=r8000\fR. \&\fB\-mips5\fR, \fB\-mips32\fR, \fB\-mips32r2\fR, \fB\-mips32r3\fR, \&\fB\-mips32r5\fR, \fB\-mips32r6\fR, \fB\-mips64\fR, \fB\-mips64r2\fR, \&\fB\-mips64r3\fR, \fB\-mips64r5\fR, and \fB\-mips64r6\fR correspond to generic -\&\s-1MIPS V, MIPS32, MIPS32\s0 Release 2, \s-1MIPS32\s0 Release 3, \s-1MIPS32\s0 Release 5, \s-1MIPS32\s0 -Release 6, \s-1MIPS64, MIPS64\s0 Release 2, \s-1MIPS64\s0 Release 3, \s-1MIPS64\s0 Release 5, and -\&\s-1MIPS64\s0 Release 6 \s-1ISA\s0 processors, respectively. -.IP "\fB\-march=\fR\fIcpu\fR" 4 +MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 Release 5, MIPS32 +Release 6, MIPS64, MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and +MIPS64 Release 6 ISA processors, respectively. +.IP \fB\-march=\fR\fIcpu\fR 4 .IX Item "-march=cpu" -Generate code for a particular \s-1MIPS CPU.\s0 -.IP "\fB\-mtune=\fR\fIcpu\fR" 4 +Generate code for a particular MIPS CPU. +.IP \fB\-mtune=\fR\fIcpu\fR 4 .IX Item "-mtune=cpu" -Schedule and tune for a particular \s-1MIPS CPU.\s0 -.IP "\fB\-mfix7000\fR" 4 +Schedule and tune for a particular MIPS CPU. +.IP \fB\-mfix7000\fR 4 .IX Item "-mfix7000" .PD 0 -.IP "\fB\-mno\-fix7000\fR" 4 +.IP \fB\-mno\-fix7000\fR 4 .IX Item "-mno-fix7000" .PD Cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions. -.IP "\fB\-mfix\-rm7000\fR" 4 +.IP \fB\-mfix\-rm7000\fR 4 .IX Item "-mfix-rm7000" .PD 0 -.IP "\fB\-mno\-fix\-rm7000\fR" 4 +.IP \fB\-mno\-fix\-rm7000\fR 4 .IX Item "-mno-fix-rm7000" .PD Cause nops to be inserted if a dmult or dmultu instruction is followed by a load instruction. -.IP "\fB\-mfix\-r5900\fR" 4 +.IP \fB\-mfix\-r5900\fR 4 .IX Item "-mfix-r5900" .PD 0 -.IP "\fB\-mno\-fix\-r5900\fR" 4 +.IP \fB\-mno\-fix\-r5900\fR 4 .IX Item "-mno-fix-r5900" .PD Do not attempt to schedule the preceding instruction into the delay slot @@ -2060,236 +2042,236 @@ of a branch instruction placed at the end of a short loop of six instructions or fewer and always schedule a \f(CW\*(C`nop\*(C'\fR instruction there instead. The short loop bug under certain conditions causes loops to execute only once or twice, due to a hardware bug in the R5900 chip. -.IP "\fB\-mdebug\fR" 4 +.IP \fB\-mdebug\fR 4 .IX Item "-mdebug" .PD 0 -.IP "\fB\-no\-mdebug\fR" 4 +.IP \fB\-no\-mdebug\fR 4 .IX Item "-no-mdebug" .PD Cause stabs-style debugging output to go into an ECOFF-style .mdebug -section instead of the standard \s-1ELF\s0 .stabs sections. -.IP "\fB\-mpdr\fR" 4 +section instead of the standard ELF .stabs sections. +.IP \fB\-mpdr\fR 4 .IX Item "-mpdr" .PD 0 -.IP "\fB\-mno\-pdr\fR" 4 +.IP \fB\-mno\-pdr\fR 4 .IX Item "-mno-pdr" .PD Control generation of \f(CW\*(C`.pdr\*(C'\fR sections. -.IP "\fB\-mgp32\fR" 4 +.IP \fB\-mgp32\fR 4 .IX Item "-mgp32" .PD 0 -.IP "\fB\-mfp32\fR" 4 +.IP \fB\-mfp32\fR 4 .IX Item "-mfp32" .PD -The register sizes are normally inferred from the \s-1ISA\s0 and \s-1ABI,\s0 but these +The register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 32 bits wide at all times. \fB\-mgp32\fR controls the size of general-purpose registers and \fB\-mfp32\fR controls the size of floating-point registers. -.IP "\fB\-mgp64\fR" 4 +.IP \fB\-mgp64\fR 4 .IX Item "-mgp64" .PD 0 -.IP "\fB\-mfp64\fR" 4 +.IP \fB\-mfp64\fR 4 .IX Item "-mfp64" .PD -The register sizes are normally inferred from the \s-1ISA\s0 and \s-1ABI,\s0 but these +The register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 64 bits wide at all times. \fB\-mgp64\fR controls the size of general-purpose registers and \fB\-mfp64\fR controls the size of floating-point registers. -.IP "\fB\-mfpxx\fR" 4 +.IP \fB\-mfpxx\fR 4 .IX Item "-mfpxx" -The register sizes are normally inferred from the \s-1ISA\s0 and \s-1ABI,\s0 but using -this flag in combination with \fB\-mabi=32\fR enables an \s-1ABI\s0 variant +The register sizes are normally inferred from the ISA and ABI, but using +this flag in combination with \fB\-mabi=32\fR enables an ABI variant which will operate correctly with floating-point registers which are 32 or 64 bits wide. -.IP "\fB\-modd\-spreg\fR" 4 +.IP \fB\-modd\-spreg\fR 4 .IX Item "-modd-spreg" .PD 0 -.IP "\fB\-mno\-odd\-spreg\fR" 4 +.IP \fB\-mno\-odd\-spreg\fR 4 .IX Item "-mno-odd-spreg" .PD Enable use of floating-point operations on odd-numbered single-precision -registers when supported by the \s-1ISA.\s0 \fB\-mfpxx\fR implies +registers when supported by the ISA. \fB\-mfpxx\fR implies \&\fB\-mno\-odd\-spreg\fR, otherwise the default is \fB\-modd\-spreg\fR. -.IP "\fB\-mips16\fR" 4 +.IP \fB\-mips16\fR 4 .IX Item "-mips16" .PD 0 -.IP "\fB\-no\-mips16\fR" 4 +.IP \fB\-no\-mips16\fR 4 .IX Item "-no-mips16" .PD -Generate code for the \s-1MIPS 16\s0 processor. This is equivalent to putting +Generate code for the MIPS 16 processor. This is equivalent to putting \&\f(CW\*(C`.module mips16\*(C'\fR at the start of the assembly file. \fB\-no\-mips16\fR turns off this option. -.IP "\fB\-mmips16e2\fR" 4 +.IP \fB\-mmips16e2\fR 4 .IX Item "-mmips16e2" .PD 0 -.IP "\fB\-mno\-mips16e2\fR" 4 +.IP \fB\-mno\-mips16e2\fR 4 .IX Item "-mno-mips16e2" .PD -Enable the use of MIPS16e2 instructions in \s-1MIPS16\s0 mode. This is equivalent +Enable the use of MIPS16e2 instructions in MIPS16 mode. This is equivalent to putting \f(CW\*(C`.module mips16e2\*(C'\fR at the start of the assembly file. \&\fB\-mno\-mips16e2\fR turns off this option. -.IP "\fB\-mmicromips\fR" 4 +.IP \fB\-mmicromips\fR 4 .IX Item "-mmicromips" .PD 0 -.IP "\fB\-mno\-micromips\fR" 4 +.IP \fB\-mno\-micromips\fR 4 .IX Item "-mno-micromips" .PD Generate code for the microMIPS processor. This is equivalent to putting \&\f(CW\*(C`.module micromips\*(C'\fR at the start of the assembly file. \&\fB\-mno\-micromips\fR turns off this option. This is equivalent to putting \&\f(CW\*(C`.module nomicromips\*(C'\fR at the start of the assembly file. -.IP "\fB\-msmartmips\fR" 4 +.IP \fB\-msmartmips\fR 4 .IX Item "-msmartmips" .PD 0 -.IP "\fB\-mno\-smartmips\fR" 4 +.IP \fB\-mno\-smartmips\fR 4 .IX Item "-mno-smartmips" .PD -Enables the SmartMIPS extension to the \s-1MIPS32\s0 instruction set. This is +Enables the SmartMIPS extension to the MIPS32 instruction set. This is equivalent to putting \f(CW\*(C`.module smartmips\*(C'\fR at the start of the assembly file. \fB\-mno\-smartmips\fR turns off this option. -.IP "\fB\-mips3d\fR" 4 +.IP \fB\-mips3d\fR 4 .IX Item "-mips3d" .PD 0 -.IP "\fB\-no\-mips3d\fR" 4 +.IP \fB\-no\-mips3d\fR 4 .IX Item "-no-mips3d" .PD -Generate code for the \s-1MIPS\-3D\s0 Application Specific Extension. -This tells the assembler to accept \s-1MIPS\-3D\s0 instructions. +Generate code for the MIPS\-3D Application Specific Extension. +This tells the assembler to accept MIPS\-3D instructions. \&\fB\-no\-mips3d\fR turns off this option. -.IP "\fB\-mdmx\fR" 4 +.IP \fB\-mdmx\fR 4 .IX Item "-mdmx" .PD 0 -.IP "\fB\-no\-mdmx\fR" 4 +.IP \fB\-no\-mdmx\fR 4 .IX Item "-no-mdmx" .PD -Generate code for the \s-1MDMX\s0 Application Specific Extension. -This tells the assembler to accept \s-1MDMX\s0 instructions. +Generate code for the MDMX Application Specific Extension. +This tells the assembler to accept MDMX instructions. \&\fB\-no\-mdmx\fR turns off this option. -.IP "\fB\-mdsp\fR" 4 +.IP \fB\-mdsp\fR 4 .IX Item "-mdsp" .PD 0 -.IP "\fB\-mno\-dsp\fR" 4 +.IP \fB\-mno\-dsp\fR 4 .IX Item "-mno-dsp" .PD -Generate code for the \s-1DSP\s0 Release 1 Application Specific Extension. -This tells the assembler to accept \s-1DSP\s0 Release 1 instructions. +Generate code for the DSP Release 1 Application Specific Extension. +This tells the assembler to accept DSP Release 1 instructions. \&\fB\-mno\-dsp\fR turns off this option. -.IP "\fB\-mdspr2\fR" 4 +.IP \fB\-mdspr2\fR 4 .IX Item "-mdspr2" .PD 0 -.IP "\fB\-mno\-dspr2\fR" 4 +.IP \fB\-mno\-dspr2\fR 4 .IX Item "-mno-dspr2" .PD -Generate code for the \s-1DSP\s0 Release 2 Application Specific Extension. +Generate code for the DSP Release 2 Application Specific Extension. This option implies \fB\-mdsp\fR. -This tells the assembler to accept \s-1DSP\s0 Release 2 instructions. +This tells the assembler to accept DSP Release 2 instructions. \&\fB\-mno\-dspr2\fR turns off this option. -.IP "\fB\-mdspr3\fR" 4 +.IP \fB\-mdspr3\fR 4 .IX Item "-mdspr3" .PD 0 -.IP "\fB\-mno\-dspr3\fR" 4 +.IP \fB\-mno\-dspr3\fR 4 .IX Item "-mno-dspr3" .PD -Generate code for the \s-1DSP\s0 Release 3 Application Specific Extension. +Generate code for the DSP Release 3 Application Specific Extension. This option implies \fB\-mdsp\fR and \fB\-mdspr2\fR. -This tells the assembler to accept \s-1DSP\s0 Release 3 instructions. +This tells the assembler to accept DSP Release 3 instructions. \&\fB\-mno\-dspr3\fR turns off this option. -.IP "\fB\-mmsa\fR" 4 +.IP \fB\-mmsa\fR 4 .IX Item "-mmsa" .PD 0 -.IP "\fB\-mno\-msa\fR" 4 +.IP \fB\-mno\-msa\fR 4 .IX Item "-mno-msa" .PD -Generate code for the \s-1MIPS SIMD\s0 Architecture Extension. -This tells the assembler to accept \s-1MSA\s0 instructions. +Generate code for the MIPS SIMD Architecture Extension. +This tells the assembler to accept MSA instructions. \&\fB\-mno\-msa\fR turns off this option. -.IP "\fB\-mxpa\fR" 4 +.IP \fB\-mxpa\fR 4 .IX Item "-mxpa" .PD 0 -.IP "\fB\-mno\-xpa\fR" 4 +.IP \fB\-mno\-xpa\fR 4 .IX Item "-mno-xpa" .PD -Generate code for the \s-1MIPS\s0 eXtended Physical Address (\s-1XPA\s0) Extension. -This tells the assembler to accept \s-1XPA\s0 instructions. +Generate code for the MIPS eXtended Physical Address (XPA) Extension. +This tells the assembler to accept XPA instructions. \&\fB\-mno\-xpa\fR turns off this option. -.IP "\fB\-mmt\fR" 4 +.IP \fB\-mmt\fR 4 .IX Item "-mmt" .PD 0 -.IP "\fB\-mno\-mt\fR" 4 +.IP \fB\-mno\-mt\fR 4 .IX Item "-mno-mt" .PD -Generate code for the \s-1MT\s0 Application Specific Extension. -This tells the assembler to accept \s-1MT\s0 instructions. +Generate code for the MT Application Specific Extension. +This tells the assembler to accept MT instructions. \&\fB\-mno\-mt\fR turns off this option. -.IP "\fB\-mmcu\fR" 4 +.IP \fB\-mmcu\fR 4 .IX Item "-mmcu" .PD 0 -.IP "\fB\-mno\-mcu\fR" 4 +.IP \fB\-mno\-mcu\fR 4 .IX Item "-mno-mcu" .PD -Generate code for the \s-1MCU\s0 Application Specific Extension. -This tells the assembler to accept \s-1MCU\s0 instructions. +Generate code for the MCU Application Specific Extension. +This tells the assembler to accept MCU instructions. \&\fB\-mno\-mcu\fR turns off this option. -.IP "\fB\-mcrc\fR" 4 +.IP \fB\-mcrc\fR 4 .IX Item "-mcrc" .PD 0 -.IP "\fB\-mno\-crc\fR" 4 +.IP \fB\-mno\-crc\fR 4 .IX Item "-mno-crc" .PD -Generate code for the \s-1MIPS\s0 cyclic redundancy check (\s-1CRC\s0) Application -Specific Extension. This tells the assembler to accept \s-1CRC\s0 instructions. +Generate code for the MIPS cyclic redundancy check (CRC) Application +Specific Extension. This tells the assembler to accept CRC instructions. \&\fB\-mno\-crc\fR turns off this option. -.IP "\fB\-mginv\fR" 4 +.IP \fB\-mginv\fR 4 .IX Item "-mginv" .PD 0 -.IP "\fB\-mno\-ginv\fR" 4 +.IP \fB\-mno\-ginv\fR 4 .IX Item "-mno-ginv" .PD -Generate code for the Global INValidate (\s-1GINV\s0) Application Specific -Extension. This tells the assembler to accept \s-1GINV\s0 instructions. +Generate code for the Global INValidate (GINV) Application Specific +Extension. This tells the assembler to accept GINV instructions. \&\fB\-mno\-ginv\fR turns off this option. -.IP "\fB\-mloongson\-mmi\fR" 4 +.IP \fB\-mloongson\-mmi\fR 4 .IX Item "-mloongson-mmi" .PD 0 -.IP "\fB\-mno\-loongson\-mmi\fR" 4 +.IP \fB\-mno\-loongson\-mmi\fR 4 .IX Item "-mno-loongson-mmi" .PD -Generate code for the Loongson MultiMedia extensions Instructions (\s-1MMI\s0) -Application Specific Extension. This tells the assembler to accept \s-1MMI\s0 +Generate code for the Loongson MultiMedia extensions Instructions (MMI) +Application Specific Extension. This tells the assembler to accept MMI instructions. \&\fB\-mno\-loongson\-mmi\fR turns off this option. -.IP "\fB\-mloongson\-cam\fR" 4 +.IP \fB\-mloongson\-cam\fR 4 .IX Item "-mloongson-cam" .PD 0 -.IP "\fB\-mno\-loongson\-cam\fR" 4 +.IP \fB\-mno\-loongson\-cam\fR 4 .IX Item "-mno-loongson-cam" .PD -Generate code for the Loongson Content Address Memory (\s-1CAM\s0) instructions. -This tells the assembler to accept Loongson \s-1CAM\s0 instructions. +Generate code for the Loongson Content Address Memory (CAM) instructions. +This tells the assembler to accept Loongson CAM instructions. \&\fB\-mno\-loongson\-cam\fR turns off this option. -.IP "\fB\-mloongson\-ext\fR" 4 +.IP \fB\-mloongson\-ext\fR 4 .IX Item "-mloongson-ext" .PD 0 -.IP "\fB\-mno\-loongson\-ext\fR" 4 +.IP \fB\-mno\-loongson\-ext\fR 4 .IX Item "-mno-loongson-ext" .PD -Generate code for the Loongson EXTensions (\s-1EXT\s0) instructions. -This tells the assembler to accept Loongson \s-1EXT\s0 instructions. +Generate code for the Loongson EXTensions (EXT) instructions. +This tells the assembler to accept Loongson EXT instructions. \&\fB\-mno\-loongson\-ext\fR turns off this option. -.IP "\fB\-mloongson\-ext2\fR" 4 +.IP \fB\-mloongson\-ext2\fR 4 .IX Item "-mloongson-ext2" .PD 0 -.IP "\fB\-mno\-loongson\-ext2\fR" 4 +.IP \fB\-mno\-loongson\-ext2\fR 4 .IX Item "-mno-loongson-ext2" .PD -Generate code for the Loongson EXTensions R2 (\s-1EXT2\s0) instructions. +Generate code for the Loongson EXTensions R2 (EXT2) instructions. This option implies \fB\-mloongson\-ext\fR. -This tells the assembler to accept Loongson \s-1EXT2\s0 instructions. +This tells the assembler to accept Loongson EXT2 instructions. \&\fB\-mno\-loongson\-ext2\fR turns off this option. -.IP "\fB\-minsn32\fR" 4 +.IP \fB\-minsn32\fR 4 .IX Item "-minsn32" .PD 0 -.IP "\fB\-mno\-insn32\fR" 4 +.IP \fB\-mno\-insn32\fR 4 .IX Item "-mno-insn32" .PD Only use 32\-bit instruction encodings when generating code for the @@ -2299,10 +2281,10 @@ the start of the assembly file. \fB\-mno\-insn32\fR turns off this option. This is equivalent to putting \f(CW\*(C`.set noinsn32\*(C'\fR at the start of the assembly file. By default \fB\-mno\-insn32\fR is selected, allowing all instructions to be used. -.IP "\fB\-\-construct\-floats\fR" 4 +.IP \fB\-\-construct\-floats\fR 4 .IX Item "--construct-floats" .PD 0 -.IP "\fB\-\-no\-construct\-floats\fR" 4 +.IP \fB\-\-no\-construct\-floats\fR 4 .IX Item "--no-construct-floats" .PD The \fB\-\-no\-construct\-floats\fR option disables the construction of @@ -2310,57 +2292,57 @@ double width floating point constants by loading the two halves of the value into the two single width floating point registers that make up the double width register. By default \fB\-\-construct\-floats\fR is selected, allowing construction of these floating point constants. -.IP "\fB\-\-relax\-branch\fR" 4 +.IP \fB\-\-relax\-branch\fR 4 .IX Item "--relax-branch" .PD 0 -.IP "\fB\-\-no\-relax\-branch\fR" 4 +.IP \fB\-\-no\-relax\-branch\fR 4 .IX Item "--no-relax-branch" .PD The \fB\-\-relax\-branch\fR option enables the relaxation of out-of-range branches. By default \fB\-\-no\-relax\-branch\fR is selected, causing any out-of-range branches to produce an error. -.IP "\fB\-mignore\-branch\-isa\fR" 4 +.IP \fB\-mignore\-branch\-isa\fR 4 .IX Item "-mignore-branch-isa" .PD 0 -.IP "\fB\-mno\-ignore\-branch\-isa\fR" 4 +.IP \fB\-mno\-ignore\-branch\-isa\fR 4 .IX Item "-mno-ignore-branch-isa" .PD -Ignore branch checks for invalid transitions between \s-1ISA\s0 modes. The -semantics of branches does not provide for an \s-1ISA\s0 mode switch, so in -most cases the \s-1ISA\s0 mode a branch has been encoded for has to be the -same as the \s-1ISA\s0 mode of the branch's target label. Therefore \s-1GAS\s0 has -checks implemented that verify in branch assembly that the two \s-1ISA\s0 +Ignore branch checks for invalid transitions between ISA modes. The +semantics of branches does not provide for an ISA mode switch, so in +most cases the ISA mode a branch has been encoded for has to be the +same as the ISA mode of the branch's target label. Therefore GAS has +checks implemented that verify in branch assembly that the two ISA modes match. \fB\-mignore\-branch\-isa\fR disables these checks. By default \fB\-mno\-ignore\-branch\-isa\fR is selected, causing any invalid -branch requiring a transition between \s-1ISA\s0 modes to produce an error. -.IP "\fB\-mnan=\fR\fIencoding\fR" 4 +branch requiring a transition between ISA modes to produce an error. +.IP \fB\-mnan=\fR\fIencoding\fR 4 .IX Item "-mnan=encoding" -Select between the \s-1IEEE 754\-2008\s0 (\fB\-mnan=2008\fR) or the legacy +Select between the IEEE 754\-2008 (\fB\-mnan=2008\fR) or the legacy (\fB\-mnan=legacy\fR) NaN encoding format. The latter is the default. -.IP "\fB\-\-emulation=\fR\fIname\fR" 4 +.IP \fB\-\-emulation=\fR\fIname\fR 4 .IX Item "--emulation=name" -This option was formerly used to switch between \s-1ELF\s0 and \s-1ECOFF\s0 output -on targets like \s-1IRIX 5\s0 that supported both. \s-1MIPS ECOFF\s0 support was -removed in \s-1GAS 2.24,\s0 so the option now serves little purpose. +This option was formerly used to switch between ELF and ECOFF output +on targets like IRIX 5 that supported both. MIPS ECOFF support was +removed in GAS 2.24, so the option now serves little purpose. It is retained for backwards compatibility. .Sp The available configuration names are: \fBmipself\fR, \fBmipslelf\fR and \&\fBmipsbelf\fR. Choosing \fBmipself\fR now has no effect, since the output -is always \s-1ELF.\s0 \fBmipslelf\fR and \fBmipsbelf\fR select little\- and +is always ELF. \fBmipslelf\fR and \fBmipsbelf\fR select little\- and big-endian output respectively, but \fB\-EL\fR and \fB\-EB\fR are now the preferred options instead. -.IP "\fB\-nocpp\fR" 4 +.IP \fB\-nocpp\fR 4 .IX Item "-nocpp" \&\fBas\fR ignores this option. It is accepted for compatibility with the native tools. -.IP "\fB\-\-trap\fR" 4 +.IP \fB\-\-trap\fR 4 .IX Item "--trap" .PD 0 -.IP "\fB\-\-no\-trap\fR" 4 +.IP \fB\-\-no\-trap\fR 4 .IX Item "--no-trap" -.IP "\fB\-\-break\fR" 4 +.IP \fB\-\-break\fR 4 .IX Item "--break" -.IP "\fB\-\-no\-break\fR" 4 +.IP \fB\-\-no\-break\fR 4 .IX Item "--no-break" .PD Control how to deal with multiplication overflow and division by zero. @@ -2368,77 +2350,77 @@ Control how to deal with multiplication overflow and division by zero. (and only work for Instruction Set Architecture level 2 and higher); \&\fB\-\-break\fR or \fB\-\-no\-trap\fR (also synonyms, and the default) take a break exception. -.IP "\fB\-n\fR" 4 +.IP \fB\-n\fR 4 .IX Item "-n" When this option is used, \fBas\fR will issue a warning every time it generates a nop instruction from a macro. .PP The following options are available when as is configured for a LoongArch processor. -.IP "\fB\-fpic\fR" 4 +.IP \fB\-fpic\fR 4 .IX Item "-fpic" .PD 0 -.IP "\fB\-fPIC\fR" 4 +.IP \fB\-fPIC\fR 4 .IX Item "-fPIC" .PD Generate position-independent code -.IP "\fB\-fno\-pic\fR" 4 +.IP \fB\-fno\-pic\fR 4 .IX Item "-fno-pic" Don't generate position-independent code (default) .PP The following options are available when as is configured for a Meta processor. .ie n .IP """\-mcpu=metac11""" 4 -.el .IP "\f(CW\-mcpu=metac11\fR" 4 +.el .IP \f(CW\-mcpu=metac11\fR 4 .IX Item "-mcpu=metac11" Generate code for Meta 1.1. .ie n .IP """\-mcpu=metac12""" 4 -.el .IP "\f(CW\-mcpu=metac12\fR" 4 +.el .IP \f(CW\-mcpu=metac12\fR 4 .IX Item "-mcpu=metac12" Generate code for Meta 1.2. .ie n .IP """\-mcpu=metac21""" 4 -.el .IP "\f(CW\-mcpu=metac21\fR" 4 +.el .IP \f(CW\-mcpu=metac21\fR 4 .IX Item "-mcpu=metac21" Generate code for Meta 2.1. .ie n .IP """\-mfpu=metac21""" 4 -.el .IP "\f(CW\-mfpu=metac21\fR" 4 +.el .IP \f(CW\-mfpu=metac21\fR 4 .IX Item "-mfpu=metac21" -Allow code to use \s-1FPU\s0 hardware of Meta 2.1. +Allow code to use FPU hardware of Meta 2.1. .PP See the info pages for documentation of the MMIX-specific options. .PP The following options are available when as is configured for a -\&\s-1NDS32\s0 processor. +NDS32 processor. .ie n .IP """\-O1""" 4 -.el .IP "\f(CW\-O1\fR" 4 +.el .IP \f(CW\-O1\fR 4 .IX Item "-O1" Optimize for performance. .ie n .IP """\-Os""" 4 -.el .IP "\f(CW\-Os\fR" 4 +.el .IP \f(CW\-Os\fR 4 .IX Item "-Os" Optimize for space. .ie n .IP """\-EL""" 4 -.el .IP "\f(CW\-EL\fR" 4 +.el .IP \f(CW\-EL\fR 4 .IX Item "-EL" Produce little endian data output. .ie n .IP """\-EB""" 4 -.el .IP "\f(CW\-EB\fR" 4 +.el .IP \f(CW\-EB\fR 4 .IX Item "-EB" Produce little endian data output. .ie n .IP """\-mpic""" 4 -.el .IP "\f(CW\-mpic\fR" 4 +.el .IP \f(CW\-mpic\fR 4 .IX Item "-mpic" -Generate \s-1PIC.\s0 +Generate PIC. .ie n .IP """\-mno\-fp\-as\-gp\-relax""" 4 -.el .IP "\f(CW\-mno\-fp\-as\-gp\-relax\fR" 4 +.el .IP \f(CW\-mno\-fp\-as\-gp\-relax\fR 4 .IX Item "-mno-fp-as-gp-relax" Suppress fp-as-gp relaxation for this file. .ie n .IP """\-mb2bb\-relax""" 4 -.el .IP "\f(CW\-mb2bb\-relax\fR" 4 +.el .IP \f(CW\-mb2bb\-relax\fR 4 .IX Item "-mb2bb-relax" Back-to-back branch optimization. .ie n .IP """\-mno\-all\-relax""" 4 -.el .IP "\f(CW\-mno\-all\-relax\fR" 4 +.el .IP \f(CW\-mno\-all\-relax\fR 4 .IX Item "-mno-all-relax" Suppress all relaxation for this file. .ie n .IP """\-march=<arch name>""" 4 @@ -2447,13 +2429,13 @@ Suppress all relaxation for this file. Assemble for architecture <arch name> which could be v3, v3j, v3m, v3f, v3s, v2, v2j, v2f, v2s. .ie n .IP """\-mbaseline=<baseline>""" 4 -.el .IP "\f(CW\-mbaseline=<baseline>\fR" 4 +.el .IP \f(CW\-mbaseline=<baseline>\fR 4 .IX Item "-mbaseline=<baseline>" Assemble for baseline <baseline> which could be v2, v3, v3m. -.ie n .IP """\-mfpu\-freg=\fIFREG\fP""" 4 -.el .IP "\f(CW\-mfpu\-freg=\f(CIFREG\f(CW\fR" 4 +.ie n .IP """\-mfpu\-freg=\fIFREG\fR""" 4 +.el .IP \f(CW\-mfpu\-freg=\fR\f(CIFREG\fR\f(CW\fR 4 .IX Item "-mfpu-freg=FREG" -Specify a \s-1FPU\s0 configuration. +Specify a FPU configuration. .RS 4 .ie n .IP """0 8 SP / 4 DP registers""" 4 .el .IP "\f(CW0 8 SP / 4 DP registers\fR" 4 @@ -2471,82 +2453,82 @@ Specify a \s-1FPU\s0 configuration. .RE .RS 4 .RE -.ie n .IP """\-mabi=\fIabi\fP""" 4 -.el .IP "\f(CW\-mabi=\f(CIabi\f(CW\fR" 4 +.ie n .IP """\-mabi=\fIabi\fR""" 4 +.el .IP \f(CW\-mabi=\fR\f(CIabi\fR\f(CW\fR 4 .IX Item "-mabi=abi" .PD Specify a abi version <abi> could be v1, v2, v2fp, v2fpp. .ie n .IP """\-m[no\-]mac""" 4 -.el .IP "\f(CW\-m[no\-]mac\fR" 4 +.el .IP \f(CW\-m[no\-]mac\fR 4 .IX Item "-m[no-]mac" Enable/Disable Multiply instructions support. .ie n .IP """\-m[no\-]div""" 4 -.el .IP "\f(CW\-m[no\-]div\fR" 4 +.el .IP \f(CW\-m[no\-]div\fR 4 .IX Item "-m[no-]div" Enable/Disable Divide instructions support. .ie n .IP """\-m[no\-]16bit\-ext""" 4 -.el .IP "\f(CW\-m[no\-]16bit\-ext\fR" 4 +.el .IP \f(CW\-m[no\-]16bit\-ext\fR 4 .IX Item "-m[no-]16bit-ext" Enable/Disable 16\-bit extension .ie n .IP """\-m[no\-]dx\-regs""" 4 -.el .IP "\f(CW\-m[no\-]dx\-regs\fR" 4 +.el .IP \f(CW\-m[no\-]dx\-regs\fR 4 .IX Item "-m[no-]dx-regs" Enable/Disable d0/d1 registers .ie n .IP """\-m[no\-]perf\-ext""" 4 -.el .IP "\f(CW\-m[no\-]perf\-ext\fR" 4 +.el .IP \f(CW\-m[no\-]perf\-ext\fR 4 .IX Item "-m[no-]perf-ext" Enable/Disable Performance extension .ie n .IP """\-m[no\-]perf2\-ext""" 4 -.el .IP "\f(CW\-m[no\-]perf2\-ext\fR" 4 +.el .IP \f(CW\-m[no\-]perf2\-ext\fR 4 .IX Item "-m[no-]perf2-ext" Enable/Disable Performance extension 2 .ie n .IP """\-m[no\-]string\-ext""" 4 -.el .IP "\f(CW\-m[no\-]string\-ext\fR" 4 +.el .IP \f(CW\-m[no\-]string\-ext\fR 4 .IX Item "-m[no-]string-ext" Enable/Disable String extension .ie n .IP """\-m[no\-]reduced\-regs""" 4 -.el .IP "\f(CW\-m[no\-]reduced\-regs\fR" 4 +.el .IP \f(CW\-m[no\-]reduced\-regs\fR 4 .IX Item "-m[no-]reduced-regs" -Enable/Disable Reduced Register configuration (\s-1GPR16\s0) option +Enable/Disable Reduced Register configuration (GPR16) option .ie n .IP """\-m[no\-]audio\-isa\-ext""" 4 -.el .IP "\f(CW\-m[no\-]audio\-isa\-ext\fR" 4 +.el .IP \f(CW\-m[no\-]audio\-isa\-ext\fR 4 .IX Item "-m[no-]audio-isa-ext" -Enable/Disable \s-1AUDIO ISA\s0 extension +Enable/Disable AUDIO ISA extension .ie n .IP """\-m[no\-]fpu\-sp\-ext""" 4 -.el .IP "\f(CW\-m[no\-]fpu\-sp\-ext\fR" 4 +.el .IP \f(CW\-m[no\-]fpu\-sp\-ext\fR 4 .IX Item "-m[no-]fpu-sp-ext" -Enable/Disable \s-1FPU SP\s0 extension +Enable/Disable FPU SP extension .ie n .IP """\-m[no\-]fpu\-dp\-ext""" 4 -.el .IP "\f(CW\-m[no\-]fpu\-dp\-ext\fR" 4 +.el .IP \f(CW\-m[no\-]fpu\-dp\-ext\fR 4 .IX Item "-m[no-]fpu-dp-ext" -Enable/Disable \s-1FPU DP\s0 extension +Enable/Disable FPU DP extension .ie n .IP """\-m[no\-]fpu\-fma""" 4 -.el .IP "\f(CW\-m[no\-]fpu\-fma\fR" 4 +.el .IP \f(CW\-m[no\-]fpu\-fma\fR 4 .IX Item "-m[no-]fpu-fma" -Enable/Disable \s-1FPU\s0 fused-multiply-add instructions +Enable/Disable FPU fused-multiply-add instructions .ie n .IP """\-mall\-ext""" 4 -.el .IP "\f(CW\-mall\-ext\fR" 4 +.el .IP \f(CW\-mall\-ext\fR 4 .IX Item "-mall-ext" Turn on all extensions and instructions support .PP The following options are available when as is configured for a PowerPC processor. -.IP "\fB\-a32\fR" 4 +.IP \fB\-a32\fR 4 .IX Item "-a32" -Generate \s-1ELF32\s0 or \s-1XCOFF32.\s0 -.IP "\fB\-a64\fR" 4 +Generate ELF32 or XCOFF32. +.IP \fB\-a64\fR 4 .IX Item "-a64" -Generate \s-1ELF64\s0 or \s-1XCOFF64.\s0 -.IP "\fB\-K \s-1PIC\s0\fR" 4 +Generate ELF64 or XCOFF64. +.IP "\fB\-K PIC\fR" 4 .IX Item "-K PIC" -Set \s-1EF_PPC_RELOCATABLE_LIB\s0 in \s-1ELF\s0 flags. +Set EF_PPC_RELOCATABLE_LIB in ELF flags. .IP "\fB\-mpwrx | \-mpwr2\fR" 4 .IX Item "-mpwrx | -mpwr2" -Generate code for \s-1POWER/2\s0 (\s-1RIOS2\s0). -.IP "\fB\-mpwr\fR" 4 +Generate code for POWER/2 (RIOS2). +.IP \fB\-mpwr\fR 4 .IX Item "-mpwr" -Generate code for \s-1POWER\s0 (\s-1RIOS1\s0) -.IP "\fB\-m601\fR" 4 +Generate code for POWER (RIOS1) +.IP \fB\-m601\fR 4 .IX Item "-m601" Generate code for PowerPC 601. .IP "\fB\-mppc, \-mppc32, \-m603, \-m604\fR" 4 @@ -2555,13 +2537,13 @@ Generate code for PowerPC 603/604. .IP "\fB\-m403, \-m405\fR" 4 .IX Item "-m403, -m405" Generate code for PowerPC 403/405. -.IP "\fB\-m440\fR" 4 +.IP \fB\-m440\fR 4 .IX Item "-m440" Generate code for PowerPC 440. BookE and some 405 instructions. -.IP "\fB\-m464\fR" 4 +.IP \fB\-m464\fR 4 .IX Item "-m464" Generate code for PowerPC 464. -.IP "\fB\-m476\fR" 4 +.IP \fB\-m476\fR 4 .IX Item "-m476" Generate code for PowerPC 476. .IP "\fB\-m7400, \-m7410, \-m7450, \-m7455\fR" 4 @@ -2578,56 +2560,56 @@ Generate code for PowerPC 821/850/860. Generate code for PowerPC 620/625/630. .IP "\fB\-me200z2, \-me200z4\fR" 4 .IX Item "-me200z2, -me200z4" -Generate code for e200 variants, e200z2 with \s-1LSP,\s0 e200z4 with \s-1SPE.\s0 -.IP "\fB\-me300\fR" 4 +Generate code for e200 variants, e200z2 with LSP, e200z4 with SPE. +.IP \fB\-me300\fR 4 .IX Item "-me300" Generate code for PowerPC e300 family. .IP "\fB\-me500, \-me500x2\fR" 4 .IX Item "-me500, -me500x2" Generate code for Motorola e500 core complex. -.IP "\fB\-me500mc\fR" 4 +.IP \fB\-me500mc\fR 4 .IX Item "-me500mc" Generate code for Freescale e500mc core complex. -.IP "\fB\-me500mc64\fR" 4 +.IP \fB\-me500mc64\fR 4 .IX Item "-me500mc64" Generate code for Freescale e500mc64 core complex. -.IP "\fB\-me5500\fR" 4 +.IP \fB\-me5500\fR 4 .IX Item "-me5500" Generate code for Freescale e5500 core complex. -.IP "\fB\-me6500\fR" 4 +.IP \fB\-me6500\fR 4 .IX Item "-me6500" Generate code for Freescale e6500 core complex. -.IP "\fB\-mlsp\fR" 4 +.IP \fB\-mlsp\fR 4 .IX Item "-mlsp" -Enable \s-1LSP\s0 instructions. (Disables \s-1SPE\s0 and \s-1SPE2.\s0) -.IP "\fB\-mspe\fR" 4 +Enable LSP instructions. (Disables SPE and SPE2.) +.IP \fB\-mspe\fR 4 .IX Item "-mspe" -Generate code for Motorola \s-1SPE\s0 instructions. (Disables \s-1LSP.\s0) -.IP "\fB\-mspe2\fR" 4 +Generate code for Motorola SPE instructions. (Disables LSP.) +.IP \fB\-mspe2\fR 4 .IX Item "-mspe2" -Generate code for Freescale \s-1SPE2\s0 instructions. (Disables \s-1LSP.\s0) -.IP "\fB\-mtitan\fR" 4 +Generate code for Freescale SPE2 instructions. (Disables LSP.) +.IP \fB\-mtitan\fR 4 .IX Item "-mtitan" Generate code for AppliedMicro Titan core complex. -.IP "\fB\-mppc64bridge\fR" 4 +.IP \fB\-mppc64bridge\fR 4 .IX Item "-mppc64bridge" Generate code for PowerPC 64, including bridge insns. -.IP "\fB\-mbooke\fR" 4 +.IP \fB\-mbooke\fR 4 .IX Item "-mbooke" Generate code for 32\-bit BookE. -.IP "\fB\-ma2\fR" 4 +.IP \fB\-ma2\fR 4 .IX Item "-ma2" Generate code for A2 architecture. -.IP "\fB\-maltivec\fR" 4 +.IP \fB\-maltivec\fR 4 .IX Item "-maltivec" Generate code for processors with AltiVec instructions. -.IP "\fB\-mvle\fR" 4 +.IP \fB\-mvle\fR 4 .IX Item "-mvle" -Generate code for Freescale PowerPC \s-1VLE\s0 instructions. -.IP "\fB\-mvsx\fR" 4 +Generate code for Freescale PowerPC VLE instructions. +.IP \fB\-mvsx\fR 4 .IX Item "-mvsx" -Generate code for processors with Vector-Scalar (\s-1VSX\s0) instructions. -.IP "\fB\-mhtm\fR" 4 +Generate code for processors with Vector-Scalar (VSX) instructions. +.IP \fB\-mhtm\fR 4 .IX Item "-mhtm" Generate code for processors with Hardware Transactional Memory instructions. .IP "\fB\-mpower4, \-mpwr4\fR" 4 @@ -2651,121 +2633,120 @@ Generate code for Power9 architecture. .IP "\fB\-mpower10, \-mpwr10\fR" 4 .IX Item "-mpower10, -mpwr10" Generate code for Power10 architecture. -.IP "\fB\-mfuture\fR" 4 +.IP \fB\-mfuture\fR 4 .IX Item "-mfuture" Generate code for 'future' architecture. -.IP "\fB\-mcell\fR" 4 +.IP \fB\-mcell\fR 4 .IX Item "-mcell" .PD 0 -.IP "\fB\-mcell\fR" 4 +.IP \fB\-mcell\fR 4 .IX Item "-mcell" .PD Generate code for Cell Broadband Engine architecture. -.IP "\fB\-mcom\fR" 4 +.IP \fB\-mcom\fR 4 .IX Item "-mcom" Generate code Power/PowerPC common instructions. -.IP "\fB\-many\fR" 4 +.IP \fB\-many\fR 4 .IX Item "-many" -Generate code for any architecture (\s-1PWR/PWRX/PPC\s0). -.IP "\fB\-mregnames\fR" 4 +Generate code for any architecture (PWR/PWRX/PPC). +.IP \fB\-mregnames\fR 4 .IX Item "-mregnames" Allow symbolic names for registers. -.IP "\fB\-mno\-regnames\fR" 4 +.IP \fB\-mno\-regnames\fR 4 .IX Item "-mno-regnames" Do not allow symbolic names for registers. -.IP "\fB\-mrelocatable\fR" 4 +.IP \fB\-mrelocatable\fR 4 .IX Item "-mrelocatable" -Support for \s-1GCC\s0's \-mrelocatable option. -.IP "\fB\-mrelocatable\-lib\fR" 4 +Support for GCC's \-mrelocatable option. +.IP \fB\-mrelocatable\-lib\fR 4 .IX Item "-mrelocatable-lib" -Support for \s-1GCC\s0's \-mrelocatable\-lib option. -.IP "\fB\-memb\fR" 4 +Support for GCC's \-mrelocatable\-lib option. +.IP \fB\-memb\fR 4 .IX Item "-memb" -Set \s-1PPC_EMB\s0 bit in \s-1ELF\s0 flags. +Set PPC_EMB bit in ELF flags. .IP "\fB\-mlittle, \-mlittle\-endian, \-le\fR" 4 .IX Item "-mlittle, -mlittle-endian, -le" Generate code for a little endian machine. .IP "\fB\-mbig, \-mbig\-endian, \-be\fR" 4 .IX Item "-mbig, -mbig-endian, -be" Generate code for a big endian machine. -.IP "\fB\-msolaris\fR" 4 +.IP \fB\-msolaris\fR 4 .IX Item "-msolaris" Generate code for Solaris. -.IP "\fB\-mno\-solaris\fR" 4 +.IP \fB\-mno\-solaris\fR 4 .IX Item "-mno-solaris" Do not generate code for Solaris. -.IP "\fB\-nops=\fR\fIcount\fR" 4 +.IP \fB\-nops=\fR\fIcount\fR 4 .IX Item "-nops=count" If an alignment directive inserts more than \fIcount\fR nops, put a branch at the beginning to skip execution of the nops. .PP The following options are available when as is configured for a RISC-V processor. -.IP "\fB\-fpic\fR" 4 +.IP \fB\-fpic\fR 4 .IX Item "-fpic" .PD 0 -.IP "\fB\-fPIC\fR" 4 +.IP \fB\-fPIC\fR 4 .IX Item "-fPIC" .PD Generate position-independent code -.IP "\fB\-fno\-pic\fR" 4 +.IP \fB\-fno\-pic\fR 4 .IX Item "-fno-pic" Don't generate position-independent code (default) -.IP "\fB\-march=ISA\fR" 4 +.IP \fB\-march=ISA\fR 4 .IX Item "-march=ISA" -Select the base isa, as specified by \s-1ISA.\s0 For example \-march=rv32ima. +Select the base isa, as specified by ISA. For example \-march=rv32ima. If this option and the architecture attributes aren't set, then assembler will check the default configure setting \-\-with\-arch=ISA. -.IP "\fB\-misa\-spec=ISAspec\fR" 4 +.IP \fB\-misa\-spec=ISAspec\fR 4 .IX Item "-misa-spec=ISAspec" -Select the default isa spec version. If the version of \s-1ISA\s0 isn't set +Select the default isa spec version. If the version of ISA isn't set by \-march, then assembler helps to set the version according to the default chosen spec. If this option isn't set, then assembler will check the default configure setting \-\-with\-isa\-spec=ISAspec. -.IP "\fB\-mpriv\-spec=PRIVspec\fR" 4 +.IP \fB\-mpriv\-spec=PRIVspec\fR 4 .IX Item "-mpriv-spec=PRIVspec" -Select the privileged spec version. We can decide whether the \s-1CSR\s0 is valid or +Select the privileged spec version. We can decide whether the CSR is valid or not according to the chosen spec. If this option and the privilege attributes aren't set, then assembler will check the default configure setting \&\-\-with\-priv\-spec=PRIVspec. -.IP "\fB\-mabi=ABI\fR" 4 +.IP \fB\-mabi=ABI\fR 4 .IX Item "-mabi=ABI" -Selects the \s-1ABI,\s0 which is either \*(L"ilp32\*(R" or \*(L"lp64\*(R", optionally followed -by \*(L"f\*(R", \*(L"d\*(R", or \*(L"q\*(R" to indicate single-precision, double-precision, or -quad-precision floating-point calling convention, or none to indicate -the soft-float calling convention. Also, \*(L"ilp32\*(R" can optionally be followed -by \*(L"e\*(R" to indicate the \s-1RVE ABI,\s0 which is always soft-float. -.IP "\fB\-mrelax\fR" 4 +Selects the ABI, which is either "ilp32" or "lp64", optionally followed +by "f", "d", or "q" to indicate single-precision, double-precision, or +quad-precision floating-point calling convention, or none or "e" to indicate +the soft-float calling convention ("e" indicates a soft-float RVE ABI). +.IP \fB\-mrelax\fR 4 .IX Item "-mrelax" Take advantage of linker relaxations to reduce the number of instructions required to materialize symbol addresses. (default) -.IP "\fB\-mno\-relax\fR" 4 +.IP \fB\-mno\-relax\fR 4 .IX Item "-mno-relax" Don't do linker relaxations. -.IP "\fB\-march\-attr\fR" 4 +.IP \fB\-march\-attr\fR 4 .IX Item "-march-attr" Generate the default contents for the riscv elf attribute section if the \&.attribute directives are not set. This section is used to record the information that a linker or runtime loader needs to check compatibility. -This information includes \s-1ISA\s0 string, stack alignment requirement, unaligned +This information includes ISA string, stack alignment requirement, unaligned memory accesses, and the major, minor and revision version of privileged specification. -.IP "\fB\-mno\-arch\-attr\fR" 4 +.IP \fB\-mno\-arch\-attr\fR 4 .IX Item "-mno-arch-attr" Don't generate the default riscv elf attribute section if the .attribute directives are not set. -.IP "\fB\-mcsr\-check\fR" 4 +.IP \fB\-mcsr\-check\fR 4 .IX Item "-mcsr-check" -Enable the \s-1CSR\s0 checking for the ISA-dependent \s-1CRS\s0 and the read-only \s-1CSR.\s0 -The ISA-dependent \s-1CSR\s0 are only valid when the specific \s-1ISA\s0 is set. The -read-only \s-1CSR\s0 can not be written by the \s-1CSR\s0 instructions. -.IP "\fB\-mno\-csr\-check\fR" 4 +Enable the CSR checking for the ISA-dependent CRS and the read-only CSR. +The ISA-dependent CSR are only valid when the specific ISA is set. The +read-only CSR can not be written by the CSR instructions. +.IP \fB\-mno\-csr\-check\fR 4 .IX Item "-mno-csr-check" -Don't do \s-1CSR\s0 checking. -.IP "\fB\-mlittle\-endian\fR" 4 +Don't do CSR checking. +.IP \fB\-mlittle\-endian\fR 4 .IX Item "-mlittle-endian" Generate code for a little endian machine. -.IP "\fB\-mbig\-endian\fR" 4 +.IP \fB\-mbig\-endian\fR 4 .IX Item "-mbig-endian" Generate code for a big endian machine. .PP @@ -2773,22 +2754,22 @@ See the info pages for documentation of the RX-specific options. .PP The following options are available when as is configured for the s390 processor family. -.IP "\fB\-m31\fR" 4 +.IP \fB\-m31\fR 4 .IX Item "-m31" .PD 0 -.IP "\fB\-m64\fR" 4 +.IP \fB\-m64\fR 4 .IX Item "-m64" .PD Select the word size, either 31/32 bits or 64 bits. -.IP "\fB\-mesa\fR" 4 +.IP \fB\-mesa\fR 4 .IX Item "-mesa" .PD 0 -.IP "\fB\-mzarch\fR" 4 +.IP \fB\-mzarch\fR 4 .IX Item "-mzarch" .PD Select the architecture mode, either the Enterprise System Architecture (esa) or the z/Architecture mode (zarch). -.IP "\fB\-march=\fR\fIprocessor\fR" 4 +.IP \fB\-march=\fR\fIprocessor\fR 4 .IX Item "-march=processor" Specify which s390 processor variant is the target, \fBg5\fR (or \&\fBarch3\fR), \fBg6\fR, \fBz900\fR (or \fBarch5\fR), \fBz990\fR (or @@ -2796,60 +2777,60 @@ Specify which s390 processor variant is the target, \fBg5\fR (or \&\fBarch8\fR), \fBz196\fR (or \fBarch9\fR), \fBzEC12\fR (or \fBarch10\fR), \&\fBz13\fR (or \fBarch11\fR), \fBz14\fR (or \fBarch12\fR), \fBz15\fR (or \fBarch13\fR), or \fBz16\fR (or \fBarch14\fR). -.IP "\fB\-mregnames\fR" 4 +.IP \fB\-mregnames\fR 4 .IX Item "-mregnames" .PD 0 -.IP "\fB\-mno\-regnames\fR" 4 +.IP \fB\-mno\-regnames\fR 4 .IX Item "-mno-regnames" .PD Allow or disallow symbolic names for registers. -.IP "\fB\-mwarn\-areg\-zero\fR" 4 +.IP \fB\-mwarn\-areg\-zero\fR 4 .IX Item "-mwarn-areg-zero" Warn whenever the operand for a base or index register has been specified but evaluates to zero. .PP The following options are available when as is configured for a -\&\s-1TMS320C6000\s0 processor. -.IP "\fB\-march=\fR\fIarch\fR" 4 +TMS320C6000 processor. +.IP \fB\-march=\fR\fIarch\fR 4 .IX Item "-march=arch" Enable (only) instructions from architecture \fIarch\fR. By default, all instructions are permitted. .Sp The following values of \fIarch\fR are accepted: \f(CW\*(C`c62x\*(C'\fR, \&\f(CW\*(C`c64x\*(C'\fR, \f(CW\*(C`c64x+\*(C'\fR, \f(CW\*(C`c67x\*(C'\fR, \f(CW\*(C`c67x+\*(C'\fR, \f(CW\*(C`c674x\*(C'\fR. -.IP "\fB\-mdsbt\fR" 4 +.IP \fB\-mdsbt\fR 4 .IX Item "-mdsbt" .PD 0 -.IP "\fB\-mno\-dsbt\fR" 4 +.IP \fB\-mno\-dsbt\fR 4 .IX Item "-mno-dsbt" .PD The \fB\-mdsbt\fR option causes the assembler to generate the \&\f(CW\*(C`Tag_ABI_DSBT\*(C'\fR attribute with a value of 1, indicating that the -code is using \s-1DSBT\s0 addressing. The \fB\-mno\-dsbt\fR option, the +code is using DSBT addressing. The \fB\-mno\-dsbt\fR option, the default, causes the tag to have a value of 0, indicating that the code -does not use \s-1DSBT\s0 addressing. The linker will emit a warning if -objects of different type (\s-1DSBT\s0 and non-DSBT) are linked together. -.IP "\fB\-mpid=no\fR" 4 +does not use DSBT addressing. The linker will emit a warning if +objects of different type (DSBT and non-DSBT) are linked together. +.IP \fB\-mpid=no\fR 4 .IX Item "-mpid=no" .PD 0 -.IP "\fB\-mpid=near\fR" 4 +.IP \fB\-mpid=near\fR 4 .IX Item "-mpid=near" -.IP "\fB\-mpid=far\fR" 4 +.IP \fB\-mpid=far\fR 4 .IX Item "-mpid=far" .PD The \fB\-mpid=\fR option causes the assembler to generate the \&\f(CW\*(C`Tag_ABI_PID\*(C'\fR attribute with a value indicating the form of data addressing used by the code. \fB\-mpid=no\fR, the default, indicates position-dependent data addressing, \fB\-mpid=near\fR -indicates position-independent addressing with \s-1GOT\s0 accesses using near -\&\s-1DP\s0 addressing, and \fB\-mpid=far\fR indicates position-independent -addressing with \s-1GOT\s0 accesses using far \s-1DP\s0 addressing. The linker will +indicates position-independent addressing with GOT accesses using near +DP addressing, and \fB\-mpid=far\fR indicates position-independent +addressing with GOT accesses using far DP addressing. The linker will emit a warning if objects built with different settings of this option are linked together. -.IP "\fB\-mpic\fR" 4 +.IP \fB\-mpic\fR 4 .IX Item "-mpic" .PD 0 -.IP "\fB\-mno\-pic\fR" 4 +.IP \fB\-mno\-pic\fR 4 .IX Item "-mno-pic" .PD The \fB\-mpic\fR option causes the assembler to generate the @@ -2859,10 +2840,10 @@ code is using position-independent code addressing, The 0, indicating position-dependent code addressing. The linker will emit a warning if objects of different type (position-dependent and position-independent) are linked together. -.IP "\fB\-mbig\-endian\fR" 4 +.IP \fB\-mbig\-endian\fR 4 .IX Item "-mbig-endian" .PD 0 -.IP "\fB\-mlittle\-endian\fR" 4 +.IP \fB\-mlittle\-endian\fR 4 .IX Item "-mlittle-endian" .PD Generate code for the specified endianness. The default is @@ -2879,7 +2860,7 @@ Select the endianness, either big-endian (\-EB) or little-endian (\-EL). .PP The following option is available when as is configured for a Visium processor. -.IP "\fB\-mtune=\fR\fIarch\fR" 4 +.IP \fB\-mtune=\fR\fIarch\fR 4 .IX Item "-mtune=arch" This option specifies the target architecture. If an attempt is made to assemble an instruction that will not execute on the target architecture, @@ -2898,7 +2879,7 @@ Xtensa processor. Control the treatment of literal pools. The default is \&\fB\-\-no\-text\-section\-literals\fR, which places literals in separate sections in the output file. This allows the literal pool to be -placed in a data \s-1RAM/ROM.\s0 With \fB\-\-text\-section\-literals\fR, the +placed in a data RAM/ROM. With \fB\-\-text\-section\-literals\fR, the literals are interspersed in the text section in order to keep them as close as possible to their references. This may be necessary for large assembly files, where the literals would otherwise be out of range of the @@ -2913,7 +2894,7 @@ Control the treatment of literal pools. The default is \&\fB\-\-no\-auto\-litpools\fR, which in the absence of \&\fB\-\-text\-section\-literals\fR places literals in separate sections in the output file. This allows the literal pool to be placed in a data -\&\s-1RAM/ROM.\s0 With \fB\-\-auto\-litpools\fR, the literals are interspersed +RAM/ROM. With \fB\-\-auto\-litpools\fR, the literals are interspersed in the text section in order to keep them as close as possible to their references, explicit \f(CW\*(C`.literal_position\*(C'\fR directives are not required. This may be necessary for very large functions, where single @@ -2965,10 +2946,10 @@ does not affect code size or performance. The default is \&\fB\-\-trampolines\fR. .IP "\fB\-\-abi\-windowed | \-\-abi\-call0\fR" 4 .IX Item "--abi-windowed | --abi-call0" -Choose \s-1ABI\s0 tag written to the \f(CW\*(C`.xtensa.info\*(C'\fR section. \s-1ABI\s0 tag -indicates \s-1ABI\s0 of the assembly code. A warning is issued by the linker -on an attempt to link object files with inconsistent \s-1ABI\s0 tags. -Default \s-1ABI\s0 is chosen by the Xtensa core configuration. +Choose ABI tag written to the \f(CW\*(C`.xtensa.info\*(C'\fR section. ABI tag +indicates ABI of the assembly code. A warning is issued by the linker +on an attempt to link object files with inconsistent ABI tags. +Default ABI is chosen by the Xtensa core configuration. .PP The following options are available when as is configured for an Z80 processor. @@ -2976,7 +2957,7 @@ Z80 processor. \&\f(CW@chapter\fR Z80 Dependent Features .SS "Command-line Options" .IX Subsection "Command-line Options" -.IP "\fB\-march=\fR\fI\s-1CPU\s0\fR\fB[\-\fR\fI\s-1EXT\s0\fR\fB...][+\fR\fI\s-1EXT\s0\fR\fB...]\fR" 4 +.IP \fB\-march=\fR\fICPU\fR\fB[\-\fR\fIEXT\fR\fB...][+\fR\fIEXT\fR\fB...]\fR 4 .IX Item "-march=CPU[-EXT...][+EXT...]" This option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which @@ -2989,50 +2970,50 @@ are recognized: \&\f(CW\*(C`z80n\*(C'\fR, \&\f(CW\*(C`r800\*(C'\fR. In addition to the basic instruction set, the assembler can be told to -accept some extention mnemonics. For example, -\&\f(CW\*(C`\-march=z180+sli+infc\*(C'\fR extends \fIz180\fR with \fI\s-1SLI\s0\fR instructions and -\&\fI\s-1IN F,\s0(C)\fR. The following extentions are currently supported: +accept some extension mnemonics. For example, +\&\f(CW\*(C`\-march=z180+sli+infc\*(C'\fR extends \fIz180\fR with \fISLI\fR instructions and +\&\fIIN F,(C)\fR. The following extensions are currently supported: \&\f(CW\*(C`full\*(C'\fR (all known instructions), -\&\f(CW\*(C`adl\*(C'\fR (\s-1ADL CPU\s0 mode by default, eZ80 only), -\&\f(CW\*(C`sli\*(C'\fR (instruction known as \fI\s-1SLI\s0\fR, \fI\s-1SLL\s0\fR or \fI\s-1SL1\s0\fR), -\&\f(CW\*(C`xyhl\*(C'\fR (instructions with halves of index registers: \fI\s-1IXL\s0\fR, \fI\s-1IXH\s0\fR, -\&\fI\s-1IYL\s0\fR, \fI\s-1IYH\s0\fR), +\&\f(CW\*(C`adl\*(C'\fR (ADL CPU mode by default, eZ80 only), +\&\f(CW\*(C`sli\*(C'\fR (instruction known as \fISLI\fR, \fISLL\fR or \fISL1\fR), +\&\f(CW\*(C`xyhl\*(C'\fR (instructions with halves of index registers: \fIIXL\fR, \fIIXH\fR, +\&\fIIYL\fR, \fIIYH\fR), \&\f(CW\*(C`xdcb\*(C'\fR (instructions like \fIRotOp (II+d),R\fR and \fIBitOp n,(II+d),R\fR), -\&\f(CW\*(C`infc\*(C'\fR (instruction \fI\s-1IN F,\s0(C)\fR or \fI\s-1IN\s0 (C)\fR), -\&\f(CW\*(C`outc0\*(C'\fR (instruction \fI\s-1OUT\s0 (C),0\fR). -Note that rather than extending a basic instruction set, the extention +\&\f(CW\*(C`infc\*(C'\fR (instruction \fIIN F,(C)\fR or \fIIN (C)\fR), +\&\f(CW\*(C`outc0\*(C'\fR (instruction \fIOUT (C),0\fR). +Note that rather than extending a basic instruction set, the extension mnemonics starting with \f(CW\*(C`\-\*(C'\fR revoke the respective functionality: -\&\f(CW\*(C`\-march=z80\-full+xyhl\*(C'\fR first removes all default extentions and adds +\&\f(CW\*(C`\-march=z80\-full+xyhl\*(C'\fR first removes all default extensions and adds support for index registers halves only. .Sp If this option is not specified then \f(CW\*(C`\-march=z80+xyhl+infc\*(C'\fR is assumed. -.IP "\fB\-local\-prefix=\fR\fIprefix\fR" 4 +.IP \fB\-local\-prefix=\fR\fIprefix\fR 4 .IX Item "-local-prefix=prefix" Mark all labels with specified prefix as local. But such label can be marked global explicitly in the code. This option do not change default local label prefix \f(CW\*(C`.L\*(C'\fR, it is just adds new one. -.IP "\fB\-colonless\fR" 4 +.IP \fB\-colonless\fR 4 .IX Item "-colonless" Accept colonless labels. All symbols at line begin are treated as labels. -.IP "\fB\-sdcc\fR" 4 +.IP \fB\-sdcc\fR 4 .IX Item "-sdcc" -Accept assembler code produced by \s-1SDCC.\s0 -.IP "\fB\-fp\-s=\fR\fI\s-1FORMAT\s0\fR" 4 +Accept assembler code produced by SDCC. +.IP \fB\-fp\-s=\fR\fIFORMAT\fR 4 .IX Item "-fp-s=FORMAT" Single precision floating point numbers format. Default: ieee754 (32 bit). -.IP "\fB\-fp\-d=\fR\fI\s-1FORMAT\s0\fR" 4 +.IP \fB\-fp\-d=\fR\fIFORMAT\fR 4 .IX Item "-fp-d=FORMAT" Double precision floating point numbers format. Default: ieee754 (64 bit). .SH "SEE ALSO" .IX Header "SEE ALSO" \&\fBgcc\fR\|(1), \fBld\fR\|(1), and the Info entries for \fIbinutils\fR and \fIld\fR. -.SH "COPYRIGHT" +.SH COPYRIGHT .IX Header "COPYRIGHT" -Copyright (c) 1991\-2023 Free Software Foundation, Inc. +Copyright (c) 1991\-2024 Free Software Foundation, Inc. .PP Permission is granted to copy, distribute and/or modify this document -under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 +under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts. A copy of the license is included in the -section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R". +section entitled "GNU Free Documentation License". |