Merging upstream version 1.74.1+dfsg1.

Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>

6 files changed, 0 insertions, 338 deletions

diff --git a/library/stdarch/crates/core_arch/src/arm/armclang.rs b/library/stdarch/crates/core_arch/src/arm/armclang.rs
deleted file mode 100644
index e44ee2f4a..000000000
--- a/library/stdarch/crates/core_arch/src/arm/armclang.rs
+++ /dev/null
@@ -1,35 +0,0 @@
-//! ARM compiler specific intrinsics
-//!
-//! # References
-//!
-//! - [ARM Compiler v 6.10 - armclang Reference Guide][arm_comp_ref]
-//!
-//! [arm_comp_ref]: https://developer.arm.com/docs/100067/0610
-
-#[cfg(test)]
-use stdarch_test::assert_instr;
-
-/// Inserts a breakpoint instruction.
-///
-/// `VAL` is a compile-time constant integer in range `[0, 255]`.
-///
-/// The breakpoint instruction inserted is `BKPT` on A32/T32.
-///
-/// # Note
-///
-/// [ARM's documentation][arm_docs] defines that `__breakpoint` accepts the
-/// following values for `VAL`:
-///
-/// - `0...65535` when compiling as A32,
-/// - `0...255` when compiling as T32.
-///
-/// The current implementation only accepts values in range `[0, 255]`.
-///
-/// [arm_docs]: https://developer.arm.com/docs/100067/latest/compiler-specific-intrinsics/__breakpoint-intrinsic
-#[cfg_attr(test, assert_instr(bkpt, VAL = 0))]
-#[inline(always)]
-#[rustc_legacy_const_generics(0)]
-pub unsafe fn __breakpoint<const VAL: i32>() {
-    static_assert_uimm_bits!(VAL, 8);
-    crate::arch::asm!("bkpt #{}", const VAL);
-}
diff --git a/library/stdarch/crates/core_arch/src/arm/ex.rs b/library/stdarch/crates/core_arch/src/arm/ex.rs
deleted file mode 100644
index 75f378642..000000000
--- a/library/stdarch/crates/core_arch/src/arm/ex.rs
+++ /dev/null
@@ -1,125 +0,0 @@
-// Reference: Section 5.4.4 "LDREX / STREX" of ACLE
-
-/// Removes the exclusive lock created by LDREX
-// Supported: v6, v6K, v7-M, v7-A, v7-R
-// Not supported: v5, v6-M
-// NOTE: there's no dedicated CLREX instruction in v6 (<v6k); to clear the exclusive monitor users
-// have to do a dummy STREX operation
-#[cfg(any(
-    all(target_feature = "v6k", not(target_feature = "mclass")), // excludes v6-M
-    all(target_feature = "v7", target_feature = "mclass"), // v7-M
-    doc
-))]
-pub unsafe fn __clrex() {
-    extern "unadjusted" {
-        #[link_name = "llvm.arm.clrex"]
-        fn clrex();
-    }
-
-    clrex()
-}
-
-/// Executes an exclusive LDR instruction for 8 bit value.
-// Supported: v6K, v7-M, v7-A, v7-R
-// Not supported: v5, v6, v6-M
-#[cfg(any(
-    target_feature = "v6k", // includes v7-M but excludes v6-M
-    doc
-))]
-pub unsafe fn __ldrexb(p: *const u8) -> u8 {
-    extern "unadjusted" {
-        #[link_name = "llvm.arm.ldrex.p0i8"]
-        fn ldrex8(p: *const u8) -> u32;
-    }
-
-    ldrex8(p) as u8
-}
-
-/// Executes an exclusive LDR instruction for 16 bit value.
-// Supported: v6K, v7-M, v7-A, v7-R, v8
-// Not supported: v5, v6, v6-M
-#[cfg(any(
-    target_feature = "v6k", // includes v7-M but excludes v6-M
-    doc
-))]
-pub unsafe fn __ldrexh(p: *const u16) -> u16 {
-    extern "unadjusted" {
-        #[link_name = "llvm.arm.ldrex.p0i16"]
-        fn ldrex16(p: *const u16) -> u32;
-    }
-
-    ldrex16(p) as u16
-}
-
-/// Executes an exclusive LDR instruction for 32 bit value.
-// Supported: v6, v7-M, v6K, v7-A, v7-R, v8
-// Not supported: v5, v6-M
-#[cfg(any(
-    all(target_feature = "v6", not(target_feature = "mclass")), // excludes v6-M
-    all(target_feature = "v7", target_feature = "mclass"), // v7-M
-    doc
-))]
-pub unsafe fn __ldrex(p: *const u32) -> u32 {
-    extern "unadjusted" {
-        #[link_name = "llvm.arm.ldrex.p0i32"]
-        fn ldrex32(p: *const u32) -> u32;
-    }
-
-    ldrex32(p)
-}
-
-/// Executes an exclusive STR instruction for 8 bit values
-///
-/// Returns `0` if the operation succeeded, or `1` if it failed
-// supported: v6K, v7-M, v7-A, v7-R
-// Not supported: v5, v6, v6-M
-#[cfg(any(
-    target_feature = "v6k", // includes v7-M but excludes v6-M
-    doc
-))]
-pub unsafe fn __strexb(value: u32, addr: *mut u8) -> u32 {
-    extern "unadjusted" {
-        #[link_name = "llvm.arm.strex.p0i8"]
-        fn strex8(value: u32, addr: *mut u8) -> u32;
-    }
-
-    strex8(value, addr)
-}
-
-/// Executes an exclusive STR instruction for 16 bit values
-///
-/// Returns `0` if the operation succeeded, or `1` if it failed
-// Supported: v6K, v7-M, v7-A, v7-R, v8
-// Not supported: v5, v6, v6-M
-#[cfg(target_feature = "aarch64")]
-#[cfg(any(
-    target_feature = "v6k", // includes v7-M but excludes v6-M
-    doc
-))]
-pub unsafe fn __strexh(value: u16, addr: *mut u16) -> u32 {
-    extern "unadjusted" {
-        #[link_name = "llvm.arm.strex.p0i16"]
-        fn strex16(value: u32, addr: *mut u16) -> u32;
-    }
-
-    strex16(value as u32, addr)
-}
-
-/// Executes an exclusive STR instruction for 32 bit values
-///
-/// Returns `0` if the operation succeeded, or `1` if it failed
-// Supported: v6, v7-M, v6K, v7-A, v7-R, v8
-// Not supported: v5, v6-M
-#[cfg(any(
-    all(target_feature = "v6", not(target_feature = "mclass")), // excludes v6-M
-    all(target_feature = "v7", target_feature = "mclass"), // v7-M
-    doc
-))]
-pub unsafe fn __strex(value: u32, addr: *mut u32) -> u32 {
-    extern "unadjusted" {
-        #[link_name = "llvm.arm.strex.p0i32"]
-        fn strex32(value: u32, addr: *mut u32) -> u32;
-    }
-
-    strex32(value, addr)
-}
diff --git a/library/stdarch/crates/core_arch/src/arm/mod.rs b/library/stdarch/crates/core_arch/src/arm/mod.rs
index ec91e5de5..9cc75a3cc 100644
--- a/library/stdarch/crates/core_arch/src/arm/mod.rs
+++ b/library/stdarch/crates/core_arch/src/arm/mod.rs
@@ -6,12 +6,6 @@
 //! [arm_ref]: http://infocenter.arm.com/help/topic/com.arm.doc.ihi0073a/IHI0073A_arm_neon_intrinsics_ref.pdf
 //! [arm_dat]: https://developer.arm.com/technologies/neon/intrinsics
 
-mod armclang;
-pub use self::armclang::*;
-
-mod v6;
-pub use self::v6::*;
-
 // Supported arches: 6, 7-M. See Section 10.1 of ACLE (e.g. SSAT)
 #[cfg(any(target_feature = "v6", doc))]
 mod sat;
@@ -62,14 +56,6 @@ mod simd32;
 ))]
 pub use self::simd32::*;
 
-#[cfg(any(target_feature = "v7", doc))]
-mod v7;
-#[cfg(any(target_feature = "v7", doc))]
-pub use self::v7::*;
-
-mod ex;
-pub use self::ex::*;
-
 pub use crate::core_arch::arm_shared::*;
 
 #[cfg(test)]
diff --git a/library/stdarch/crates/core_arch/src/arm/neon.rs b/library/stdarch/crates/core_arch/src/arm/neon.rs
index e1de48538..75d3f19e8 100644
--- a/library/stdarch/crates/core_arch/src/arm/neon.rs
+++ b/library/stdarch/crates/core_arch/src/arm/neon.rs
@@ -1,16 +1,9 @@
 use crate::core_arch::arm_shared::neon::*;
-use crate::core_arch::simd::{f32x4, i32x4, u32x4};
-use crate::core_arch::simd_llvm::*;
 use crate::mem::{align_of, transmute};
 
 #[cfg(test)]
 use stdarch_test::assert_instr;
 
-#[allow(non_camel_case_types)]
-pub(crate) type p8 = u8;
-#[allow(non_camel_case_types)]
-pub(crate) type p16 = u16;
-
 #[allow(improper_ctypes)]
 extern "unadjusted" {
     #[link_name = "llvm.arm.neon.vbsl.v8i8"]
@@ -794,27 +787,6 @@ pub unsafe fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t
     ))
 }
 
-// These float-to-int implementations have undefined behaviour when `a` overflows
-// the destination type. Clang has the same problem: https://llvm.org/PR47510
-
-/// Floating-point Convert to Signed fixed-point, rounding toward Zero (vector)
-#[inline]
-#[target_feature(enable = "neon")]
-#[target_feature(enable = "v7")]
-#[cfg_attr(test, assert_instr("vcvt.s32.f32"))]
-pub unsafe fn vcvtq_s32_f32(a: float32x4_t) -> int32x4_t {
-    transmute(simd_cast::<_, i32x4>(transmute::<_, f32x4>(a)))
-}
-
-/// Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector)
-#[inline]
-#[target_feature(enable = "neon")]
-#[target_feature(enable = "v7")]
-#[cfg_attr(test, assert_instr("vcvt.u32.f32"))]
-pub unsafe fn vcvtq_u32_f32(a: float32x4_t) -> uint32x4_t {
-    transmute(simd_cast::<_, u32x4>(transmute::<_, f32x4>(a)))
-}
-
 /// Shift Left and Insert (immediate)
 #[inline]
 #[target_feature(enable = "neon,v7")]
diff --git a/library/stdarch/crates/core_arch/src/arm/v6.rs b/library/stdarch/crates/core_arch/src/arm/v6.rs
deleted file mode 100644
index 5df30cd62..000000000
--- a/library/stdarch/crates/core_arch/src/arm/v6.rs
+++ /dev/null
@@ -1,49 +0,0 @@
-//! ARMv6 intrinsics.
-//!
-//! The reference is [ARMv6-M Architecture Reference Manual][armv6m].
-//!
-//! [armv6m]:
-//! http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0419c/index.
-//! html
-
-#[cfg(test)]
-use stdarch_test::assert_instr;
-
-/// Reverse the order of the bytes.
-#[inline]
-#[cfg_attr(test, assert_instr(rev))]
-pub unsafe fn _rev_u16(x: u16) -> u16 {
-    x.swap_bytes() as u16
-}
-
-/// Reverse the order of the bytes.
-#[inline]
-#[cfg_attr(test, assert_instr(rev))]
-pub unsafe fn _rev_u32(x: u32) -> u32 {
-    x.swap_bytes() as u32
-}
-
-#[cfg(test)]
-mod tests {
-    use crate::core_arch::arm::v6;
-
-    #[test]
-    fn _rev_u16() {
-        unsafe {
-            assert_eq!(
-                v6::_rev_u16(0b0000_0000_1111_1111_u16),
-                0b1111_1111_0000_0000_u16
-            );
-        }
-    }
-
-    #[test]
-    fn _rev_u32() {
-        unsafe {
-            assert_eq!(
-                v6::_rev_u32(0b0000_0000_1111_1111_0000_0000_1111_1111_u32),
-                0b1111_1111_0000_0000_1111_1111_0000_0000_u32
-            );
-        }
-    }
-}
diff --git a/library/stdarch/crates/core_arch/src/arm/v7.rs b/library/stdarch/crates/core_arch/src/arm/v7.rs
deleted file mode 100644
index 59beaf722..000000000
--- a/library/stdarch/crates/core_arch/src/arm/v7.rs
+++ /dev/null
@@ -1,87 +0,0 @@
-//! ARMv7 intrinsics.
-//!
-//! The reference is [ARMv7-M Architecture Reference Manual (Issue
-//! E.b)][armv7m].
-//!
-//! [armv7m]:
-//! http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0403e.
-//! b/index.html
-
-pub use super::v6::*;
-
-#[cfg(test)]
-use stdarch_test::assert_instr;
-
-/// Count Leading Zeros.
-#[inline]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(clz))]
-// FIXME: https://github.com/rust-lang/stdarch/issues/382
-// #[cfg_attr(all(test, target_arch = "arm"), assert_instr(clz))]
-pub unsafe fn _clz_u8(x: u8) -> u8 {
-    x.leading_zeros() as u8
-}
-
-/// Count Leading Zeros.
-#[inline]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(clz))]
-// FIXME: https://github.com/rust-lang/stdarch/issues/382
-// #[cfg_attr(all(test, target_arch = "arm"), assert_instr(clz))]
-pub unsafe fn _clz_u16(x: u16) -> u16 {
-    x.leading_zeros() as u16
-}
-
-/// Count Leading Zeros.
-#[inline]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(clz))]
-// FIXME: https://github.com/rust-lang/stdarch/issues/382
-// #[cfg_attr(all(test, target_arch = "arm"), assert_instr(clz))]
-pub unsafe fn _clz_u32(x: u32) -> u32 {
-    x.leading_zeros() as u32
-}
-
-/// Reverse the bit order.
-#[inline]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(test, assert_instr(rbit))]
-pub unsafe fn _rbit_u32(x: u32) -> u32 {
-    crate::intrinsics::bitreverse(x)
-}
-
-#[cfg(test)]
-mod tests {
-    use crate::core_arch::arm::v7;
-
-    #[test]
-    fn _clz_u8() {
-        unsafe {
-            assert_eq!(v7::_clz_u8(0b0000_1010u8), 4u8);
-        }
-    }
-
-    #[test]
-    fn _clz_u16() {
-        unsafe {
-            assert_eq!(v7::_clz_u16(0b0000_1010u16), 12u16);
-        }
-    }
-
-    #[test]
-    fn _clz_u32() {
-        unsafe {
-            assert_eq!(v7::_clz_u32(0b0000_1010u32), 28u32);
-        }
-    }
-
-    #[test]
-    fn _rbit_u32() {
-        unsafe {
-            assert_eq!(
-                v7::_rbit_u32(0b0000_1010u32),
-                0b0101_0000_0000_0000_0000_0000_0000_0000u32
-            );
-        }
-    }
-}