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| author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-06-07 05:48:48 +0000 |
|---|---|---|
| committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-06-07 05:48:48 +0000 |
| commit | ef24de24a82fe681581cc130f342363c47c0969a (patch) | |
| tree | 0d494f7e1a38b95c92426f58fe6eaa877303a86c /library/stdarch/crates/stdarch-test | |
| parent | Releasing progress-linux version 1.74.1+dfsg1-1~progress7.99u1. (diff) | |
| download | rustc-ef24de24a82fe681581cc130f342363c47c0969a.tar.xz rustc-ef24de24a82fe681581cc130f342363c47c0969a.zip | |
Merging upstream version 1.75.0+dfsg1.
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'library/stdarch/crates/stdarch-test')
| -rw-r--r-- | library/stdarch/crates/stdarch-test/Cargo.toml | 2 | ||||
| -rw-r--r-- | library/stdarch/crates/stdarch-test/src/disassembly.rs | 2 |
2 files changed, 3 insertions, 1 deletions
diff --git a/library/stdarch/crates/stdarch-test/Cargo.toml b/library/stdarch/crates/stdarch-test/Cargo.toml index 3a2130d4e..3682fcd7e 100644 --- a/library/stdarch/crates/stdarch-test/Cargo.toml +++ b/library/stdarch/crates/stdarch-test/Cargo.toml @@ -20,7 +20,7 @@ cc = "1.0" # time, and we want to make updates to this explicit rather than automatically # picking up updates which might break CI with new instruction names. [target.'cfg(target_arch = "wasm32")'.dependencies] -wasmprinter = "=0.2.53" +wasmprinter = "=0.2.67" [features] default = [] diff --git a/library/stdarch/crates/stdarch-test/src/disassembly.rs b/library/stdarch/crates/stdarch-test/src/disassembly.rs index 54df7261e..087fc46d4 100644 --- a/library/stdarch/crates/stdarch-test/src/disassembly.rs +++ b/library/stdarch/crates/stdarch-test/src/disassembly.rs @@ -81,6 +81,8 @@ pub(crate) fn disassemble_myself() -> HashSet<Function> { let add_args = if cfg!(target_os = "macos") && cfg!(target_arch = "aarch64") { // Target features need to be enabled for LLVM objdump on Macos ARM64 vec!["--mattr=+v8.6a,+crypto,+tme"] + } else if cfg!(target_arch = "riscv64") { + vec!["--mattr=+zk,+zks,+zbc,+zbb"] } else { vec![] }; |