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-rw-r--r--compiler/rustc_target/src/abi/call/riscv.rs4
1 files changed, 2 insertions, 2 deletions
diff --git a/compiler/rustc_target/src/abi/call/riscv.rs b/compiler/rustc_target/src/abi/call/riscv.rs
index 1cb360f83..34280d38e 100644
--- a/compiler/rustc_target/src/abi/call/riscv.rs
+++ b/compiler/rustc_target/src/abi/call/riscv.rs
@@ -25,7 +25,7 @@ enum FloatConv {
#[derive(Copy, Clone)]
struct CannotUseFpConv;
-fn is_riscv_aggregate<'a, Ty>(arg: &ArgAbi<'a, Ty>) -> bool {
+fn is_riscv_aggregate<Ty>(arg: &ArgAbi<'_, Ty>) -> bool {
match arg.layout.abi {
Abi::Vector { .. } => true,
_ => arg.layout.is_aggregate(),
@@ -296,7 +296,7 @@ fn classify_arg<'a, Ty, C>(
}
}
-fn extend_integer_width<'a, Ty>(arg: &mut ArgAbi<'a, Ty>, xlen: u64) {
+fn extend_integer_width<Ty>(arg: &mut ArgAbi<'_, Ty>, xlen: u64) {
if let Abi::Scalar(scalar) = arg.layout.abi {
if let abi::Int(i, _) = scalar.primitive() {
// 32-bit integers are always sign-extended