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// MIR for `inclusive_loop` after PreCodegen
fn inclusive_loop(_1: u32, _2: u32, _3: impl Fn(u32)) -> () {
debug start => _1;
debug end => _2;
debug f => _3;
let mut _0: ();
let mut _4: std::ops::RangeInclusive<u32>;
let mut _5: std::ops::RangeInclusive<u32>;
let mut _6: &mut std::ops::RangeInclusive<u32>;
let mut _7: std::option::Option<u32>;
let mut _8: isize;
let mut _10: &impl Fn(u32);
let mut _11: (u32,);
let _12: ();
scope 1 {
debug iter => _5;
let _9: u32;
scope 2 {
debug x => _9;
}
scope 5 (inlined iter::range::<impl Iterator for RangeInclusive<u32>>::next) {
debug self => _6;
}
}
scope 3 (inlined RangeInclusive::<u32>::new) {
debug start => _1;
debug end => _2;
}
scope 4 (inlined <RangeInclusive<u32> as IntoIterator>::into_iter) {
debug self => _4;
}
bb0: {
_4 = RangeInclusive::<u32> { start: _1, end: _2, exhausted: const false };
StorageLive(_5);
_5 = move _4;
goto -> bb1;
}
bb1: {
StorageLive(_7);
StorageLive(_6);
_6 = &mut _5;
_7 = <RangeInclusive<u32> as iter::range::RangeInclusiveIteratorImpl>::spec_next(move _6) -> [return: bb2, unwind unreachable];
}
bb2: {
StorageDead(_6);
_8 = discriminant(_7);
switchInt(move _8) -> [0: bb3, 1: bb5, otherwise: bb7];
}
bb3: {
StorageDead(_7);
StorageDead(_5);
drop(_3) -> [return: bb4, unwind unreachable];
}
bb4: {
return;
}
bb5: {
_9 = ((_7 as Some).0: u32);
StorageLive(_10);
_10 = &_3;
StorageLive(_11);
_11 = (_9,);
_12 = <impl Fn(u32) as Fn<(u32,)>>::call(move _10, move _11) -> [return: bb6, unwind unreachable];
}
bb6: {
StorageDead(_11);
StorageDead(_10);
StorageDead(_7);
goto -> bb1;
}
bb7: {
unreachable;
}
}
|
