diff options
Diffstat (limited to 'src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/IntelFsp2Pkg.dec')
| -rw-r--r-- | src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/IntelFsp2Pkg.dec | 109 |
1 files changed, 109 insertions, 0 deletions
diff --git a/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/IntelFsp2Pkg.dec b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/IntelFsp2Pkg.dec new file mode 100644 index 00000000..d49f8227 --- /dev/null +++ b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/IntelFsp2Pkg.dec @@ -0,0 +1,109 @@ +## @file +# Provides driver and definitions to build fsp in EDKII bios. +# +# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR> +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + DEC_SPECIFICATION = 0x00010005 + PACKAGE_NAME = IntelFsp2Pkg + PACKAGE_GUID = A8C53B5E-D556-4F3E-874D-0D6FA2CDC7BF + PACKAGE_VERSION = 0.1 + +[Includes] + Include + +[LibraryClasses] + ## @libraryclass Provides cache-as-ram support. + CacheAsRamLib|Include/Library/CacheAsRamLib.h + + ## @libraryclass Provides cache setting on MTRR. + CacheLib|Include/Library/CacheLib.h + + ## @libraryclass Provides debug device abstraction. + DebugDeviceLib|Include/Library/DebugDeviceLib.h + + ## @libraryclass Provides FSP related services. + FspCommonLib|Include/Library/FspCommonLib.h + + ## @libraryclass Provides FSP platform related actions. + FspPlatformLib|Include/Library/FspPlatformLib.h + + ## @libraryclass Provides FSP switch stack function. + FspSwitchStackLib|Include/Library/FspSwitchStackLib.h + + ## @libraryclass Provides FSP platform sec related actions. + FspSecPlatformLib|Include/Library/FspSecPlatformLib.h + +[Ppis] + # + # PPI to indicate FSP is ready to enter notify phase + # This provides flexibility for any late initialization that must be done right before entering notify phase. + # + gFspReadyForNotifyPhasePpiGuid = { 0xcd167c1e, 0x6e0b, 0x42b3, {0x82, 0xf6, 0xe3, 0xe9, 0x06, 0x19, 0x98, 0x10}} + + # + # PPI as dependency on some modules which only required for API mode + # + gFspInApiModePpiGuid = { 0xa1eeab87, 0xc859, 0x479d, {0x89, 0xb5, 0x14, 0x61, 0xf4, 0x06, 0x1a, 0x3e}} + + # + # PPI for Architectural configuration data for FSP-M + # + gFspmArchConfigPpiGuid = { 0x824d5a3a, 0xaf92, 0x4c0c, {0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb}} + + # + # PPI to tear down the temporary memory set up by TempRamInit (). + # + gFspTempRamExitPpiGuid = { 0xbc1cfbdb, 0x7e50, 0x42be, {0xb4, 0x87, 0x22, 0xe0, 0xa9, 0x0c, 0xb0, 0x52}} + +[Guids] + # + # GUID defined in package + # + gIntelFsp2PkgTokenSpaceGuid = { 0xed6e0531, 0xf715, 0x4a3d, { 0x9b, 0x12, 0xc1, 0xca, 0x5e, 0xf6, 0x98, 0xa2 } } + + # Guid define in FSP EAS + gFspHeaderFileGuid = { 0x912740BE, 0x2284, 0x4734, { 0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C } } + gFspReservedMemoryResourceHobGuid = { 0x69a79759, 0x1373, 0x4367, { 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e } } + gFspNonVolatileStorageHobGuid = { 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0 } } + gFspBootLoaderTolumHobGuid = { 0x73ff4f56, 0xaa8e, 0x4451, { 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44 } } # FSP EAS v1.1 + + gFspPerformanceDataGuid = { 0x56ed21b6, 0xba23, 0x429e, { 0x89, 0x32, 0x37, 0x6d, 0x8e, 0x18, 0x2e, 0xe3 } } + gFspEventEndOfFirmwareGuid = { 0xbd44f629, 0xeae7, 0x4198, { 0x87, 0xf1, 0x39, 0xfa, 0xb0, 0xfd, 0x71, 0x7e } } + +[PcdsFixedAtBuild] + gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress |0xFED00108|UINT32|0x00000001 + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase |0xFEF00000|UINT32|0x10001001 + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize | 0x2000|UINT32|0x10001002 + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize | 0x1000|UINT32|0x10001003 + gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize | 0x100|UINT32|0x10001004 + gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry | 32|UINT32|0x00002001 + gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry | 6|UINT32|0x00002002 + gIntelFsp2PkgTokenSpaceGuid.PcdFspAreaBaseAddress |0xFFF80000|UINT32|0x10000001 + gIntelFsp2PkgTokenSpaceGuid.PcdFspAreaSize |0x00040000|UINT32|0x10000002 + gIntelFsp2PkgTokenSpaceGuid.PcdFspBootFirmwareVolumeBase|0xFFF80000|UINT32|0x10000003 + gIntelFsp2PkgTokenSpaceGuid.PcdFspHeaderSpecVersion | 0x20| UINT8|0x00000002 + + # + # x % of FSP temporary memory will be used for heap + # (100 - x) % of FSP temporary memory will be used for stack + # 0 means FSP will share the stack with boot loader and FSP temporary memory is heap + # Note: This mode assumes boot loader stack is large enough for FSP to use. + # + gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage | 50| UINT8|0x10000004 + # + # Maximal Interrupt supported in IDT table. + # + gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxInterruptSupported | 34| UINT8|0x10000005 + # + # Allows FSP-M to reserve a section of Temporary RAM for implementation specific use. + # Reduces the amount of memory available for the PeiCore heap. + # + gIntelFsp2PkgTokenSpaceGuid.PcdFspPrivateTemporaryRamSize |0x00000000|UINT32|0x10000006 + +[PcdsFixedAtBuild,PcdsDynamic,PcdsDynamicEx] + gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedMemoryLength |0x00100000|UINT32|0x46530000 + gIntelFsp2PkgTokenSpaceGuid.PcdBootLoaderEntry |0xFFFFFFE4|UINT32|0x46530100 |