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| author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-07 18:49:45 +0000 |
|---|---|---|
| committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-07 18:49:45 +0000 |
| commit | 2c3c1048746a4622d8c89a29670120dc8fab93c4 (patch) | |
| tree | 848558de17fb3008cdf4d861b01ac7781903ce39 /arch/arm64/boot/dts/mediatek | |
| parent | Initial commit. (diff) | |
| download | linux-2c3c1048746a4622d8c89a29670120dc8fab93c4.tar.xz linux-2c3c1048746a4622d8c89a29670120dc8fab93c4.zip | |
Adding upstream version 6.1.76.upstream/6.1.76
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'arch/arm64/boot/dts/mediatek')
92 files changed, 27887 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile new file mode 100644 index 000000000..0ec90cb3e --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana-rev7.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-burnet.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-cozmo.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-damu.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku1.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku6.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku7.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14-sku2.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-juniper-sku16.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kappa.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kenzo.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku0.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku1.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu-sku22.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku16.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku272.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku288.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku32.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r1.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r2.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r3.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts new file mode 100644 index 000000000..d31a19412 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts @@ -0,0 +1,236 @@ +/* + * Copyright (c) 2017 MediaTek Inc. + * Author: YT Shen <yt.shen@mediatek.com> + * + * SPDX-License-Identifier: (GPL-2.0 OR MIT) + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include "mt2712e.dtsi" + +/ { + model = "MediaTek MT2712 evaluation board"; + compatible = "mediatek,mt2712-evb", "mediatek,mt2712"; + + aliases { + serial0 = &uart0; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + cpus_fixed_vproc0: regulator-vproc-buck0 { + compatible = "regulator-fixed"; + regulator-name = "vproc_buck0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + cpus_fixed_vproc1: regulator-vproc-buck1 { + compatible = "regulator-fixed"; + regulator-name = "vproc_buck1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + extcon_usb: extcon_iddig { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&pio 12 GPIO_ACTIVE_HIGH>; + }; + + extcon_usb1: extcon_iddig1 { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&pio 14 GPIO_ACTIVE_HIGH>; + }; + + usb_p0_vbus: regulator-usb-p0-vbus { + compatible = "regulator-fixed"; + regulator-name = "p0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_p1_vbus: regulator-usb-p1-vbus { + compatible = "regulator-fixed"; + regulator-name = "p1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_p2_vbus: regulator-usb-p2-vbus { + compatible = "regulator-fixed"; + regulator-name = "p2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_p3_vbus: regulator-usb-p3-vbus { + compatible = "regulator-fixed"; + regulator-name = "p3_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + +}; + +&auxadc { + status = "okay"; +}; + +&cpu0 { + proc-supply = <&cpus_fixed_vproc0>; +}; + +&cpu1 { + proc-supply = <&cpus_fixed_vproc0>; +}; + +&cpu2 { + proc-supply = <&cpus_fixed_vproc1>; +}; + +ð { + phy-mode = "rgmii-rxid"; + phy-handle = <ðernet_phy0>; + mediatek,tx-delay-ps = <1530>; + snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>; + snps,reset-delays-us = <0 10000 10000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ð_default>; + pinctrl-1 = <ð_sleep>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + ethernet_phy0: ethernet-phy@5 { + compatible = "ethernet-phy-id0243.0d90"; + reg = <0x5>; + }; + }; +}; + +&pio { + eth_default: eth_default { + tx_pins { + pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GBE_TXD3>, + <MT2712_PIN_72_GBE_TXD2__FUNC_GBE_TXD2>, + <MT2712_PIN_73_GBE_TXD1__FUNC_GBE_TXD1>, + <MT2712_PIN_74_GBE_TXD0__FUNC_GBE_TXD0>, + <MT2712_PIN_75_GBE_TXC__FUNC_GBE_TXC>, + <MT2712_PIN_76_GBE_TXEN__FUNC_GBE_TXEN>; + drive-strength = <MTK_DRIVE_8mA>; + }; + rx_pins { + pinmux = <MT2712_PIN_78_GBE_RXD3__FUNC_GBE_RXD3>, + <MT2712_PIN_79_GBE_RXD2__FUNC_GBE_RXD2>, + <MT2712_PIN_80_GBE_RXD1__FUNC_GBE_RXD1>, + <MT2712_PIN_81_GBE_RXD0__FUNC_GBE_RXD0>, + <MT2712_PIN_82_GBE_RXDV__FUNC_GBE_RXDV>, + <MT2712_PIN_84_GBE_RXC__FUNC_GBE_RXC>; + input-enable; + }; + mdio_pins { + pinmux = <MT2712_PIN_85_GBE_MDC__FUNC_GBE_MDC>, + <MT2712_PIN_86_GBE_MDIO__FUNC_GBE_MDIO>; + drive-strength = <MTK_DRIVE_8mA>; + input-enable; + }; + }; + + eth_sleep: eth_sleep { + tx_pins { + pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GPIO71>, + <MT2712_PIN_72_GBE_TXD2__FUNC_GPIO72>, + <MT2712_PIN_73_GBE_TXD1__FUNC_GPIO73>, + <MT2712_PIN_74_GBE_TXD0__FUNC_GPIO74>, + <MT2712_PIN_75_GBE_TXC__FUNC_GPIO75>, + <MT2712_PIN_76_GBE_TXEN__FUNC_GPIO76>; + }; + rx_pins { + pinmux = <MT2712_PIN_78_GBE_RXD3__FUNC_GPIO78>, + <MT2712_PIN_79_GBE_RXD2__FUNC_GPIO79>, + <MT2712_PIN_80_GBE_RXD1__FUNC_GPIO80>, + <MT2712_PIN_81_GBE_RXD0__FUNC_GPIO81>, + <MT2712_PIN_82_GBE_RXDV__FUNC_GPIO82>, + <MT2712_PIN_84_GBE_RXC__FUNC_GPIO84>; + input-disable; + }; + mdio_pins { + pinmux = <MT2712_PIN_85_GBE_MDC__FUNC_GPIO85>, + <MT2712_PIN_86_GBE_MDIO__FUNC_GPIO86>; + input-disable; + bias-disable; + }; + }; + + usb0_id_pins_float: usb0_iddig { + pins_iddig { + pinmux = <MT2712_PIN_12_IDDIG_P0__FUNC_IDDIG_A>; + bias-pull-up; + }; + }; + + usb1_id_pins_float: usb1_iddig { + pins_iddig { + pinmux = <MT2712_PIN_14_IDDIG_P1__FUNC_IDDIG_B>; + bias-pull-up; + }; + }; +}; + +&ssusb { + vbus-supply = <&usb_p0_vbus>; + extcon = <&extcon_usb>; + dr_mode = "otg"; + wakeup-source; + mediatek,u3p-dis-msk = <0x1>; + //enable-manual-drd; + //maximum-speed = "full-speed"; + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_pins_float>; + status = "okay"; +}; + +&ssusb1 { + vbus-supply = <&usb_p1_vbus>; + extcon = <&extcon_usb1>; + dr_mode = "otg"; + //mediatek,u3p-dis-msk = <0x1>; + enable-manual-drd; + wakeup-source; + //maximum-speed = "full-speed"; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_id_pins_float>; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&usb_host0 { + vbus-supply = <&usb_p2_vbus>; + status = "okay"; +}; + +&usb_host1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h new file mode 100644 index 000000000..385c455a7 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h @@ -0,0 +1,1123 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + * Author: Zhiyong Tao <zhiyong.tao@mediatek.com> + * + */ +#ifndef __DTS_MT2712_PINFUNC_H +#define __DTS_MT2712_PINFUNC_H + +#include <dt-bindings/pinctrl/mt65xx.h> + +#define MT2712_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT2712_PIN_0_EINT0__FUNC_EINT0 (MTK_PIN_NO(0) | 1) +#define MT2712_PIN_0_EINT0__FUNC_MBIST_DIAG_SCANOUT (MTK_PIN_NO(0) | 2) +#define MT2712_PIN_0_EINT0__FUNC_DSIA_TE (MTK_PIN_NO(0) | 3) +#define MT2712_PIN_0_EINT0__FUNC_DSIC_TE (MTK_PIN_NO(0) | 4) +#define MT2712_PIN_0_EINT0__FUNC_DIN_D3 (MTK_PIN_NO(0) | 5) +#define MT2712_PIN_0_EINT0__FUNC_PURE_HW_PROTECT (MTK_PIN_NO(0) | 6) + +#define MT2712_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT2712_PIN_1_EINT1__FUNC_EINT1 (MTK_PIN_NO(1) | 1) +#define MT2712_PIN_1_EINT1__FUNC_IR_IN (MTK_PIN_NO(1) | 2) +#define MT2712_PIN_1_EINT1__FUNC_DSIB_TE (MTK_PIN_NO(1) | 3) +#define MT2712_PIN_1_EINT1__FUNC_DSID_TE (MTK_PIN_NO(1) | 4) +#define MT2712_PIN_1_EINT1__FUNC_DIN_D4 (MTK_PIN_NO(1) | 5) + +#define MT2712_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT2712_PIN_2_EINT2__FUNC_EINT2 (MTK_PIN_NO(2) | 1) +#define MT2712_PIN_2_EINT2__FUNC_IR_IN (MTK_PIN_NO(2) | 2) +#define MT2712_PIN_2_EINT2__FUNC_LCM_RST1 (MTK_PIN_NO(2) | 3) +#define MT2712_PIN_2_EINT2__FUNC_DIN_D5 (MTK_PIN_NO(2) | 5) + +#define MT2712_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT2712_PIN_3_EINT3__FUNC_EINT3 (MTK_PIN_NO(3) | 1) +#define MT2712_PIN_3_EINT3__FUNC_IR_IN (MTK_PIN_NO(3) | 2) +#define MT2712_PIN_3_EINT3__FUNC_LCM_RST0 (MTK_PIN_NO(3) | 3) +#define MT2712_PIN_3_EINT3__FUNC_DIN_D6 (MTK_PIN_NO(3) | 5) + +#define MT2712_PIN_4_PWM0__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT2712_PIN_4_PWM0__FUNC_PWM0 (MTK_PIN_NO(4) | 1) +#define MT2712_PIN_4_PWM0__FUNC_DISP0_PWM (MTK_PIN_NO(4) | 2) +#define MT2712_PIN_4_PWM0__FUNC_DISP1_PWM (MTK_PIN_NO(4) | 3) +#define MT2712_PIN_4_PWM0__FUNC_DIN_CLK (MTK_PIN_NO(4) | 5) + +#define MT2712_PIN_5_PWM1__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT2712_PIN_5_PWM1__FUNC_PWM1 (MTK_PIN_NO(5) | 1) +#define MT2712_PIN_5_PWM1__FUNC_DISP1_PWM (MTK_PIN_NO(5) | 2) +#define MT2712_PIN_5_PWM1__FUNC_DISP0_PWM (MTK_PIN_NO(5) | 3) +#define MT2712_PIN_5_PWM1__FUNC_DIN_VSYNC (MTK_PIN_NO(5) | 5) + +#define MT2712_PIN_6_PWM2__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT2712_PIN_6_PWM2__FUNC_PWM2 (MTK_PIN_NO(6) | 1) +#define MT2712_PIN_6_PWM2__FUNC_DISP0_PWM (MTK_PIN_NO(6) | 2) +#define MT2712_PIN_6_PWM2__FUNC_DISP1_PWM (MTK_PIN_NO(6) | 3) +#define MT2712_PIN_6_PWM2__FUNC_DISP2_PWM (MTK_PIN_NO(6) | 4) +#define MT2712_PIN_6_PWM2__FUNC_DIN_HSYNC (MTK_PIN_NO(6) | 5) + +#define MT2712_PIN_7_PWM3__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define MT2712_PIN_7_PWM3__FUNC_PWM3 (MTK_PIN_NO(7) | 1) +#define MT2712_PIN_7_PWM3__FUNC_DISP1_PWM (MTK_PIN_NO(7) | 2) +#define MT2712_PIN_7_PWM3__FUNC_DISP0_PWM (MTK_PIN_NO(7) | 3) +#define MT2712_PIN_7_PWM3__FUNC_LCM_RST2 (MTK_PIN_NO(7) | 4) +#define MT2712_PIN_7_PWM3__FUNC_DIN_D0 (MTK_PIN_NO(7) | 5) + +#define MT2712_PIN_8_PWM4__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define MT2712_PIN_8_PWM4__FUNC_PWM4 (MTK_PIN_NO(8) | 1) +#define MT2712_PIN_8_PWM4__FUNC_DISP0_PWM (MTK_PIN_NO(8) | 2) +#define MT2712_PIN_8_PWM4__FUNC_DISP1_PWM (MTK_PIN_NO(8) | 3) +#define MT2712_PIN_8_PWM4__FUNC_DSIA_TE (MTK_PIN_NO(8) | 4) +#define MT2712_PIN_8_PWM4__FUNC_DIN_D1 (MTK_PIN_NO(8) | 5) + +#define MT2712_PIN_9_PWM5__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define MT2712_PIN_9_PWM5__FUNC_PWM5 (MTK_PIN_NO(9) | 1) +#define MT2712_PIN_9_PWM5__FUNC_DISP1_PWM (MTK_PIN_NO(9) | 2) +#define MT2712_PIN_9_PWM5__FUNC_DISP0_PWM (MTK_PIN_NO(9) | 3) +#define MT2712_PIN_9_PWM5__FUNC_DSIB_TE (MTK_PIN_NO(9) | 4) +#define MT2712_PIN_9_PWM5__FUNC_DIN_D2 (MTK_PIN_NO(9) | 5) + +#define MT2712_PIN_10_PWM6__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define MT2712_PIN_10_PWM6__FUNC_PWM6 (MTK_PIN_NO(10) | 1) +#define MT2712_PIN_10_PWM6__FUNC_DISP0_PWM (MTK_PIN_NO(10) | 2) +#define MT2712_PIN_10_PWM6__FUNC_DISP1_PWM (MTK_PIN_NO(10) | 3) +#define MT2712_PIN_10_PWM6__FUNC_LCM_RST0 (MTK_PIN_NO(10) | 4) + +#define MT2712_PIN_11_PWM7__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define MT2712_PIN_11_PWM7__FUNC_PWM7 (MTK_PIN_NO(11) | 1) +#define MT2712_PIN_11_PWM7__FUNC_DISP1_PWM (MTK_PIN_NO(11) | 2) +#define MT2712_PIN_11_PWM7__FUNC_DISP0_PWM (MTK_PIN_NO(11) | 3) +#define MT2712_PIN_11_PWM7__FUNC_LCM_RST1 (MTK_PIN_NO(11) | 4) + +#define MT2712_PIN_12_IDDIG_P0__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define MT2712_PIN_12_IDDIG_P0__FUNC_IDDIG_A (MTK_PIN_NO(12) | 1) +#define MT2712_PIN_12_IDDIG_P0__FUNC_DIN_D7 (MTK_PIN_NO(12) | 5) + +#define MT2712_PIN_13_DRV_VBUS_P0__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define MT2712_PIN_13_DRV_VBUS_P0__FUNC_DRV_VBUS_A (MTK_PIN_NO(13) | 1) + +#define MT2712_PIN_14_IDDIG_P1__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define MT2712_PIN_14_IDDIG_P1__FUNC_IDDIG_B (MTK_PIN_NO(14) | 1) + +#define MT2712_PIN_15_DRV_VBUS_P1__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define MT2712_PIN_15_DRV_VBUS_P1__FUNC_DRV_VBUS_B (MTK_PIN_NO(15) | 1) + +#define MT2712_PIN_16_DRV_VBUS_P2__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define MT2712_PIN_16_DRV_VBUS_P2__FUNC_DRV_VBUS_C (MTK_PIN_NO(16) | 1) + +#define MT2712_PIN_17_DRV_VBUS_P3__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define MT2712_PIN_17_DRV_VBUS_P3__FUNC_DRV_VBUS_D (MTK_PIN_NO(17) | 1) + +#define MT2712_PIN_18_KPROW0__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define MT2712_PIN_18_KPROW0__FUNC_KROW0 (MTK_PIN_NO(18) | 1) + +#define MT2712_PIN_19_KPCOL0__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define MT2712_PIN_19_KPCOL0__FUNC_KCOL0 (MTK_PIN_NO(19) | 1) + +#define MT2712_PIN_20_KPROW1__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define MT2712_PIN_20_KPROW1__FUNC_KROW1 (MTK_PIN_NO(20) | 1) + +#define MT2712_PIN_21_KPCOL1__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define MT2712_PIN_21_KPCOL1__FUNC_KCOL1 (MTK_PIN_NO(21) | 1) + +#define MT2712_PIN_22_KPROW2__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define MT2712_PIN_22_KPROW2__FUNC_KROW2 (MTK_PIN_NO(22) | 1) +#define MT2712_PIN_22_KPROW2__FUNC_DISP1_PWM (MTK_PIN_NO(22) | 2) + +#define MT2712_PIN_23_KPCOL2__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define MT2712_PIN_23_KPCOL2__FUNC_KCOL2 (MTK_PIN_NO(23) | 1) +#define MT2712_PIN_23_KPCOL2__FUNC_DISP0_PWM (MTK_PIN_NO(23) | 2) + +#define MT2712_PIN_24_CMMCLK__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define MT2712_PIN_24_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(24) | 1) +#define MT2712_PIN_24_CMMCLK__FUNC_DBG_MON_A_1_ (MTK_PIN_NO(24) | 7) + +#define MT2712_PIN_25_CM2MCLK__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define MT2712_PIN_25_CM2MCLK__FUNC_CM2MCLK (MTK_PIN_NO(25) | 1) +#define MT2712_PIN_25_CM2MCLK__FUNC_DBG_MON_A_2_ (MTK_PIN_NO(25) | 7) + +#define MT2712_PIN_26_PCM_TX__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define MT2712_PIN_26_PCM_TX__FUNC_PCM1_DO (MTK_PIN_NO(26) | 1) +#define MT2712_PIN_26_PCM_TX__FUNC_MRG_TX (MTK_PIN_NO(26) | 2) +#define MT2712_PIN_26_PCM_TX__FUNC_DAI_TX (MTK_PIN_NO(26) | 3) +#define MT2712_PIN_26_PCM_TX__FUNC_MRG_RX (MTK_PIN_NO(26) | 4) +#define MT2712_PIN_26_PCM_TX__FUNC_DAI_RX (MTK_PIN_NO(26) | 5) +#define MT2712_PIN_26_PCM_TX__FUNC_PCM1_DI (MTK_PIN_NO(26) | 6) +#define MT2712_PIN_26_PCM_TX__FUNC_DBG_MON_A_3_ (MTK_PIN_NO(26) | 7) + +#define MT2712_PIN_27_PCM_CLK__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define MT2712_PIN_27_PCM_CLK__FUNC_PCM1_CLK (MTK_PIN_NO(27) | 1) +#define MT2712_PIN_27_PCM_CLK__FUNC_MRG_CLK (MTK_PIN_NO(27) | 2) +#define MT2712_PIN_27_PCM_CLK__FUNC_DAI_CLK (MTK_PIN_NO(27) | 3) +#define MT2712_PIN_27_PCM_CLK__FUNC_DBG_MON_A_4_ (MTK_PIN_NO(27) | 7) + +#define MT2712_PIN_28_PCM_RX__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define MT2712_PIN_28_PCM_RX__FUNC_PCM1_DI (MTK_PIN_NO(28) | 1) +#define MT2712_PIN_28_PCM_RX__FUNC_MRG_RX (MTK_PIN_NO(28) | 2) +#define MT2712_PIN_28_PCM_RX__FUNC_DAI_RX (MTK_PIN_NO(28) | 3) +#define MT2712_PIN_28_PCM_RX__FUNC_MRG_TX (MTK_PIN_NO(28) | 4) +#define MT2712_PIN_28_PCM_RX__FUNC_DAI_TX (MTK_PIN_NO(28) | 5) +#define MT2712_PIN_28_PCM_RX__FUNC_PCM1_DO (MTK_PIN_NO(28) | 6) +#define MT2712_PIN_28_PCM_RX__FUNC_DBG_MON_A_5_ (MTK_PIN_NO(28) | 7) + +#define MT2712_PIN_29_PCM_SYNC__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define MT2712_PIN_29_PCM_SYNC__FUNC_PCM1_SYNC (MTK_PIN_NO(29) | 1) +#define MT2712_PIN_29_PCM_SYNC__FUNC_MRG_SYNC (MTK_PIN_NO(29) | 2) +#define MT2712_PIN_29_PCM_SYNC__FUNC_DAI_SYNC (MTK_PIN_NO(29) | 3) +#define MT2712_PIN_29_PCM_SYNC__FUNC_DBG_MON_A_6_ (MTK_PIN_NO(29) | 7) + +#define MT2712_PIN_30_NCEB0__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define MT2712_PIN_30_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(30) | 1) +#define MT2712_PIN_30_NCEB0__FUNC_USB0_FT_SDA (MTK_PIN_NO(30) | 2) +#define MT2712_PIN_30_NCEB0__FUNC_DBG_MON_A_7_ (MTK_PIN_NO(30) | 7) + +#define MT2712_PIN_31_NCEB1__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define MT2712_PIN_31_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(31) | 1) +#define MT2712_PIN_31_NCEB1__FUNC_USB1_FT_SCL (MTK_PIN_NO(31) | 2) +#define MT2712_PIN_31_NCEB1__FUNC_DBG_MON_A_8_ (MTK_PIN_NO(31) | 7) + +#define MT2712_PIN_32_NF_DQS__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define MT2712_PIN_32_NF_DQS__FUNC_NF_DQS (MTK_PIN_NO(32) | 1) +#define MT2712_PIN_32_NF_DQS__FUNC_USB1_FT_SDA (MTK_PIN_NO(32) | 2) +#define MT2712_PIN_32_NF_DQS__FUNC_DBG_MON_A_9_ (MTK_PIN_NO(32) | 7) + +#define MT2712_PIN_33_NWEB__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define MT2712_PIN_33_NWEB__FUNC_NWEB (MTK_PIN_NO(33) | 1) +#define MT2712_PIN_33_NWEB__FUNC_USB2_FT_SCL (MTK_PIN_NO(33) | 2) +#define MT2712_PIN_33_NWEB__FUNC_DBG_MON_A_10_ (MTK_PIN_NO(33) | 7) + +#define MT2712_PIN_34_NREB__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define MT2712_PIN_34_NREB__FUNC_NREB (MTK_PIN_NO(34) | 1) +#define MT2712_PIN_34_NREB__FUNC_USB2_FT_SDA (MTK_PIN_NO(34) | 2) +#define MT2712_PIN_34_NREB__FUNC_DBG_MON_A_11_ (MTK_PIN_NO(34) | 7) + +#define MT2712_PIN_35_NCLE__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define MT2712_PIN_35_NCLE__FUNC_NCLE (MTK_PIN_NO(35) | 1) +#define MT2712_PIN_35_NCLE__FUNC_USB3_FT_SCL (MTK_PIN_NO(35) | 2) +#define MT2712_PIN_35_NCLE__FUNC_DBG_MON_A_12_ (MTK_PIN_NO(35) | 7) + +#define MT2712_PIN_36_NALE__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define MT2712_PIN_36_NALE__FUNC_NALE (MTK_PIN_NO(36) | 1) +#define MT2712_PIN_36_NALE__FUNC_USB3_FT_SDA (MTK_PIN_NO(36) | 2) +#define MT2712_PIN_36_NALE__FUNC_DBG_MON_A_13_ (MTK_PIN_NO(36) | 7) + +#define MT2712_PIN_37_MSDC0E_CLK__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define MT2712_PIN_37_MSDC0E_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(37) | 1) +#define MT2712_PIN_37_MSDC0E_CLK__FUNC_USB0_FT_SCL (MTK_PIN_NO(37) | 2) +#define MT2712_PIN_37_MSDC0E_CLK__FUNC_DBG_MON_A_0_ (MTK_PIN_NO(37) | 7) + +#define MT2712_PIN_38_MSDC0E_DAT7__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define MT2712_PIN_38_MSDC0E_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(38) | 1) +#define MT2712_PIN_38_MSDC0E_DAT7__FUNC_NAND_ND7 (MTK_PIN_NO(38) | 2) +#define MT2712_PIN_38_MSDC0E_DAT7__FUNC_DBG_MON_A_14_ (MTK_PIN_NO(38) | 7) + +#define MT2712_PIN_39_MSDC0E_DAT6__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define MT2712_PIN_39_MSDC0E_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(39) | 1) +#define MT2712_PIN_39_MSDC0E_DAT6__FUNC_NAND_ND6 (MTK_PIN_NO(39) | 2) +#define MT2712_PIN_39_MSDC0E_DAT6__FUNC_DBG_MON_A_15_ (MTK_PIN_NO(39) | 7) + +#define MT2712_PIN_40_MSDC0E_DAT5__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define MT2712_PIN_40_MSDC0E_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(40) | 1) +#define MT2712_PIN_40_MSDC0E_DAT5__FUNC_NAND_ND5 (MTK_PIN_NO(40) | 2) +#define MT2712_PIN_40_MSDC0E_DAT5__FUNC_DBG_MON_A_16_ (MTK_PIN_NO(40) | 7) + +#define MT2712_PIN_41_MSDC0E_DAT4__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define MT2712_PIN_41_MSDC0E_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(41) | 1) +#define MT2712_PIN_41_MSDC0E_DAT4__FUNC_NAND_ND4 (MTK_PIN_NO(41) | 2) +#define MT2712_PIN_41_MSDC0E_DAT4__FUNC_DBG_MON_A_17_ (MTK_PIN_NO(41) | 7) + +#define MT2712_PIN_42_MSDC0E_DAT3__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define MT2712_PIN_42_MSDC0E_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(42) | 1) +#define MT2712_PIN_42_MSDC0E_DAT3__FUNC_NAND_ND3 (MTK_PIN_NO(42) | 2) +#define MT2712_PIN_42_MSDC0E_DAT3__FUNC_DBG_MON_A_18_ (MTK_PIN_NO(42) | 7) + +#define MT2712_PIN_43_MSDC0E_DAT2__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define MT2712_PIN_43_MSDC0E_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(43) | 1) +#define MT2712_PIN_43_MSDC0E_DAT2__FUNC_NAND_ND2 (MTK_PIN_NO(43) | 2) +#define MT2712_PIN_43_MSDC0E_DAT2__FUNC_DBG_MON_A_19_ (MTK_PIN_NO(43) | 7) + +#define MT2712_PIN_44_MSDC0E_DAT1__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define MT2712_PIN_44_MSDC0E_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(44) | 1) +#define MT2712_PIN_44_MSDC0E_DAT1__FUNC_NAND_ND1 (MTK_PIN_NO(44) | 2) +#define MT2712_PIN_44_MSDC0E_DAT1__FUNC_DBG_MON_A_20_ (MTK_PIN_NO(44) | 7) + +#define MT2712_PIN_45_MSDC0E_DAT0__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define MT2712_PIN_45_MSDC0E_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(45) | 1) +#define MT2712_PIN_45_MSDC0E_DAT0__FUNC_NAND_ND0 (MTK_PIN_NO(45) | 2) +#define MT2712_PIN_45_MSDC0E_DAT0__FUNC_DBG_MON_A_21_ (MTK_PIN_NO(45) | 7) + +#define MT2712_PIN_46_MSDC0E_CMD__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define MT2712_PIN_46_MSDC0E_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(46) | 1) +#define MT2712_PIN_46_MSDC0E_CMD__FUNC_NAND_NRNB (MTK_PIN_NO(46) | 2) +#define MT2712_PIN_46_MSDC0E_CMD__FUNC_DBG_MON_A_22_ (MTK_PIN_NO(46) | 7) + +#define MT2712_PIN_47_MSDC0E_DSL__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define MT2712_PIN_47_MSDC0E_DSL__FUNC_MSDC0_DSL (MTK_PIN_NO(47) | 1) +#define MT2712_PIN_47_MSDC0E_DSL__FUNC_DBG_MON_A_23_ (MTK_PIN_NO(47) | 7) + +#define MT2712_PIN_48_MSDC0E_RSTB__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define MT2712_PIN_48_MSDC0E_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(48) | 1) +#define MT2712_PIN_48_MSDC0E_RSTB__FUNC_DBG_MON_A_24_ (MTK_PIN_NO(48) | 7) + +#define MT2712_PIN_49_MSDC3_DAT3__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define MT2712_PIN_49_MSDC3_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(49) | 1) +#define MT2712_PIN_49_MSDC3_DAT3__FUNC_DBG_MON_A_25_ (MTK_PIN_NO(49) | 7) + +#define MT2712_PIN_50_MSDC3_DAT2__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define MT2712_PIN_50_MSDC3_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(50) | 1) +#define MT2712_PIN_50_MSDC3_DAT2__FUNC_DBG_MON_A_26_ (MTK_PIN_NO(50) | 7) + +#define MT2712_PIN_51_MSDC3_DAT1__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define MT2712_PIN_51_MSDC3_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(51) | 1) +#define MT2712_PIN_51_MSDC3_DAT1__FUNC_DBG_MON_A_27_ (MTK_PIN_NO(51) | 7) + +#define MT2712_PIN_52_MSDC3_DAT0__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define MT2712_PIN_52_MSDC3_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(52) | 1) +#define MT2712_PIN_52_MSDC3_DAT0__FUNC_DBG_MON_A_28_ (MTK_PIN_NO(52) | 7) + +#define MT2712_PIN_53_MSDC3_CMD__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define MT2712_PIN_53_MSDC3_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(53) | 1) +#define MT2712_PIN_53_MSDC3_CMD__FUNC_DBG_MON_A_29_ (MTK_PIN_NO(53) | 7) + +#define MT2712_PIN_54_MSDC3_INS__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define MT2712_PIN_54_MSDC3_INS__FUNC_MSDC3_INS (MTK_PIN_NO(54) | 1) +#define MT2712_PIN_54_MSDC3_INS__FUNC_DBG_MON_A_30_ (MTK_PIN_NO(54) | 7) + +#define MT2712_PIN_55_MSDC3_DSL__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define MT2712_PIN_55_MSDC3_DSL__FUNC_MSDC3_DSL (MTK_PIN_NO(55) | 1) +#define MT2712_PIN_55_MSDC3_DSL__FUNC_DBG_MON_A_31_ (MTK_PIN_NO(55) | 7) + +#define MT2712_PIN_56_MSDC3_CLK__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define MT2712_PIN_56_MSDC3_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(56) | 1) +#define MT2712_PIN_56_MSDC3_CLK__FUNC_DBG_MON_A_32_ (MTK_PIN_NO(56) | 7) + +#define MT2712_PIN_57_NOR_CS__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define MT2712_PIN_57_NOR_CS__FUNC_NOR_CS (MTK_PIN_NO(57) | 1) + +#define MT2712_PIN_58_NOR_CK__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define MT2712_PIN_58_NOR_CK__FUNC_NOR_CK (MTK_PIN_NO(58) | 1) + +#define MT2712_PIN_59_NOR_IO0__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define MT2712_PIN_59_NOR_IO0__FUNC_NOR_IO0 (MTK_PIN_NO(59) | 1) + +#define MT2712_PIN_60_NOR_IO1__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define MT2712_PIN_60_NOR_IO1__FUNC_NOR_IO1 (MTK_PIN_NO(60) | 1) + +#define MT2712_PIN_61_NOR_IO2__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define MT2712_PIN_61_NOR_IO2__FUNC_NOR_IO2 (MTK_PIN_NO(61) | 1) + +#define MT2712_PIN_62_NOR_IO3__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define MT2712_PIN_62_NOR_IO3__FUNC_NOR_IO3 (MTK_PIN_NO(62) | 1) + +#define MT2712_PIN_63_MSDC1_CLK__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define MT2712_PIN_63_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(63) | 1) +#define MT2712_PIN_63_MSDC1_CLK__FUNC_UDI_TCK (MTK_PIN_NO(63) | 2) + +#define MT2712_PIN_64_MSDC1_DAT3__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define MT2712_PIN_64_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(64) | 1) +#define MT2712_PIN_64_MSDC1_DAT3__FUNC_UDI_TDI (MTK_PIN_NO(64) | 2) + +#define MT2712_PIN_65_MSDC1_DAT1__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define MT2712_PIN_65_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(65) | 1) +#define MT2712_PIN_65_MSDC1_DAT1__FUNC_UDI_TMS (MTK_PIN_NO(65) | 2) + +#define MT2712_PIN_66_MSDC1_DAT2__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define MT2712_PIN_66_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(66) | 1) +#define MT2712_PIN_66_MSDC1_DAT2__FUNC_UDI_TDO (MTK_PIN_NO(66) | 2) + +#define MT2712_PIN_67_MSDC1_PSW__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define MT2712_PIN_67_MSDC1_PSW__FUNC_UDI_NTRST (MTK_PIN_NO(67) | 2) + +#define MT2712_PIN_68_MSDC1_DAT0__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define MT2712_PIN_68_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(68) | 1) + +#define MT2712_PIN_69_MSDC1_CMD__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define MT2712_PIN_69_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(69) | 1) + +#define MT2712_PIN_70_MSDC1_INS__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) + +#define MT2712_PIN_71_GBE_TXD3__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define MT2712_PIN_71_GBE_TXD3__FUNC_GBE_TXD3 (MTK_PIN_NO(71) | 1) +#define MT2712_PIN_71_GBE_TXD3__FUNC_DBG_MON_B_0_ (MTK_PIN_NO(71) | 7) + +#define MT2712_PIN_72_GBE_TXD2__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define MT2712_PIN_72_GBE_TXD2__FUNC_GBE_TXD2 (MTK_PIN_NO(72) | 1) +#define MT2712_PIN_72_GBE_TXD2__FUNC_DBG_MON_B_1_ (MTK_PIN_NO(72) | 7) + +#define MT2712_PIN_73_GBE_TXD1__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define MT2712_PIN_73_GBE_TXD1__FUNC_GBE_TXD1 (MTK_PIN_NO(73) | 1) +#define MT2712_PIN_73_GBE_TXD1__FUNC_DBG_MON_B_2_ (MTK_PIN_NO(73) | 7) + +#define MT2712_PIN_74_GBE_TXD0__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define MT2712_PIN_74_GBE_TXD0__FUNC_GBE_TXD0 (MTK_PIN_NO(74) | 1) +#define MT2712_PIN_74_GBE_TXD0__FUNC_DBG_MON_B_3_ (MTK_PIN_NO(74) | 7) + +#define MT2712_PIN_75_GBE_TXC__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define MT2712_PIN_75_GBE_TXC__FUNC_GBE_TXC (MTK_PIN_NO(75) | 1) +#define MT2712_PIN_75_GBE_TXC__FUNC_DBG_MON_B_4_ (MTK_PIN_NO(75) | 7) + +#define MT2712_PIN_76_GBE_TXEN__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define MT2712_PIN_76_GBE_TXEN__FUNC_GBE_TXEN (MTK_PIN_NO(76) | 1) +#define MT2712_PIN_76_GBE_TXEN__FUNC_DBG_MON_B_5_ (MTK_PIN_NO(76) | 7) + +#define MT2712_PIN_77_GBE_TXER__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define MT2712_PIN_77_GBE_TXER__FUNC_GBE_TXER (MTK_PIN_NO(77) | 1) +#define MT2712_PIN_77_GBE_TXER__FUNC_DBG_MON_B_6_ (MTK_PIN_NO(77) | 7) + +#define MT2712_PIN_78_GBE_RXD3__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define MT2712_PIN_78_GBE_RXD3__FUNC_GBE_RXD3 (MTK_PIN_NO(78) | 1) +#define MT2712_PIN_78_GBE_RXD3__FUNC_DBG_MON_B_7_ (MTK_PIN_NO(78) | 7) + +#define MT2712_PIN_79_GBE_RXD2__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define MT2712_PIN_79_GBE_RXD2__FUNC_GBE_RXD2 (MTK_PIN_NO(79) | 1) +#define MT2712_PIN_79_GBE_RXD2__FUNC_DBG_MON_B_8_ (MTK_PIN_NO(79) | 7) + +#define MT2712_PIN_80_GBE_RXD1__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define MT2712_PIN_80_GBE_RXD1__FUNC_GBE_RXD1 (MTK_PIN_NO(80) | 1) +#define MT2712_PIN_80_GBE_RXD1__FUNC_DBG_MON_B_9_ (MTK_PIN_NO(80) | 7) + +#define MT2712_PIN_81_GBE_RXD0__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define MT2712_PIN_81_GBE_RXD0__FUNC_GBE_RXD0 (MTK_PIN_NO(81) | 1) +#define MT2712_PIN_81_GBE_RXD0__FUNC_DBG_MON_B_10_ (MTK_PIN_NO(81) | 7) + +#define MT2712_PIN_82_GBE_RXDV__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define MT2712_PIN_82_GBE_RXDV__FUNC_GBE_RXDV (MTK_PIN_NO(82) | 1) +#define MT2712_PIN_82_GBE_RXDV__FUNC_DBG_MON_B_11_ (MTK_PIN_NO(82) | 7) + +#define MT2712_PIN_83_GBE_RXER__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define MT2712_PIN_83_GBE_RXER__FUNC_GBE_RXER (MTK_PIN_NO(83) | 1) +#define MT2712_PIN_83_GBE_RXER__FUNC_DBG_MON_B_12_ (MTK_PIN_NO(83) | 7) + +#define MT2712_PIN_84_GBE_RXC__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define MT2712_PIN_84_GBE_RXC__FUNC_GBE_RXC (MTK_PIN_NO(84) | 1) +#define MT2712_PIN_84_GBE_RXC__FUNC_DBG_MON_B_13_ (MTK_PIN_NO(84) | 7) + +#define MT2712_PIN_85_GBE_MDC__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +#define MT2712_PIN_85_GBE_MDC__FUNC_GBE_MDC (MTK_PIN_NO(85) | 1) +#define MT2712_PIN_85_GBE_MDC__FUNC_DBG_MON_B_14_ (MTK_PIN_NO(85) | 7) + +#define MT2712_PIN_86_GBE_MDIO__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +#define MT2712_PIN_86_GBE_MDIO__FUNC_GBE_MDIO (MTK_PIN_NO(86) | 1) +#define MT2712_PIN_86_GBE_MDIO__FUNC_DBG_MON_B_15_ (MTK_PIN_NO(86) | 7) + +#define MT2712_PIN_87_GBE_COL__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +#define MT2712_PIN_87_GBE_COL__FUNC_GBE_COL (MTK_PIN_NO(87) | 1) +#define MT2712_PIN_87_GBE_COL__FUNC_DBG_MON_B_16_ (MTK_PIN_NO(87) | 7) + +#define MT2712_PIN_88_GBE_INTR__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +#define MT2712_PIN_88_GBE_INTR__FUNC_GBE_INTR (MTK_PIN_NO(88) | 1) +#define MT2712_PIN_88_GBE_INTR__FUNC_GBE_CRS (MTK_PIN_NO(88) | 2) +#define MT2712_PIN_88_GBE_INTR__FUNC_DBG_MON_B_17_ (MTK_PIN_NO(88) | 7) + +#define MT2712_PIN_89_MSDC2_CLK__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +#define MT2712_PIN_89_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(89) | 1) +#define MT2712_PIN_89_MSDC2_CLK__FUNC_DBG_MON_B_18_ (MTK_PIN_NO(89) | 7) + +#define MT2712_PIN_90_MSDC2_DAT3__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +#define MT2712_PIN_90_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(90) | 1) +#define MT2712_PIN_90_MSDC2_DAT3__FUNC_DBG_MON_B_19_ (MTK_PIN_NO(90) | 7) + +#define MT2712_PIN_91_MSDC2_DAT2__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define MT2712_PIN_91_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(91) | 1) +#define MT2712_PIN_91_MSDC2_DAT2__FUNC_DBG_MON_B_20_ (MTK_PIN_NO(91) | 7) + +#define MT2712_PIN_92_MSDC2_DAT1__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define MT2712_PIN_92_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(92) | 1) +#define MT2712_PIN_92_MSDC2_DAT1__FUNC_DBG_MON_B_21_ (MTK_PIN_NO(92) | 7) + +#define MT2712_PIN_93_MSDC2_DAT0__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define MT2712_PIN_93_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(93) | 1) +#define MT2712_PIN_93_MSDC2_DAT0__FUNC_DBG_MON_B_22_ (MTK_PIN_NO(93) | 7) + +#define MT2712_PIN_94_MSDC2_INS__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define MT2712_PIN_94_MSDC2_INS__FUNC_DBG_MON_B_23_ (MTK_PIN_NO(94) | 7) + +#define MT2712_PIN_95_MSDC2_CMD__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +#define MT2712_PIN_95_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(95) | 1) +#define MT2712_PIN_95_MSDC2_CMD__FUNC_DBG_MON_B_24_ (MTK_PIN_NO(95) | 7) + +#define MT2712_PIN_96_MSDC2_PSW__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +#define MT2712_PIN_96_MSDC2_PSW__FUNC_DBG_MON_B_25_ (MTK_PIN_NO(96) | 7) + +#define MT2712_PIN_97_URXD4__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +#define MT2712_PIN_97_URXD4__FUNC_URXD4 (MTK_PIN_NO(97) | 1) +#define MT2712_PIN_97_URXD4__FUNC_UTXD4 (MTK_PIN_NO(97) | 2) +#define MT2712_PIN_97_URXD4__FUNC_MRG_CLK (MTK_PIN_NO(97) | 3) +#define MT2712_PIN_97_URXD4__FUNC_PCM1_CLK (MTK_PIN_NO(97) | 4) +#define MT2712_PIN_97_URXD4__FUNC_I2S_IQ2_SDQB (MTK_PIN_NO(97) | 5) +#define MT2712_PIN_97_URXD4__FUNC_I2SO1_WS (MTK_PIN_NO(97) | 6) +#define MT2712_PIN_97_URXD4__FUNC_DBG_MON_B_26_ (MTK_PIN_NO(97) | 7) + +#define MT2712_PIN_98_URTS4__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +#define MT2712_PIN_98_URTS4__FUNC_URTS4 (MTK_PIN_NO(98) | 1) +#define MT2712_PIN_98_URTS4__FUNC_UCTS4 (MTK_PIN_NO(98) | 2) +#define MT2712_PIN_98_URTS4__FUNC_MRG_RX (MTK_PIN_NO(98) | 3) +#define MT2712_PIN_98_URTS4__FUNC_PCM1_DI (MTK_PIN_NO(98) | 4) +#define MT2712_PIN_98_URTS4__FUNC_I2S_IQ1_SDIB (MTK_PIN_NO(98) | 5) +#define MT2712_PIN_98_URTS4__FUNC_I2SO1_MCK (MTK_PIN_NO(98) | 6) +#define MT2712_PIN_98_URTS4__FUNC_DBG_MON_B_27_ (MTK_PIN_NO(98) | 7) + +#define MT2712_PIN_99_UTXD4__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +#define MT2712_PIN_99_UTXD4__FUNC_UTXD4 (MTK_PIN_NO(99) | 1) +#define MT2712_PIN_99_UTXD4__FUNC_URXD4 (MTK_PIN_NO(99) | 2) +#define MT2712_PIN_99_UTXD4__FUNC_MRG_SYNC (MTK_PIN_NO(99) | 3) +#define MT2712_PIN_99_UTXD4__FUNC_PCM1_SYNC (MTK_PIN_NO(99) | 4) +#define MT2712_PIN_99_UTXD4__FUNC_I2S_IQ0_SDQB (MTK_PIN_NO(99) | 5) +#define MT2712_PIN_99_UTXD4__FUNC_I2SO1_BCK (MTK_PIN_NO(99) | 6) +#define MT2712_PIN_99_UTXD4__FUNC_DBG_MON_B_28_ (MTK_PIN_NO(99) | 7) + +#define MT2712_PIN_100_UCTS4__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define MT2712_PIN_100_UCTS4__FUNC_UCTS4 (MTK_PIN_NO(100) | 1) +#define MT2712_PIN_100_UCTS4__FUNC_URTS4 (MTK_PIN_NO(100) | 2) +#define MT2712_PIN_100_UCTS4__FUNC_MRG_TX (MTK_PIN_NO(100) | 3) +#define MT2712_PIN_100_UCTS4__FUNC_PCM1_DO (MTK_PIN_NO(100) | 4) +#define MT2712_PIN_100_UCTS4__FUNC_I2S_IQ0_SDIB (MTK_PIN_NO(100) | 5) +#define MT2712_PIN_100_UCTS4__FUNC_I2SO1_DO (MTK_PIN_NO(100) | 6) +#define MT2712_PIN_100_UCTS4__FUNC_DBG_MON_B_29_ (MTK_PIN_NO(100) | 7) + +#define MT2712_PIN_101_URXD5__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define MT2712_PIN_101_URXD5__FUNC_URXD5 (MTK_PIN_NO(101) | 1) +#define MT2712_PIN_101_URXD5__FUNC_UTXD5 (MTK_PIN_NO(101) | 2) +#define MT2712_PIN_101_URXD5__FUNC_I2SO3_WS (MTK_PIN_NO(101) | 3) +#define MT2712_PIN_101_URXD5__FUNC_TDMIN_LRCK (MTK_PIN_NO(101) | 4) +#define MT2712_PIN_101_URXD5__FUNC_I2SO0_WS (MTK_PIN_NO(101) | 6) +#define MT2712_PIN_101_URXD5__FUNC_DBG_MON_B_30_ (MTK_PIN_NO(101) | 7) + +#define MT2712_PIN_102_URTS5__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define MT2712_PIN_102_URTS5__FUNC_URTS5 (MTK_PIN_NO(102) | 1) +#define MT2712_PIN_102_URTS5__FUNC_UCTS5 (MTK_PIN_NO(102) | 2) +#define MT2712_PIN_102_URTS5__FUNC_I2SO3_MCK (MTK_PIN_NO(102) | 3) +#define MT2712_PIN_102_URTS5__FUNC_TDMIN_MCLK (MTK_PIN_NO(102) | 4) +#define MT2712_PIN_102_URTS5__FUNC_IR_IN (MTK_PIN_NO(102) | 5) +#define MT2712_PIN_102_URTS5__FUNC_I2SO0_MCK (MTK_PIN_NO(102) | 6) +#define MT2712_PIN_102_URTS5__FUNC_DBG_MON_B_31_ (MTK_PIN_NO(102) | 7) + +#define MT2712_PIN_103_UTXD5__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define MT2712_PIN_103_UTXD5__FUNC_UTXD5 (MTK_PIN_NO(103) | 1) +#define MT2712_PIN_103_UTXD5__FUNC_URXD5 (MTK_PIN_NO(103) | 2) +#define MT2712_PIN_103_UTXD5__FUNC_I2SO3_BCK (MTK_PIN_NO(103) | 3) +#define MT2712_PIN_103_UTXD5__FUNC_TDMIN_BCK (MTK_PIN_NO(103) | 4) +#define MT2712_PIN_103_UTXD5__FUNC_I2SO0_BCK (MTK_PIN_NO(103) | 6) +#define MT2712_PIN_103_UTXD5__FUNC_DBG_MON_B_32_ (MTK_PIN_NO(103) | 7) + +#define MT2712_PIN_104_UCTS5__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define MT2712_PIN_104_UCTS5__FUNC_UCTS5 (MTK_PIN_NO(104) | 1) +#define MT2712_PIN_104_UCTS5__FUNC_URTS5 (MTK_PIN_NO(104) | 2) +#define MT2712_PIN_104_UCTS5__FUNC_I2SO0_DO1 (MTK_PIN_NO(104) | 3) +#define MT2712_PIN_104_UCTS5__FUNC_TDMIN_DI (MTK_PIN_NO(104) | 4) +#define MT2712_PIN_104_UCTS5__FUNC_IR_IN (MTK_PIN_NO(104) | 5) +#define MT2712_PIN_104_UCTS5__FUNC_I2SO0_DO0 (MTK_PIN_NO(104) | 6) + +#define MT2712_PIN_105_I2C_SDA0__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define MT2712_PIN_105_I2C_SDA0__FUNC_SDA0 (MTK_PIN_NO(105) | 1) + +#define MT2712_PIN_106_I2C_SDA1__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define MT2712_PIN_106_I2C_SDA1__FUNC_SDA1 (MTK_PIN_NO(106) | 1) + +#define MT2712_PIN_107_I2C_SDA2__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define MT2712_PIN_107_I2C_SDA2__FUNC_SDA2 (MTK_PIN_NO(107) | 1) + +#define MT2712_PIN_108_I2C_SDA3__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define MT2712_PIN_108_I2C_SDA3__FUNC_SDA3 (MTK_PIN_NO(108) | 1) + +#define MT2712_PIN_109_I2C_SDA4__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define MT2712_PIN_109_I2C_SDA4__FUNC_SDA4 (MTK_PIN_NO(109) | 1) + +#define MT2712_PIN_110_I2C_SDA5__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define MT2712_PIN_110_I2C_SDA5__FUNC_SDA5 (MTK_PIN_NO(110) | 1) + +#define MT2712_PIN_111_I2C_SCL0__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define MT2712_PIN_111_I2C_SCL0__FUNC_SCL0 (MTK_PIN_NO(111) | 1) + +#define MT2712_PIN_112_I2C_SCL1__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define MT2712_PIN_112_I2C_SCL1__FUNC_SCL1 (MTK_PIN_NO(112) | 1) + +#define MT2712_PIN_113_I2C_SCL2__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define MT2712_PIN_113_I2C_SCL2__FUNC_SCL2 (MTK_PIN_NO(113) | 1) + +#define MT2712_PIN_114_I2C_SCL3__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define MT2712_PIN_114_I2C_SCL3__FUNC_SCL3 (MTK_PIN_NO(114) | 1) + +#define MT2712_PIN_115_I2C_SCL4__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define MT2712_PIN_115_I2C_SCL4__FUNC_SCL4 (MTK_PIN_NO(115) | 1) + +#define MT2712_PIN_116_I2C_SCL5__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define MT2712_PIN_116_I2C_SCL5__FUNC_SCL5 (MTK_PIN_NO(116) | 1) + +#define MT2712_PIN_117_URXD0__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define MT2712_PIN_117_URXD0__FUNC_URXD0 (MTK_PIN_NO(117) | 1) +#define MT2712_PIN_117_URXD0__FUNC_UTXD0 (MTK_PIN_NO(117) | 2) + +#define MT2712_PIN_118_URXD1__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define MT2712_PIN_118_URXD1__FUNC_URXD1 (MTK_PIN_NO(118) | 1) +#define MT2712_PIN_118_URXD1__FUNC_UTXD1 (MTK_PIN_NO(118) | 2) + +#define MT2712_PIN_119_URXD2__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define MT2712_PIN_119_URXD2__FUNC_URXD2 (MTK_PIN_NO(119) | 1) +#define MT2712_PIN_119_URXD2__FUNC_UTXD2 (MTK_PIN_NO(119) | 2) + +#define MT2712_PIN_120_UTXD0__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define MT2712_PIN_120_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(120) | 1) +#define MT2712_PIN_120_UTXD0__FUNC_URXD0 (MTK_PIN_NO(120) | 2) + +#define MT2712_PIN_121_UTXD1__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define MT2712_PIN_121_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(121) | 1) +#define MT2712_PIN_121_UTXD1__FUNC_URXD1 (MTK_PIN_NO(121) | 2) + +#define MT2712_PIN_122_UTXD2__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define MT2712_PIN_122_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(122) | 1) +#define MT2712_PIN_122_UTXD2__FUNC_URXD2 (MTK_PIN_NO(122) | 2) + +#define MT2712_PIN_123_URXD3__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define MT2712_PIN_123_URXD3__FUNC_URXD3 (MTK_PIN_NO(123) | 1) +#define MT2712_PIN_123_URXD3__FUNC_UTXD3 (MTK_PIN_NO(123) | 2) +#define MT2712_PIN_123_URXD3__FUNC_PURE_HW_PROTECT (MTK_PIN_NO(123) | 3) + +#define MT2712_PIN_124_UTXD3__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define MT2712_PIN_124_UTXD3__FUNC_UTXD3 (MTK_PIN_NO(124) | 1) +#define MT2712_PIN_124_UTXD3__FUNC_URXD3 (MTK_PIN_NO(124) | 2) +#define MT2712_PIN_124_UTXD3__FUNC_PURE_HW_PROTECT (MTK_PIN_NO(124) | 3) + +#define MT2712_PIN_125_URTS3__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +#define MT2712_PIN_125_URTS3__FUNC_URTS3 (MTK_PIN_NO(125) | 1) +#define MT2712_PIN_125_URTS3__FUNC_UCTS3 (MTK_PIN_NO(125) | 2) +#define MT2712_PIN_125_URTS3__FUNC_WATCH_DOG (MTK_PIN_NO(125) | 3) + +#define MT2712_PIN_126_UCTS3__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define MT2712_PIN_126_UCTS3__FUNC_UCTS3 (MTK_PIN_NO(126) | 1) +#define MT2712_PIN_126_UCTS3__FUNC_URTS3 (MTK_PIN_NO(126) | 2) +#define MT2712_PIN_126_UCTS3__FUNC_SRCLKENA0 (MTK_PIN_NO(126) | 3) + +#define MT2712_PIN_127_SPI2_CSN__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +#define MT2712_PIN_127_SPI2_CSN__FUNC_SPI_CS_2_ (MTK_PIN_NO(127) | 1) +#define MT2712_PIN_127_SPI2_CSN__FUNC_SPI_CS_1_ (MTK_PIN_NO(127) | 2) + +#define MT2712_PIN_128_SPI2_MO__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +#define MT2712_PIN_128_SPI2_MO__FUNC_SPI_MO_2_ (MTK_PIN_NO(128) | 1) +#define MT2712_PIN_128_SPI2_MO__FUNC_SPI_SO_1_ (MTK_PIN_NO(128) | 2) + +#define MT2712_PIN_129_SPI2_MI__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +#define MT2712_PIN_129_SPI2_MI__FUNC_SPI_MI_2_ (MTK_PIN_NO(129) | 1) +#define MT2712_PIN_129_SPI2_MI__FUNC_SPI_SI_1_ (MTK_PIN_NO(129) | 2) + +#define MT2712_PIN_130_SPI2_CK__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +#define MT2712_PIN_130_SPI2_CK__FUNC_SPI_CK_2_ (MTK_PIN_NO(130) | 1) +#define MT2712_PIN_130_SPI2_CK__FUNC_SPI_CK_1_ (MTK_PIN_NO(130) | 2) + +#define MT2712_PIN_131_SPI3_CSN__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +#define MT2712_PIN_131_SPI3_CSN__FUNC_SPI_CS_3_ (MTK_PIN_NO(131) | 1) + +#define MT2712_PIN_132_SPI3_MO__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +#define MT2712_PIN_132_SPI3_MO__FUNC_SPI_MO_3_ (MTK_PIN_NO(132) | 1) + +#define MT2712_PIN_133_SPI3_MI__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +#define MT2712_PIN_133_SPI3_MI__FUNC_SPI_MI_3_ (MTK_PIN_NO(133) | 1) + +#define MT2712_PIN_134_SPI3_CK__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +#define MT2712_PIN_134_SPI3_CK__FUNC_SPI_CK_3_ (MTK_PIN_NO(134) | 1) + +#define MT2712_PIN_135_KPROW3__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +#define MT2712_PIN_135_KPROW3__FUNC_KROW3 (MTK_PIN_NO(135) | 1) +#define MT2712_PIN_135_KPROW3__FUNC_DSIC_TE (MTK_PIN_NO(135) | 2) + +#define MT2712_PIN_136_KPROW4__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +#define MT2712_PIN_136_KPROW4__FUNC_KROW4 (MTK_PIN_NO(136) | 1) +#define MT2712_PIN_136_KPROW4__FUNC_DSID_TE (MTK_PIN_NO(136) | 2) + +#define MT2712_PIN_137_KPCOL3__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +#define MT2712_PIN_137_KPCOL3__FUNC_KCOL3 (MTK_PIN_NO(137) | 1) +#define MT2712_PIN_137_KPCOL3__FUNC_DISP2_PWM (MTK_PIN_NO(137) | 2) + +#define MT2712_PIN_138_KPCOL4__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +#define MT2712_PIN_138_KPCOL4__FUNC_KCOL4 (MTK_PIN_NO(138) | 1) +#define MT2712_PIN_138_KPCOL4__FUNC_LCM_RST2 (MTK_PIN_NO(138) | 2) + +#define MT2712_PIN_139_KPCOL5__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +#define MT2712_PIN_139_KPCOL5__FUNC_KCOL5 (MTK_PIN_NO(139) | 1) +#define MT2712_PIN_139_KPCOL5__FUNC_DSIA_TE (MTK_PIN_NO(139) | 3) +#define MT2712_PIN_139_KPCOL5__FUNC_PURE_HW_PROTECT (MTK_PIN_NO(139) | 4) + +#define MT2712_PIN_140_KPCOL6__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +#define MT2712_PIN_140_KPCOL6__FUNC_KCOL6 (MTK_PIN_NO(140) | 1) +#define MT2712_PIN_140_KPCOL6__FUNC_WATCH_DOG (MTK_PIN_NO(140) | 2) +#define MT2712_PIN_140_KPCOL6__FUNC_LCM_RST1 (MTK_PIN_NO(140) | 3) + +#define MT2712_PIN_141_KPROW5__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +#define MT2712_PIN_141_KPROW5__FUNC_KROW5 (MTK_PIN_NO(141) | 1) +#define MT2712_PIN_141_KPROW5__FUNC_LCM_RST0 (MTK_PIN_NO(141) | 3) +#define MT2712_PIN_141_KPROW5__FUNC_PURE_HW_PROTECT (MTK_PIN_NO(141) | 4) + +#define MT2712_PIN_142_KPROW6__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +#define MT2712_PIN_142_KPROW6__FUNC_KROW6 (MTK_PIN_NO(142) | 1) +#define MT2712_PIN_142_KPROW6__FUNC_SRCLKENA0 (MTK_PIN_NO(142) | 2) +#define MT2712_PIN_142_KPROW6__FUNC_DSIB_TE (MTK_PIN_NO(142) | 3) + +#define MT2712_PIN_143_JTDO_ICE__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +#define MT2712_PIN_143_JTDO_ICE__FUNC_JTDO_ICE (MTK_PIN_NO(143) | 1) +#define MT2712_PIN_143_JTDO_ICE__FUNC_DFD_TDO (MTK_PIN_NO(143) | 3) + +#define MT2712_PIN_144_JTCK_ICE__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +#define MT2712_PIN_144_JTCK_ICE__FUNC_JTCK_ICE (MTK_PIN_NO(144) | 1) +#define MT2712_PIN_144_JTCK_ICE__FUNC_DFD_TCK (MTK_PIN_NO(144) | 3) + +#define MT2712_PIN_145_JTDI_ICE__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) +#define MT2712_PIN_145_JTDI_ICE__FUNC_JTDI_ICE (MTK_PIN_NO(145) | 1) +#define MT2712_PIN_145_JTDI_ICE__FUNC_DFD_TDI (MTK_PIN_NO(145) | 3) + +#define MT2712_PIN_146_JTMS_ICE__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) +#define MT2712_PIN_146_JTMS_ICE__FUNC_JTMS_ICE (MTK_PIN_NO(146) | 1) +#define MT2712_PIN_146_JTMS_ICE__FUNC_DFD_TMS (MTK_PIN_NO(146) | 3) + +#define MT2712_PIN_147_JTRSTB_ICE__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) +#define MT2712_PIN_147_JTRSTB_ICE__FUNC_JTRST_B_ICE (MTK_PIN_NO(147) | 1) +#define MT2712_PIN_147_JTRSTB_ICE__FUNC_DFD_NTRST (MTK_PIN_NO(147) | 3) + +#define MT2712_PIN_148_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) +#define MT2712_PIN_148_GPIO148__FUNC_JTRSTB_CM4 (MTK_PIN_NO(148) | 1) +#define MT2712_PIN_148_GPIO148__FUNC_DFD_NTRST (MTK_PIN_NO(148) | 3) + +#define MT2712_PIN_149_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) +#define MT2712_PIN_149_GPIO149__FUNC_JTCK_CM4 (MTK_PIN_NO(149) | 1) +#define MT2712_PIN_149_GPIO149__FUNC_DFD_TCK (MTK_PIN_NO(149) | 3) + +#define MT2712_PIN_150_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) +#define MT2712_PIN_150_GPIO150__FUNC_JTMS_CM4 (MTK_PIN_NO(150) | 1) +#define MT2712_PIN_150_GPIO150__FUNC_DFD_TMS (MTK_PIN_NO(150) | 3) + +#define MT2712_PIN_151_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) +#define MT2712_PIN_151_GPIO151__FUNC_JTDI_CM4 (MTK_PIN_NO(151) | 1) +#define MT2712_PIN_151_GPIO151__FUNC_DFD_TDI (MTK_PIN_NO(151) | 3) + +#define MT2712_PIN_152_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) +#define MT2712_PIN_152_GPIO152__FUNC_JTDO_CM4 (MTK_PIN_NO(152) | 1) +#define MT2712_PIN_152_GPIO152__FUNC_DFD_TDO (MTK_PIN_NO(152) | 3) + +#define MT2712_PIN_153_SPI0_CSN__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) +#define MT2712_PIN_153_SPI0_CSN__FUNC_SPI_CS_0_ (MTK_PIN_NO(153) | 1) +#define MT2712_PIN_153_SPI0_CSN__FUNC_SRCLKENA0 (MTK_PIN_NO(153) | 2) +#define MT2712_PIN_153_SPI0_CSN__FUNC_UTXD0 (MTK_PIN_NO(153) | 3) +#define MT2712_PIN_153_SPI0_CSN__FUNC_I2SO0_DO1 (MTK_PIN_NO(153) | 4) +#define MT2712_PIN_153_SPI0_CSN__FUNC_TDMO0_DATA1 (MTK_PIN_NO(153) | 6) +#define MT2712_PIN_153_SPI0_CSN__FUNC_I2S_IQ2_SDQB (MTK_PIN_NO(153) | 7) + +#define MT2712_PIN_154_SPI0_MI__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) +#define MT2712_PIN_154_SPI0_MI__FUNC_SPI_MI_0_ (MTK_PIN_NO(154) | 1) +#define MT2712_PIN_154_SPI0_MI__FUNC_SRCLKENA0 (MTK_PIN_NO(154) | 2) +#define MT2712_PIN_154_SPI0_MI__FUNC_URXD0 (MTK_PIN_NO(154) | 3) +#define MT2712_PIN_154_SPI0_MI__FUNC_I2SO0_DO0 (MTK_PIN_NO(154) | 4) +#define MT2712_PIN_154_SPI0_MI__FUNC_I2SO1_DO (MTK_PIN_NO(154) | 5) +#define MT2712_PIN_154_SPI0_MI__FUNC_TDMO0_DATA (MTK_PIN_NO(154) | 6) +#define MT2712_PIN_154_SPI0_MI__FUNC_I2S_IQ1_SDIB (MTK_PIN_NO(154) | 7) + +#define MT2712_PIN_155_SPI0_CK__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) +#define MT2712_PIN_155_SPI0_CK__FUNC_SPI_CK_0_ (MTK_PIN_NO(155) | 1) +#define MT2712_PIN_155_SPI0_CK__FUNC_SC_APBIAS_OFF (MTK_PIN_NO(155) | 2) +#define MT2712_PIN_155_SPI0_CK__FUNC_UTXD1 (MTK_PIN_NO(155) | 3) +#define MT2712_PIN_155_SPI0_CK__FUNC_I2SO0_BCK (MTK_PIN_NO(155) | 4) +#define MT2712_PIN_155_SPI0_CK__FUNC_I2SO1_BCK (MTK_PIN_NO(155) | 5) +#define MT2712_PIN_155_SPI0_CK__FUNC_TDMO0_BCK (MTK_PIN_NO(155) | 6) +#define MT2712_PIN_155_SPI0_CK__FUNC_I2S_IQ0_SDQB (MTK_PIN_NO(155) | 7) + +#define MT2712_PIN_156_SPI0_MO__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) +#define MT2712_PIN_156_SPI0_MO__FUNC_SPI_MO_0_ (MTK_PIN_NO(156) | 1) +#define MT2712_PIN_156_SPI0_MO__FUNC_SC_APBIAS_OFF (MTK_PIN_NO(156) | 2) +#define MT2712_PIN_156_SPI0_MO__FUNC_URXD1 (MTK_PIN_NO(156) | 3) +#define MT2712_PIN_156_SPI0_MO__FUNC_I2SO0_WS (MTK_PIN_NO(156) | 4) +#define MT2712_PIN_156_SPI0_MO__FUNC_I2SO1_WS (MTK_PIN_NO(156) | 5) +#define MT2712_PIN_156_SPI0_MO__FUNC_TDMO0_LRCK (MTK_PIN_NO(156) | 6) +#define MT2712_PIN_156_SPI0_MO__FUNC_I2S_IQ0_SDIB (MTK_PIN_NO(156) | 7) + +#define MT2712_PIN_157_SPI5_CSN__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) +#define MT2712_PIN_157_SPI5_CSN__FUNC_SPI_CS_5_ (MTK_PIN_NO(157) | 1) +#define MT2712_PIN_157_SPI5_CSN__FUNC_LCM_RST0 (MTK_PIN_NO(157) | 2) +#define MT2712_PIN_157_SPI5_CSN__FUNC_UTXD2 (MTK_PIN_NO(157) | 3) +#define MT2712_PIN_157_SPI5_CSN__FUNC_I2SO0_MCK (MTK_PIN_NO(157) | 4) +#define MT2712_PIN_157_SPI5_CSN__FUNC_I2SO1_MCK (MTK_PIN_NO(157) | 5) +#define MT2712_PIN_157_SPI5_CSN__FUNC_TDMO0_MCLK (MTK_PIN_NO(157) | 6) + +#define MT2712_PIN_158_SPI5_MI__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) +#define MT2712_PIN_158_SPI5_MI__FUNC_SPI_MI_5_ (MTK_PIN_NO(158) | 1) +#define MT2712_PIN_158_SPI5_MI__FUNC_DSIA_TE (MTK_PIN_NO(158) | 2) +#define MT2712_PIN_158_SPI5_MI__FUNC_URXD2 (MTK_PIN_NO(158) | 3) + +#define MT2712_PIN_159_SPI5_MO__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) +#define MT2712_PIN_159_SPI5_MO__FUNC_SPI_MO_5_ (MTK_PIN_NO(159) | 1) +#define MT2712_PIN_159_SPI5_MO__FUNC_DSIB_TE (MTK_PIN_NO(159) | 2) +#define MT2712_PIN_159_SPI5_MO__FUNC_UTXD3 (MTK_PIN_NO(159) | 3) + +#define MT2712_PIN_160_SPI5_CK__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) +#define MT2712_PIN_160_SPI5_CK__FUNC_SPI_CK_5_ (MTK_PIN_NO(160) | 1) +#define MT2712_PIN_160_SPI5_CK__FUNC_LCM_RST1 (MTK_PIN_NO(160) | 2) +#define MT2712_PIN_160_SPI5_CK__FUNC_URXD3 (MTK_PIN_NO(160) | 3) + +#define MT2712_PIN_161_SPI1_CSN__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) +#define MT2712_PIN_161_SPI1_CSN__FUNC_SPI_CS_1_ (MTK_PIN_NO(161) | 1) +#define MT2712_PIN_161_SPI1_CSN__FUNC_SPI_CS_4_ (MTK_PIN_NO(161) | 2) +#define MT2712_PIN_161_SPI1_CSN__FUNC_I2S_IQ2_SDQB (MTK_PIN_NO(161) | 4) +#define MT2712_PIN_161_SPI1_CSN__FUNC_I2SO2_DO (MTK_PIN_NO(161) | 5) +#define MT2712_PIN_161_SPI1_CSN__FUNC_TDMO0_DATA1 (MTK_PIN_NO(161) | 6) +#define MT2712_PIN_161_SPI1_CSN__FUNC_I2SO0_DO1 (MTK_PIN_NO(161) | 7) + +#define MT2712_PIN_162_SPI1_SI__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) +#define MT2712_PIN_162_SPI1_SI__FUNC_SPI_SI_1_ (MTK_PIN_NO(162) | 1) +#define MT2712_PIN_162_SPI1_SI__FUNC_SPI_MI_4_ (MTK_PIN_NO(162) | 2) +#define MT2712_PIN_162_SPI1_SI__FUNC_I2S_IQ1_SDIB (MTK_PIN_NO(162) | 4) +#define MT2712_PIN_162_SPI1_SI__FUNC_I2SO2_BCK (MTK_PIN_NO(162) | 5) +#define MT2712_PIN_162_SPI1_SI__FUNC_TDMO0_DATA (MTK_PIN_NO(162) | 6) +#define MT2712_PIN_162_SPI1_SI__FUNC_I2SO0_DO0 (MTK_PIN_NO(162) | 7) + +#define MT2712_PIN_163_SPI1_CK__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) +#define MT2712_PIN_163_SPI1_CK__FUNC_SPI_CK_1_ (MTK_PIN_NO(163) | 1) +#define MT2712_PIN_163_SPI1_CK__FUNC_SPI_CK_4_ (MTK_PIN_NO(163) | 2) +#define MT2712_PIN_163_SPI1_CK__FUNC_I2S_IQ0_SDQB (MTK_PIN_NO(163) | 4) +#define MT2712_PIN_163_SPI1_CK__FUNC_I2SO2_WS (MTK_PIN_NO(163) | 5) +#define MT2712_PIN_163_SPI1_CK__FUNC_TDMO0_BCK (MTK_PIN_NO(163) | 6) +#define MT2712_PIN_163_SPI1_CK__FUNC_I2SO0_BCK (MTK_PIN_NO(163) | 7) + +#define MT2712_PIN_164_SPI1_SO__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) +#define MT2712_PIN_164_SPI1_SO__FUNC_SPI_SO_1_ (MTK_PIN_NO(164) | 1) +#define MT2712_PIN_164_SPI1_SO__FUNC_SPI_MO_4_ (MTK_PIN_NO(164) | 2) +#define MT2712_PIN_164_SPI1_SO__FUNC_I2S_IQ0_SDIB (MTK_PIN_NO(164) | 4) +#define MT2712_PIN_164_SPI1_SO__FUNC_I2SO2_MCK (MTK_PIN_NO(164) | 5) +#define MT2712_PIN_164_SPI1_SO__FUNC_TDMO0_LRCK (MTK_PIN_NO(164) | 6) +#define MT2712_PIN_164_SPI1_SO__FUNC_I2SO0_WS (MTK_PIN_NO(164) | 7) + +#define MT2712_PIN_165_SPI4_CSN__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) +#define MT2712_PIN_165_SPI4_CSN__FUNC_SPI_CS_4_ (MTK_PIN_NO(165) | 1) +#define MT2712_PIN_165_SPI4_CSN__FUNC_LCM_RST0 (MTK_PIN_NO(165) | 2) +#define MT2712_PIN_165_SPI4_CSN__FUNC_SPI_CS_1_ (MTK_PIN_NO(165) | 3) +#define MT2712_PIN_165_SPI4_CSN__FUNC_UTXD4 (MTK_PIN_NO(165) | 4) +#define MT2712_PIN_165_SPI4_CSN__FUNC_I2SO1_DO (MTK_PIN_NO(165) | 5) +#define MT2712_PIN_165_SPI4_CSN__FUNC_TDMO0_MCLK (MTK_PIN_NO(165) | 6) +#define MT2712_PIN_165_SPI4_CSN__FUNC_I2SO0_MCK (MTK_PIN_NO(165) | 7) + +#define MT2712_PIN_166_SPI4_MI__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) +#define MT2712_PIN_166_SPI4_MI__FUNC_SPI_MI_4_ (MTK_PIN_NO(166) | 1) +#define MT2712_PIN_166_SPI4_MI__FUNC_DSIA_TE (MTK_PIN_NO(166) | 2) +#define MT2712_PIN_166_SPI4_MI__FUNC_SPI_SI_1_ (MTK_PIN_NO(166) | 3) +#define MT2712_PIN_166_SPI4_MI__FUNC_URXD4 (MTK_PIN_NO(166) | 4) +#define MT2712_PIN_166_SPI4_MI__FUNC_I2SO1_BCK (MTK_PIN_NO(166) | 5) + +#define MT2712_PIN_167_SPI4_MO__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) +#define MT2712_PIN_167_SPI4_MO__FUNC_SPI_MO_4_ (MTK_PIN_NO(167) | 1) +#define MT2712_PIN_167_SPI4_MO__FUNC_DSIB_TE (MTK_PIN_NO(167) | 2) +#define MT2712_PIN_167_SPI4_MO__FUNC_SPI_SO_1_ (MTK_PIN_NO(167) | 3) +#define MT2712_PIN_167_SPI4_MO__FUNC_UTXD5 (MTK_PIN_NO(167) | 4) +#define MT2712_PIN_167_SPI4_MO__FUNC_I2SO1_WS (MTK_PIN_NO(167) | 5) + +#define MT2712_PIN_168_SPI4_CK__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) +#define MT2712_PIN_168_SPI4_CK__FUNC_SPI_CK_4_ (MTK_PIN_NO(168) | 1) +#define MT2712_PIN_168_SPI4_CK__FUNC_LCM_RST1 (MTK_PIN_NO(168) | 2) +#define MT2712_PIN_168_SPI4_CK__FUNC_SPI_CK_1_ (MTK_PIN_NO(168) | 3) +#define MT2712_PIN_168_SPI4_CK__FUNC_URXD5 (MTK_PIN_NO(168) | 4) +#define MT2712_PIN_168_SPI4_CK__FUNC_I2SO1_MCK (MTK_PIN_NO(168) | 5) + +#define MT2712_PIN_169_I2SI0_DATA__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) +#define MT2712_PIN_169_I2SI0_DATA__FUNC_I2SI0_DI (MTK_PIN_NO(169) | 1) +#define MT2712_PIN_169_I2SI0_DATA__FUNC_I2SI1_DI (MTK_PIN_NO(169) | 2) +#define MT2712_PIN_169_I2SI0_DATA__FUNC_I2SI2_DI (MTK_PIN_NO(169) | 3) +#define MT2712_PIN_169_I2SI0_DATA__FUNC_TDMIN_DI (MTK_PIN_NO(169) | 4) + +#define MT2712_PIN_170_I2SI0_LRCK__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) +#define MT2712_PIN_170_I2SI0_LRCK__FUNC_I2SI0_WS (MTK_PIN_NO(170) | 1) +#define MT2712_PIN_170_I2SI0_LRCK__FUNC_I2SI1_WS (MTK_PIN_NO(170) | 2) +#define MT2712_PIN_170_I2SI0_LRCK__FUNC_I2SI2_WS (MTK_PIN_NO(170) | 3) +#define MT2712_PIN_170_I2SI0_LRCK__FUNC_TDMIN_LRCK (MTK_PIN_NO(170) | 4) +#define MT2712_PIN_170_I2SI0_LRCK__FUNC_TDMO0_DATA3 (MTK_PIN_NO(170) | 5) +#define MT2712_PIN_170_I2SI0_LRCK__FUNC_TDMO1_DATA3 (MTK_PIN_NO(170) | 6) + +#define MT2712_PIN_171_I2SI0_MCLK__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) +#define MT2712_PIN_171_I2SI0_MCLK__FUNC_I2SI0_MCK (MTK_PIN_NO(171) | 1) +#define MT2712_PIN_171_I2SI0_MCLK__FUNC_I2SI1_MCK (MTK_PIN_NO(171) | 2) +#define MT2712_PIN_171_I2SI0_MCLK__FUNC_I2SI2_MCK (MTK_PIN_NO(171) | 3) +#define MT2712_PIN_171_I2SI0_MCLK__FUNC_TDMIN_MCLK (MTK_PIN_NO(171) | 4) +#define MT2712_PIN_171_I2SI0_MCLK__FUNC_TDMO0_DATA2 (MTK_PIN_NO(171) | 5) +#define MT2712_PIN_171_I2SI0_MCLK__FUNC_TDMO1_DATA2 (MTK_PIN_NO(171) | 6) + +#define MT2712_PIN_172_I2SI0_BCK__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) +#define MT2712_PIN_172_I2SI0_BCK__FUNC_I2SI0_BCK (MTK_PIN_NO(172) | 1) +#define MT2712_PIN_172_I2SI0_BCK__FUNC_I2SI1_BCK (MTK_PIN_NO(172) | 2) +#define MT2712_PIN_172_I2SI0_BCK__FUNC_I2SI2_BCK (MTK_PIN_NO(172) | 3) +#define MT2712_PIN_172_I2SI0_BCK__FUNC_TDMIN_BCK (MTK_PIN_NO(172) | 4) +#define MT2712_PIN_172_I2SI0_BCK__FUNC_TDMO0_DATA1 (MTK_PIN_NO(172) | 5) +#define MT2712_PIN_172_I2SI0_BCK__FUNC_TDMO1_DATA1 (MTK_PIN_NO(172) | 6) + +#define MT2712_PIN_173_I2SI2_DATA__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) +#define MT2712_PIN_173_I2SI2_DATA__FUNC_I2SI2_DI (MTK_PIN_NO(173) | 1) +#define MT2712_PIN_173_I2SI2_DATA__FUNC_I2SI0_DI (MTK_PIN_NO(173) | 2) +#define MT2712_PIN_173_I2SI2_DATA__FUNC_I2SI1_DI (MTK_PIN_NO(173) | 3) +#define MT2712_PIN_173_I2SI2_DATA__FUNC_PCM1_DI (MTK_PIN_NO(173) | 4) +#define MT2712_PIN_173_I2SI2_DATA__FUNC_TDMIN_DI (MTK_PIN_NO(173) | 5) +#define MT2712_PIN_173_I2SI2_DATA__FUNC_PCM1_DO (MTK_PIN_NO(173) | 6) + +#define MT2712_PIN_174_I2SI2_MCLK__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) +#define MT2712_PIN_174_I2SI2_MCLK__FUNC_I2SI2_MCK (MTK_PIN_NO(174) | 1) +#define MT2712_PIN_174_I2SI2_MCLK__FUNC_I2SI0_MCK (MTK_PIN_NO(174) | 2) +#define MT2712_PIN_174_I2SI2_MCLK__FUNC_I2SI1_MCK (MTK_PIN_NO(174) | 3) +#define MT2712_PIN_174_I2SI2_MCLK__FUNC_PCM1_DO (MTK_PIN_NO(174) | 4) +#define MT2712_PIN_174_I2SI2_MCLK__FUNC_TDMIN_MCLK (MTK_PIN_NO(174) | 5) +#define MT2712_PIN_174_I2SI2_MCLK__FUNC_PCM1_DI (MTK_PIN_NO(174) | 6) +#define MT2712_PIN_174_I2SI2_MCLK__FUNC_I2S_IQ2_SDQB (MTK_PIN_NO(174) | 7) + +#define MT2712_PIN_175_I2SI2_BCK__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) +#define MT2712_PIN_175_I2SI2_BCK__FUNC_I2SI2_BCK (MTK_PIN_NO(175) | 1) +#define MT2712_PIN_175_I2SI2_BCK__FUNC_I2SI0_BCK (MTK_PIN_NO(175) | 2) +#define MT2712_PIN_175_I2SI2_BCK__FUNC_I2SI1_BCK (MTK_PIN_NO(175) | 3) +#define MT2712_PIN_175_I2SI2_BCK__FUNC_PCM1_CLK (MTK_PIN_NO(175) | 4) +#define MT2712_PIN_175_I2SI2_BCK__FUNC_TDMIN_BCK (MTK_PIN_NO(175) | 5) + +#define MT2712_PIN_176_I2SI2_LRCK__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) +#define MT2712_PIN_176_I2SI2_LRCK__FUNC_I2SI2_WS (MTK_PIN_NO(176) | 1) +#define MT2712_PIN_176_I2SI2_LRCK__FUNC_I2SI0_WS (MTK_PIN_NO(176) | 2) +#define MT2712_PIN_176_I2SI2_LRCK__FUNC_I2SI1_WS (MTK_PIN_NO(176) | 3) +#define MT2712_PIN_176_I2SI2_LRCK__FUNC_PCM1_SYNC (MTK_PIN_NO(176) | 4) +#define MT2712_PIN_176_I2SI2_LRCK__FUNC_TDMIN_LRCK (MTK_PIN_NO(176) | 5) + +#define MT2712_PIN_177_I2SI1_DATA__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) +#define MT2712_PIN_177_I2SI1_DATA__FUNC_I2SI1_DI (MTK_PIN_NO(177) | 1) +#define MT2712_PIN_177_I2SI1_DATA__FUNC_I2SI0_DI (MTK_PIN_NO(177) | 2) +#define MT2712_PIN_177_I2SI1_DATA__FUNC_I2SI2_DI (MTK_PIN_NO(177) | 3) +#define MT2712_PIN_177_I2SI1_DATA__FUNC_TDMIN_DI (MTK_PIN_NO(177) | 4) + +#define MT2712_PIN_178_I2SI1_BCK__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) +#define MT2712_PIN_178_I2SI1_BCK__FUNC_I2SI1_BCK (MTK_PIN_NO(178) | 1) +#define MT2712_PIN_178_I2SI1_BCK__FUNC_I2SI0_BCK (MTK_PIN_NO(178) | 2) +#define MT2712_PIN_178_I2SI1_BCK__FUNC_I2SI2_BCK (MTK_PIN_NO(178) | 3) +#define MT2712_PIN_178_I2SI1_BCK__FUNC_TDMIN_BCK (MTK_PIN_NO(178) | 4) +#define MT2712_PIN_178_I2SI1_BCK__FUNC_TDMO0_DATA3 (MTK_PIN_NO(178) | 5) +#define MT2712_PIN_178_I2SI1_BCK__FUNC_TDMO1_DATA3 (MTK_PIN_NO(178) | 6) + +#define MT2712_PIN_179_I2SI1_LRCK__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) +#define MT2712_PIN_179_I2SI1_LRCK__FUNC_I2SI1_WS (MTK_PIN_NO(179) | 1) +#define MT2712_PIN_179_I2SI1_LRCK__FUNC_I2SI0_WS (MTK_PIN_NO(179) | 2) +#define MT2712_PIN_179_I2SI1_LRCK__FUNC_I2SI2_WS (MTK_PIN_NO(179) | 3) +#define MT2712_PIN_179_I2SI1_LRCK__FUNC_TDMIN_LRCK (MTK_PIN_NO(179) | 4) +#define MT2712_PIN_179_I2SI1_LRCK__FUNC_TDMO0_DATA2 (MTK_PIN_NO(179) | 5) +#define MT2712_PIN_179_I2SI1_LRCK__FUNC_TDMO1_DATA2 (MTK_PIN_NO(179) | 6) + +#define MT2712_PIN_180_I2SI1_MCLK__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) +#define MT2712_PIN_180_I2SI1_MCLK__FUNC_I2SI1_MCK (MTK_PIN_NO(180) | 1) +#define MT2712_PIN_180_I2SI1_MCLK__FUNC_I2SI0_MCK (MTK_PIN_NO(180) | 2) +#define MT2712_PIN_180_I2SI1_MCLK__FUNC_I2SI2_MCK (MTK_PIN_NO(180) | 3) +#define MT2712_PIN_180_I2SI1_MCLK__FUNC_TDMIN_MCLK (MTK_PIN_NO(180) | 4) +#define MT2712_PIN_180_I2SI1_MCLK__FUNC_TDMO0_DATA1 (MTK_PIN_NO(180) | 5) +#define MT2712_PIN_180_I2SI1_MCLK__FUNC_TDMO1_DATA1 (MTK_PIN_NO(180) | 6) +#define MT2712_PIN_180_I2SI1_MCLK__FUNC_I2S_IQ2_SDIB (MTK_PIN_NO(180) | 7) + +#define MT2712_PIN_181_I2SO1_DATA0__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) +#define MT2712_PIN_181_I2SO1_DATA0__FUNC_I2SO1_DO (MTK_PIN_NO(181) | 1) +#define MT2712_PIN_181_I2SO1_DATA0__FUNC_I2SO0_DO0 (MTK_PIN_NO(181) | 2) +#define MT2712_PIN_181_I2SO1_DATA0__FUNC_I2SO2_DO (MTK_PIN_NO(181) | 3) +#define MT2712_PIN_181_I2SO1_DATA0__FUNC_DAI_TX (MTK_PIN_NO(181) | 4) +#define MT2712_PIN_181_I2SO1_DATA0__FUNC_TDMIN_MCLK (MTK_PIN_NO(181) | 5) +#define MT2712_PIN_181_I2SO1_DATA0__FUNC_I2S_IQ2_SDIA (MTK_PIN_NO(181) | 7) + +#define MT2712_PIN_182_I2SO1_BCK__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) +#define MT2712_PIN_182_I2SO1_BCK__FUNC_I2SO1_BCK (MTK_PIN_NO(182) | 1) +#define MT2712_PIN_182_I2SO1_BCK__FUNC_I2SO0_BCK (MTK_PIN_NO(182) | 2) +#define MT2712_PIN_182_I2SO1_BCK__FUNC_I2SO2_BCK (MTK_PIN_NO(182) | 3) +#define MT2712_PIN_182_I2SO1_BCK__FUNC_DAI_SYNC (MTK_PIN_NO(182) | 4) +#define MT2712_PIN_182_I2SO1_BCK__FUNC_TDMIN_BCK (MTK_PIN_NO(182) | 5) +#define MT2712_PIN_182_I2SO1_BCK__FUNC_TDMO0_DATA3 (MTK_PIN_NO(182) | 6) +#define MT2712_PIN_182_I2SO1_BCK__FUNC_I2S_IQ2_BCK (MTK_PIN_NO(182) | 7) + +#define MT2712_PIN_183_I2SO1_LRCK__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) +#define MT2712_PIN_183_I2SO1_LRCK__FUNC_I2SO1_WS (MTK_PIN_NO(183) | 1) +#define MT2712_PIN_183_I2SO1_LRCK__FUNC_I2SO0_WS (MTK_PIN_NO(183) | 2) +#define MT2712_PIN_183_I2SO1_LRCK__FUNC_I2SO2_WS (MTK_PIN_NO(183) | 3) +#define MT2712_PIN_183_I2SO1_LRCK__FUNC_DAI_CLK (MTK_PIN_NO(183) | 4) +#define MT2712_PIN_183_I2SO1_LRCK__FUNC_TDMIN_DI (MTK_PIN_NO(183) | 5) +#define MT2712_PIN_183_I2SO1_LRCK__FUNC_TDMO0_DATA2 (MTK_PIN_NO(183) | 6) +#define MT2712_PIN_183_I2SO1_LRCK__FUNC_I2S_IQ2_WS (MTK_PIN_NO(183) | 7) + +#define MT2712_PIN_184_I2SO1_MCLK__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) +#define MT2712_PIN_184_I2SO1_MCLK__FUNC_I2SO1_MCK (MTK_PIN_NO(184) | 1) +#define MT2712_PIN_184_I2SO1_MCLK__FUNC_I2SO0_MCK (MTK_PIN_NO(184) | 2) +#define MT2712_PIN_184_I2SO1_MCLK__FUNC_I2SO2_MCK (MTK_PIN_NO(184) | 3) +#define MT2712_PIN_184_I2SO1_MCLK__FUNC_DAI_RX (MTK_PIN_NO(184) | 4) +#define MT2712_PIN_184_I2SO1_MCLK__FUNC_TDMIN_LRCK (MTK_PIN_NO(184) | 5) +#define MT2712_PIN_184_I2SO1_MCLK__FUNC_TDMO0_DATA1 (MTK_PIN_NO(184) | 6) +#define MT2712_PIN_184_I2SO1_MCLK__FUNC_I2S_IQ2_SDQA (MTK_PIN_NO(184) | 7) + +#define MT2712_PIN_185_AUD_EXT_CK2__FUNC_GPIO185 (MTK_PIN_NO(185) | 0) +#define MT2712_PIN_185_AUD_EXT_CK2__FUNC_AUD_EXT_CK2 (MTK_PIN_NO(185) | 1) +#define MT2712_PIN_185_AUD_EXT_CK2__FUNC_AUD_EXT_CK1 (MTK_PIN_NO(185) | 2) +#define MT2712_PIN_185_AUD_EXT_CK2__FUNC_I2SO1_DO (MTK_PIN_NO(185) | 3) +#define MT2712_PIN_185_AUD_EXT_CK2__FUNC_I2SI2_DI (MTK_PIN_NO(185) | 4) +#define MT2712_PIN_185_AUD_EXT_CK2__FUNC_MRG_RX (MTK_PIN_NO(185) | 5) +#define MT2712_PIN_185_AUD_EXT_CK2__FUNC_PCM1_DI (MTK_PIN_NO(185) | 6) +#define MT2712_PIN_185_AUD_EXT_CK2__FUNC_I2S_IQ0_SDQB (MTK_PIN_NO(185) | 7) + +#define MT2712_PIN_186_AUD_EXT_CK1__FUNC_GPIO186 (MTK_PIN_NO(186) | 0) +#define MT2712_PIN_186_AUD_EXT_CK1__FUNC_AUD_EXT_CK1 (MTK_PIN_NO(186) | 1) +#define MT2712_PIN_186_AUD_EXT_CK1__FUNC_AUD_EXT_CK2 (MTK_PIN_NO(186) | 2) +#define MT2712_PIN_186_AUD_EXT_CK1__FUNC_I2SO0_DO1 (MTK_PIN_NO(186) | 3) +#define MT2712_PIN_186_AUD_EXT_CK1__FUNC_I2SI1_DI (MTK_PIN_NO(186) | 4) +#define MT2712_PIN_186_AUD_EXT_CK1__FUNC_MRG_TX (MTK_PIN_NO(186) | 5) +#define MT2712_PIN_186_AUD_EXT_CK1__FUNC_PCM1_DO (MTK_PIN_NO(186) | 6) +#define MT2712_PIN_186_AUD_EXT_CK1__FUNC_I2S_IQ0_SDIB (MTK_PIN_NO(186) | 7) + +#define MT2712_PIN_187_I2SO2_BCK__FUNC_GPIO187 (MTK_PIN_NO(187) | 0) +#define MT2712_PIN_187_I2SO2_BCK__FUNC_I2SO2_BCK (MTK_PIN_NO(187) | 1) +#define MT2712_PIN_187_I2SO2_BCK__FUNC_I2SO0_BCK (MTK_PIN_NO(187) | 2) +#define MT2712_PIN_187_I2SO2_BCK__FUNC_I2SO1_BCK (MTK_PIN_NO(187) | 3) +#define MT2712_PIN_187_I2SO2_BCK__FUNC_PCM1_CLK (MTK_PIN_NO(187) | 4) +#define MT2712_PIN_187_I2SO2_BCK__FUNC_MRG_SYNC (MTK_PIN_NO(187) | 5) +#define MT2712_PIN_187_I2SO2_BCK__FUNC_TDMO1_DATA3 (MTK_PIN_NO(187) | 6) +#define MT2712_PIN_187_I2SO2_BCK__FUNC_I2S_IQ0_BCK (MTK_PIN_NO(187) | 7) + +#define MT2712_PIN_188_I2SO2_LRCK__FUNC_GPIO188 (MTK_PIN_NO(188) | 0) +#define MT2712_PIN_188_I2SO2_LRCK__FUNC_I2SO2_WS (MTK_PIN_NO(188) | 1) +#define MT2712_PIN_188_I2SO2_LRCK__FUNC_I2SO0_WS (MTK_PIN_NO(188) | 2) +#define MT2712_PIN_188_I2SO2_LRCK__FUNC_I2SO1_WS (MTK_PIN_NO(188) | 3) +#define MT2712_PIN_188_I2SO2_LRCK__FUNC_PCM1_SYNC (MTK_PIN_NO(188) | 4) +#define MT2712_PIN_188_I2SO2_LRCK__FUNC_MRG_CLK (MTK_PIN_NO(188) | 5) +#define MT2712_PIN_188_I2SO2_LRCK__FUNC_TDMO1_DATA2 (MTK_PIN_NO(188) | 6) +#define MT2712_PIN_188_I2SO2_LRCK__FUNC_I2S_IQ0_WS (MTK_PIN_NO(188) | 7) + +#define MT2712_PIN_189_I2SO2_MCLK__FUNC_GPIO189 (MTK_PIN_NO(189) | 0) +#define MT2712_PIN_189_I2SO2_MCLK__FUNC_I2SO2_MCK (MTK_PIN_NO(189) | 1) +#define MT2712_PIN_189_I2SO2_MCLK__FUNC_I2SO0_MCK (MTK_PIN_NO(189) | 2) +#define MT2712_PIN_189_I2SO2_MCLK__FUNC_I2SO1_MCK (MTK_PIN_NO(189) | 3) +#define MT2712_PIN_189_I2SO2_MCLK__FUNC_PCM1_DO (MTK_PIN_NO(189) | 4) +#define MT2712_PIN_189_I2SO2_MCLK__FUNC_MRG_RX (MTK_PIN_NO(189) | 5) +#define MT2712_PIN_189_I2SO2_MCLK__FUNC_TDMO1_DATA1 (MTK_PIN_NO(189) | 6) +#define MT2712_PIN_189_I2SO2_MCLK__FUNC_I2S_IQ0_SDQA (MTK_PIN_NO(189) | 7) + +#define MT2712_PIN_190_I2SO2_DATA0__FUNC_GPIO190 (MTK_PIN_NO(190) | 0) +#define MT2712_PIN_190_I2SO2_DATA0__FUNC_I2SO2_DO (MTK_PIN_NO(190) | 1) +#define MT2712_PIN_190_I2SO2_DATA0__FUNC_I2SO0_DO0 (MTK_PIN_NO(190) | 2) +#define MT2712_PIN_190_I2SO2_DATA0__FUNC_I2SO1_DO (MTK_PIN_NO(190) | 3) +#define MT2712_PIN_190_I2SO2_DATA0__FUNC_PCM1_DI (MTK_PIN_NO(190) | 4) +#define MT2712_PIN_190_I2SO2_DATA0__FUNC_MRG_TX (MTK_PIN_NO(190) | 5) +#define MT2712_PIN_190_I2SO2_DATA0__FUNC_PCM1_DO (MTK_PIN_NO(190) | 6) +#define MT2712_PIN_190_I2SO2_DATA0__FUNC_I2S_IQ0_SDIA (MTK_PIN_NO(190) | 7) + +#define MT2712_PIN_191_I2SO0_DATA1__FUNC_GPIO191 (MTK_PIN_NO(191) | 0) +#define MT2712_PIN_191_I2SO0_DATA1__FUNC_I2SO0_DO1 (MTK_PIN_NO(191) | 1) +#define MT2712_PIN_191_I2SO0_DATA1__FUNC_I2SI0_DI (MTK_PIN_NO(191) | 2) +#define MT2712_PIN_191_I2SO0_DATA1__FUNC_I2SI1_DI (MTK_PIN_NO(191) | 3) +#define MT2712_PIN_191_I2SO0_DATA1__FUNC_I2SI2_DI (MTK_PIN_NO(191) | 4) +#define MT2712_PIN_191_I2SO0_DATA1__FUNC_DAI_TX (MTK_PIN_NO(191) | 5) +#define MT2712_PIN_191_I2SO0_DATA1__FUNC_I2S_IQ0_SDQB (MTK_PIN_NO(191) | 6) +#define MT2712_PIN_191_I2SO0_DATA1__FUNC_I2S_IQ1_SDQB (MTK_PIN_NO(191) | 7) + +#define MT2712_PIN_192_I2SO0_MCLK__FUNC_GPIO192 (MTK_PIN_NO(192) | 0) +#define MT2712_PIN_192_I2SO0_MCLK__FUNC_I2SO0_MCK (MTK_PIN_NO(192) | 1) +#define MT2712_PIN_192_I2SO0_MCLK__FUNC_I2SO1_MCK (MTK_PIN_NO(192) | 2) +#define MT2712_PIN_192_I2SO0_MCLK__FUNC_I2SO2_MCK (MTK_PIN_NO(192) | 3) +#define MT2712_PIN_192_I2SO0_MCLK__FUNC_USB4_FT_SCL (MTK_PIN_NO(192) | 4) +#define MT2712_PIN_192_I2SO0_MCLK__FUNC_TDMO1_DATA3 (MTK_PIN_NO(192) | 5) +#define MT2712_PIN_192_I2SO0_MCLK__FUNC_I2S_IQ0_SDIB (MTK_PIN_NO(192) | 6) +#define MT2712_PIN_192_I2SO0_MCLK__FUNC_I2S_IQ1_SDQA (MTK_PIN_NO(192) | 7) + +#define MT2712_PIN_193_I2SO0_DATA0__FUNC_GPIO193 (MTK_PIN_NO(193) | 0) +#define MT2712_PIN_193_I2SO0_DATA0__FUNC_I2SO0_DO0 (MTK_PIN_NO(193) | 1) +#define MT2712_PIN_193_I2SO0_DATA0__FUNC_I2SO1_DO (MTK_PIN_NO(193) | 2) +#define MT2712_PIN_193_I2SO0_DATA0__FUNC_I2SO2_DO (MTK_PIN_NO(193) | 3) +#define MT2712_PIN_193_I2SO0_DATA0__FUNC_USB4_FT_SDA (MTK_PIN_NO(193) | 4) +#define MT2712_PIN_193_I2SO0_DATA0__FUNC_I2S_IQ1_SDIA (MTK_PIN_NO(193) | 7) + +#define MT2712_PIN_194_I2SO0_LRCK__FUNC_GPIO194 (MTK_PIN_NO(194) | 0) +#define MT2712_PIN_194_I2SO0_LRCK__FUNC_I2SO0_WS (MTK_PIN_NO(194) | 1) +#define MT2712_PIN_194_I2SO0_LRCK__FUNC_I2SO1_WS (MTK_PIN_NO(194) | 2) +#define MT2712_PIN_194_I2SO0_LRCK__FUNC_I2SO2_WS (MTK_PIN_NO(194) | 3) +#define MT2712_PIN_194_I2SO0_LRCK__FUNC_USB5_FT_SCL (MTK_PIN_NO(194) | 4) +#define MT2712_PIN_194_I2SO0_LRCK__FUNC_TDMO1_DATA2 (MTK_PIN_NO(194) | 5) +#define MT2712_PIN_194_I2SO0_LRCK__FUNC_I2S_IQ1_WS (MTK_PIN_NO(194) | 7) + +#define MT2712_PIN_195_I2SO0_BCK__FUNC_GPIO195 (MTK_PIN_NO(195) | 0) +#define MT2712_PIN_195_I2SO0_BCK__FUNC_I2SO0_BCK (MTK_PIN_NO(195) | 1) +#define MT2712_PIN_195_I2SO0_BCK__FUNC_I2SO1_BCK (MTK_PIN_NO(195) | 2) +#define MT2712_PIN_195_I2SO0_BCK__FUNC_I2SO2_BCK (MTK_PIN_NO(195) | 3) +#define MT2712_PIN_195_I2SO0_BCK__FUNC_USB5_FT_SDA (MTK_PIN_NO(195) | 4) +#define MT2712_PIN_195_I2SO0_BCK__FUNC_TDMO1_DATA1 (MTK_PIN_NO(195) | 5) +#define MT2712_PIN_195_I2SO0_BCK__FUNC_I2S_IQ1_BCK (MTK_PIN_NO(195) | 7) + +#define MT2712_PIN_196_TDMO1_MCLK__FUNC_GPIO196 (MTK_PIN_NO(196) | 0) +#define MT2712_PIN_196_TDMO1_MCLK__FUNC_TDMO1_MCLK (MTK_PIN_NO(196) | 1) +#define MT2712_PIN_196_TDMO1_MCLK__FUNC_TDMO0_MCLK (MTK_PIN_NO(196) | 2) +#define MT2712_PIN_196_TDMO1_MCLK__FUNC_TDMIN_MCLK (MTK_PIN_NO(196) | 3) +#define MT2712_PIN_196_TDMO1_MCLK__FUNC_I2SO0_DO1 (MTK_PIN_NO(196) | 6) +#define MT2712_PIN_196_TDMO1_MCLK__FUNC_I2S_IQ1_SDIB (MTK_PIN_NO(196) | 7) + +#define MT2712_PIN_197_TDMO1_LRCK__FUNC_GPIO197 (MTK_PIN_NO(197) | 0) +#define MT2712_PIN_197_TDMO1_LRCK__FUNC_TDMO1_LRCK (MTK_PIN_NO(197) | 1) +#define MT2712_PIN_197_TDMO1_LRCK__FUNC_TDMO0_LRCK (MTK_PIN_NO(197) | 2) +#define MT2712_PIN_197_TDMO1_LRCK__FUNC_TDMIN_LRCK (MTK_PIN_NO(197) | 3) +#define MT2712_PIN_197_TDMO1_LRCK__FUNC_TDMO0_DATA3 (MTK_PIN_NO(197) | 4) +#define MT2712_PIN_197_TDMO1_LRCK__FUNC_TDMO1_DATA3 (MTK_PIN_NO(197) | 5) +#define MT2712_PIN_197_TDMO1_LRCK__FUNC_I2SO3_MCK (MTK_PIN_NO(197) | 6) +#define MT2712_PIN_197_TDMO1_LRCK__FUNC_TDMO1_DATA2 (MTK_PIN_NO(197) | 7) + +#define MT2712_PIN_198_TDMO1_BCK__FUNC_GPIO198 (MTK_PIN_NO(198) | 0) +#define MT2712_PIN_198_TDMO1_BCK__FUNC_TDMO1_BCK (MTK_PIN_NO(198) | 1) +#define MT2712_PIN_198_TDMO1_BCK__FUNC_TDMO0_BCK (MTK_PIN_NO(198) | 2) +#define MT2712_PIN_198_TDMO1_BCK__FUNC_TDMIN_BCK (MTK_PIN_NO(198) | 3) +#define MT2712_PIN_198_TDMO1_BCK__FUNC_TDMO0_DATA2 (MTK_PIN_NO(198) | 4) +#define MT2712_PIN_198_TDMO1_BCK__FUNC_TDMO1_DATA2 (MTK_PIN_NO(198) | 5) +#define MT2712_PIN_198_TDMO1_BCK__FUNC_I2SO3_BCK (MTK_PIN_NO(198) | 6) +#define MT2712_PIN_198_TDMO1_BCK__FUNC_TDMO1_DATA1 (MTK_PIN_NO(198) | 7) + +#define MT2712_PIN_199_TDMO1_DATA__FUNC_GPIO199 (MTK_PIN_NO(199) | 0) +#define MT2712_PIN_199_TDMO1_DATA__FUNC_TDMO1_DATA (MTK_PIN_NO(199) | 1) +#define MT2712_PIN_199_TDMO1_DATA__FUNC_TDMO0_DATA (MTK_PIN_NO(199) | 2) +#define MT2712_PIN_199_TDMO1_DATA__FUNC_TDMIN_DI (MTK_PIN_NO(199) | 3) +#define MT2712_PIN_199_TDMO1_DATA__FUNC_TDMO0_DATA1 (MTK_PIN_NO(199) | 4) +#define MT2712_PIN_199_TDMO1_DATA__FUNC_TDMO1_DATA1 (MTK_PIN_NO(199) | 5) +#define MT2712_PIN_199_TDMO1_DATA__FUNC_I2SO3_WS (MTK_PIN_NO(199) | 6) + +#define MT2712_PIN_200_TDMO0_MCLK__FUNC_GPIO200 (MTK_PIN_NO(200) | 0) +#define MT2712_PIN_200_TDMO0_MCLK__FUNC_TDMO0_MCLK0 (MTK_PIN_NO(200) | 1) +#define MT2712_PIN_200_TDMO0_MCLK__FUNC_TDMO1_MCLK0 (MTK_PIN_NO(200) | 2) +#define MT2712_PIN_200_TDMO0_MCLK__FUNC_PCM1_DI (MTK_PIN_NO(200) | 3) +#define MT2712_PIN_200_TDMO0_MCLK__FUNC_TDMO0_MCLK1 (MTK_PIN_NO(200) | 4) +#define MT2712_PIN_200_TDMO0_MCLK__FUNC_TDMO1_MCLK1 (MTK_PIN_NO(200) | 5) +#define MT2712_PIN_200_TDMO0_MCLK__FUNC_MRG_TX (MTK_PIN_NO(200) | 6) +#define MT2712_PIN_200_TDMO0_MCLK__FUNC_I2SO2_MCK (MTK_PIN_NO(200) | 7) + +#define MT2712_PIN_201_TDMO0_LRCK__FUNC_GPIO201 (MTK_PIN_NO(201) | 0) +#define MT2712_PIN_201_TDMO0_LRCK__FUNC_TDMO0_LRCK0 (MTK_PIN_NO(201) | 1) +#define MT2712_PIN_201_TDMO0_LRCK__FUNC_TDMO1_LRCK0 (MTK_PIN_NO(201) | 2) +#define MT2712_PIN_201_TDMO0_LRCK__FUNC_PCM1_SYNC (MTK_PIN_NO(201) | 3) +#define MT2712_PIN_201_TDMO0_LRCK__FUNC_TDMO0_LRCK1 (MTK_PIN_NO(201) | 4) +#define MT2712_PIN_201_TDMO0_LRCK__FUNC_TDMO1_LRCK1 (MTK_PIN_NO(201) | 5) +#define MT2712_PIN_201_TDMO0_LRCK__FUNC_MRG_RX (MTK_PIN_NO(201) | 6) +#define MT2712_PIN_201_TDMO0_LRCK__FUNC_I2SO2_WS (MTK_PIN_NO(201) | 7) + +#define MT2712_PIN_202_TDMO0_BCK__FUNC_GPIO202 (MTK_PIN_NO(202) | 0) +#define MT2712_PIN_202_TDMO0_BCK__FUNC_TDMO0_BCK0 (MTK_PIN_NO(202) | 1) +#define MT2712_PIN_202_TDMO0_BCK__FUNC_TDMO1_BCK0 (MTK_PIN_NO(202) | 2) +#define MT2712_PIN_202_TDMO0_BCK__FUNC_PCM1_CLK (MTK_PIN_NO(202) | 3) +#define MT2712_PIN_202_TDMO0_BCK__FUNC_TDMO0_BCK1 (MTK_PIN_NO(202) | 4) +#define MT2712_PIN_202_TDMO0_BCK__FUNC_TDMO1_BCK1 (MTK_PIN_NO(202) | 5) +#define MT2712_PIN_202_TDMO0_BCK__FUNC_MRG_SYNC (MTK_PIN_NO(202) | 6) +#define MT2712_PIN_202_TDMO0_BCK__FUNC_I2SO2_BCK (MTK_PIN_NO(202) | 7) + +#define MT2712_PIN_203_TDMO0_DATA__FUNC_GPIO203 (MTK_PIN_NO(203) | 0) +#define MT2712_PIN_203_TDMO0_DATA__FUNC_TDMO0_DATA0 (MTK_PIN_NO(203) | 1) +#define MT2712_PIN_203_TDMO0_DATA__FUNC_TDMO1_DATA0 (MTK_PIN_NO(203) | 2) +#define MT2712_PIN_203_TDMO0_DATA__FUNC_PCM1_DO (MTK_PIN_NO(203) | 3) +#define MT2712_PIN_203_TDMO0_DATA__FUNC_TDMO0_DATA1 (MTK_PIN_NO(203) | 4) +#define MT2712_PIN_203_TDMO0_DATA__FUNC_TDMO1_DATA1 (MTK_PIN_NO(203) | 5) +#define MT2712_PIN_203_TDMO0_DATA__FUNC_MRG_CLK (MTK_PIN_NO(203) | 6) +#define MT2712_PIN_203_TDMO0_DATA__FUNC_I2SO2_DO (MTK_PIN_NO(203) | 7) + +#define MT2712_PIN_204_PERSTB_P0__FUNC_GPIO204 (MTK_PIN_NO(204) | 0) +#define MT2712_PIN_204_PERSTB_P0__FUNC_PERST_B_P0 (MTK_PIN_NO(204) | 1) + +#define MT2712_PIN_205_CLKREQN_P0__FUNC_GPIO205 (MTK_PIN_NO(205) | 0) +#define MT2712_PIN_205_CLKREQN_P0__FUNC_CLKREQ_N_P0 (MTK_PIN_NO(205) | 1) + +#define MT2712_PIN_206_WAKEEN_P0__FUNC_GPIO206 (MTK_PIN_NO(206) | 0) +#define MT2712_PIN_206_WAKEEN_P0__FUNC_WAKE_EN_P0 (MTK_PIN_NO(206) | 1) + +#define MT2712_PIN_207_PERSTB_P1__FUNC_GPIO207 (MTK_PIN_NO(207) | 0) +#define MT2712_PIN_207_PERSTB_P1__FUNC_PERST_B_P1 (MTK_PIN_NO(207) | 1) + +#define MT2712_PIN_208_CLKREQN_P1__FUNC_GPIO208 (MTK_PIN_NO(208) | 0) +#define MT2712_PIN_208_CLKREQN_P1__FUNC_CLKREQ_N_P1 (MTK_PIN_NO(208) | 1) + +#define MT2712_PIN_209_WAKEEN_P1__FUNC_GPIO209 (MTK_PIN_NO(209) | 0) +#define MT2712_PIN_209_WAKEEN_P1__FUNC_WAKE_EN_P1 (MTK_PIN_NO(209) | 1) + +#endif /* __DTS_MT2712_PINFUNC_H */ diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi new file mode 100644 index 000000000..1ac0b2cf3 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -0,0 +1,1136 @@ +/* + * Copyright (c) 2017 MediaTek Inc. + * Author: YT Shen <yt.shen@mediatek.com> + * + * SPDX-License-Identifier: (GPL-2.0 OR MIT) + */ + +#include <dt-bindings/clock/mt2712-clk.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/memory/mt2712-larb-port.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/power/mt2712-power.h> +#include "mt2712-pinfunc.h" + +/ { + compatible = "mediatek,mt2712"; + interrupt-parent = <&sysirq>; + #address-cells = <2>; + #size-cells = <2>; + + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + opp00 { + opp-hz = /bits/ 64 <598000000>; + opp-microvolt = <1000000>; + }; + opp01 { + opp-hz = /bits/ 64 <702000000>; + opp-microvolt = <1000000>; + }; + opp02 { + opp-hz = /bits/ 64 <793000000>; + opp-microvolt = <1000000>; + }; + }; + + cluster1_opp: opp-table-1 { + compatible = "operating-points-v2"; + opp-shared; + opp00 { + opp-hz = /bits/ 64 <598000000>; + opp-microvolt = <1000000>; + }; + opp01 { + opp-hz = /bits/ 64 <702000000>; + opp-microvolt = <1000000>; + }; + opp02 { + opp-hz = /bits/ 64 <793000000>; + opp-microvolt = <1000000>; + }; + opp03 { + opp-hz = /bits/ 64 <897000000>; + opp-microvolt = <1000000>; + }; + opp04 { + opp-hz = /bits/ 64 <1001000000>; + opp-microvolt = <1000000>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu2>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x000>; + clocks = <&mcucfg CLK_MCU_MP0_SEL>, + <&topckgen CLK_TOP_F_MP0_PLL1>; + clock-names = "cpu", "intermediate"; + proc-supply = <&cpus_fixed_vproc0>; + operating-points-v2 = <&cluster0_opp>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x001>; + enable-method = "psci"; + clocks = <&mcucfg CLK_MCU_MP0_SEL>, + <&topckgen CLK_TOP_F_MP0_PLL1>; + clock-names = "cpu", "intermediate"; + proc-supply = <&cpus_fixed_vproc0>; + operating-points-v2 = <&cluster0_opp>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x200>; + enable-method = "psci"; + clocks = <&mcucfg CLK_MCU_MP2_SEL>, + <&topckgen CLK_TOP_F_BIG_PLL1>; + clock-names = "cpu", "intermediate"; + proc-supply = <&cpus_fixed_vproc1>; + operating-points-v2 = <&cluster1_opp>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + entry-latency-us = <100>; + exit-latency-us = <80>; + min-residency-us = <2000>; + arm,psci-suspend-param = <0x0010000>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + entry-latency-us = <350>; + exit-latency-us = <80>; + min-residency-us = <3000>; + arm,psci-suspend-param = <0x1010000>; + }; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + baud_clk: dummy26m { + compatible = "fixed-clock"; + clock-frequency = <26000000>; + #clock-cells = <0>; + }; + + sys_clk: dummyclk { + compatible = "fixed-clock"; + clock-frequency = <26000000>; + #clock-cells = <0>; + }; + + clk26m: oscillator-26m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + clk32k: oscillator-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "clk32k"; + }; + + clkfpc: oscillator-50m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "clkfpc"; + }; + + clkaud_ext_i_0: oscillator-aud0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <6500000>; + clock-output-names = "clkaud_ext_i_0"; + }; + + clkaud_ext_i_1: oscillator-aud1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <196608000>; + clock-output-names = "clkaud_ext_i_1"; + }; + + clkaud_ext_i_2: oscillator-aud2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <180633600>; + clock-output-names = "clkaud_ext_i_2"; + }; + + clki2si0_mck_i: oscillator-i2s0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <30000000>; + clock-output-names = "clki2si0_mck_i"; + }; + + clki2si1_mck_i: oscillator-i2s1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <30000000>; + clock-output-names = "clki2si1_mck_i"; + }; + + clki2si2_mck_i: oscillator-i2s2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <30000000>; + clock-output-names = "clki2si2_mck_i"; + }; + + clktdmin_mclk_i: oscillator-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <30000000>; + clock-output-names = "clktdmin_mclk_i"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>; + }; + + topckgen: syscon@10000000 { + compatible = "mediatek,mt2712-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: syscon@10001000 { + compatible = "mediatek,mt2712-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + pericfg: syscon@10003000 { + compatible = "mediatek,mt2712-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + }; + + syscfg_pctl_a: syscfg_pctl_a@10005000 { + compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon"; + reg = <0 0x10005000 0 0x1000>; + }; + + pio: pinctrl@1000b000 { + compatible = "mediatek,mt2712-pinctrl"; + reg = <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl_a>; + pins-are-numbered; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + }; + + scpsys: power-controller@10006000 { + compatible = "mediatek,mt2712-scpsys", "syscon"; + #power-domain-cells = <1>; + reg = <0 0x10006000 0 0x1000>; + clocks = <&topckgen CLK_TOP_MM_SEL>, + <&topckgen CLK_TOP_MFG_SEL>, + <&topckgen CLK_TOP_VENC_SEL>, + <&topckgen CLK_TOP_JPGDEC_SEL>, + <&topckgen CLK_TOP_A1SYS_HP_SEL>, + <&topckgen CLK_TOP_VDEC_SEL>; + clock-names = "mm", "mfg", "venc", + "jpgdec", "audio", "vdec"; + infracfg = <&infracfg>; + }; + + uart5: serial@1000f000 { + compatible = "mediatek,mt2712-uart", + "mediatek,mt6577-uart"; + reg = <0 0x1000f000 0 0x400>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; + clocks = <&baud_clk>, <&sys_clk>; + clock-names = "baud", "bus"; + dmas = <&apdma 10 + &apdma 11>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + rtc: rtc@10011000 { + compatible = "mediatek,mt2712-rtc"; + reg = <0 0x10011000 0 0x1000>; + interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_LOW>; + }; + + spis1: spi@10013000 { + compatible = "mediatek,mt2712-spi-slave"; + reg = <0 0x10013000 0 0x100>; + interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_AO_SPI1>; + clock-names = "spi"; + assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>; + status = "disabled"; + }; + + iommu0: iommu@10205000 { + compatible = "mediatek,mt2712-m4u"; + reg = <0 0x10205000 0 0x1000>; + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_M4U>; + clock-names = "bclk"; + mediatek,infracfg = <&infracfg>; + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, + <&larb3>, <&larb6>; + #iommu-cells = <1>; + }; + + apmixedsys: syscon@10209000 { + compatible = "mediatek,mt2712-apmixedsys", "syscon"; + reg = <0 0x10209000 0 0x1000>; + #clock-cells = <1>; + }; + + iommu1: iommu@1020a000 { + compatible = "mediatek,mt2712-m4u"; + reg = <0 0x1020a000 0 0x1000>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_M4U>; + clock-names = "bclk"; + mediatek,infracfg = <&infracfg>; + mediatek,larbs = <&larb4>, <&larb5>, <&larb7>; + #iommu-cells = <1>; + }; + + mcucfg: syscon@10220000 { + compatible = "mediatek,mt2712-mcucfg", "syscon"; + reg = <0 0x10220000 0 0x1000>; + #clock-cells = <1>; + }; + + sysirq: interrupt-controller@10220a80 { + compatible = "mediatek,mt2712-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10220a80 0 0x40>; + }; + + gic: interrupt-controller@10510000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x10510000 0 0x10000>, + <0 0x10520000 0 0x20000>, + <0 0x10540000 0 0x20000>, + <0 0x10560000 0 0x20000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + apdma: dma-controller@11000400 { + compatible = "mediatek,mt2712-uart-dma", + "mediatek,mt6577-uart-dma"; + reg = <0 0x11000400 0 0x80>, + <0 0x11000480 0 0x80>, + <0 0x11000500 0 0x80>, + <0 0x11000580 0 0x80>, + <0 0x11000600 0 0x80>, + <0 0x11000680 0 0x80>, + <0 0x11000700 0 0x80>, + <0 0x11000780 0 0x80>, + <0 0x11000800 0 0x80>, + <0 0x11000880 0 0x80>, + <0 0x11000900 0 0x80>, + <0 0x11000980 0 0x80>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>; + dma-requests = <12>; + clocks = <&pericfg CLK_PERI_AP_DMA>; + clock-names = "apdma"; + #dma-cells = <1>; + }; + + auxadc: adc@11001000 { + compatible = "mediatek,mt2712-auxadc"; + reg = <0 0x11001000 0 0x1000>; + clocks = <&pericfg CLK_PERI_AUXADC>; + clock-names = "main"; + #io-channel-cells = <1>; + status = "disabled"; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt2712-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; + clocks = <&baud_clk>, <&sys_clk>; + clock-names = "baud", "bus"; + dmas = <&apdma 0 + &apdma 1>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt2712-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; + clocks = <&baud_clk>, <&sys_clk>; + clock-names = "baud", "bus"; + dmas = <&apdma 2 + &apdma 3>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt2712-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x400>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; + clocks = <&baud_clk>, <&sys_clk>; + clock-names = "baud", "bus"; + dmas = <&apdma 4 + &apdma 5>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart3: serial@11005000 { + compatible = "mediatek,mt2712-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11005000 0 0x400>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; + clocks = <&baud_clk>, <&sys_clk>; + clock-names = "baud", "bus"; + dmas = <&apdma 6 + &apdma 7>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + pwm: pwm@11006000 { + compatible = "mediatek,mt2712-pwm"; + reg = <0 0x11006000 0 0x1000>; + #pwm-cells = <2>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_PWM_SEL>, + <&pericfg CLK_PERI_PWM>, + <&pericfg CLK_PERI_PWM0>, + <&pericfg CLK_PERI_PWM1>, + <&pericfg CLK_PERI_PWM2>, + <&pericfg CLK_PERI_PWM3>, + <&pericfg CLK_PERI_PWM4>, + <&pericfg CLK_PERI_PWM5>, + <&pericfg CLK_PERI_PWM6>, + <&pericfg CLK_PERI_PWM7>; + clock-names = "top", + "main", + "pwm1", + "pwm2", + "pwm3", + "pwm4", + "pwm5", + "pwm6", + "pwm7", + "pwm8"; + status = "disabled"; + }; + + i2c0: i2c@11007000 { + compatible = "mediatek,mt2712-i2c"; + reg = <0 0x11007000 0 0x90>, + <0 0x11000180 0 0x80>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; + clock-div = <4>; + clocks = <&pericfg CLK_PERI_I2C0>, + <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", + "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@11008000 { + compatible = "mediatek,mt2712-i2c"; + reg = <0 0x11008000 0 0x90>, + <0 0x11000200 0 0x80>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; + clock-div = <4>; + clocks = <&pericfg CLK_PERI_I2C1>, + <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", + "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11009000 { + compatible = "mediatek,mt2712-i2c"; + reg = <0 0x11009000 0 0x90>, + <0 0x11000280 0 0x80>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; + clock-div = <4>; + clocks = <&pericfg CLK_PERI_I2C2>, + <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", + "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@1100a000 { + compatible = "mediatek,mt2712-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100a000 0 0x100>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&pericfg CLK_PERI_SPI0>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + nandc: nfi@1100e000 { + compatible = "mediatek,mt2712-nfc"; + reg = <0 0x1100e000 0 0x1000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_NFI2X_EN>, <&pericfg CLK_PERI_NFI>; + clock-names = "nfi_clk", "pad_clk"; + ecc-engine = <&bch>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + bch: ecc@1100f000 { + compatible = "mediatek,mt2712-ecc"; + reg = <0 0x1100f000 0 0x1000>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_NFI1X_CK_EN>; + clock-names = "nfiecc_clk"; + status = "disabled"; + }; + + i2c3: i2c@11010000 { + compatible = "mediatek,mt2712-i2c"; + reg = <0 0x11010000 0 0x90>, + <0 0x11000300 0 0x80>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; + clock-div = <4>; + clocks = <&pericfg CLK_PERI_I2C3>, + <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", + "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@11011000 { + compatible = "mediatek,mt2712-i2c"; + reg = <0 0x11011000 0 0x90>, + <0 0x11000380 0 0x80>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; + clock-div = <4>; + clocks = <&pericfg CLK_PERI_I2C4>, + <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", + "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@11013000 { + compatible = "mediatek,mt2712-i2c"; + reg = <0 0x11013000 0 0x90>, + <0 0x11000100 0 0x80>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>; + clock-div = <4>; + clocks = <&pericfg CLK_PERI_I2C5>, + <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", + "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@11015000 { + compatible = "mediatek,mt2712-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11015000 0 0x100>; + interrupts = <GIC_SPI 284 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&pericfg CLK_PERI_SPI2>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi3: spi@11016000 { + compatible = "mediatek,mt2712-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11016000 0 0x100>; + interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&pericfg CLK_PERI_SPI3>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi4: spi@10012000 { + compatible = "mediatek,mt2712-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x10012000 0 0x100>; + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_AO_SPI0>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi5: spi@11018000 { + compatible = "mediatek,mt2712-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11018000 0 0x100>; + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&pericfg CLK_PERI_SPI5>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + uart4: serial@11019000 { + compatible = "mediatek,mt2712-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11019000 0 0x400>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>; + clocks = <&baud_clk>, <&sys_clk>; + clock-names = "baud", "bus"; + dmas = <&apdma 8 + &apdma 9>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <0x7>; + snps,rd_osr_lmt = <0x7>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,priority = <0x0>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <3>; + snps,tx-sched-wrr; + queue0 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,priority = <0x0>; + }; + queue1 { + snps,weight = <0x11>; + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + queue2 { + snps,weight = <0x12>; + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + }; + + eth: ethernet@1101c000 { + compatible = "mediatek,mt2712-gmac", "snps,dwmac-4.20a"; + reg = <0 0x1101c000 0 0x1300>; + interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "macirq"; + mac-address = [00 55 7b b5 7d f7]; + clock-names = "axi", + "apb", + "mac_main", + "ptp_ref", + "rmii_internal"; + clocks = <&pericfg CLK_PERI_GMAC>, + <&pericfg CLK_PERI_GMAC_PCLK>, + <&topckgen CLK_TOP_ETHER_125M_SEL>, + <&topckgen CLK_TOP_ETHER_50M_SEL>, + <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>; + assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>, + <&topckgen CLK_TOP_ETHER_50M_SEL>, + <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>, + <&topckgen CLK_TOP_APLL1_D3>, + <&topckgen CLK_TOP_ETHERPLL_50M>; + power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>; + mediatek,pericfg = <&pericfg>; + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,txpbl = <1>; + snps,rxpbl = <1>; + snps,clk-csr = <0>; + status = "disabled"; + }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt2712-mmc"; + reg = <0 0x11230000 0 0x1000>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_MSDC30_0>, + <&pericfg CLK_PERI_MSDC50_0_HCLK_EN>, + <&pericfg CLK_PERI_MSDC30_0_QTR_EN>, + <&pericfg CLK_PERI_MSDC50_0_EN>; + clock-names = "source", "hclk", "bus_clk", "source_cg"; + status = "disabled"; + }; + + mmc1: mmc@11240000 { + compatible = "mediatek,mt2712-mmc"; + reg = <0 0x11240000 0 0x1000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_MSDC30_1>, + <&topckgen CLK_TOP_AXI_SEL>, + <&pericfg CLK_PERI_MSDC30_1_EN>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + mmc2: mmc@11250000 { + compatible = "mediatek,mt2712-mmc"; + reg = <0 0x11250000 0 0x1000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_MSDC30_2>, + <&topckgen CLK_TOP_AXI_SEL>, + <&pericfg CLK_PERI_MSDC30_2_EN>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + ssusb: usb@11271000 { + compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3"; + reg = <0 0x11271000 0 0x3000>, + <0 0x11280700 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u2port1 PHY_TYPE_USB2>; + power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>; + clocks = <&topckgen CLK_TOP_USB30_SEL>; + clock-names = "sys_ck"; + mediatek,syscon-wakeup = <&pericfg 0x510 2>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb_host0: usb@11270000 { + compatible = "mediatek,mt2712-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11270000 0 0x1000>; + reg-names = "mac"; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>; + clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; + clock-names = "sys_ck", "ref_ck"; + status = "disabled"; + }; + }; + + u3phy0: t-phy@11290000 { + compatible = "mediatek,mt2712-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11290000 0x9000>; + status = "okay"; + + u2port0: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u2port1: usb-phy@8000 { + reg = <0x8000 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u3port0: usb-phy@8700 { + reg = <0x8700 0x900>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + + ssusb1: usb@112c1000 { + compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3"; + reg = <0 0x112c1000 0 0x3000>, + <0 0x112d0700 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_LOW>; + phys = <&u2port2 PHY_TYPE_USB2>, + <&u2port3 PHY_TYPE_USB2>, + <&u3port1 PHY_TYPE_USB3>; + power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>; + clocks = <&topckgen CLK_TOP_USB30_SEL>; + clock-names = "sys_ck"; + mediatek,syscon-wakeup = <&pericfg 0x514 2>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb_host1: usb@112c0000 { + compatible = "mediatek,mt2712-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x112c0000 0 0x1000>; + reg-names = "mac"; + interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>; + clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; + clock-names = "sys_ck", "ref_ck"; + status = "disabled"; + }; + }; + + u3phy1: t-phy@112e0000 { + compatible = "mediatek,mt2712-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x112e0000 0x9000>; + status = "okay"; + + u2port2: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u2port3: usb-phy@8000 { + reg = <0x8000 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u3port1: usb-phy@8700 { + reg = <0x8700 0x900>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + + pcie1: pcie@112ff000 { + compatible = "mediatek,mt2712-pcie"; + device_type = "pci"; + reg = <0 0x112ff000 0 0x1000>; + reg-names = "port1"; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pcie_irq"; + clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, + <&pericfg CLK_PERI_PCIE1>; + clock-names = "sys_ck1", "ahb_ck1"; + phys = <&u3port1 PHY_TYPE_PCIE>; + phy-names = "pcie-phy1"; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>; + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + pcie_intc1: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + pcie0: pcie@11700000 { + compatible = "mediatek,mt2712-pcie"; + device_type = "pci"; + reg = <0 0x11700000 0 0x1000>; + reg-names = "port0"; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pcie_irq"; + clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, + <&pericfg CLK_PERI_PCIE0>; + clock-names = "sys_ck0", "ahb_ck0"; + phys = <&u3port0 PHY_TYPE_PCIE>; + phy-names = "pcie-phy0"; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + mfgcfg: syscon@13000000 { + compatible = "mediatek,mt2712-mfgcfg", "syscon"; + reg = <0 0x13000000 0 0x1000>; + #clock-cells = <1>; + }; + + mmsys: syscon@14000000 { + compatible = "mediatek,mt2712-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb0: larb@14021000 { + compatible = "mediatek,mt2712-smi-larb"; + reg = <0 0x14021000 0 0x1000>; + mediatek,smi = <&smi_common0>; + mediatek,larb-id = <0>; + power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_SMI_LARB0>, + <&mmsys CLK_MM_SMI_LARB0>; + clock-names = "apb", "smi"; + }; + + smi_common0: smi@14022000 { + compatible = "mediatek,mt2712-smi-common"; + reg = <0 0x14022000 0 0x1000>; + power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_COMMON>; + clock-names = "apb", "smi"; + }; + + larb4: larb@14027000 { + compatible = "mediatek,mt2712-smi-larb"; + reg = <0 0x14027000 0 0x1000>; + mediatek,smi = <&smi_common1>; + mediatek,larb-id = <4>; + power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_SMI_LARB4>, + <&mmsys CLK_MM_SMI_LARB4>; + clock-names = "apb", "smi"; + }; + + larb5: larb@14030000 { + compatible = "mediatek,mt2712-smi-larb"; + reg = <0 0x14030000 0 0x1000>; + mediatek,smi = <&smi_common1>; + mediatek,larb-id = <5>; + power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_SMI_LARB5>, + <&mmsys CLK_MM_SMI_LARB5>; + clock-names = "apb", "smi"; + }; + + smi_common1: smi@14031000 { + compatible = "mediatek,mt2712-smi-common"; + reg = <0 0x14031000 0 0x1000>; + power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_SMI_COMMON1>, + <&mmsys CLK_MM_SMI_COMMON1>; + clock-names = "apb", "smi"; + }; + + larb7: larb@14032000 { + compatible = "mediatek,mt2712-smi-larb"; + reg = <0 0x14032000 0 0x1000>; + mediatek,smi = <&smi_common1>; + mediatek,larb-id = <7>; + power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_SMI_LARB7>, + <&mmsys CLK_MM_SMI_LARB7>; + clock-names = "apb", "smi"; + }; + + imgsys: syscon@15000000 { + compatible = "mediatek,mt2712-imgsys", "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb2: larb@15001000 { + compatible = "mediatek,mt2712-smi-larb"; + reg = <0 0x15001000 0 0x1000>; + mediatek,smi = <&smi_common0>; + mediatek,larb-id = <2>; + power-domains = <&scpsys MT2712_POWER_DOMAIN_ISP>; + clocks = <&imgsys CLK_IMG_SMI_LARB2>, + <&imgsys CLK_IMG_SMI_LARB2>; + clock-names = "apb", "smi"; + }; + + bdpsys: syscon@15010000 { + compatible = "mediatek,mt2712-bdpsys", "syscon"; + reg = <0 0x15010000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys: syscon@16000000 { + compatible = "mediatek,mt2712-vdecsys", "syscon"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb1: larb@16010000 { + compatible = "mediatek,mt2712-smi-larb"; + reg = <0 0x16010000 0 0x1000>; + mediatek,smi = <&smi_common0>; + mediatek,larb-id = <1>; + power-domains = <&scpsys MT2712_POWER_DOMAIN_VDEC>; + clocks = <&vdecsys CLK_VDEC_CKEN>, + <&vdecsys CLK_VDEC_LARB1_CKEN>; + clock-names = "apb", "smi"; + }; + + vencsys: syscon@18000000 { + compatible = "mediatek,mt2712-vencsys", "syscon"; + reg = <0 0x18000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb3: larb@18001000 { + compatible = "mediatek,mt2712-smi-larb"; + reg = <0 0x18001000 0 0x1000>; + mediatek,smi = <&smi_common0>; + mediatek,larb-id = <3>; + power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>; + clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>, + <&vencsys CLK_VENC_VENC>; + clock-names = "apb", "smi"; + }; + + larb6: larb@18002000 { + compatible = "mediatek,mt2712-smi-larb"; + reg = <0 0x18002000 0 0x1000>; + mediatek,smi = <&smi_common0>; + mediatek,larb-id = <6>; + power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>; + clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>, + <&vencsys CLK_VENC_VENC>; + clock-names = "apb", "smi"; + }; + + jpgdecsys: syscon@19000000 { + compatible = "mediatek,mt2712-jpgdecsys", "syscon"; + reg = <0 0x19000000 0 0x1000>; + #clock-cells = <1>; + }; +}; + diff --git a/arch/arm64/boot/dts/mediatek/mt6358.dtsi b/arch/arm64/boot/dts/mediatek/mt6358.dtsi new file mode 100644 index 000000000..98f3b0e0c --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6358.dtsi @@ -0,0 +1,373 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2020 MediaTek Inc. + */ +#include <dt-bindings/input/input.h> + +&pwrap { + pmic: mt6358 { + compatible = "mediatek,mt6358"; + interrupt-controller; + interrupt-parent = <&pio>; + interrupts = <182 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + + mt6358codec: mt6358codec { + compatible = "mediatek,mt6358-sound"; + mediatek,dmic-mode = <0>; /* two-wires */ + }; + + mt6358regulator: mt6358regulator { + compatible = "mediatek,mt6358-regulator"; + + mt6358_vdram1_reg: buck_vdram1 { + regulator-name = "vdram1"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2087500>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <0>; + regulator-always-on; + regulator-allowed-modes = <0 1>; + }; + + mt6358_vcore_reg: buck_vcore { + regulator-name = "vcore"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1293750>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <200>; + regulator-always-on; + regulator-allowed-modes = <0 1>; + }; + + mt6358_vpa_reg: buck_vpa { + regulator-name = "vpa"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3650000>; + regulator-ramp-delay = <50000>; + regulator-enable-ramp-delay = <250>; + regulator-allowed-modes = <0 1>; + }; + + mt6358_vproc11_reg: buck_vproc11 { + regulator-name = "vproc11"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1293750>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <200>; + regulator-always-on; + regulator-allowed-modes = <0 1>; + }; + + mt6358_vproc12_reg: buck_vproc12 { + regulator-name = "vproc12"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1293750>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <200>; + regulator-always-on; + regulator-allowed-modes = <0 1>; + }; + + mt6358_vgpu_reg: buck_vgpu { + regulator-name = "vgpu"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1293750>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <200>; + regulator-allowed-modes = <0 1>; + }; + + mt6358_vs2_reg: buck_vs2 { + regulator-name = "vs2"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2087500>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <0>; + regulator-always-on; + }; + + mt6358_vmodem_reg: buck_vmodem { + regulator-name = "vmodem"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1293750>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <900>; + regulator-always-on; + regulator-allowed-modes = <0 1>; + }; + + mt6358_vs1_reg: buck_vs1 { + regulator-name = "vs1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <2587500>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <0>; + regulator-always-on; + }; + + mt6358_vdram2_reg: ldo_vdram2 { + regulator-name = "vdram2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <3300>; + }; + + mt6358_vsim1_reg: ldo_vsim1 { + regulator-name = "vsim1"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3100000>; + regulator-enable-ramp-delay = <540>; + }; + + mt6358_vibr_reg: ldo_vibr { + regulator-name = "vibr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <60>; + }; + + mt6358_vrf12_reg: ldo_vrf12 { + compatible = "regulator-fixed"; + regulator-name = "vrf12"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <120>; + }; + + mt6358_vio18_reg: ldo_vio18 { + compatible = "regulator-fixed"; + regulator-name = "vio18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <2700>; + regulator-always-on; + }; + + mt6358_vusb_reg: ldo_vusb { + regulator-name = "vusb"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3100000>; + regulator-enable-ramp-delay = <270>; + regulator-always-on; + }; + + mt6358_vcamio_reg: ldo_vcamio { + compatible = "regulator-fixed"; + regulator-name = "vcamio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <325>; + }; + + mt6358_vcamd_reg: ldo_vcamd { + regulator-name = "vcamd"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <325>; + }; + + mt6358_vcn18_reg: ldo_vcn18 { + compatible = "regulator-fixed"; + regulator-name = "vcn18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6358_vfe28_reg: ldo_vfe28 { + compatible = "regulator-fixed"; + regulator-name = "vfe28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6358_vsram_proc11_reg: ldo_vsram_proc11 { + regulator-name = "vsram_proc11"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1293750>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <240>; + regulator-always-on; + }; + + mt6358_vcn28_reg: ldo_vcn28 { + compatible = "regulator-fixed"; + regulator-name = "vcn28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6358_vsram_others_reg: ldo_vsram_others { + regulator-name = "vsram_others"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1293750>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <240>; + regulator-always-on; + }; + + mt6358_vsram_gpu_reg: ldo_vsram_gpu { + regulator-name = "vsram_gpu"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1293750>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <240>; + }; + + mt6358_vxo22_reg: ldo_vxo22 { + compatible = "regulator-fixed"; + regulator-name = "vxo22"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-enable-ramp-delay = <120>; + regulator-always-on; + }; + + mt6358_vefuse_reg: ldo_vefuse { + regulator-name = "vefuse"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6358_vaux18_reg: ldo_vaux18 { + compatible = "regulator-fixed"; + regulator-name = "vaux18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6358_vmch_reg: ldo_vmch { + regulator-name = "vmch"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <60>; + }; + + mt6358_vbif28_reg: ldo_vbif28 { + compatible = "regulator-fixed"; + regulator-name = "vbif28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6358_vsram_proc12_reg: ldo_vsram_proc12 { + regulator-name = "vsram_proc12"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1293750>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <240>; + regulator-always-on; + }; + + mt6358_vcama1_reg: ldo_vcama1 { + regulator-name = "vcama1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <325>; + }; + + mt6358_vemc_reg: ldo_vemc { + regulator-name = "vemc"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <60>; + }; + + mt6358_vio28_reg: ldo_vio28 { + compatible = "regulator-fixed"; + regulator-name = "vio28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6358_va12_reg: ldo_va12 { + compatible = "regulator-fixed"; + regulator-name = "va12"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <270>; + regulator-always-on; + }; + + mt6358_vrf18_reg: ldo_vrf18 { + compatible = "regulator-fixed"; + regulator-name = "vrf18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <120>; + }; + + mt6358_vcn33_bt_reg: ldo_vcn33_bt { + regulator-name = "vcn33_bt"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3500000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6358_vcn33_wifi_reg: ldo_vcn33_wifi { + regulator-name = "vcn33_wifi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3500000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6358_vcama2_reg: ldo_vcama2 { + regulator-name = "vcama2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <325>; + }; + + mt6358_vmc_reg: ldo_vmc { + regulator-name = "vmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <60>; + }; + + mt6358_vldo28_reg: ldo_vldo28 { + regulator-name = "vldo28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6358_vaud28_reg: ldo_vaud28 { + compatible = "regulator-fixed"; + regulator-name = "vaud28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6358_vsim2_reg: ldo_vsim2 { + regulator-name = "vsim2"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3100000>; + regulator-enable-ramp-delay = <540>; + }; + }; + + mt6358rtc: mt6358rtc { + compatible = "mediatek,mt6358-rtc"; + }; + + mt6358keys: mt6358keys { + compatible = "mediatek,mt6358-keys"; + power { + linux,keycodes = <KEY_POWER>; + wakeup-source; + }; + home { + linux,keycodes = <KEY_HOME>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt6359.dtsi b/arch/arm64/boot/dts/mediatek/mt6359.dtsi new file mode 100644 index 000000000..df3e82223 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6359.dtsi @@ -0,0 +1,298 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + */ + +&pwrap { + pmic: pmic { + compatible = "mediatek,mt6359"; + interrupt-controller; + #interrupt-cells = <2>; + + mt6359codec: mt6359codec { + }; + + regulators { + mt6359_vs1_buck_reg: buck_vs1 { + regulator-name = "vs1"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <2200000>; + regulator-enable-ramp-delay = <0>; + regulator-always-on; + }; + mt6359_vgpu11_buck_reg: buck_vgpu11 { + regulator-name = "vgpu11"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1193750>; + regulator-ramp-delay = <5000>; + regulator-enable-ramp-delay = <200>; + regulator-allowed-modes = <0 1 2>; + }; + mt6359_vmodem_buck_reg: buck_vmodem { + regulator-name = "vmodem"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1100000>; + regulator-ramp-delay = <10760>; + regulator-enable-ramp-delay = <200>; + }; + mt6359_vpu_buck_reg: buck_vpu { + regulator-name = "vpu"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1193750>; + regulator-ramp-delay = <5000>; + regulator-enable-ramp-delay = <200>; + regulator-allowed-modes = <0 1 2>; + }; + mt6359_vcore_buck_reg: buck_vcore { + regulator-name = "vcore"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <5000>; + regulator-enable-ramp-delay = <200>; + regulator-allowed-modes = <0 1 2>; + }; + mt6359_vs2_buck_reg: buck_vs2 { + regulator-name = "vs2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1600000>; + regulator-enable-ramp-delay = <0>; + regulator-always-on; + }; + mt6359_vpa_buck_reg: buck_vpa { + regulator-name = "vpa"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3650000>; + regulator-enable-ramp-delay = <300>; + }; + mt6359_vproc2_buck_reg: buck_vproc2 { + regulator-name = "vproc2"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1193750>; + regulator-ramp-delay = <7500>; + regulator-enable-ramp-delay = <200>; + regulator-allowed-modes = <0 1 2>; + }; + mt6359_vproc1_buck_reg: buck_vproc1 { + regulator-name = "vproc1"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1193750>; + regulator-ramp-delay = <7500>; + regulator-enable-ramp-delay = <200>; + regulator-allowed-modes = <0 1 2>; + }; + mt6359_vcore_sshub_buck_reg: buck_vcore_sshub { + regulator-name = "vcore_sshub"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1193750>; + }; + mt6359_vgpu11_sshub_buck_reg: buck_vgpu11_sshub { + regulator-name = "vgpu11_sshub"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1193750>; + }; + mt6359_vaud18_ldo_reg: ldo_vaud18 { + regulator-name = "vaud18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <240>; + }; + mt6359_vsim1_ldo_reg: ldo_vsim1 { + regulator-name = "vsim1"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3100000>; + }; + mt6359_vibr_ldo_reg: ldo_vibr { + regulator-name = "vibr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + }; + mt6359_vrf12_ldo_reg: ldo_vrf12 { + regulator-name = "vrf12"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + }; + mt6359_vusb_ldo_reg: ldo_vusb { + regulator-name = "vusb"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <960>; + regulator-always-on; + }; + mt6359_vsram_proc2_ldo_reg: ldo_vsram_proc2 { + regulator-name = "vsram_proc2"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1293750>; + regulator-ramp-delay = <7500>; + regulator-enable-ramp-delay = <240>; + regulator-always-on; + }; + mt6359_vio18_ldo_reg: ldo_vio18 { + regulator-name = "vio18"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-enable-ramp-delay = <960>; + regulator-always-on; + }; + mt6359_vcamio_ldo_reg: ldo_vcamio { + regulator-name = "vcamio"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + }; + mt6359_vcn18_ldo_reg: ldo_vcn18 { + regulator-name = "vcn18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <240>; + }; + mt6359_vfe28_ldo_reg: ldo_vfe28 { + regulator-name = "vfe28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <120>; + }; + mt6359_vcn13_ldo_reg: ldo_vcn13 { + regulator-name = "vcn13"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1300000>; + }; + mt6359_vcn33_1_bt_ldo_reg: ldo_vcn33_1_bt { + regulator-name = "vcn33_1_bt"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3500000>; + }; + mt6359_vcn33_1_wifi_ldo_reg: ldo_vcn33_1_wifi { + regulator-name = "vcn33_1_wifi"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3500000>; + }; + mt6359_vaux18_ldo_reg: ldo_vaux18 { + regulator-name = "vaux18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <240>; + regulator-always-on; + }; + mt6359_vsram_others_ldo_reg: ldo_vsram_others { + regulator-name = "vsram_others"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1293750>; + regulator-ramp-delay = <5000>; + regulator-enable-ramp-delay = <240>; + }; + mt6359_vefuse_ldo_reg: ldo_vefuse { + regulator-name = "vefuse"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <2000000>; + }; + mt6359_vxo22_ldo_reg: ldo_vxo22 { + regulator-name = "vxo22"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2200000>; + regulator-always-on; + }; + mt6359_vrfck_ldo_reg: ldo_vrfck { + regulator-name = "vrfck"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1700000>; + }; + mt6359_vrfck_1_ldo_reg: ldo_vrfck_1 { + regulator-name = "vrfck"; + regulator-min-microvolt = <1240000>; + regulator-max-microvolt = <1600000>; + }; + mt6359_vbif28_ldo_reg: ldo_vbif28 { + regulator-name = "vbif28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <240>; + }; + mt6359_vio28_ldo_reg: ldo_vio28 { + regulator-name = "vio28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + mt6359_vemc_ldo_reg: ldo_vemc { + regulator-name = "vemc"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3300000>; + }; + mt6359_vemc_1_ldo_reg: ldo_vemc_1 { + regulator-name = "vemc"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + }; + mt6359_vcn33_2_bt_ldo_reg: ldo_vcn33_2_bt { + regulator-name = "vcn33_2_bt"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3500000>; + }; + mt6359_vcn33_2_wifi_ldo_reg: ldo_vcn33_2_wifi { + regulator-name = "vcn33_2_wifi"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3500000>; + }; + mt6359_va12_ldo_reg: ldo_va12 { + regulator-name = "va12"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + }; + mt6359_va09_ldo_reg: ldo_va09 { + regulator-name = "va09"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1200000>; + }; + mt6359_vrf18_ldo_reg: ldo_vrf18 { + regulator-name = "vrf18"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1810000>; + }; + mt6359_vsram_md_ldo_reg: ldo_vsram_md { + regulator-name = "vsram_md"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1293750>; + regulator-ramp-delay = <10760>; + regulator-enable-ramp-delay = <240>; + }; + mt6359_vufs_ldo_reg: ldo_vufs { + regulator-name = "vufs"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + }; + mt6359_vm18_ldo_reg: ldo_vm18 { + regulator-name = "vm18"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-always-on; + }; + mt6359_vbbck_ldo_reg: ldo_vbbck { + regulator-name = "vbbck"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1200000>; + }; + mt6359_vsram_proc1_ldo_reg: ldo_vsram_proc1 { + regulator-name = "vsram_proc1"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1293750>; + regulator-ramp-delay = <7500>; + regulator-enable-ramp-delay = <240>; + regulator-always-on; + }; + mt6359_vsim2_ldo_reg: ldo_vsim2 { + regulator-name = "vsim2"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3100000>; + }; + mt6359_vsram_others_sshub_ldo: ldo_vsram_others_sshub { + regulator-name = "vsram_others_sshub"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1293750>; + }; + }; + + mt6359rtc: mt6359rtc { + compatible = "mediatek,mt6358-rtc"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt6380.dtsi b/arch/arm64/boot/dts/mediatek/mt6380.dtsi new file mode 100644 index 000000000..53b335d2d --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6380.dtsi @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for MediaTek MT6380 regulator + * + * Copyright (c) 2018 MediaTek Inc. + * Author: Chenglin Xu <chenglin.xu@mediatek.com> + * Sean Wang <sean.wang@mediatek.com> + */ + +&pwrap { + regulators { + compatible = "mediatek,mt6380-regulator"; + + mt6380_vcpu_reg: buck-vcore1 { + regulator-name = "vcore1"; + regulator-min-microvolt = < 600000>; + regulator-max-microvolt = <1393750>; + regulator-ramp-delay = <6250>; + regulator-always-on; + regulator-boot-on; + }; + + mt6380_vcore_reg: buck-vcore { + regulator-name = "vcore"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1393750>; + regulator-ramp-delay = <6250>; + regulator-always-on; + regulator-boot-on; + }; + + mt6380_vrf_reg: buck-vrf { + regulator-name = "vrf"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1575000>; + regulator-ramp-delay = <0>; + regulator-always-on; + regulator-boot-on; + }; + + mt6380_vm_reg: ldo-vm { + regulator-name = "vm"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1400000>; + regulator-ramp-delay = <0>; + regulator-always-on; + regulator-boot-on; + }; + + mt6380_va_reg: ldo-va { + regulator-name = "va"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <0>; + regulator-always-on; + regulator-boot-on; + }; + + mt6380_vphy_reg: ldo-vphy { + regulator-name = "vphy"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <0>; + regulator-always-on; + regulator-boot-on; + }; + + mt6380_vddr_reg: ldo-vddr { + regulator-name = "vddr"; + regulator-min-microvolt = <1240000>; + regulator-max-microvolt = <1840000>; + regulator-ramp-delay = <0>; + regulator-always-on; + regulator-boot-on; + }; + + mt6380_vt_reg: ldo-vt { + regulator-name = "vt"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <0>; + regulator-always-on; + regulator-boot-on; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt6755-evb.dts b/arch/arm64/boot/dts/mediatek/mt6755-evb.dts new file mode 100644 index 000000000..e079b7932 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6755-evb.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016 MediaTek Inc. + * Author: Mars.C <mars.cheng@mediatek.com> + */ + +/dts-v1/; +#include "mt6755.dtsi" + +/ { + model = "MediaTek MT6755 EVB"; + compatible = "mediatek,mt6755-evb", "mediatek,mt6755"; + + aliases { + serial0 = &uart0; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x1e800000>; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt6755.dtsi b/arch/arm64/boot/dts/mediatek/mt6755.dtsi new file mode 100644 index 000000000..b55d3fac9 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6755.dtsi @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016 MediaTek Inc. + * Author: Mars.C <mars.cheng@mediatek.com> + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "mediatek,mt6755"; + interrupt-parent = <&sysirq>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x001>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x002>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x003>; + }; + + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x100>; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x101>; + }; + + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x102>; + }; + + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x103>; + }; + }; + + uart_clk: dummy26m { + compatible = "fixed-clock"; + clock-frequency = <26000000>; + #clock-cells = <0>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + }; + + sysirq: intpol-controller@10200620 { + compatible = "mediatek,mt6755-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10200620 0 0x20>; + }; + + gic: interrupt-controller@10231000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x10231000 0 0x1000>, + <0 0x10232000 0 0x2000>, + <0 0x10234000 0 0x2000>, + <0 0x10236000 0 0x2000>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt6755-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt6755-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; + clocks = <&uart_clk>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts new file mode 100644 index 000000000..164f5cbb3 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 MediaTek Inc. + * Author: Mars.C <mars.cheng@mediatek.com> + * + */ + +/dts-v1/; +#include "mt6779.dtsi" + +/ { + model = "MediaTek MT6779 EVB"; + compatible = "mediatek,mt6779-evb", "mediatek,mt6779"; + + aliases { + serial0 = &uart0; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x1e800000>; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi new file mode 100644 index 000000000..dde9ce137 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi @@ -0,0 +1,288 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 MediaTek Inc. + * Author: Mars.C <mars.cheng@mediatek.com> + * + */ + +#include <dt-bindings/clock/mt6779-clk.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/mt6779-pinfunc.h> + +/ { + compatible = "mediatek,mt6779"; + interrupt-parent = <&sysirq>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x100>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x200>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x300>; + }; + + cpu4: cpu@4 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x400>; + }; + + cpu5: cpu@5 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x500>; + }; + + cpu6: cpu@6 { + device_type = "cpu"; + compatible = "arm,cortex-a75"; + enable-method = "psci"; + reg = <0x600>; + }; + + cpu7: cpu@7 { + device_type = "cpu"; + compatible = "arm,cortex-a75"; + enable-method = "psci"; + reg = <0x700>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW 0>; + }; + + clk26m: oscillator-26m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + clk32k: oscillator-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "clk32k"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <4>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x40000>, /* GICD */ + <0 0x0c040000 0 0x200000>; /* GICR */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 \ + &cpu2 &cpu3 &cpu4 &cpu5>; + }; + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu6 &cpu7>; + }; + }; + + }; + + sysirq: intpol-controller@c53a650 { + compatible = "mediatek,mt6779-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x0c53a650 0 0x50>; + }; + + topckgen: clock-controller@10000000 { + compatible = "mediatek,mt6779-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg_ao: clock-controller@10001000 { + compatible = "mediatek,mt6779-infracfg_ao", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + pio: pinctrl@10005000 { + compatible = "mediatek,mt6779-pinctrl", "syscon"; + reg = <0 0x10005000 0 0x1000>, + <0 0x11c20000 0 0x1000>, + <0 0x11d10000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11e70000 0 0x1000>, + <0 0x11ea0000 0 0x1000>, + <0 0x11f20000 0 0x1000>, + <0 0x11f30000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_rm", + "iocfg_br", "iocfg_lm", + "iocfg_lb", "iocfg_rt", + "iocfg_lt", "iocfg_tl", + "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 210>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; + }; + + apmixed: clock-controller@1000c000 { + compatible = "mediatek,mt6779-apmixed", "syscon"; + reg = <0 0x1000c000 0 0xe00>; + #clock-cells = <1>; + }; + + pwrap: pwrap@1000d000 { + compatible = "mediatek,mt6779-pwrap"; + reg = <0 0x1000d000 0 0x1000>; + reg-names = "pwrap"; + interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_PMIC_AP>; + clock-names = "spi", "wrap"; + }; + + devapc: devapc@10207000 { + compatible = "mediatek,mt6779-devapc"; + reg = <0 0x10207000 0 0x1000>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg_ao CLK_INFRA_DEVICE_APC>; + clock-names = "devapc-infra-clock"; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt6779-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART0>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt6779-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART1>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt6779-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x400>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART2>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + audio: clock-controller@11210000 { + compatible = "mediatek,mt6779-audio", "syscon"; + reg = <0 0x11210000 0 0x1000>; + #clock-cells = <1>; + }; + + mfgcfg: clock-controller@13fbf000 { + compatible = "mediatek,mt6779-mfgcfg", "syscon"; + reg = <0 0x13fbf000 0 0x1000>; + #clock-cells = <1>; + }; + + mmsys: syscon@14000000 { + compatible = "mediatek,mt6779-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys: clock-controller@15020000 { + compatible = "mediatek,mt6779-imgsys", "syscon"; + reg = <0 0x15020000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys: clock-controller@16000000 { + compatible = "mediatek,mt6779-vdecsys", "syscon"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + vencsys: clock-controller@17000000 { + compatible = "mediatek,mt6779-vencsys", "syscon"; + reg = <0 0x17000000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys: clock-controller@1a000000 { + compatible = "mediatek,mt6779-camsys", "syscon"; + reg = <0 0x1a000000 0 0x10000>; + #clock-cells = <1>; + }; + + ipesys: clock-controller@1b000000 { + compatible = "mediatek,mt6779-ipesys", "syscon"; + reg = <0 0x1b000000 0 0x1000>; + #clock-cells = <1>; + }; + + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt6795-evb.dts b/arch/arm64/boot/dts/mediatek/mt6795-evb.dts new file mode 100644 index 000000000..1ed2f81ed --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6795-evb.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Mars.C <mars.cheng@mediatek.com> + */ + +/dts-v1/; +#include "mt6795.dtsi" + +/ { + model = "MediaTek MT6795 Evaluation Board"; + compatible = "mediatek,mt6795-evb", "mediatek,mt6795"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x1e800000>; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi new file mode 100644 index 000000000..46f0e54be --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -0,0 +1,326 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Mars.C <mars.cheng@mediatek.com> + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/mt6795-pinfunc.h> + +/ { + compatible = "mediatek,mt6795"; + interrupt-parent = <&sysirq>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x000>; + cci-control-port = <&cci_control2>; + next-level-cache = <&l2_0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x001>; + cci-control-port = <&cci_control2>; + next-level-cache = <&l2_0>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x002>; + cci-control-port = <&cci_control2>; + next-level-cache = <&l2_0>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x003>; + cci-control-port = <&cci_control2>; + next-level-cache = <&l2_0>; + }; + + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x100>; + cci-control-port = <&cci_control1>; + next-level-cache = <&l2_1>; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x101>; + cci-control-port = <&cci_control1>; + next-level-cache = <&l2_1>; + }; + + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x102>; + cci-control-port = <&cci_control1>; + next-level-cache = <&l2_1>; + }; + + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x103>; + cci-control-port = <&cci_control1>; + next-level-cache = <&l2_1>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + + core1 { + cpu = <&cpu5>; + }; + + core2 { + cpu = <&cpu6>; + }; + + core3 { + cpu = <&cpu7>; + }; + }; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + }; + + l2_1: l2-cache1 { + compatible = "cache"; + cache-level = <2>; + }; + }; + + clk26m: oscillator-26m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + clk32k: oscillator-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + clock-output-names = "clk32k"; + }; + + system_clk: dummy13m { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_LOW>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + pio: pinctrl@10005000 { + compatible = "mediatek,mt6795-pinctrl"; + reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>; + reg-names = "base", "eint"; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 196>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + watchdog: watchdog@10007000 { + compatible = "mediatek,mt6795-wdt"; + reg = <0 0x10007000 0 0x100>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>; + #reset-cells = <1>; + timeout-sec = <20>; + }; + + timer: timer@10008000 { + compatible = "mediatek,mt6795-timer", + "mediatek,mt6577-timer"; + reg = <0 0x10008000 0 0x1000>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>; + clocks = <&system_clk>, <&clk32k>; + }; + + sysirq: intpol-controller@10200620 { + compatible = "mediatek,mt6795-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10200620 0 0x20>; + }; + + systimer: timer@10200670 { + compatible = "mediatek,mt6795-systimer"; + reg = <0 0x10200670 0 0x10>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&system_clk>; + clock-names = "clk13m"; + }; + + gic: interrupt-controller@10221000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x10221000 0 0x1000>, + <0 0x10222000 0 0x2000>, + <0 0x10224000 0 0x2000>, + <0 0x10226000 0 0x2000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + cci: cci@10390000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x10390000 0 0x1000>; + ranges = <0 0 0x10390000 0x10000>; + + cci_control0: slave-if@1000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace-lite"; + reg = <0x1000 0x1000>; + }; + + cci_control1: slave-if@4000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x4000 0x1000>; + }; + + cci_control2: slave-if@5000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x5000 0x1000>; + }; + + pmu@9000 { + compatible = "arm,cci-400-pmu,r1"; + reg = <0x9000 0x5000>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt6795-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk26m>; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt6795-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk26m>; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt6795-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x400>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk26m>; + status = "disabled"; + }; + + uart3: serial@11005000 { + compatible = "mediatek,mt6795-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11005000 0 0x400>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk26m>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt6797-evb.dts b/arch/arm64/boot/dts/mediatek/mt6797-evb.dts new file mode 100644 index 000000000..2327e752d --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6797-evb.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017 MediaTek Inc. + * Author: Mars.C <mars.cheng@mediatek.com> + */ + +/dts-v1/; +#include "mt6797.dtsi" + +/ { + model = "MediaTek MT6797 Evaluation Board"; + compatible = "mediatek,mt6797-evb", "mediatek,mt6797"; + + aliases { + serial0 = &uart0; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x1e800000>; + }; + + chosen {}; +}; + +&uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts b/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts new file mode 100644 index 000000000..eff9e8dbd --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for MediaTek X20 Development Board + * + * Copyright (C) 2018, Linaro Ltd. + * + */ + +/dts-v1/; + +#include "mt6797.dtsi" + +/ { + model = "Mediatek X20 Development Board"; + compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797"; + + aliases { + serial0 = &uart1; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +/* HDMI */ +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; + +/* HS - I2C2 */ +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; +}; + +/* HS - I2C3 */ +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins_a>; + status = "okay"; +}; + +/* LS - I2C0 */ +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_a>; + status = "okay"; +}; + +/* LS - I2C1 */ +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins_a>; + status = "okay"; +}; + +/* POWER_VPROC */ +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pins_a>; + status = "okay"; +}; + +/* FAN53555 */ +&i2c7 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_pins_a>; + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_a>; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi b/arch/arm64/boot/dts/mediatek/mt6797.dtsi new file mode 100644 index 000000000..c3677d77e --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6797.dtsi @@ -0,0 +1,483 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2017 MediaTek Inc. + * Author: Mars.C <mars.cheng@mediatek.com> + */ + +#include <dt-bindings/clock/mt6797-clk.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/mt6797-pinfunc.h> + +/ { + compatible = "mediatek,mt6797"; + interrupt-parent = <&sysirq>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x001>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x002>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x003>; + }; + + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x100>; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x101>; + }; + + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x102>; + }; + + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x103>; + }; + + cpu8: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + enable-method = "psci"; + reg = <0x200>; + }; + + cpu9: cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + enable-method = "psci"; + reg = <0x201>; + }; + }; + + clk26m: oscillator-26m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; + + topckgen: topckgen@10000000 { + compatible = "mediatek,mt6797-topckgen"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infrasys: infracfg_ao@10001000 { + compatible = "mediatek,mt6797-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + pio: pinctrl@10005000 { + compatible = "mediatek,mt6797-pinctrl"; + reg = <0 0x10005000 0 0x1000>, + <0 0x10002000 0 0x400>, + <0 0x10002400 0 0x400>, + <0 0x10002800 0 0x400>, + <0 0x10002C00 0 0x400>; + reg-names = "gpio", "iocfgl", "iocfgb", + "iocfgr", "iocfgt"; + gpio-controller; + #gpio-cells = <2>; + + uart0_pins_a: uart0 { + pins0 { + pinmux = <MT6797_GPIO234__FUNC_UTXD0>, + <MT6797_GPIO235__FUNC_URXD0>; + }; + }; + + uart1_pins_a: uart1 { + pins1 { + pinmux = <MT6797_GPIO232__FUNC_URXD1>, + <MT6797_GPIO233__FUNC_UTXD1>; + }; + }; + + i2c0_pins_a: i2c0 { + pins0 { + pinmux = <MT6797_GPIO37__FUNC_SCL0_0>, + <MT6797_GPIO38__FUNC_SDA0_0>; + }; + }; + + i2c1_pins_a: i2c1 { + pins1 { + pinmux = <MT6797_GPIO55__FUNC_SCL1_0>, + <MT6797_GPIO56__FUNC_SDA1_0>; + }; + }; + + i2c2_pins_a: i2c2 { + pins2 { + pinmux = <MT6797_GPIO96__FUNC_SCL2_0>, + <MT6797_GPIO95__FUNC_SDA2_0>; + }; + }; + + i2c3_pins_a: i2c3 { + pins3 { + pinmux = <MT6797_GPIO75__FUNC_SDA3_0>, + <MT6797_GPIO74__FUNC_SCL3_0>; + }; + }; + + i2c4_pins_a: i2c4 { + pins4 { + pinmux = <MT6797_GPIO238__FUNC_SDA4_0>, + <MT6797_GPIO239__FUNC_SCL4_0>; + }; + }; + + i2c5_pins_a: i2c5 { + pins5 { + pinmux = <MT6797_GPIO240__FUNC_SDA5_0>, + <MT6797_GPIO241__FUNC_SCL5_0>; + }; + }; + + i2c6_pins_a: i2c6 { + pins6 { + pinmux = <MT6797_GPIO152__FUNC_SDA6_0>, + <MT6797_GPIO151__FUNC_SCL6_0>; + }; + }; + + i2c7_pins_a: i2c7 { + pins7 { + pinmux = <MT6797_GPIO154__FUNC_SDA7_0>, + <MT6797_GPIO153__FUNC_SCL7_0>; + }; + }; + }; + + scpsys: power-controller@10006000 { + compatible = "mediatek,mt6797-scpsys"; + #power-domain-cells = <1>; + reg = <0 0x10006000 0 0x1000>; + clocks = <&topckgen CLK_TOP_MUX_MFG>, + <&topckgen CLK_TOP_MUX_MM>, + <&topckgen CLK_TOP_MUX_VDEC>; + clock-names = "mfg", "mm", "vdec"; + infracfg = <&infrasys>; + }; + + watchdog: watchdog@10007000 { + compatible = "mediatek,mt6797-wdt", "mediatek,mt6589-wdt"; + reg = <0 0x10007000 0 0x100>; + }; + + apmixedsys: apmixed@1000c000 { + compatible = "mediatek,mt6797-apmixedsys"; + reg = <0 0x1000c000 0 0x1000>; + #clock-cells = <1>; + }; + + sysirq: intpol-controller@10200620 { + compatible = "mediatek,mt6797-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10220620 0 0x20>, + <0 0x10220690 0 0x10>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt6797-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infrasys CLK_INFRA_UART0>, + <&infrasys CLK_INFRA_AP_DMA>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt6797-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infrasys CLK_INFRA_UART1>, + <&infrasys CLK_INFRA_AP_DMA>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt6797-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x400>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infrasys CLK_INFRA_UART2>, + <&infrasys CLK_INFRA_AP_DMA>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart3: serial@11005000 { + compatible = "mediatek,mt6797-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11005000 0 0x400>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infrasys CLK_INFRA_UART3>, + <&infrasys CLK_INFRA_AP_DMA>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + i2c0: i2c@11007000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <0>; + reg = <0 0x11007000 0 0x1000>, + <0 0x11000100 0 0x80>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infrasys CLK_INFRA_I2C0>, + <&infrasys CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@11008000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <1>; + reg = <0 0x11008000 0 0x1000>, + <0 0x11000180 0 0x80>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infrasys CLK_INFRA_I2C1>, + <&infrasys CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@11009000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <8>; + reg = <0 0x11009000 0 0x1000>, + <0 0x11000200 0 0x80>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infrasys CLK_INFRA_I2C2>, + <&infrasys CLK_INFRA_AP_DMA>, + <&infrasys CLK_INFRA_I2C2_ARB>; + clock-names = "main", "dma", "arb"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c9: i2c@1100d000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <9>; + reg = <0 0x1100d000 0 0x1000>, + <0 0x11000280 0 0x80>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infrasys CLK_INFRA_I2C3>, + <&infrasys CLK_INFRA_AP_DMA>, + <&infrasys CLK_INFRA_I2C3_ARB>; + clock-names = "main", "dma", "arb"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@1100e000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <6>; + reg = <0 0x1100e000 0 0x1000>, + <0 0x11000500 0 0x80>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infrasys CLK_INFRA_I2C_APPM>, + <&infrasys CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@11010000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <7>; + reg = <0 0x11010000 0 0x1000>, + <0 0x11000580 0 0x80>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infrasys CLK_INFRA_I2C_GPUPM>, + <&infrasys CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@11011000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <4>; + reg = <0 0x11011000 0 0x1000>, + <0 0x11000300 0 0x80>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infrasys CLK_INFRA_I2C4>, + <&infrasys CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11013000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <2>; + reg = <0 0x11013000 0 0x1000>, + <0 0x11000400 0 0x80>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infrasys CLK_INFRA_I2C2_IMM>, + <&infrasys CLK_INFRA_AP_DMA>, + <&infrasys CLK_INFRA_I2C2_ARB>; + clock-names = "main", "dma", "arb"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@11014000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <3>; + reg = <0 0x11014000 0 0x1000>, + <0 0x11000480 0 0x80>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infrasys CLK_INFRA_I2C3_IMM>, + <&infrasys CLK_INFRA_AP_DMA>, + <&infrasys CLK_INFRA_I2C3_ARB>; + clock-names = "main", "dma", "arb"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@1101c000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <5>; + reg = <0 0x1101c000 0 0x1000>, + <0 0x11000380 0 0x80>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infrasys CLK_INFRA_I2C5>, + <&infrasys CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mmsys: syscon@14000000 { + compatible = "mediatek,mt6797-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys: imgsys_config@15000000 { + compatible = "mediatek,mt6797-imgsys", "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys: vdec_gcon@16000000 { + compatible = "mediatek,mt6797-vdecsys", "syscon"; + reg = <0 0x16000000 0 0x10000>; + #clock-cells = <1>; + }; + + vencsys: venc_gcon@17000000 { + compatible = "mediatek,mt6797-vencsys", "syscon"; + reg = <0 0x17000000 0 0x1000>; + #clock-cells = <1>; + }; + + gic: interrupt-controller@19000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + reg = <0 0x19000000 0 0x10000>, /* GICD */ + <0 0x19200000 0 0x200000>, /* GICR */ + <0 0x10240000 0 0x2000>; /* GICC */ + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts new file mode 100644 index 000000000..2c35ed073 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts @@ -0,0 +1,603 @@ +/* + * Copyright (c) 2018 MediaTek Inc. + * Author: Ryder Lee <ryder.lee@mediatek.com> + * + * SPDX-License-Identifier: (GPL-2.0 OR MIT) + */ + +/dts-v1/; +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> + +#include "mt7622.dtsi" +#include "mt6380.dtsi" + +/ { + model = "Bananapi BPI-R64"; + compatible = "bananapi,bpi-r64", "mediatek,mt7622"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512"; + }; + + cpus { + cpu@0 { + proc-supply = <&mt6380_vcpu_reg>; + sram-supply = <&mt6380_vm_reg>; + }; + + cpu@1 { + proc-supply = <&mt6380_vcpu_reg>; + sram-supply = <&mt6380_vm_reg>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + factory-key { + label = "factory"; + linux,code = <BTN_0>; + gpios = <&pio 0 GPIO_ACTIVE_HIGH>; + }; + + wps-key { + label = "wps"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&pio 102 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "bpi-r64:pio:green"; + color = <LED_COLOR_ID_GREEN>; + gpios = <&pio 89 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-1 { + label = "bpi-r64:pio:red"; + color = <LED_COLOR_ID_RED>; + gpios = <&pio 88 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + memory@40000000 { + reg = <0 0x40000000 0 0x40000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&bch { + status = "disabled"; +}; + +&btif { + status = "okay"; +}; + +&cir { + pinctrl-names = "default"; + pinctrl-0 = <&irrx_pins>; + status = "okay"; +}; + +ð { + status = "okay"; + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + switch@0 { + compatible = "mediatek,mt7531"; + reg = <0>; + reset-gpios = <&pio 54 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "wan"; + }; + + port@1 { + reg = <1>; + label = "lan0"; + }; + + port@2 { + reg = <2>; + label = "lan1"; + }; + + port@3 { + reg = <3>; + label = "lan2"; + }; + + port@4 { + reg = <4>; + label = "lan3"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; + + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&emmc_pins_default>; + pinctrl-1 = <&emmc_pins_uhs>; + status = "okay"; + bus-width = <8>; + max-frequency = <50000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; + non-removable; +}; + +&mmc1 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&sd0_pins_default>; + pinctrl-1 = <&sd0_pins_uhs>; + status = "okay"; + bus-width = <4>; + max-frequency = <50000000>; + cap-sd-highspeed; + r_smpl = <1>; + cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; +}; + +&nandc { + pinctrl-names = "default"; + pinctrl-0 = <¶llel_nand_pins>; + status = "disabled"; +}; + +&nor_flash { + pinctrl-names = "default"; + pinctrl-0 = <&spi_nor_pins>; + status = "disabled"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + }; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; + status = "okay"; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins>; + status = "okay"; +}; + +&pio { + /* Attention: GPIO 90 is used to switch between PCIe@1,0 and + * SATA functions. i.e. output-high: PCIe, output-low: SATA + */ + asm_sel { + gpio-hog; + gpios = <90 GPIO_ACTIVE_HIGH>; + output-high; + }; + + /* eMMC is shared pin with parallel NAND */ + emmc_pins_default: emmc-pins-default { + mux { + function = "emmc", "emmc_rst"; + groups = "emmc"; + }; + + /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7", + * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4, + * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively + */ + conf-cmd-dat { + pins = "NDL0", "NDL1", "NDL2", + "NDL3", "NDL4", "NDL5", + "NDL6", "NDL7", "NRB"; + input-enable; + bias-pull-up; + }; + + conf-clk { + pins = "NCLE"; + bias-pull-down; + }; + }; + + emmc_pins_uhs: emmc-pins-uhs { + mux { + function = "emmc"; + groups = "emmc"; + }; + + conf-cmd-dat { + pins = "NDL0", "NDL1", "NDL2", + "NDL3", "NDL4", "NDL5", + "NDL6", "NDL7", "NRB"; + input-enable; + drive-strength = <4>; + bias-pull-up; + }; + + conf-clk { + pins = "NCLE"; + drive-strength = <4>; + bias-pull-down; + }; + }; + + eth_pins: eth-pins { + mux { + function = "eth"; + groups = "mdc_mdio", "rgmii_via_gmac2"; + }; + }; + + i2c1_pins: i2c1-pins { + mux { + function = "i2c"; + groups = "i2c1_0"; + }; + }; + + i2c2_pins: i2c2-pins { + mux { + function = "i2c"; + groups = "i2c2_0"; + }; + }; + + i2s1_pins: i2s1-pins { + mux { + function = "i2s"; + groups = "i2s_out_mclk_bclk_ws", + "i2s1_in_data", + "i2s1_out_data"; + }; + + conf { + pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK", + "I2S_WS", "I2S_MCLK"; + drive-strength = <12>; + bias-pull-down; + }; + }; + + irrx_pins: irrx-pins { + mux { + function = "ir"; + groups = "ir_1_rx"; + }; + }; + + irtx_pins: irtx-pins { + mux { + function = "ir"; + groups = "ir_1_tx"; + }; + }; + + /* Parallel nand is shared pin with eMMC */ + parallel_nand_pins: parallel-nand-pins { + mux { + function = "flash"; + groups = "par_nand"; + }; + }; + + pcie0_pins: pcie0-pins { + mux { + function = "pcie"; + groups = "pcie0_pad_perst", + "pcie0_1_waken", + "pcie0_1_clkreq"; + }; + }; + + pcie1_pins: pcie1-pins { + mux { + function = "pcie"; + groups = "pcie1_pad_perst", + "pcie1_0_waken", + "pcie1_0_clkreq"; + }; + }; + + pmic_bus_pins: pmic-bus-pins { + mux { + function = "pmic"; + groups = "pmic_bus"; + }; + }; + + pwm_pins: pwm-pins { + mux { + function = "pwm"; + groups = "pwm_ch1_0", /* mt7622_pwm_ch1_0_pins[] = { 51, }; */ + "pwm_ch2_0", /* mt7622_pwm_ch2_0_pins[] = { 52, }; */ + "pwm_ch3_2", /* mt7622_pwm_ch3_2_pins[] = { 97, }; */ + "pwm_ch4_1", /* mt7622_pwm_ch4_1_pins[] = { 67, }; */ + "pwm_ch5_0", /* mt7622_pwm_ch5_0_pins[] = { 68, }; */ + "pwm_ch6_0"; /* mt7622_pwm_ch6_0_pins[] = { 69, }; */ + }; + }; + + wled_pins: wled-pins { + mux { + function = "led"; + groups = "wled"; + }; + }; + + sd0_pins_default: sd0-pins-default { + mux { + function = "sd"; + groups = "sd_0"; + }; + + /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN", + * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1, + * DAT2, DAT3, CMD, CLK for SD respectively. + */ + conf-cmd-data { + pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", + "I2S2_IN","I2S4_OUT"; + input-enable; + drive-strength = <8>; + bias-pull-up; + }; + conf-clk { + pins = "I2S3_OUT"; + drive-strength = <12>; + bias-pull-down; + }; + conf-cd { + pins = "TXD3"; + bias-pull-up; + }; + }; + + sd0_pins_uhs: sd0-pins-uhs { + mux { + function = "sd"; + groups = "sd_0"; + }; + + conf-cmd-data { + pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", + "I2S2_IN","I2S4_OUT"; + input-enable; + bias-pull-up; + }; + + conf-clk { + pins = "I2S3_OUT"; + bias-pull-down; + }; + }; + + /* Serial NAND is shared pin with SPI-NOR */ + serial_nand_pins: serial-nand-pins { + mux { + function = "flash"; + groups = "snfi"; + }; + }; + + spic0_pins: spic0-pins { + mux { + function = "spi"; + groups = "spic0_0"; + }; + }; + + spic1_pins: spic1-pins { + mux { + function = "spi"; + groups = "spic1_0"; + }; + }; + + /* SPI-NOR is shared pin with serial NAND */ + spi_nor_pins: spi-nor-pins { + mux { + function = "flash"; + groups = "spi_nor"; + }; + }; + + /* serial NAND is shared pin with SPI-NOR */ + serial_nand_pins: serial-nand-pins { + mux { + function = "flash"; + groups = "snfi"; + }; + }; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0_0_tx_rx" ; + }; + }; + + uart2_pins: uart2-pins { + mux { + function = "uart"; + groups = "uart2_1_tx_rx" ; + }; + }; + + watchdog_pins: watchdog-pins { + mux { + function = "watchdog"; + groups = "watchdog"; + }; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + +&pwrap { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_bus_pins>; + + status = "okay"; +}; + +&sata { + status = "disable"; +}; + +&sata_phy { + status = "disable"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spic0_pins>; + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spic1_pins>; +}; + +&ssusb { + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; + status = "okay"; +}; + +&u3phy { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&watchdog { + pinctrl-names = "default"; + pinctrl-0 = <&watchdog_pins>; + status = "okay"; +}; + +&wmac { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts new file mode 100644 index 000000000..f9313b697 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts @@ -0,0 +1,570 @@ +/* + * Copyright (c) 2017 MediaTek Inc. + * Author: Ming Huang <ming.huang@mediatek.com> + * Sean Wang <sean.wang@mediatek.com> + * + * SPDX-License-Identifier: (GPL-2.0 OR MIT) + */ + +/dts-v1/; +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> + +#include "mt7622.dtsi" +#include "mt6380.dtsi" + +/ { + model = "MediaTek MT7622 RFB1 board"; + compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512"; + }; + + cpus { + cpu@0 { + proc-supply = <&mt6380_vcpu_reg>; + sram-supply = <&mt6380_vm_reg>; + }; + + cpu@1 { + proc-supply = <&mt6380_vcpu_reg>; + sram-supply = <&mt6380_vm_reg>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-factory { + label = "factory"; + linux,code = <BTN_0>; + gpios = <&pio 0 0>; + }; + + key-wps { + label = "wps"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&pio 102 0>; + }; + }; + + memory@40000000 { + reg = <0 0x40000000 0 0x20000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&bch { + status = "disabled"; +}; + +&btif { + status = "okay"; +}; + +&cir { + pinctrl-names = "default"; + pinctrl-0 = <&irrx_pins>; + status = "okay"; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <ð_pins>; + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + switch@0 { + compatible = "mediatek,mt7531"; + reg = <0>; + reset-gpios = <&pio 54 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan0"; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan3"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; + + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&emmc_pins_default>; + pinctrl-1 = <&emmc_pins_uhs>; + status = "okay"; + bus-width = <8>; + max-frequency = <50000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; + non-removable; +}; + +&mmc1 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&sd0_pins_default>; + pinctrl-1 = <&sd0_pins_uhs>; + status = "okay"; + bus-width = <4>; + max-frequency = <50000000>; + cap-sd-highspeed; + r_smpl = <1>; + cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; +}; + +&nandc { + pinctrl-names = "default"; + pinctrl-0 = <¶llel_nand_pins>; + status = "disabled"; +}; + +&nor_flash { + pinctrl-names = "default"; + pinctrl-0 = <&spi_nor_pins>; + status = "disabled"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + }; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; + status = "okay"; +}; + +&pio { + /* eMMC is shared pin with parallel NAND */ + emmc_pins_default: emmc-pins-default { + mux { + function = "emmc", "emmc_rst"; + groups = "emmc"; + }; + + /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7", + * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4, + * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively + */ + conf-cmd-dat { + pins = "NDL0", "NDL1", "NDL2", + "NDL3", "NDL4", "NDL5", + "NDL6", "NDL7", "NRB"; + input-enable; + bias-pull-up; + }; + + conf-clk { + pins = "NCLE"; + bias-pull-down; + }; + }; + + emmc_pins_uhs: emmc-pins-uhs { + mux { + function = "emmc"; + groups = "emmc"; + }; + + conf-cmd-dat { + pins = "NDL0", "NDL1", "NDL2", + "NDL3", "NDL4", "NDL5", + "NDL6", "NDL7", "NRB"; + input-enable; + drive-strength = <4>; + bias-pull-up; + }; + + conf-clk { + pins = "NCLE"; + drive-strength = <4>; + bias-pull-down; + }; + }; + + eth_pins: eth-pins { + mux { + function = "eth"; + groups = "mdc_mdio", "rgmii_via_gmac2"; + }; + }; + + i2c1_pins: i2c1-pins { + mux { + function = "i2c"; + groups = "i2c1_0"; + }; + }; + + i2c2_pins: i2c2-pins { + mux { + function = "i2c"; + groups = "i2c2_0"; + }; + }; + + i2s1_pins: i2s1-pins { + mux { + function = "i2s"; + groups = "i2s_out_mclk_bclk_ws", + "i2s1_in_data", + "i2s1_out_data"; + }; + + conf { + pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK", + "I2S_WS", "I2S_MCLK"; + drive-strength = <12>; + bias-pull-down; + }; + }; + + irrx_pins: irrx-pins { + mux { + function = "ir"; + groups = "ir_1_rx"; + }; + }; + + irtx_pins: irtx-pins { + mux { + function = "ir"; + groups = "ir_1_tx"; + }; + }; + + /* Parallel nand is shared pin with eMMC */ + parallel_nand_pins: parallel-nand-pins { + mux { + function = "flash"; + groups = "par_nand"; + }; + }; + + pcie0_pins: pcie0-pins { + mux { + function = "pcie"; + groups = "pcie0_pad_perst", + "pcie0_1_waken", + "pcie0_1_clkreq"; + }; + }; + + pcie1_pins: pcie1-pins { + mux { + function = "pcie"; + groups = "pcie1_pad_perst", + "pcie1_0_waken", + "pcie1_0_clkreq"; + }; + }; + + pmic_bus_pins: pmic-bus-pins { + mux { + function = "pmic"; + groups = "pmic_bus"; + }; + }; + + pwm7_pins: pwm1-2-pins { + mux { + function = "pwm"; + groups = "pwm_ch7_2"; + }; + }; + + wled_pins: wled-pins { + mux { + function = "led"; + groups = "wled"; + }; + }; + + sd0_pins_default: sd0-pins-default { + mux { + function = "sd"; + groups = "sd_0"; + }; + + /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN", + * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1, + * DAT2, DAT3, CMD, CLK for SD respectively. + */ + conf-cmd-data { + pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", + "I2S2_IN","I2S4_OUT"; + input-enable; + drive-strength = <8>; + bias-pull-up; + }; + conf-clk { + pins = "I2S3_OUT"; + drive-strength = <12>; + bias-pull-down; + }; + conf-cd { + pins = "TXD3"; + bias-pull-up; + }; + }; + + sd0_pins_uhs: sd0-pins-uhs { + mux { + function = "sd"; + groups = "sd_0"; + }; + + conf-cmd-data { + pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", + "I2S2_IN","I2S4_OUT"; + input-enable; + bias-pull-up; + }; + + conf-clk { + pins = "I2S3_OUT"; + bias-pull-down; + }; + }; + + /* Serial NAND is shared pin with SPI-NOR */ + serial_nand_pins: serial-nand-pins { + mux { + function = "flash"; + groups = "snfi"; + }; + }; + + spic0_pins: spic0-pins { + mux { + function = "spi"; + groups = "spic0_0"; + }; + }; + + spic1_pins: spic1-pins { + mux { + function = "spi"; + groups = "spic1_0"; + }; + }; + + /* SPI-NOR is shared pin with serial NAND */ + spi_nor_pins: spi-nor-pins { + mux { + function = "flash"; + groups = "spi_nor"; + }; + }; + + /* serial NAND is shared pin with SPI-NOR */ + serial_nand_pins: serial-nand-pins { + mux { + function = "flash"; + groups = "snfi"; + }; + }; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0_0_tx_rx" ; + }; + }; + + uart2_pins: uart2-pins { + mux { + function = "uart"; + groups = "uart2_1_tx_rx" ; + }; + }; + + watchdog_pins: watchdog-pins { + mux { + function = "watchdog"; + groups = "watchdog"; + }; + }; + + wmac_pins: wmac-pins { + mux { + function = "antsel"; + groups = "antsel0", "antsel1", "antsel2", "antsel3", + "antsel4", "antsel5", "antsel6", "antsel7", + "antsel8", "antsel9", "antsel12", "antsel13", + "antsel14", "antsel15", "antsel16", "antsel17"; + }; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm7_pins>; + status = "okay"; +}; + +&pwrap { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_bus_pins>; + + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&sata_phy { + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spic0_pins>; + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spic1_pins>; + status = "okay"; +}; + +&ssusb { + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; + status = "okay"; +}; + +&u3phy { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + +&watchdog { + pinctrl-names = "default"; + pinctrl-0 = <&watchdog_pins>; + status = "okay"; +}; + +&wmac { + pinctrl-names = "default"; + pinctrl-0 = <&wmac_pins>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi new file mode 100644 index 000000000..7bb316922 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -0,0 +1,1010 @@ +/* + * Copyright (c) 2017 MediaTek Inc. + * Author: Ming Huang <ming.huang@mediatek.com> + * Sean Wang <sean.wang@mediatek.com> + * + * SPDX-License-Identifier: (GPL-2.0 OR MIT) + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/mt7622-clk.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/power/mt7622-power.h> +#include <dt-bindings/reset/mt7622-reset.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + compatible = "mediatek,mt7622"; + interrupt-parent = <&sysirq>; + #address-cells = <2>; + #size-cells = <2>; + + cpu_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + opp-300000000 { + opp-hz = /bits/ 64 <30000000>; + opp-microvolt = <950000>; + }; + + opp-437500000 { + opp-hz = /bits/ 64 <437500000>; + opp-microvolt = <1000000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1050000>; + }; + + opp-812500000 { + opp-hz = /bits/ 64 <812500000>; + opp-microvolt = <1100000>; + }; + + opp-1025000000 { + opp-hz = /bits/ 64 <1025000000>; + opp-microvolt = <1150000>; + }; + + opp-1137500000 { + opp-hz = /bits/ 64 <1137500000>; + opp-microvolt = <1200000>; + }; + + opp-1262500000 { + opp-hz = /bits/ 64 <1262500000>; + opp-microvolt = <1250000>; + }; + + opp-1350000000 { + opp-hz = /bits/ 64 <1350000000>; + opp-microvolt = <1310000>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + clocks = <&infracfg CLK_INFRA_MUX1_SEL>, + <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; + enable-method = "psci"; + clock-frequency = <1300000000>; + cci-control-port = <&cci_control2>; + next-level-cache = <&L2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + clocks = <&infracfg CLK_INFRA_MUX1_SEL>, + <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; + enable-method = "psci"; + clock-frequency = <1300000000>; + cci-control-port = <&cci_control2>; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + pwrap_clk: dummy40m { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + #clock-cells = <0>; + }; + + clk25m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "clkxtal"; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@43000000 { + reg = <0 0x43000000 0 0x30000>; + no-map; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + + thermal-sensors = <&thermal 0>; + + trips { + cpu_passive: cpu-passive { + temperature = <47000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_active: cpu-active { + temperature = <67000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_hot: cpu-hot { + temperature = <87000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu-crit { + temperature = <107000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_passive>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip = <&cpu_active>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map2 { + trip = <&cpu_hot>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>; + }; + + infracfg: infracfg@10000000 { + compatible = "mediatek,mt7622-infracfg", + "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pwrap: pwrap@10001000 { + compatible = "mediatek,mt7622-pwrap"; + reg = <0 0x10001000 0 0x250>; + reg-names = "pwrap"; + clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>; + clock-names = "spi", "wrap"; + resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>; + reset-names = "pwrap"; + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pericfg: pericfg@10002000 { + compatible = "mediatek,mt7622-pericfg", + "syscon"; + reg = <0 0x10002000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + scpsys: power-controller@10006000 { + compatible = "mediatek,mt7622-scpsys", + "syscon"; + #power-domain-cells = <1>; + reg = <0 0x10006000 0 0x1000>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>; + infracfg = <&infracfg>; + clocks = <&topckgen CLK_TOP_HIF_SEL>; + clock-names = "hif_sel"; + }; + + cir: cir@10009000 { + compatible = "mediatek,mt7622-cir"; + reg = <0 0x10009000 0 0x1000>; + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_IRRX_PD>, + <&topckgen CLK_TOP_AXI_SEL>; + clock-names = "clk", "bus"; + status = "disabled"; + }; + + sysirq: interrupt-controller@10200620 { + compatible = "mediatek,mt7622-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10200620 0 0x20>; + }; + + efuse: efuse@10206000 { + compatible = "mediatek,mt7622-efuse", + "mediatek,efuse"; + reg = <0 0x10206000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + thermal_calibration: calib@198 { + reg = <0x198 0xc>; + }; + }; + + apmixedsys: apmixedsys@10209000 { + compatible = "mediatek,mt7622-apmixedsys", + "syscon"; + reg = <0 0x10209000 0 0x1000>; + #clock-cells = <1>; + }; + + topckgen: topckgen@10210000 { + compatible = "mediatek,mt7622-topckgen", + "syscon"; + reg = <0 0x10210000 0 0x1000>; + #clock-cells = <1>; + }; + + rng: rng@1020f000 { + compatible = "mediatek,mt7622-rng", + "mediatek,mt7623-rng"; + reg = <0 0x1020f000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_TRNG>; + clock-names = "rng"; + }; + + pio: pinctrl@10211000 { + compatible = "mediatek,mt7622-pinctrl"; + reg = <0 0x10211000 0 0x1000>, + <0 0x10005000 0 0x1000>; + reg-names = "base", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 103>; + interrupt-controller; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + }; + + watchdog: watchdog@10212000 { + compatible = "mediatek,mt7622-wdt", + "mediatek,mt6589-wdt"; + reg = <0 0x10212000 0 0x800>; + }; + + rtc: rtc@10212800 { + compatible = "mediatek,mt7622-rtc", + "mediatek,soc-rtc"; + reg = <0 0x10212800 0 0x200>; + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_RTC>; + clock-names = "rtc"; + }; + + gic: interrupt-controller@10300000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10310000 0 0x1000>, + <0 0x10320000 0 0x1000>, + <0 0x10340000 0 0x2000>, + <0 0x10360000 0 0x2000>; + }; + + cci: cci@10390000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x10390000 0 0x1000>; + ranges = <0 0 0x10390000 0x10000>; + + cci_control0: slave-if@1000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace-lite"; + reg = <0x1000 0x1000>; + }; + + cci_control1: slave-if@4000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x4000 0x1000>; + }; + + cci_control2: slave-if@5000 { + compatible = "arm,cci-400-ctrl-if", "syscon"; + interface-type = "ace"; + reg = <0x5000 0x1000>; + }; + + pmu@9000 { + compatible = "arm,cci-400-pmu,r1"; + reg = <0x9000 0x5000>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + auxadc: adc@11001000 { + compatible = "mediatek,mt7622-auxadc"; + reg = <0 0x11001000 0 0x1000>; + clocks = <&pericfg CLK_PERI_AUXADC_PD>; + clock-names = "main"; + #io-channel-cells = <1>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt7622-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&pericfg CLK_PERI_UART0_PD>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt7622-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&pericfg CLK_PERI_UART1_PD>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt7622-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x400>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&pericfg CLK_PERI_UART2_PD>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart3: serial@11005000 { + compatible = "mediatek,mt7622-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11005000 0 0x400>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&pericfg CLK_PERI_UART3_PD>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + pwm: pwm@11006000 { + compatible = "mediatek,mt7622-pwm"; + reg = <0 0x11006000 0 0x1000>; + #pwm-cells = <2>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_PWM_SEL>, + <&pericfg CLK_PERI_PWM_PD>, + <&pericfg CLK_PERI_PWM1_PD>, + <&pericfg CLK_PERI_PWM2_PD>, + <&pericfg CLK_PERI_PWM3_PD>, + <&pericfg CLK_PERI_PWM4_PD>, + <&pericfg CLK_PERI_PWM5_PD>, + <&pericfg CLK_PERI_PWM6_PD>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4", + "pwm5", "pwm6"; + status = "disabled"; + }; + + i2c0: i2c@11007000 { + compatible = "mediatek,mt7622-i2c"; + reg = <0 0x11007000 0 0x90>, + <0 0x11000100 0 0x80>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C0_PD>, + <&pericfg CLK_PERI_AP_DMA_PD>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@11008000 { + compatible = "mediatek,mt7622-i2c"; + reg = <0 0x11008000 0 0x90>, + <0 0x11000180 0 0x80>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C1_PD>, + <&pericfg CLK_PERI_AP_DMA_PD>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11009000 { + compatible = "mediatek,mt7622-i2c"; + reg = <0 0x11009000 0 0x90>, + <0 0x11000200 0 0x80>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C2_PD>, + <&pericfg CLK_PERI_AP_DMA_PD>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@1100a000 { + compatible = "mediatek,mt7622-spi"; + reg = <0 0x1100a000 0 0x100>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, + <&topckgen CLK_TOP_SPI0_SEL>, + <&pericfg CLK_PERI_SPI0_PD>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + thermal: thermal@1100b000 { + #thermal-sensor-cells = <1>; + compatible = "mediatek,mt7622-thermal"; + reg = <0 0x1100b000 0 0x1000>; + interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_THERM_PD>, + <&pericfg CLK_PERI_AUXADC_PD>; + clock-names = "therm", "auxadc"; + resets = <&pericfg MT7622_PERI_THERM_SW_RST>; + reset-names = "therm"; + mediatek,auxadc = <&auxadc>; + mediatek,apmixedsys = <&apmixedsys>; + nvmem-cells = <&thermal_calibration>; + nvmem-cell-names = "calibration-data"; + }; + + btif: serial@1100c000 { + compatible = "mediatek,mt7622-btif", + "mediatek,mtk-btif"; + reg = <0 0x1100c000 0 0x1000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_BTIF_PD>; + clock-names = "main"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + + bluetooth { + compatible = "mediatek,mt7622-bluetooth"; + power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>; + clocks = <&clk25m>; + clock-names = "ref"; + }; + }; + + nandc: nfi@1100d000 { + compatible = "mediatek,mt7622-nfc"; + reg = <0 0x1100D000 0 0x1000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_NFI_PD>, + <&pericfg CLK_PERI_SNFI_PD>; + clock-names = "nfi_clk", "pad_clk"; + ecc-engine = <&bch>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + snfi: spi@1100d000 { + compatible = "mediatek,mt7622-snand"; + reg = <0 0x1100d000 0 0x1000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>; + clock-names = "nfi_clk", "pad_clk"; + nand-ecc-engine = <&bch>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + bch: ecc@1100e000 { + compatible = "mediatek,mt7622-ecc"; + reg = <0 0x1100e000 0 0x1000>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_NFIECC_PD>; + clock-names = "nfiecc_clk"; + status = "disabled"; + }; + + nor_flash: spi@11014000 { + compatible = "mediatek,mt7622-nor", + "mediatek,mt8173-nor"; + reg = <0 0x11014000 0 0xe0>; + clocks = <&pericfg CLK_PERI_FLASH_PD>, + <&topckgen CLK_TOP_FLASH_SEL>; + clock-names = "spi", "sf"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@11016000 { + compatible = "mediatek,mt7622-spi"; + reg = <0 0x11016000 0 0x100>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, + <&topckgen CLK_TOP_SPI1_SEL>, + <&pericfg CLK_PERI_SPI1_PD>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart4: serial@11019000 { + compatible = "mediatek,mt7622-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11019000 0 0x400>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&pericfg CLK_PERI_UART4_PD>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + audsys: clock-controller@11220000 { + compatible = "mediatek,mt7622-audsys", "syscon"; + reg = <0 0x11220000 0 0x2000>; + #clock-cells = <1>; + + afe: audio-controller { + compatible = "mediatek,mt7622-audio"; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "afe", "asys"; + + clocks = <&infracfg CLK_INFRA_AUDIO_PD>, + <&topckgen CLK_TOP_AUD1_SEL>, + <&topckgen CLK_TOP_AUD2_SEL>, + <&topckgen CLK_TOP_A1SYS_HP_DIV_PD>, + <&topckgen CLK_TOP_A2SYS_HP_DIV_PD>, + <&topckgen CLK_TOP_I2S0_MCK_SEL>, + <&topckgen CLK_TOP_I2S1_MCK_SEL>, + <&topckgen CLK_TOP_I2S2_MCK_SEL>, + <&topckgen CLK_TOP_I2S3_MCK_SEL>, + <&topckgen CLK_TOP_I2S0_MCK_DIV>, + <&topckgen CLK_TOP_I2S1_MCK_DIV>, + <&topckgen CLK_TOP_I2S2_MCK_DIV>, + <&topckgen CLK_TOP_I2S3_MCK_DIV>, + <&topckgen CLK_TOP_I2S0_MCK_DIV_PD>, + <&topckgen CLK_TOP_I2S1_MCK_DIV_PD>, + <&topckgen CLK_TOP_I2S2_MCK_DIV_PD>, + <&topckgen CLK_TOP_I2S3_MCK_DIV_PD>, + <&audsys CLK_AUDIO_I2SO1>, + <&audsys CLK_AUDIO_I2SO2>, + <&audsys CLK_AUDIO_I2SO3>, + <&audsys CLK_AUDIO_I2SO4>, + <&audsys CLK_AUDIO_I2SIN1>, + <&audsys CLK_AUDIO_I2SIN2>, + <&audsys CLK_AUDIO_I2SIN3>, + <&audsys CLK_AUDIO_I2SIN4>, + <&audsys CLK_AUDIO_ASRCO1>, + <&audsys CLK_AUDIO_ASRCO2>, + <&audsys CLK_AUDIO_ASRCO3>, + <&audsys CLK_AUDIO_ASRCO4>, + <&audsys CLK_AUDIO_AFE>, + <&audsys CLK_AUDIO_AFE_CONN>, + <&audsys CLK_AUDIO_A1SYS>, + <&audsys CLK_AUDIO_A2SYS>; + + clock-names = "infra_sys_audio_clk", + "top_audio_mux1_sel", + "top_audio_mux2_sel", + "top_audio_a1sys_hp", + "top_audio_a2sys_hp", + "i2s0_src_sel", + "i2s1_src_sel", + "i2s2_src_sel", + "i2s3_src_sel", + "i2s0_src_div", + "i2s1_src_div", + "i2s2_src_div", + "i2s3_src_div", + "i2s0_mclk_en", + "i2s1_mclk_en", + "i2s2_mclk_en", + "i2s3_mclk_en", + "i2so0_hop_ck", + "i2so1_hop_ck", + "i2so2_hop_ck", + "i2so3_hop_ck", + "i2si0_hop_ck", + "i2si1_hop_ck", + "i2si2_hop_ck", + "i2si3_hop_ck", + "asrc0_out_ck", + "asrc1_out_ck", + "asrc2_out_ck", + "asrc3_out_ck", + "audio_afe_pd", + "audio_afe_conn_pd", + "audio_a1sys_pd", + "audio_a2sys_pd"; + + assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>, + <&topckgen CLK_TOP_A2SYS_HP_SEL>, + <&topckgen CLK_TOP_A1SYS_HP_DIV>, + <&topckgen CLK_TOP_A2SYS_HP_DIV>; + assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL>, + <&topckgen CLK_TOP_AUD2PLL>; + assigned-clock-rates = <0>, <0>, <49152000>, <45158400>; + }; + }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt7622-mmc"; + reg = <0 0x11230000 0 0x1000>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_MSDC30_0_PD>, + <&topckgen CLK_TOP_MSDC50_0_SEL>; + clock-names = "source", "hclk"; + resets = <&pericfg MT7622_PERI_MSDC0_SW_RST>; + reset-names = "hrst"; + status = "disabled"; + }; + + mmc1: mmc@11240000 { + compatible = "mediatek,mt7622-mmc"; + reg = <0 0x11240000 0 0x1000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_MSDC30_1_PD>, + <&topckgen CLK_TOP_AXI_SEL>; + clock-names = "source", "hclk"; + resets = <&pericfg MT7622_PERI_MSDC1_SW_RST>; + reset-names = "hrst"; + status = "disabled"; + }; + + wmac: wmac@18000000 { + compatible = "mediatek,mt7622-wmac"; + reg = <0 0x18000000 0 0x100000>; + interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>; + + mediatek,infracfg = <&infracfg>; + status = "disabled"; + + power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>; + }; + + ssusbsys: ssusbsys@1a000000 { + compatible = "mediatek,mt7622-ssusbsys", + "syscon"; + reg = <0 0x1a000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + ssusb: usb@1a0c0000 { + compatible = "mediatek,mt7622-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x1a0c0000 0 0x01000>, + <0 0x1a0c4700 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>; + clocks = <&ssusbsys CLK_SSUSB_SYS_EN>, + <&ssusbsys CLK_SSUSB_REF_EN>, + <&ssusbsys CLK_SSUSB_MCU_EN>, + <&ssusbsys CLK_SSUSB_DMA_EN>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>, + <&u2port1 PHY_TYPE_USB2>; + + status = "disabled"; + }; + + u3phy: t-phy@1a0c4000 { + compatible = "mediatek,mt7622-tphy", + "mediatek,generic-tphy-v1"; + reg = <0 0x1a0c4000 0 0x700>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + u2port0: usb-phy@1a0c4800 { + reg = <0 0x1a0c4800 0 0x0100>; + #phy-cells = <1>; + clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>; + clock-names = "ref"; + }; + + u3port0: usb-phy@1a0c4900 { + reg = <0 0x1a0c4900 0 0x0700>; + #phy-cells = <1>; + clocks = <&clk25m>; + clock-names = "ref"; + }; + + u2port1: usb-phy@1a0c5000 { + reg = <0 0x1a0c5000 0 0x0100>; + #phy-cells = <1>; + clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>; + clock-names = "ref"; + }; + }; + + pciesys: pciesys@1a100800 { + compatible = "mediatek,mt7622-pciesys", + "syscon"; + reg = <0 0x1a100800 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pciecfg: pciecfg@1a140000 { + compatible = "mediatek,generic-pciecfg", "syscon"; + reg = <0 0x1a140000 0 0x1000>; + }; + + pcie0: pcie@1a143000 { + compatible = "mediatek,mt7622-pcie"; + device_type = "pci"; + reg = <0 0x1a143000 0 0x1000>; + reg-names = "port0"; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "pcie_irq"; + clocks = <&pciesys CLK_PCIE_P0_MAC_EN>, + <&pciesys CLK_PCIE_P0_AHB_EN>, + <&pciesys CLK_PCIE_P0_AUX_EN>, + <&pciesys CLK_PCIE_P0_AXI_EN>, + <&pciesys CLK_PCIE_P0_OBFF_EN>, + <&pciesys CLK_PCIE_P0_PIPE_EN>; + clock-names = "sys_ck0", "ahb_ck0", "aux_ck0", + "axi_ck0", "obff_ck0", "pipe_ck0"; + + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + pcie1: pcie@1a145000 { + compatible = "mediatek,mt7622-pcie"; + device_type = "pci"; + reg = <0 0x1a145000 0 0x1000>; + reg-names = "port1"; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "pcie_irq"; + clocks = <&pciesys CLK_PCIE_P1_MAC_EN>, + /* designer has connect RC1 with p0_ahb clock */ + <&pciesys CLK_PCIE_P0_AHB_EN>, + <&pciesys CLK_PCIE_P1_AUX_EN>, + <&pciesys CLK_PCIE_P1_AXI_EN>, + <&pciesys CLK_PCIE_P1_OBFF_EN>, + <&pciesys CLK_PCIE_P1_PIPE_EN>; + clock-names = "sys_ck1", "ahb_ck1", "aux_ck1", + "axi_ck1", "obff_ck1", "pipe_ck1"; + + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + pcie_intc1: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + sata: sata@1a200000 { + compatible = "mediatek,mt7622-ahci", + "mediatek,mtk-ahci"; + reg = <0 0x1a200000 0 0x1100>; + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hostc"; + clocks = <&pciesys CLK_SATA_AHB_EN>, + <&pciesys CLK_SATA_AXI_EN>, + <&pciesys CLK_SATA_ASIC_EN>, + <&pciesys CLK_SATA_RBC_EN>, + <&pciesys CLK_SATA_PM_EN>; + clock-names = "ahb", "axi", "asic", "rbc", "pm"; + phys = <&sata_port PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; + resets = <&pciesys MT7622_SATA_AXI_BUS_RST>, + <&pciesys MT7622_SATA_PHY_SW_RST>, + <&pciesys MT7622_SATA_PHY_REG_RST>; + reset-names = "axi", "sw", "reg"; + mediatek,phy-mode = <&pciesys>; + status = "disabled"; + }; + + sata_phy: t-phy@1a243000 { + compatible = "mediatek,mt7622-tphy", + "mediatek,generic-tphy-v1"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + sata_port: sata-phy@1a243000 { + reg = <0 0x1a243000 0 0x0100>; + clocks = <&topckgen CLK_TOP_ETH_500M>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + + hifsys: syscon@1af00000 { + compatible = "mediatek,mt7622-hifsys", "syscon"; + reg = <0 0x1af00000 0 0x70>; + }; + + ethsys: syscon@1b000000 { + compatible = "mediatek,mt7622-ethsys", + "syscon"; + reg = <0 0x1b000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + hsdma: dma-controller@1b007000 { + compatible = "mediatek,mt7622-hsdma"; + reg = <0 0x1b007000 0 0x1000>; + interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_LOW>; + clocks = <ðsys CLK_ETH_HSDMA_EN>; + clock-names = "hsdma"; + power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>; + #dma-cells = <1>; + dma-requests = <3>; + }; + + pcie_mirror: pcie-mirror@10000400 { + compatible = "mediatek,mt7622-pcie-mirror", + "syscon"; + reg = <0 0x10000400 0 0x10>; + }; + + wed0: wed@1020a000 { + compatible = "mediatek,mt7622-wed", + "syscon"; + reg = <0 0x1020a000 0 0x1000>; + interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_LOW>; + }; + + wed1: wed@1020b000 { + compatible = "mediatek,mt7622-wed", + "syscon"; + reg = <0 0x1020b000 0 0x1000>; + interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_LOW>; + }; + + eth: ethernet@1b100000 { + compatible = "mediatek,mt7622-eth", + "mediatek,mt2701-eth", + "syscon"; + reg = <0 0x1b100000 0 0x20000>; + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_ETH_SEL>, + <ðsys CLK_ETH_ESW_EN>, + <ðsys CLK_ETH_GP0_EN>, + <ðsys CLK_ETH_GP1_EN>, + <ðsys CLK_ETH_GP2_EN>, + <&sgmiisys CLK_SGMII_TX250M_EN>, + <&sgmiisys CLK_SGMII_RX250M_EN>, + <&sgmiisys CLK_SGMII_CDR_REF>, + <&sgmiisys CLK_SGMII_CDR_FB>, + <&topckgen CLK_TOP_SGMIIPLL>, + <&apmixedsys CLK_APMIXED_ETH2PLL>; + clock-names = "ethif", "esw", "gp0", "gp1", "gp2", + "sgmii_tx250m", "sgmii_rx250m", + "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", + "eth2pll"; + power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>; + mediatek,ethsys = <ðsys>; + mediatek,sgmiisys = <&sgmiisys>; + cci-control-port = <&cci_control2>; + mediatek,wed = <&wed0>, <&wed1>; + mediatek,pcie-mirror = <&pcie_mirror>; + mediatek,hifsys = <&hifsys>; + dma-coherent; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sgmiisys: sgmiisys@1b128000 { + compatible = "mediatek,mt7622-sgmiisys", + "syscon"; + reg = <0 0x1b128000 0 0x3000>; + #clock-cells = <1>; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts new file mode 100644 index 000000000..afe37b702 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih <sam.shih@mediatek.com> + */ + +/dts-v1/; +#include "mt7986a.dtsi" + +/ { + model = "MediaTek MT7986a RFB"; + compatible = "mediatek,mt7986a-rfb"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&mdio { + switch: switch@0 { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 5 0>; + }; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan0"; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan3"; + }; + + port@4 { + reg = <4>; + label = "lan4"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + +&wifi { + status = "okay"; + pinctrl-names = "default", "dbdc"; + pinctrl-0 = <&wf_2g_5g_pins>; + pinctrl-1 = <&wf_dbdc_pins>; +}; + +&pio { + uart1_pins: uart1-pins { + mux { + function = "uart"; + groups = "uart1"; + }; + }; + + uart2_pins: uart2-pins { + mux { + function = "uart"; + groups = "uart2"; + }; + }; + + wf_2g_5g_pins: wf-2g-5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + wf_dbdc_pins: wf-dbdc-pins { + mux { + function = "wifi"; + groups = "wf_dbdc"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA"; + drive-strength = <4>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi new file mode 100644 index 000000000..fc338bd49 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -0,0 +1,312 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih <sam.shih@mediatek.com> + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/mt7986-clk.h> +#include <dt-bindings/reset/mt7986-resets.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + clk40m: oscillator-40m { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + #clock-cells = <0>; + clock-output-names = "clkxtal"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x0>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x1>; + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x2>; + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + enable-method = "psci"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + #cooling-cells = <2>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@43000000 { + reg = <0 0x43000000 0 0x30000>; + no-map; + }; + + wmcpu_emi: wmcpu-reserved@4fc00000 { + no-map; + reg = <0 0x4fc00000 0 0x00100000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x10000>, /* GICD */ + <0 0x0c080000 0 0x80000>, /* GICR */ + <0 0x0c400000 0 0x2000>, /* GICC */ + <0 0x0c410000 0 0x1000>, /* GICH */ + <0 0x0c420000 0 0x2000>; /* GICV */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + infracfg: infracfg@10001000 { + compatible = "mediatek,mt7986-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + wed_pcie: wed-pcie@10003000 { + compatible = "mediatek,mt7986-wed-pcie", + "syscon"; + reg = <0 0x10003000 0 0x10>; + }; + + topckgen: topckgen@1001b000 { + compatible = "mediatek,mt7986-topckgen", "syscon"; + reg = <0 0x1001B000 0 0x1000>; + #clock-cells = <1>; + }; + + watchdog: watchdog@1001c000 { + compatible = "mediatek,mt7986-wdt"; + reg = <0 0x1001c000 0 0x1000>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + #reset-cells = <1>; + status = "disabled"; + }; + + apmixedsys: apmixedsys@1001e000 { + compatible = "mediatek,mt7986-apmixedsys"; + reg = <0 0x1001E000 0 0x1000>; + #clock-cells = <1>; + }; + + pio: pinctrl@1001f000 { + compatible = "mediatek,mt7986a-pinctrl"; + reg = <0 0x1001f000 0 0x1000>, + <0 0x11c30000 0 0x1000>, + <0 0x11c40000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11e30000 0 0x1000>, + <0 0x11f00000 0 0x1000>, + <0 0x11f10000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt", + "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 100>; + interrupt-controller; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + }; + + sgmiisys0: syscon@10060000 { + compatible = "mediatek,mt7986-sgmiisys_0", + "syscon"; + reg = <0 0x10060000 0 0x1000>; + #clock-cells = <1>; + }; + + sgmiisys1: syscon@10070000 { + compatible = "mediatek,mt7986-sgmiisys_1", + "syscon"; + reg = <0 0x10070000 0 0x1000>; + #clock-cells = <1>; + }; + + trng: rng@1020f000 { + compatible = "mediatek,mt7986-rng", + "mediatek,mt7623-rng"; + reg = <0 0x1020f000 0 0x100>; + clocks = <&infracfg CLK_INFRA_TRNG_CK>; + clock-names = "rng"; + status = "disabled"; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt7986-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg CLK_INFRA_UART0_SEL>, + <&infracfg CLK_INFRA_UART0_CK>; + clock-names = "baud", "bus"; + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_UART0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, + <&topckgen CLK_TOP_UART_SEL>; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt7986-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg CLK_INFRA_UART1_SEL>, + <&infracfg CLK_INFRA_UART1_CK>; + clock-names = "baud", "bus"; + assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt7986-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x400>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg CLK_INFRA_UART2_SEL>, + <&infracfg CLK_INFRA_UART2_CK>; + clock-names = "baud", "bus"; + assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>; + status = "disabled"; + }; + + ethsys: syscon@15000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mediatek,mt7986-ethsys", + "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + wed0: wed@15010000 { + compatible = "mediatek,mt7986-wed", + "syscon"; + reg = <0 0x15010000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; + }; + + wed1: wed@15011000 { + compatible = "mediatek,mt7986-wed", + "syscon"; + reg = <0 0x15011000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; + }; + + eth: ethernet@15100000 { + compatible = "mediatek,mt7986-eth"; + reg = <0 0x15100000 0 0x80000>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; + clocks = <ðsys CLK_ETH_FE_EN>, + <ðsys CLK_ETH_GP2_EN>, + <ðsys CLK_ETH_GP1_EN>, + <ðsys CLK_ETH_WOCPU1_EN>, + <ðsys CLK_ETH_WOCPU0_EN>, + <&sgmiisys0 CLK_SGMII0_TX250M_EN>, + <&sgmiisys0 CLK_SGMII0_RX250M_EN>, + <&sgmiisys0 CLK_SGMII0_CDR_REF>, + <&sgmiisys0 CLK_SGMII0_CDR_FB>, + <&sgmiisys1 CLK_SGMII1_TX250M_EN>, + <&sgmiisys1 CLK_SGMII1_RX250M_EN>, + <&sgmiisys1 CLK_SGMII1_CDR_REF>, + <&sgmiisys1 CLK_SGMII1_CDR_FB>, + <&topckgen CLK_TOP_NETSYS_SEL>, + <&topckgen CLK_TOP_NETSYS_500M_SEL>; + clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0", + "sgmii_tx250m", "sgmii_rx250m", + "sgmii_cdr_ref", "sgmii_cdr_fb", + "sgmii2_tx250m", "sgmii2_rx250m", + "sgmii2_cdr_ref", "sgmii2_cdr_fb", + "netsys0", "netsys1"; + assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, + <&topckgen CLK_TOP_SGM_325M_SEL>; + assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, + <&apmixedsys CLK_APMIXED_SGMPLL>; + mediatek,ethsys = <ðsys>; + mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; + mediatek,wed-pcie = <&wed_pcie>; + mediatek,wed = <&wed0>, <&wed1>; + #reset-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + wifi: wifi@18000000 { + compatible = "mediatek,mt7986-wmac"; + resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; + reset-names = "consys"; + clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>, + <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; + clock-names = "mcu", "ap2conn"; + reg = <0 0x18000000 0 0x1000000>, + <0 0x10003000 0 0x1000>, + <0 0x11d10000 0 0x1000>; + interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; + memory-region = <&wmcpu_emi>; + }; + }; + +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts new file mode 100644 index 000000000..3443013b5 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih <sam.shih@mediatek.com> + */ + +/dts-v1/; +#include "mt7986b.dtsi" + +/ { + model = "MediaTek MT7986b RFB"; + compatible = "mediatek,mt7986b-rfb"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + switch@0 { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 5 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan0"; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan3"; + }; + + port@4 { + reg = <4>; + label = "lan4"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; + }; +}; + +&wifi { + status = "okay"; + pinctrl-names = "default", "dbdc"; + pinctrl-0 = <&wf_2g_5g_pins>; + pinctrl-1 = <&wf_dbdc_pins>; +}; + +&pio { + wf_2g_5g_pins: wf-2g-5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + wf_dbdc_pins: wf-dbdc-pins { + mux { + function = "wifi"; + groups = "wf_dbdc"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA"; + drive-strength = <4>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi new file mode 100644 index 000000000..23923b9f8 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih <sam.shih@mediatek.com> + */ + +#include "mt7986a.dtsi" + +&pio { + compatible = "mediatek,mt7986b-pinctrl"; + gpio-ranges = <&pio 0 0 41>, <&pio 66 66 35>; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8167-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt8167-pinfunc.h new file mode 100644 index 000000000..061c3255a --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8167-pinfunc.h @@ -0,0 +1,744 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 MediaTek Inc. + */ +#ifndef __DTS_MT8167_PINFUNC_H +#define __DTS_MT8167_PINFUNC_H + +#include <dt-bindings/pinctrl/mt65xx.h> + +#define MT8167_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT8167_PIN_0_EINT0__FUNC_PWM_B (MTK_PIN_NO(0) | 1) +#define MT8167_PIN_0_EINT0__FUNC_DPI_CK (MTK_PIN_NO(0) | 2) +#define MT8167_PIN_0_EINT0__FUNC_I2S2_BCK (MTK_PIN_NO(0) | 3) +#define MT8167_PIN_0_EINT0__FUNC_EXT_TXD0 (MTK_PIN_NO(0) | 4) +#define MT8167_PIN_0_EINT0__FUNC_SQICS (MTK_PIN_NO(0) | 6) +#define MT8167_PIN_0_EINT0__FUNC_DBG_MON_A_6 (MTK_PIN_NO(0) | 7) + +#define MT8167_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT8167_PIN_1_EINT1__FUNC_PWM_C (MTK_PIN_NO(1) | 1) +#define MT8167_PIN_1_EINT1__FUNC_DPI_D12 (MTK_PIN_NO(1) | 2) +#define MT8167_PIN_1_EINT1__FUNC_I2S2_DI (MTK_PIN_NO(1) | 3) +#define MT8167_PIN_1_EINT1__FUNC_EXT_TXD1 (MTK_PIN_NO(1) | 4) +#define MT8167_PIN_1_EINT1__FUNC_CONN_MCU_TDO (MTK_PIN_NO(1) | 5) +#define MT8167_PIN_1_EINT1__FUNC_SQISO (MTK_PIN_NO(1) | 6) +#define MT8167_PIN_1_EINT1__FUNC_DBG_MON_A_7 (MTK_PIN_NO(1) | 7) + +#define MT8167_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT8167_PIN_2_EINT2__FUNC_CLKM0 (MTK_PIN_NO(2) | 1) +#define MT8167_PIN_2_EINT2__FUNC_DPI_D13 (MTK_PIN_NO(2) | 2) +#define MT8167_PIN_2_EINT2__FUNC_I2S2_LRCK (MTK_PIN_NO(2) | 3) +#define MT8167_PIN_2_EINT2__FUNC_EXT_TXD2 (MTK_PIN_NO(2) | 4) +#define MT8167_PIN_2_EINT2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(2) | 5) +#define MT8167_PIN_2_EINT2__FUNC_SQISI (MTK_PIN_NO(2) | 6) +#define MT8167_PIN_2_EINT2__FUNC_DBG_MON_A_8 (MTK_PIN_NO(2) | 7) + +#define MT8167_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT8167_PIN_3_EINT3__FUNC_CLKM1 (MTK_PIN_NO(3) | 1) +#define MT8167_PIN_3_EINT3__FUNC_DPI_D14 (MTK_PIN_NO(3) | 2) +#define MT8167_PIN_3_EINT3__FUNC_SPI_MI (MTK_PIN_NO(3) | 3) +#define MT8167_PIN_3_EINT3__FUNC_EXT_TXD3 (MTK_PIN_NO(3) | 4) +#define MT8167_PIN_3_EINT3__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(3) | 5) +#define MT8167_PIN_3_EINT3__FUNC_SQIWP (MTK_PIN_NO(3) | 6) +#define MT8167_PIN_3_EINT3__FUNC_DBG_MON_A_9 (MTK_PIN_NO(3) | 7) + +#define MT8167_PIN_4_EINT4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT8167_PIN_4_EINT4__FUNC_CLKM2 (MTK_PIN_NO(4) | 1) +#define MT8167_PIN_4_EINT4__FUNC_DPI_D15 (MTK_PIN_NO(4) | 2) +#define MT8167_PIN_4_EINT4__FUNC_SPI_MO (MTK_PIN_NO(4) | 3) +#define MT8167_PIN_4_EINT4__FUNC_EXT_TXC (MTK_PIN_NO(4) | 4) +#define MT8167_PIN_4_EINT4__FUNC_CONN_MCU_TCK (MTK_PIN_NO(4) | 5) +#define MT8167_PIN_4_EINT4__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(4) | 6) +#define MT8167_PIN_4_EINT4__FUNC_DBG_MON_A_10 (MTK_PIN_NO(4) | 7) + +#define MT8167_PIN_5_EINT5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT8167_PIN_5_EINT5__FUNC_UCTS2 (MTK_PIN_NO(5) | 1) +#define MT8167_PIN_5_EINT5__FUNC_DPI_D16 (MTK_PIN_NO(5) | 2) +#define MT8167_PIN_5_EINT5__FUNC_SPI_CSB (MTK_PIN_NO(5) | 3) +#define MT8167_PIN_5_EINT5__FUNC_EXT_RXER (MTK_PIN_NO(5) | 4) +#define MT8167_PIN_5_EINT5__FUNC_CONN_MCU_TDI (MTK_PIN_NO(5) | 5) +#define MT8167_PIN_5_EINT5__FUNC_CONN_TEST_CK (MTK_PIN_NO(5) | 6) +#define MT8167_PIN_5_EINT5__FUNC_DBG_MON_A_11 (MTK_PIN_NO(5) | 7) + +#define MT8167_PIN_6_EINT6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT8167_PIN_6_EINT6__FUNC_URTS2 (MTK_PIN_NO(6) | 1) +#define MT8167_PIN_6_EINT6__FUNC_DPI_D17 (MTK_PIN_NO(6) | 2) +#define MT8167_PIN_6_EINT6__FUNC_SPI_CLK (MTK_PIN_NO(6) | 3) +#define MT8167_PIN_6_EINT6__FUNC_EXT_RXC (MTK_PIN_NO(6) | 4) +#define MT8167_PIN_6_EINT6__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(6) | 5) +#define MT8167_PIN_6_EINT6__FUNC_MM_TEST_CK (MTK_PIN_NO(6) | 6) +#define MT8167_PIN_6_EINT6__FUNC_DBG_MON_A_12 (MTK_PIN_NO(6) | 7) + +#define MT8167_PIN_7_EINT7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define MT8167_PIN_7_EINT7__FUNC_SQIRST (MTK_PIN_NO(7) | 1) +#define MT8167_PIN_7_EINT7__FUNC_DPI_D6 (MTK_PIN_NO(7) | 2) +#define MT8167_PIN_7_EINT7__FUNC_SDA1_0 (MTK_PIN_NO(7) | 3) +#define MT8167_PIN_7_EINT7__FUNC_EXT_RXDV (MTK_PIN_NO(7) | 4) +#define MT8167_PIN_7_EINT7__FUNC_CONN_MCU_TMS (MTK_PIN_NO(7) | 5) +#define MT8167_PIN_7_EINT7__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(7) | 6) +#define MT8167_PIN_7_EINT7__FUNC_DBG_MON_A_13 (MTK_PIN_NO(7) | 7) + +#define MT8167_PIN_8_EINT8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define MT8167_PIN_8_EINT8__FUNC_SQICK (MTK_PIN_NO(8) | 1) +#define MT8167_PIN_8_EINT8__FUNC_CLKM3 (MTK_PIN_NO(8) | 2) +#define MT8167_PIN_8_EINT8__FUNC_SCL1_0 (MTK_PIN_NO(8) | 3) +#define MT8167_PIN_8_EINT8__FUNC_EXT_RXD0 (MTK_PIN_NO(8) | 4) +#define MT8167_PIN_8_EINT8__FUNC_ANT_SEL0 (MTK_PIN_NO(8) | 5) +#define MT8167_PIN_8_EINT8__FUNC_DPI_D7 (MTK_PIN_NO(8) | 6) +#define MT8167_PIN_8_EINT8__FUNC_DBG_MON_A_14 (MTK_PIN_NO(8) | 7) + +#define MT8167_PIN_9_EINT9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define MT8167_PIN_9_EINT9__FUNC_CLKM4 (MTK_PIN_NO(9) | 1) +#define MT8167_PIN_9_EINT9__FUNC_SDA2_0 (MTK_PIN_NO(9) | 2) +#define MT8167_PIN_9_EINT9__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(9) | 3) +#define MT8167_PIN_9_EINT9__FUNC_EXT_RXD1 (MTK_PIN_NO(9) | 4) +#define MT8167_PIN_9_EINT9__FUNC_ANT_SEL1 (MTK_PIN_NO(9) | 5) +#define MT8167_PIN_9_EINT9__FUNC_DPI_D8 (MTK_PIN_NO(9) | 6) +#define MT8167_PIN_9_EINT9__FUNC_DBG_MON_A_15 (MTK_PIN_NO(9) | 7) + +#define MT8167_PIN_10_EINT10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define MT8167_PIN_10_EINT10__FUNC_CLKM5 (MTK_PIN_NO(10) | 1) +#define MT8167_PIN_10_EINT10__FUNC_SCL2_0 (MTK_PIN_NO(10) | 2) +#define MT8167_PIN_10_EINT10__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(10) | 3) +#define MT8167_PIN_10_EINT10__FUNC_EXT_RXD2 (MTK_PIN_NO(10) | 4) +#define MT8167_PIN_10_EINT10__FUNC_ANT_SEL2 (MTK_PIN_NO(10) | 5) +#define MT8167_PIN_10_EINT10__FUNC_DPI_D9 (MTK_PIN_NO(10) | 6) +#define MT8167_PIN_10_EINT10__FUNC_DBG_MON_A_16 (MTK_PIN_NO(10) | 7) + +#define MT8167_PIN_11_EINT11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define MT8167_PIN_11_EINT11__FUNC_CLKM4 (MTK_PIN_NO(11) | 1) +#define MT8167_PIN_11_EINT11__FUNC_PWM_C (MTK_PIN_NO(11) | 2) +#define MT8167_PIN_11_EINT11__FUNC_CONN_TEST_CK (MTK_PIN_NO(11) | 3) +#define MT8167_PIN_11_EINT11__FUNC_ANT_SEL3 (MTK_PIN_NO(11) | 4) +#define MT8167_PIN_11_EINT11__FUNC_DPI_D10 (MTK_PIN_NO(11) | 5) +#define MT8167_PIN_11_EINT11__FUNC_EXT_RXD3 (MTK_PIN_NO(11) | 6) +#define MT8167_PIN_11_EINT11__FUNC_DBG_MON_A_17 (MTK_PIN_NO(11) | 7) + +#define MT8167_PIN_12_EINT12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define MT8167_PIN_12_EINT12__FUNC_CLKM5 (MTK_PIN_NO(12) | 1) +#define MT8167_PIN_12_EINT12__FUNC_PWM_A (MTK_PIN_NO(12) | 2) +#define MT8167_PIN_12_EINT12__FUNC_SPDIF_OUT (MTK_PIN_NO(12) | 3) +#define MT8167_PIN_12_EINT12__FUNC_ANT_SEL4 (MTK_PIN_NO(12) | 4) +#define MT8167_PIN_12_EINT12__FUNC_DPI_D11 (MTK_PIN_NO(12) | 5) +#define MT8167_PIN_12_EINT12__FUNC_EXT_TXEN (MTK_PIN_NO(12) | 6) +#define MT8167_PIN_12_EINT12__FUNC_DBG_MON_A_18 (MTK_PIN_NO(12) | 7) + +#define MT8167_PIN_13_EINT13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define MT8167_PIN_13_EINT13__FUNC_TSF_IN (MTK_PIN_NO(13) | 3) +#define MT8167_PIN_13_EINT13__FUNC_ANT_SEL5 (MTK_PIN_NO(13) | 4) +#define MT8167_PIN_13_EINT13__FUNC_DPI_D0 (MTK_PIN_NO(13) | 5) +#define MT8167_PIN_13_EINT13__FUNC_SPDIF_IN (MTK_PIN_NO(13) | 6) +#define MT8167_PIN_13_EINT13__FUNC_DBG_MON_A_19 (MTK_PIN_NO(13) | 7) + +#define MT8167_PIN_14_EINT14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define MT8167_PIN_14_EINT14__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(14) | 2) +#define MT8167_PIN_14_EINT14__FUNC_TDM_RX_MCK (MTK_PIN_NO(14) | 3) +#define MT8167_PIN_14_EINT14__FUNC_ANT_SEL1 (MTK_PIN_NO(14) | 4) +#define MT8167_PIN_14_EINT14__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(14) | 5) +#define MT8167_PIN_14_EINT14__FUNC_NCLE (MTK_PIN_NO(14) | 6) +#define MT8167_PIN_14_EINT14__FUNC_DBG_MON_B_8 (MTK_PIN_NO(14) | 7) + +#define MT8167_PIN_15_EINT15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define MT8167_PIN_15_EINT15__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(15) | 2) +#define MT8167_PIN_15_EINT15__FUNC_TDM_RX_BCK (MTK_PIN_NO(15) | 3) +#define MT8167_PIN_15_EINT15__FUNC_ANT_SEL2 (MTK_PIN_NO(15) | 4) +#define MT8167_PIN_15_EINT15__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(15) | 5) +#define MT8167_PIN_15_EINT15__FUNC_NCEB1 (MTK_PIN_NO(15) | 6) +#define MT8167_PIN_15_EINT15__FUNC_DBG_MON_B_9 (MTK_PIN_NO(15) | 7) + +#define MT8167_PIN_16_EINT16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define MT8167_PIN_16_EINT16__FUNC_I2S_8CH_BCK (MTK_PIN_NO(16) | 2) +#define MT8167_PIN_16_EINT16__FUNC_TDM_RX_LRCK (MTK_PIN_NO(16) | 3) +#define MT8167_PIN_16_EINT16__FUNC_ANT_SEL3 (MTK_PIN_NO(16) | 4) +#define MT8167_PIN_16_EINT16__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(16) | 5) +#define MT8167_PIN_16_EINT16__FUNC_NCEB0 (MTK_PIN_NO(16) | 6) +#define MT8167_PIN_16_EINT16__FUNC_DBG_MON_B_10 (MTK_PIN_NO(16) | 7) + +#define MT8167_PIN_17_EINT17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define MT8167_PIN_17_EINT17__FUNC_I2S_8CH_MCK (MTK_PIN_NO(17) | 2) +#define MT8167_PIN_17_EINT17__FUNC_TDM_RX_DI (MTK_PIN_NO(17) | 3) +#define MT8167_PIN_17_EINT17__FUNC_IDDIG (MTK_PIN_NO(17) | 4) +#define MT8167_PIN_17_EINT17__FUNC_ANT_SEL4 (MTK_PIN_NO(17) | 5) +#define MT8167_PIN_17_EINT17__FUNC_NREB (MTK_PIN_NO(17) | 6) +#define MT8167_PIN_17_EINT17__FUNC_DBG_MON_B_11 (MTK_PIN_NO(17) | 7) + +#define MT8167_PIN_18_EINT18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define MT8167_PIN_18_EINT18__FUNC_USB_DRVVBUS (MTK_PIN_NO(18) | 2) +#define MT8167_PIN_18_EINT18__FUNC_I2S3_LRCK (MTK_PIN_NO(18) | 3) +#define MT8167_PIN_18_EINT18__FUNC_CLKM1 (MTK_PIN_NO(18) | 4) +#define MT8167_PIN_18_EINT18__FUNC_ANT_SEL3 (MTK_PIN_NO(18) | 5) +#define MT8167_PIN_18_EINT18__FUNC_I2S2_BCK (MTK_PIN_NO(18) | 6) +#define MT8167_PIN_18_EINT18__FUNC_DBG_MON_A_20 (MTK_PIN_NO(18) | 7) + +#define MT8167_PIN_19_EINT19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define MT8167_PIN_19_EINT19__FUNC_UCTS1 (MTK_PIN_NO(19) | 1) +#define MT8167_PIN_19_EINT19__FUNC_IDDIG (MTK_PIN_NO(19) | 2) +#define MT8167_PIN_19_EINT19__FUNC_I2S3_BCK (MTK_PIN_NO(19) | 3) +#define MT8167_PIN_19_EINT19__FUNC_CLKM2 (MTK_PIN_NO(19) | 4) +#define MT8167_PIN_19_EINT19__FUNC_ANT_SEL4 (MTK_PIN_NO(19) | 5) +#define MT8167_PIN_19_EINT19__FUNC_I2S2_DI (MTK_PIN_NO(19) | 6) +#define MT8167_PIN_19_EINT19__FUNC_DBG_MON_A_21 (MTK_PIN_NO(19) | 7) + +#define MT8167_PIN_20_EINT20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define MT8167_PIN_20_EINT20__FUNC_URTS1 (MTK_PIN_NO(20) | 1) +#define MT8167_PIN_20_EINT20__FUNC_I2S3_DO (MTK_PIN_NO(20) | 3) +#define MT8167_PIN_20_EINT20__FUNC_CLKM3 (MTK_PIN_NO(20) | 4) +#define MT8167_PIN_20_EINT20__FUNC_ANT_SEL5 (MTK_PIN_NO(20) | 5) +#define MT8167_PIN_20_EINT20__FUNC_I2S2_LRCK (MTK_PIN_NO(20) | 6) +#define MT8167_PIN_20_EINT20__FUNC_DBG_MON_A_22 (MTK_PIN_NO(20) | 7) + +#define MT8167_PIN_21_EINT21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define MT8167_PIN_21_EINT21__FUNC_NRNB (MTK_PIN_NO(21) | 1) +#define MT8167_PIN_21_EINT21__FUNC_ANT_SEL0 (MTK_PIN_NO(21) | 2) +#define MT8167_PIN_21_EINT21__FUNC_I2S_8CH_DO4 (MTK_PIN_NO(21) | 3) +#define MT8167_PIN_21_EINT21__FUNC_DBG_MON_B_31 (MTK_PIN_NO(21) | 7) + +#define MT8167_PIN_22_EINT22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define MT8167_PIN_22_EINT22__FUNC_I2S_8CH_DO2 (MTK_PIN_NO(22) | 2) +#define MT8167_PIN_22_EINT22__FUNC_TSF_IN (MTK_PIN_NO(22) | 3) +#define MT8167_PIN_22_EINT22__FUNC_USB_DRVVBUS (MTK_PIN_NO(22) | 4) +#define MT8167_PIN_22_EINT22__FUNC_SPDIF_OUT (MTK_PIN_NO(22) | 5) +#define MT8167_PIN_22_EINT22__FUNC_NRE_C (MTK_PIN_NO(22) | 6) +#define MT8167_PIN_22_EINT22__FUNC_DBG_MON_B_12 (MTK_PIN_NO(22) | 7) + +#define MT8167_PIN_23_EINT23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define MT8167_PIN_23_EINT23__FUNC_I2S_8CH_DO3 (MTK_PIN_NO(23) | 2) +#define MT8167_PIN_23_EINT23__FUNC_CLKM0 (MTK_PIN_NO(23) | 3) +#define MT8167_PIN_23_EINT23__FUNC_IR (MTK_PIN_NO(23) | 4) +#define MT8167_PIN_23_EINT23__FUNC_SPDIF_IN (MTK_PIN_NO(23) | 5) +#define MT8167_PIN_23_EINT23__FUNC_NDQS_C (MTK_PIN_NO(23) | 6) +#define MT8167_PIN_23_EINT23__FUNC_DBG_MON_B_13 (MTK_PIN_NO(23) | 7) + +#define MT8167_PIN_24_EINT24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define MT8167_PIN_24_EINT24__FUNC_DPI_D20 (MTK_PIN_NO(24) | 1) +#define MT8167_PIN_24_EINT24__FUNC_DPI_DE (MTK_PIN_NO(24) | 2) +#define MT8167_PIN_24_EINT24__FUNC_ANT_SEL1 (MTK_PIN_NO(24) | 3) +#define MT8167_PIN_24_EINT24__FUNC_UCTS2 (MTK_PIN_NO(24) | 4) +#define MT8167_PIN_24_EINT24__FUNC_PWM_A (MTK_PIN_NO(24) | 5) +#define MT8167_PIN_24_EINT24__FUNC_I2S0_MCK (MTK_PIN_NO(24) | 6) +#define MT8167_PIN_24_EINT24__FUNC_DBG_MON_A_0 (MTK_PIN_NO(24) | 7) + +#define MT8167_PIN_25_EINT25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define MT8167_PIN_25_EINT25__FUNC_DPI_D19 (MTK_PIN_NO(25) | 1) +#define MT8167_PIN_25_EINT25__FUNC_DPI_VSYNC (MTK_PIN_NO(25) | 2) +#define MT8167_PIN_25_EINT25__FUNC_ANT_SEL0 (MTK_PIN_NO(25) | 3) +#define MT8167_PIN_25_EINT25__FUNC_URTS2 (MTK_PIN_NO(25) | 4) +#define MT8167_PIN_25_EINT25__FUNC_PWM_B (MTK_PIN_NO(25) | 5) +#define MT8167_PIN_25_EINT25__FUNC_I2S_8CH_MCK (MTK_PIN_NO(25) | 6) +#define MT8167_PIN_25_EINT25__FUNC_DBG_MON_A_1 (MTK_PIN_NO(25) | 7) + +#define MT8167_PIN_26_PWRAP_SPI0_MI__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define MT8167_PIN_26_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(26) | 1) +#define MT8167_PIN_26_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(26) | 2) + +#define MT8167_PIN_27_PWRAP_SPI0_MO__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define MT8167_PIN_27_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(27) | 1) +#define MT8167_PIN_27_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(27) | 2) + +#define MT8167_PIN_28_PWRAP_INT__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define MT8167_PIN_28_PWRAP_INT__FUNC_I2S0_MCK (MTK_PIN_NO(28) | 1) +#define MT8167_PIN_28_PWRAP_INT__FUNC_I2S_8CH_MCK (MTK_PIN_NO(28) | 4) +#define MT8167_PIN_28_PWRAP_INT__FUNC_I2S2_MCK (MTK_PIN_NO(28) | 5) +#define MT8167_PIN_28_PWRAP_INT__FUNC_I2S3_MCK (MTK_PIN_NO(28) | 6) + +#define MT8167_PIN_29_PWRAP_SPI0_CK__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define MT8167_PIN_29_PWRAP_SPI0_CK__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(29) | 1) + +#define MT8167_PIN_30_PWRAP_SPI0_CSN__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define MT8167_PIN_30_PWRAP_SPI0_CSN__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(30) | 1) + +#define MT8167_PIN_31_RTC32K_CK__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define MT8167_PIN_31_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(31) | 1) + +#define MT8167_PIN_32_WATCHDOG__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define MT8167_PIN_32_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(32) | 1) + +#define MT8167_PIN_33_SRCLKENA__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define MT8167_PIN_33_SRCLKENA__FUNC_SRCLKENA0 (MTK_PIN_NO(33) | 1) + +#define MT8167_PIN_34_URXD2__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define MT8167_PIN_34_URXD2__FUNC_URXD2 (MTK_PIN_NO(34) | 1) +#define MT8167_PIN_34_URXD2__FUNC_DPI_D5 (MTK_PIN_NO(34) | 2) +#define MT8167_PIN_34_URXD2__FUNC_UTXD2 (MTK_PIN_NO(34) | 3) +#define MT8167_PIN_34_URXD2__FUNC_DBG_SCL (MTK_PIN_NO(34) | 4) +#define MT8167_PIN_34_URXD2__FUNC_I2S2_MCK (MTK_PIN_NO(34) | 6) +#define MT8167_PIN_34_URXD2__FUNC_DBG_MON_B_0 (MTK_PIN_NO(34) | 7) + +#define MT8167_PIN_35_UTXD2__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define MT8167_PIN_35_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(35) | 1) +#define MT8167_PIN_35_UTXD2__FUNC_DPI_HSYNC (MTK_PIN_NO(35) | 2) +#define MT8167_PIN_35_UTXD2__FUNC_URXD2 (MTK_PIN_NO(35) | 3) +#define MT8167_PIN_35_UTXD2__FUNC_DBG_SDA (MTK_PIN_NO(35) | 4) +#define MT8167_PIN_35_UTXD2__FUNC_DPI_D18 (MTK_PIN_NO(35) | 5) +#define MT8167_PIN_35_UTXD2__FUNC_I2S3_MCK (MTK_PIN_NO(35) | 6) +#define MT8167_PIN_35_UTXD2__FUNC_DBG_MON_B_1 (MTK_PIN_NO(35) | 7) + +#define MT8167_PIN_36_MRG_CLK__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define MT8167_PIN_36_MRG_CLK__FUNC_MRG_CLK (MTK_PIN_NO(36) | 1) +#define MT8167_PIN_36_MRG_CLK__FUNC_DPI_D4 (MTK_PIN_NO(36) | 2) +#define MT8167_PIN_36_MRG_CLK__FUNC_I2S0_BCK (MTK_PIN_NO(36) | 3) +#define MT8167_PIN_36_MRG_CLK__FUNC_I2S3_BCK (MTK_PIN_NO(36) | 4) +#define MT8167_PIN_36_MRG_CLK__FUNC_PCM0_CLK (MTK_PIN_NO(36) | 5) +#define MT8167_PIN_36_MRG_CLK__FUNC_IR (MTK_PIN_NO(36) | 6) +#define MT8167_PIN_36_MRG_CLK__FUNC_DBG_MON_A_2 (MTK_PIN_NO(36) | 7) + +#define MT8167_PIN_37_MRG_SYNC__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define MT8167_PIN_37_MRG_SYNC__FUNC_MRG_SYNC (MTK_PIN_NO(37) | 1) +#define MT8167_PIN_37_MRG_SYNC__FUNC_DPI_D3 (MTK_PIN_NO(37) | 2) +#define MT8167_PIN_37_MRG_SYNC__FUNC_I2S0_LRCK (MTK_PIN_NO(37) | 3) +#define MT8167_PIN_37_MRG_SYNC__FUNC_I2S3_LRCK (MTK_PIN_NO(37) | 4) +#define MT8167_PIN_37_MRG_SYNC__FUNC_PCM0_SYNC (MTK_PIN_NO(37) | 5) +#define MT8167_PIN_37_MRG_SYNC__FUNC_EXT_COL (MTK_PIN_NO(37) | 6) +#define MT8167_PIN_37_MRG_SYNC__FUNC_DBG_MON_A_3 (MTK_PIN_NO(37) | 7) + +#define MT8167_PIN_38_MRG_DI__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define MT8167_PIN_38_MRG_DI__FUNC_MRG_DI (MTK_PIN_NO(38) | 1) +#define MT8167_PIN_38_MRG_DI__FUNC_DPI_D1 (MTK_PIN_NO(38) | 2) +#define MT8167_PIN_38_MRG_DI__FUNC_I2S0_DI (MTK_PIN_NO(38) | 3) +#define MT8167_PIN_38_MRG_DI__FUNC_I2S3_DO (MTK_PIN_NO(38) | 4) +#define MT8167_PIN_38_MRG_DI__FUNC_PCM0_DI (MTK_PIN_NO(38) | 5) +#define MT8167_PIN_38_MRG_DI__FUNC_EXT_MDIO (MTK_PIN_NO(38) | 6) +#define MT8167_PIN_38_MRG_DI__FUNC_DBG_MON_A_4 (MTK_PIN_NO(38) | 7) + +#define MT8167_PIN_39_MRG_DO__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define MT8167_PIN_39_MRG_DO__FUNC_MRG_DO (MTK_PIN_NO(39) | 1) +#define MT8167_PIN_39_MRG_DO__FUNC_DPI_D2 (MTK_PIN_NO(39) | 2) +#define MT8167_PIN_39_MRG_DO__FUNC_I2S0_MCK (MTK_PIN_NO(39) | 3) +#define MT8167_PIN_39_MRG_DO__FUNC_I2S3_MCK (MTK_PIN_NO(39) | 4) +#define MT8167_PIN_39_MRG_DO__FUNC_PCM0_DO (MTK_PIN_NO(39) | 5) +#define MT8167_PIN_39_MRG_DO__FUNC_EXT_MDC (MTK_PIN_NO(39) | 6) +#define MT8167_PIN_39_MRG_DO__FUNC_DBG_MON_A_5 (MTK_PIN_NO(39) | 7) + +#define MT8167_PIN_40_KPROW0__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define MT8167_PIN_40_KPROW0__FUNC_KPROW0 (MTK_PIN_NO(40) | 1) +#define MT8167_PIN_40_KPROW0__FUNC_IMG_TEST_CK (MTK_PIN_NO(40) | 4) +#define MT8167_PIN_40_KPROW0__FUNC_DBG_MON_B_4 (MTK_PIN_NO(40) | 7) + +#define MT8167_PIN_41_KPROW1__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define MT8167_PIN_41_KPROW1__FUNC_KPROW1 (MTK_PIN_NO(41) | 1) +#define MT8167_PIN_41_KPROW1__FUNC_IDDIG (MTK_PIN_NO(41) | 2) +#define MT8167_PIN_41_KPROW1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(41) | 3) +#define MT8167_PIN_41_KPROW1__FUNC_MFG_TEST_CK (MTK_PIN_NO(41) | 4) +#define MT8167_PIN_41_KPROW1__FUNC_DBG_MON_B_5 (MTK_PIN_NO(41) | 7) + +#define MT8167_PIN_42_KPCOL0__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define MT8167_PIN_42_KPCOL0__FUNC_KPCOL0 (MTK_PIN_NO(42) | 1) +#define MT8167_PIN_42_KPCOL0__FUNC_DBG_MON_B_6 (MTK_PIN_NO(42) | 7) + +#define MT8167_PIN_43_KPCOL1__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define MT8167_PIN_43_KPCOL1__FUNC_KPCOL1 (MTK_PIN_NO(43) | 1) +#define MT8167_PIN_43_KPCOL1__FUNC_USB_DRVVBUS (MTK_PIN_NO(43) | 2) +#define MT8167_PIN_43_KPCOL1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(43) | 3) +#define MT8167_PIN_43_KPCOL1__FUNC_TSF_IN (MTK_PIN_NO(43) | 4) +#define MT8167_PIN_43_KPCOL1__FUNC_DFD_NTRST_XI (MTK_PIN_NO(43) | 5) +#define MT8167_PIN_43_KPCOL1__FUNC_UDI_NTRST_XI (MTK_PIN_NO(43) | 6) +#define MT8167_PIN_43_KPCOL1__FUNC_DBG_MON_B_7 (MTK_PIN_NO(43) | 7) + +#define MT8167_PIN_44_JTMS__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define MT8167_PIN_44_JTMS__FUNC_JTMS (MTK_PIN_NO(44) | 1) +#define MT8167_PIN_44_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(44) | 2) +#define MT8167_PIN_44_JTMS__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(44) | 3) +#define MT8167_PIN_44_JTMS__FUNC_GPUDFD_TMS_XI (MTK_PIN_NO(44) | 4) +#define MT8167_PIN_44_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(44) | 5) +#define MT8167_PIN_44_JTMS__FUNC_UDI_TMS_XI (MTK_PIN_NO(44) | 6) + +#define MT8167_PIN_45_JTCK__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define MT8167_PIN_45_JTCK__FUNC_JTCK (MTK_PIN_NO(45) | 1) +#define MT8167_PIN_45_JTCK__FUNC_CONN_MCU_TCK (MTK_PIN_NO(45) | 2) +#define MT8167_PIN_45_JTCK__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(45) | 3) +#define MT8167_PIN_45_JTCK__FUNC_GPUDFD_TCK_XI (MTK_PIN_NO(45) | 4) +#define MT8167_PIN_45_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(45) | 5) +#define MT8167_PIN_45_JTCK__FUNC_UDI_TCK_XI (MTK_PIN_NO(45) | 6) + +#define MT8167_PIN_46_JTDI__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define MT8167_PIN_46_JTDI__FUNC_JTDI (MTK_PIN_NO(46) | 1) +#define MT8167_PIN_46_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(46) | 2) +#define MT8167_PIN_46_JTDI__FUNC_GPUDFD_TDI_XI (MTK_PIN_NO(46) | 4) +#define MT8167_PIN_46_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(46) | 5) +#define MT8167_PIN_46_JTDI__FUNC_UDI_TDI_XI (MTK_PIN_NO(46) | 6) + +#define MT8167_PIN_47_JTDO__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define MT8167_PIN_47_JTDO__FUNC_JTDO (MTK_PIN_NO(47) | 1) +#define MT8167_PIN_47_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(47) | 2) +#define MT8167_PIN_47_JTDO__FUNC_GPUDFD_TDO (MTK_PIN_NO(47) | 4) +#define MT8167_PIN_47_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(47) | 5) +#define MT8167_PIN_47_JTDO__FUNC_UDI_TDO (MTK_PIN_NO(47) | 6) + +#define MT8167_PIN_48_SPI_CS__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define MT8167_PIN_48_SPI_CS__FUNC_SPI_CSB (MTK_PIN_NO(48) | 1) +#define MT8167_PIN_48_SPI_CS__FUNC_I2S0_DI (MTK_PIN_NO(48) | 3) +#define MT8167_PIN_48_SPI_CS__FUNC_I2S2_BCK (MTK_PIN_NO(48) | 4) +#define MT8167_PIN_48_SPI_CS__FUNC_DBG_MON_A_23 (MTK_PIN_NO(48) | 7) + +#define MT8167_PIN_49_SPI_CK__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define MT8167_PIN_49_SPI_CK__FUNC_SPI_CLK (MTK_PIN_NO(49) | 1) +#define MT8167_PIN_49_SPI_CK__FUNC_I2S0_LRCK (MTK_PIN_NO(49) | 3) +#define MT8167_PIN_49_SPI_CK__FUNC_I2S2_DI (MTK_PIN_NO(49) | 4) +#define MT8167_PIN_49_SPI_CK__FUNC_DBG_MON_A_24 (MTK_PIN_NO(49) | 7) + +#define MT8167_PIN_50_SPI_MI__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define MT8167_PIN_50_SPI_MI__FUNC_SPI_MI (MTK_PIN_NO(50) | 1) +#define MT8167_PIN_50_SPI_MI__FUNC_SPI_MO (MTK_PIN_NO(50) | 2) +#define MT8167_PIN_50_SPI_MI__FUNC_I2S0_BCK (MTK_PIN_NO(50) | 3) +#define MT8167_PIN_50_SPI_MI__FUNC_I2S2_LRCK (MTK_PIN_NO(50) | 4) +#define MT8167_PIN_50_SPI_MI__FUNC_DBG_MON_A_25 (MTK_PIN_NO(50) | 7) + +#define MT8167_PIN_51_SPI_MO__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define MT8167_PIN_51_SPI_MO__FUNC_SPI_MO (MTK_PIN_NO(51) | 1) +#define MT8167_PIN_51_SPI_MO__FUNC_SPI_MI (MTK_PIN_NO(51) | 2) +#define MT8167_PIN_51_SPI_MO__FUNC_I2S0_MCK (MTK_PIN_NO(51) | 3) +#define MT8167_PIN_51_SPI_MO__FUNC_I2S2_MCK (MTK_PIN_NO(51) | 4) +#define MT8167_PIN_51_SPI_MO__FUNC_DBG_MON_A_26 (MTK_PIN_NO(51) | 7) + +#define MT8167_PIN_52_SDA1__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define MT8167_PIN_52_SDA1__FUNC_SDA1_0 (MTK_PIN_NO(52) | 1) + +#define MT8167_PIN_53_SCL1__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define MT8167_PIN_53_SCL1__FUNC_SCL1_0 (MTK_PIN_NO(53) | 1) + +#define MT8167_PIN_54_DISP_PWM__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define MT8167_PIN_54_DISP_PWM__FUNC_DISP_PWM (MTK_PIN_NO(54) | 1) +#define MT8167_PIN_54_DISP_PWM__FUNC_PWM_B (MTK_PIN_NO(54) | 2) +#define MT8167_PIN_54_DISP_PWM__FUNC_DBG_MON_B_2 (MTK_PIN_NO(54) | 7) + +#define MT8167_PIN_55_I2S_DATA_IN__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define MT8167_PIN_55_I2S_DATA_IN__FUNC_I2S0_DI (MTK_PIN_NO(55) | 1) +#define MT8167_PIN_55_I2S_DATA_IN__FUNC_UCTS0 (MTK_PIN_NO(55) | 2) +#define MT8167_PIN_55_I2S_DATA_IN__FUNC_I2S3_DO (MTK_PIN_NO(55) | 3) +#define MT8167_PIN_55_I2S_DATA_IN__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(55) | 4) +#define MT8167_PIN_55_I2S_DATA_IN__FUNC_PWM_A (MTK_PIN_NO(55) | 5) +#define MT8167_PIN_55_I2S_DATA_IN__FUNC_I2S2_BCK (MTK_PIN_NO(55) | 6) +#define MT8167_PIN_55_I2S_DATA_IN__FUNC_DBG_MON_A_28 (MTK_PIN_NO(55) | 7) + +#define MT8167_PIN_56_I2S_LRCK__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define MT8167_PIN_56_I2S_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(56) | 1) +#define MT8167_PIN_56_I2S_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(56) | 3) +#define MT8167_PIN_56_I2S_LRCK__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(56) | 4) +#define MT8167_PIN_56_I2S_LRCK__FUNC_PWM_B (MTK_PIN_NO(56) | 5) +#define MT8167_PIN_56_I2S_LRCK__FUNC_I2S2_DI (MTK_PIN_NO(56) | 6) +#define MT8167_PIN_56_I2S_LRCK__FUNC_DBG_MON_A_29 (MTK_PIN_NO(56) | 7) + +#define MT8167_PIN_57_I2S_BCK__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define MT8167_PIN_57_I2S_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(57) | 1) +#define MT8167_PIN_57_I2S_BCK__FUNC_URTS0 (MTK_PIN_NO(57) | 2) +#define MT8167_PIN_57_I2S_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(57) | 3) +#define MT8167_PIN_57_I2S_BCK__FUNC_I2S_8CH_BCK (MTK_PIN_NO(57) | 4) +#define MT8167_PIN_57_I2S_BCK__FUNC_PWM_C (MTK_PIN_NO(57) | 5) +#define MT8167_PIN_57_I2S_BCK__FUNC_I2S2_LRCK (MTK_PIN_NO(57) | 6) +#define MT8167_PIN_57_I2S_BCK__FUNC_DBG_MON_A_30 (MTK_PIN_NO(57) | 7) + +#define MT8167_PIN_58_SDA0__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define MT8167_PIN_58_SDA0__FUNC_SDA0_0 (MTK_PIN_NO(58) | 1) + +#define MT8167_PIN_59_SCL0__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define MT8167_PIN_59_SCL0__FUNC_SCL0_0 (MTK_PIN_NO(59) | 1) + +#define MT8167_PIN_60_SDA2__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define MT8167_PIN_60_SDA2__FUNC_SDA2_0 (MTK_PIN_NO(60) | 1) +#define MT8167_PIN_60_SDA2__FUNC_PWM_B (MTK_PIN_NO(60) | 2) + +#define MT8167_PIN_61_SCL2__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define MT8167_PIN_61_SCL2__FUNC_SCL2_0 (MTK_PIN_NO(61) | 1) +#define MT8167_PIN_61_SCL2__FUNC_PWM_C (MTK_PIN_NO(61) | 2) + +#define MT8167_PIN_62_URXD0__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define MT8167_PIN_62_URXD0__FUNC_URXD0 (MTK_PIN_NO(62) | 1) +#define MT8167_PIN_62_URXD0__FUNC_UTXD0 (MTK_PIN_NO(62) | 2) + +#define MT8167_PIN_63_UTXD0__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define MT8167_PIN_63_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(63) | 1) +#define MT8167_PIN_63_UTXD0__FUNC_URXD0 (MTK_PIN_NO(63) | 2) + +#define MT8167_PIN_64_URXD1__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define MT8167_PIN_64_URXD1__FUNC_URXD1 (MTK_PIN_NO(64) | 1) +#define MT8167_PIN_64_URXD1__FUNC_UTXD1 (MTK_PIN_NO(64) | 2) +#define MT8167_PIN_64_URXD1__FUNC_DBG_MON_A_27 (MTK_PIN_NO(64) | 7) + +#define MT8167_PIN_65_UTXD1__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define MT8167_PIN_65_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(65) | 1) +#define MT8167_PIN_65_UTXD1__FUNC_URXD1 (MTK_PIN_NO(65) | 2) +#define MT8167_PIN_65_UTXD1__FUNC_DBG_MON_A_31 (MTK_PIN_NO(65) | 7) + +#define MT8167_PIN_66_LCM_RST__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define MT8167_PIN_66_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(66) | 1) +#define MT8167_PIN_66_LCM_RST__FUNC_I2S0_MCK (MTK_PIN_NO(66) | 3) +#define MT8167_PIN_66_LCM_RST__FUNC_DBG_MON_B_3 (MTK_PIN_NO(66) | 7) + +#define MT8167_PIN_67_DSI_TE__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define MT8167_PIN_67_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(67) | 1) +#define MT8167_PIN_67_DSI_TE__FUNC_I2S_8CH_MCK (MTK_PIN_NO(67) | 3) +#define MT8167_PIN_67_DSI_TE__FUNC_DBG_MON_B_14 (MTK_PIN_NO(67) | 7) + +#define MT8167_PIN_68_MSDC2_CMD__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define MT8167_PIN_68_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(68) | 1) +#define MT8167_PIN_68_MSDC2_CMD__FUNC_I2S_8CH_DO4 (MTK_PIN_NO(68) | 2) +#define MT8167_PIN_68_MSDC2_CMD__FUNC_SDA1_0 (MTK_PIN_NO(68) | 3) +#define MT8167_PIN_68_MSDC2_CMD__FUNC_USB_SDA (MTK_PIN_NO(68) | 5) +#define MT8167_PIN_68_MSDC2_CMD__FUNC_I2S3_BCK (MTK_PIN_NO(68) | 6) +#define MT8167_PIN_68_MSDC2_CMD__FUNC_DBG_MON_B_15 (MTK_PIN_NO(68) | 7) + +#define MT8167_PIN_69_MSDC2_CLK__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define MT8167_PIN_69_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(69) | 1) +#define MT8167_PIN_69_MSDC2_CLK__FUNC_I2S_8CH_DO3 (MTK_PIN_NO(69) | 2) +#define MT8167_PIN_69_MSDC2_CLK__FUNC_SCL1_0 (MTK_PIN_NO(69) | 3) +#define MT8167_PIN_69_MSDC2_CLK__FUNC_DPI_D21 (MTK_PIN_NO(69) | 4) +#define MT8167_PIN_69_MSDC2_CLK__FUNC_USB_SCL (MTK_PIN_NO(69) | 5) +#define MT8167_PIN_69_MSDC2_CLK__FUNC_I2S3_LRCK (MTK_PIN_NO(69) | 6) +#define MT8167_PIN_69_MSDC2_CLK__FUNC_DBG_MON_B_16 (MTK_PIN_NO(69) | 7) + +#define MT8167_PIN_70_MSDC2_DAT0__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define MT8167_PIN_70_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(70) | 1) +#define MT8167_PIN_70_MSDC2_DAT0__FUNC_I2S_8CH_DO2 (MTK_PIN_NO(70) | 2) +#define MT8167_PIN_70_MSDC2_DAT0__FUNC_DPI_D22 (MTK_PIN_NO(70) | 4) +#define MT8167_PIN_70_MSDC2_DAT0__FUNC_UTXD0 (MTK_PIN_NO(70) | 5) +#define MT8167_PIN_70_MSDC2_DAT0__FUNC_I2S3_DO (MTK_PIN_NO(70) | 6) +#define MT8167_PIN_70_MSDC2_DAT0__FUNC_DBG_MON_B_17 (MTK_PIN_NO(70) | 7) + +#define MT8167_PIN_71_MSDC2_DAT1__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define MT8167_PIN_71_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(71) | 1) +#define MT8167_PIN_71_MSDC2_DAT1__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(71) | 2) +#define MT8167_PIN_71_MSDC2_DAT1__FUNC_PWM_A (MTK_PIN_NO(71) | 3) +#define MT8167_PIN_71_MSDC2_DAT1__FUNC_I2S3_MCK (MTK_PIN_NO(71) | 4) +#define MT8167_PIN_71_MSDC2_DAT1__FUNC_URXD0 (MTK_PIN_NO(71) | 5) +#define MT8167_PIN_71_MSDC2_DAT1__FUNC_PWM_B (MTK_PIN_NO(71) | 6) +#define MT8167_PIN_71_MSDC2_DAT1__FUNC_DBG_MON_B_18 (MTK_PIN_NO(71) | 7) + +#define MT8167_PIN_72_MSDC2_DAT2__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define MT8167_PIN_72_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(72) | 1) +#define MT8167_PIN_72_MSDC2_DAT2__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(72) | 2) +#define MT8167_PIN_72_MSDC2_DAT2__FUNC_SDA2_0 (MTK_PIN_NO(72) | 3) +#define MT8167_PIN_72_MSDC2_DAT2__FUNC_DPI_D23 (MTK_PIN_NO(72) | 4) +#define MT8167_PIN_72_MSDC2_DAT2__FUNC_UTXD1 (MTK_PIN_NO(72) | 5) +#define MT8167_PIN_72_MSDC2_DAT2__FUNC_PWM_C (MTK_PIN_NO(72) | 6) +#define MT8167_PIN_72_MSDC2_DAT2__FUNC_DBG_MON_B_19 (MTK_PIN_NO(72) | 7) + +#define MT8167_PIN_73_MSDC2_DAT3__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define MT8167_PIN_73_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(73) | 1) +#define MT8167_PIN_73_MSDC2_DAT3__FUNC_I2S_8CH_BCK (MTK_PIN_NO(73) | 2) +#define MT8167_PIN_73_MSDC2_DAT3__FUNC_SCL2_0 (MTK_PIN_NO(73) | 3) +#define MT8167_PIN_73_MSDC2_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(73) | 4) +#define MT8167_PIN_73_MSDC2_DAT3__FUNC_URXD1 (MTK_PIN_NO(73) | 5) +#define MT8167_PIN_73_MSDC2_DAT3__FUNC_PWM_A (MTK_PIN_NO(73) | 6) +#define MT8167_PIN_73_MSDC2_DAT3__FUNC_DBG_MON_B_20 (MTK_PIN_NO(73) | 7) + +#define MT8167_PIN_74_TDN3__FUNC_GPI74 (MTK_PIN_NO(74) | 0) +#define MT8167_PIN_74_TDN3__FUNC_TDN3 (MTK_PIN_NO(74) | 1) + +#define MT8167_PIN_75_TDP3__FUNC_GPI75 (MTK_PIN_NO(75) | 0) +#define MT8167_PIN_75_TDP3__FUNC_TDP3 (MTK_PIN_NO(75) | 1) + +#define MT8167_PIN_76_TDN2__FUNC_GPI76 (MTK_PIN_NO(76) | 0) +#define MT8167_PIN_76_TDN2__FUNC_TDN2 (MTK_PIN_NO(76) | 1) + +#define MT8167_PIN_77_TDP2__FUNC_GPI77 (MTK_PIN_NO(77) | 0) +#define MT8167_PIN_77_TDP2__FUNC_TDP2 (MTK_PIN_NO(77) | 1) + +#define MT8167_PIN_78_TCN__FUNC_GPI78 (MTK_PIN_NO(78) | 0) +#define MT8167_PIN_78_TCN__FUNC_TCN (MTK_PIN_NO(78) | 1) + +#define MT8167_PIN_79_TCP__FUNC_GPI79 (MTK_PIN_NO(79) | 0) +#define MT8167_PIN_79_TCP__FUNC_TCP (MTK_PIN_NO(79) | 1) + +#define MT8167_PIN_80_TDN1__FUNC_GPI80 (MTK_PIN_NO(80) | 0) +#define MT8167_PIN_80_TDN1__FUNC_TDN1 (MTK_PIN_NO(80) | 1) + +#define MT8167_PIN_81_TDP1__FUNC_GPI81 (MTK_PIN_NO(81) | 0) +#define MT8167_PIN_81_TDP1__FUNC_TDP1 (MTK_PIN_NO(81) | 1) + +#define MT8167_PIN_82_TDN0__FUNC_GPI82 (MTK_PIN_NO(82) | 0) +#define MT8167_PIN_82_TDN0__FUNC_TDN0 (MTK_PIN_NO(82) | 1) + +#define MT8167_PIN_83_TDP0__FUNC_GPI83 (MTK_PIN_NO(83) | 0) +#define MT8167_PIN_83_TDP0__FUNC_TDP0 (MTK_PIN_NO(83) | 1) + +#define MT8167_PIN_84_RDN0__FUNC_GPI84 (MTK_PIN_NO(84) | 0) +#define MT8167_PIN_84_RDN0__FUNC_RDN0 (MTK_PIN_NO(84) | 1) + +#define MT8167_PIN_85_RDP0__FUNC_GPI85 (MTK_PIN_NO(85) | 0) +#define MT8167_PIN_85_RDP0__FUNC_RDP0 (MTK_PIN_NO(85) | 1) + +#define MT8167_PIN_86_RDN1__FUNC_GPI86 (MTK_PIN_NO(86) | 0) +#define MT8167_PIN_86_RDN1__FUNC_RDN1 (MTK_PIN_NO(86) | 1) + +#define MT8167_PIN_87_RDP1__FUNC_GPI87 (MTK_PIN_NO(87) | 0) +#define MT8167_PIN_87_RDP1__FUNC_RDP1 (MTK_PIN_NO(87) | 1) + +#define MT8167_PIN_88_RCN__FUNC_GPI88 (MTK_PIN_NO(88) | 0) +#define MT8167_PIN_88_RCN__FUNC_RCN (MTK_PIN_NO(88) | 1) + +#define MT8167_PIN_89_RCP__FUNC_GPI89 (MTK_PIN_NO(89) | 0) +#define MT8167_PIN_89_RCP__FUNC_RCP (MTK_PIN_NO(89) | 1) + +#define MT8167_PIN_90_RDN2__FUNC_GPI90 (MTK_PIN_NO(90) | 0) +#define MT8167_PIN_90_RDN2__FUNC_RDN2 (MTK_PIN_NO(90) | 1) +#define MT8167_PIN_90_RDN2__FUNC_CMDAT8 (MTK_PIN_NO(90) | 2) + +#define MT8167_PIN_91_RDP2__FUNC_GPI91 (MTK_PIN_NO(91) | 0) +#define MT8167_PIN_91_RDP2__FUNC_RDP2 (MTK_PIN_NO(91) | 1) +#define MT8167_PIN_91_RDP2__FUNC_CMDAT9 (MTK_PIN_NO(91) | 2) + +#define MT8167_PIN_92_RDN3__FUNC_GPI92 (MTK_PIN_NO(92) | 0) +#define MT8167_PIN_92_RDN3__FUNC_RDN3 (MTK_PIN_NO(92) | 1) +#define MT8167_PIN_92_RDN3__FUNC_CMDAT4 (MTK_PIN_NO(92) | 2) + +#define MT8167_PIN_93_RDP3__FUNC_GPI93 (MTK_PIN_NO(93) | 0) +#define MT8167_PIN_93_RDP3__FUNC_RDP3 (MTK_PIN_NO(93) | 1) +#define MT8167_PIN_93_RDP3__FUNC_CMDAT5 (MTK_PIN_NO(93) | 2) + +#define MT8167_PIN_94_RCN_A__FUNC_GPI94 (MTK_PIN_NO(94) | 0) +#define MT8167_PIN_94_RCN_A__FUNC_RCN_A (MTK_PIN_NO(94) | 1) +#define MT8167_PIN_94_RCN_A__FUNC_CMDAT6 (MTK_PIN_NO(94) | 2) + +#define MT8167_PIN_95_RCP_A__FUNC_GPI95 (MTK_PIN_NO(95) | 0) +#define MT8167_PIN_95_RCP_A__FUNC_RCP_A (MTK_PIN_NO(95) | 1) +#define MT8167_PIN_95_RCP_A__FUNC_CMDAT7 (MTK_PIN_NO(95) | 2) + +#define MT8167_PIN_96_RDN1_A__FUNC_GPI96 (MTK_PIN_NO(96) | 0) +#define MT8167_PIN_96_RDN1_A__FUNC_RDN1_A (MTK_PIN_NO(96) | 1) +#define MT8167_PIN_96_RDN1_A__FUNC_CMDAT2 (MTK_PIN_NO(96) | 2) +#define MT8167_PIN_96_RDN1_A__FUNC_CMCSD2 (MTK_PIN_NO(96) | 3) + +#define MT8167_PIN_97_RDP1_A__FUNC_GPI97 (MTK_PIN_NO(97) | 0) +#define MT8167_PIN_97_RDP1_A__FUNC_RDP1_A (MTK_PIN_NO(97) | 1) +#define MT8167_PIN_97_RDP1_A__FUNC_CMDAT3 (MTK_PIN_NO(97) | 2) +#define MT8167_PIN_97_RDP1_A__FUNC_CMCSD3 (MTK_PIN_NO(97) | 3) + +#define MT8167_PIN_98_RDN0_A__FUNC_GPI98 (MTK_PIN_NO(98) | 0) +#define MT8167_PIN_98_RDN0_A__FUNC_RDN0_A (MTK_PIN_NO(98) | 1) +#define MT8167_PIN_98_RDN0_A__FUNC_CMHSYNC (MTK_PIN_NO(98) | 2) + +#define MT8167_PIN_99_RDP0_A__FUNC_GPI99 (MTK_PIN_NO(99) | 0) +#define MT8167_PIN_99_RDP0_A__FUNC_RDP0_A (MTK_PIN_NO(99) | 1) +#define MT8167_PIN_99_RDP0_A__FUNC_CMVSYNC (MTK_PIN_NO(99) | 2) + +#define MT8167_PIN_100_CMDAT0__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define MT8167_PIN_100_CMDAT0__FUNC_CMDAT0 (MTK_PIN_NO(100) | 1) +#define MT8167_PIN_100_CMDAT0__FUNC_CMCSD0 (MTK_PIN_NO(100) | 2) +#define MT8167_PIN_100_CMDAT0__FUNC_ANT_SEL2 (MTK_PIN_NO(100) | 3) +#define MT8167_PIN_100_CMDAT0__FUNC_TDM_RX_MCK (MTK_PIN_NO(100) | 5) +#define MT8167_PIN_100_CMDAT0__FUNC_DBG_MON_B_21 (MTK_PIN_NO(100) | 7) + +#define MT8167_PIN_101_CMDAT1__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define MT8167_PIN_101_CMDAT1__FUNC_CMDAT1 (MTK_PIN_NO(101) | 1) +#define MT8167_PIN_101_CMDAT1__FUNC_CMCSD1 (MTK_PIN_NO(101) | 2) +#define MT8167_PIN_101_CMDAT1__FUNC_ANT_SEL3 (MTK_PIN_NO(101) | 3) +#define MT8167_PIN_101_CMDAT1__FUNC_CMFLASH (MTK_PIN_NO(101) | 4) +#define MT8167_PIN_101_CMDAT1__FUNC_TDM_RX_BCK (MTK_PIN_NO(101) | 5) +#define MT8167_PIN_101_CMDAT1__FUNC_DBG_MON_B_22 (MTK_PIN_NO(101) | 7) + +#define MT8167_PIN_102_CMMCLK__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define MT8167_PIN_102_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(102) | 1) +#define MT8167_PIN_102_CMMCLK__FUNC_ANT_SEL4 (MTK_PIN_NO(102) | 3) +#define MT8167_PIN_102_CMMCLK__FUNC_TDM_RX_LRCK (MTK_PIN_NO(102) | 5) +#define MT8167_PIN_102_CMMCLK__FUNC_DBG_MON_B_23 (MTK_PIN_NO(102) | 7) + +#define MT8167_PIN_103_CMPCLK__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define MT8167_PIN_103_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(103) | 1) +#define MT8167_PIN_103_CMPCLK__FUNC_CMCSK (MTK_PIN_NO(103) | 2) +#define MT8167_PIN_103_CMPCLK__FUNC_ANT_SEL5 (MTK_PIN_NO(103) | 3) +#define MT8167_PIN_103_CMPCLK__FUNC_TDM_RX_DI (MTK_PIN_NO(103) | 5) +#define MT8167_PIN_103_CMPCLK__FUNC_DBG_MON_B_24 (MTK_PIN_NO(103) | 7) + +#define MT8167_PIN_104_MSDC1_CMD__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define MT8167_PIN_104_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(104) | 1) +#define MT8167_PIN_104_MSDC1_CMD__FUNC_SQICS (MTK_PIN_NO(104) | 4) +#define MT8167_PIN_104_MSDC1_CMD__FUNC_DBG_MON_B_25 (MTK_PIN_NO(104) | 7) + +#define MT8167_PIN_105_MSDC1_CLK__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define MT8167_PIN_105_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(105) | 1) +#define MT8167_PIN_105_MSDC1_CLK__FUNC_UDI_NTRST_XI (MTK_PIN_NO(105) | 2) +#define MT8167_PIN_105_MSDC1_CLK__FUNC_DFD_NTRST_XI (MTK_PIN_NO(105) | 3) +#define MT8167_PIN_105_MSDC1_CLK__FUNC_SQISO (MTK_PIN_NO(105) | 4) +#define MT8167_PIN_105_MSDC1_CLK__FUNC_GPUEJ_NTRST_XI (MTK_PIN_NO(105) | 5) +#define MT8167_PIN_105_MSDC1_CLK__FUNC_DBG_MON_B_26 (MTK_PIN_NO(105) | 7) + +#define MT8167_PIN_106_MSDC1_DAT0__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define MT8167_PIN_106_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(106) | 1) +#define MT8167_PIN_106_MSDC1_DAT0__FUNC_UDI_TMS_XI (MTK_PIN_NO(106) | 2) +#define MT8167_PIN_106_MSDC1_DAT0__FUNC_DFD_TMS_XI (MTK_PIN_NO(106) | 3) +#define MT8167_PIN_106_MSDC1_DAT0__FUNC_SQISI (MTK_PIN_NO(106) | 4) +#define MT8167_PIN_106_MSDC1_DAT0__FUNC_GPUEJ_TMS_XI (MTK_PIN_NO(106) | 5) +#define MT8167_PIN_106_MSDC1_DAT0__FUNC_DBG_MON_B_27 (MTK_PIN_NO(106) | 7) + +#define MT8167_PIN_107_MSDC1_DAT1__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define MT8167_PIN_107_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(107) | 1) +#define MT8167_PIN_107_MSDC1_DAT1__FUNC_UDI_TCK_XI (MTK_PIN_NO(107) | 2) +#define MT8167_PIN_107_MSDC1_DAT1__FUNC_DFD_TCK_XI (MTK_PIN_NO(107) | 3) +#define MT8167_PIN_107_MSDC1_DAT1__FUNC_SQIWP (MTK_PIN_NO(107) | 4) +#define MT8167_PIN_107_MSDC1_DAT1__FUNC_GPUEJ_TCK_XI (MTK_PIN_NO(107) | 5) +#define MT8167_PIN_107_MSDC1_DAT1__FUNC_DBG_MON_B_28 (MTK_PIN_NO(107) | 7) + +#define MT8167_PIN_108_MSDC1_DAT2__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define MT8167_PIN_108_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(108) | 1) +#define MT8167_PIN_108_MSDC1_DAT2__FUNC_UDI_TDI_XI (MTK_PIN_NO(108) | 2) +#define MT8167_PIN_108_MSDC1_DAT2__FUNC_DFD_TDI_XI (MTK_PIN_NO(108) | 3) +#define MT8167_PIN_108_MSDC1_DAT2__FUNC_SQIRST (MTK_PIN_NO(108) | 4) +#define MT8167_PIN_108_MSDC1_DAT2__FUNC_GPUEJ_TDI_XI (MTK_PIN_NO(108) | 5) +#define MT8167_PIN_108_MSDC1_DAT2__FUNC_DBG_MON_B_29 (MTK_PIN_NO(108) | 7) + +#define MT8167_PIN_109_MSDC1_DAT3__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define MT8167_PIN_109_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(109) | 1) +#define MT8167_PIN_109_MSDC1_DAT3__FUNC_UDI_TDO (MTK_PIN_NO(109) | 2) +#define MT8167_PIN_109_MSDC1_DAT3__FUNC_DFD_TDO (MTK_PIN_NO(109) | 3) +#define MT8167_PIN_109_MSDC1_DAT3__FUNC_SQICK (MTK_PIN_NO(109) | 4) +#define MT8167_PIN_109_MSDC1_DAT3__FUNC_GPUEJ_TDO (MTK_PIN_NO(109) | 5) +#define MT8167_PIN_109_MSDC1_DAT3__FUNC_DBG_MON_B_30 (MTK_PIN_NO(109) | 7) + +#define MT8167_PIN_110_MSDC0_DAT7__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define MT8167_PIN_110_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(110) | 1) +#define MT8167_PIN_110_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(110) | 4) + +#define MT8167_PIN_111_MSDC0_DAT6__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define MT8167_PIN_111_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(111) | 1) +#define MT8167_PIN_111_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(111) | 4) + +#define MT8167_PIN_112_MSDC0_DAT5__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define MT8167_PIN_112_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(112) | 1) +#define MT8167_PIN_112_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(112) | 4) + +#define MT8167_PIN_113_MSDC0_DAT4__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define MT8167_PIN_113_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(113) | 1) +#define MT8167_PIN_113_MSDC0_DAT4__FUNC_NLD3 (MTK_PIN_NO(113) | 4) + +#define MT8167_PIN_114_MSDC0_RSTB__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define MT8167_PIN_114_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(114) | 1) +#define MT8167_PIN_114_MSDC0_RSTB__FUNC_NLD0 (MTK_PIN_NO(114) | 4) + +#define MT8167_PIN_115_MSDC0_CMD__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define MT8167_PIN_115_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(115) | 1) +#define MT8167_PIN_115_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(115) | 4) + +#define MT8167_PIN_116_MSDC0_CLK__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define MT8167_PIN_116_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(116) | 1) +#define MT8167_PIN_116_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(116) | 4) + +#define MT8167_PIN_117_MSDC0_DAT3__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define MT8167_PIN_117_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(117) | 1) +#define MT8167_PIN_117_MSDC0_DAT3__FUNC_NLD1 (MTK_PIN_NO(117) | 4) + +#define MT8167_PIN_118_MSDC0_DAT2__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define MT8167_PIN_118_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(118) | 1) +#define MT8167_PIN_118_MSDC0_DAT2__FUNC_NLD5 (MTK_PIN_NO(118) | 4) + +#define MT8167_PIN_119_MSDC0_DAT1__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define MT8167_PIN_119_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(119) | 1) +#define MT8167_PIN_119_MSDC0_DAT1__FUNC_NLD8 (MTK_PIN_NO(119) | 4) + +#define MT8167_PIN_120_MSDC0_DAT0__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define MT8167_PIN_120_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(120) | 1) +#define MT8167_PIN_120_MSDC0_DAT0__FUNC_WATCHDOG (MTK_PIN_NO(120) | 4) +#define MT8167_PIN_120_MSDC0_DAT0__FUNC_NLD2 (MTK_PIN_NO(120) | 5) + +#define MT8167_PIN_121_CEC__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define MT8167_PIN_121_CEC__FUNC_CEC (MTK_PIN_NO(121) | 1) + +#define MT8167_PIN_122_HTPLG__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define MT8167_PIN_122_HTPLG__FUNC_HTPLG (MTK_PIN_NO(122) | 1) + +#define MT8167_PIN_123_HDMISCK__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define MT8167_PIN_123_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(123) | 1) + +#define MT8167_PIN_124_HDMISD__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define MT8167_PIN_124_HDMISD__FUNC_HDMISD (MTK_PIN_NO(124) | 1) + +#endif /* __DTS_MT8167_PINFUNC_H */ diff --git a/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts new file mode 100644 index 000000000..774a2f3fb --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 BayLibre, SAS. + * Author: Fabien Parent <fparent@baylibre.com> + */ + +/dts-v1/; + +#include "mt8167.dtsi" +#include "pumpkin-common.dtsi" + +/ { + model = "Pumpkin MT8167"; + compatible = "mediatek,mt8167-pumpkin", "mediatek,mt8167"; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi new file mode 100644 index 000000000..fbe1a1128 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi @@ -0,0 +1,181 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 MediaTek Inc. + * Copyright (c) 2020 BayLibre, SAS. + * Author: Fabien Parent <fparent@baylibre.com> + */ + +#include <dt-bindings/clock/mt8167-clk.h> +#include <dt-bindings/memory/mt8167-larb-port.h> +#include <dt-bindings/power/mt8167-power.h> + +#include "mt8167-pinfunc.h" + +#include "mt8516.dtsi" + +/ { + compatible = "mediatek,mt8167"; + + soc { + topckgen: topckgen@10000000 { + compatible = "mediatek,mt8167-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: infracfg@10001000 { + compatible = "mediatek,mt8167-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + apmixedsys: apmixedsys@10018000 { + compatible = "mediatek,mt8167-apmixedsys", "syscon"; + reg = <0 0x10018000 0 0x710>; + #clock-cells = <1>; + }; + + scpsys: syscon@10006000 { + compatible = "mediatek,mt8167-scpsys", "syscon", "simple-mfd"; + reg = <0 0x10006000 0 0x1000>; + + spm: power-controller { + compatible = "mediatek,mt8167-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* power domains of the SoC */ + power-domain@MT8167_POWER_DOMAIN_MM { + reg = <MT8167_POWER_DOMAIN_MM>; + clocks = <&topckgen CLK_TOP_SMI_MM>; + clock-names = "mm"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + + power-domain@MT8167_POWER_DOMAIN_VDEC { + reg = <MT8167_POWER_DOMAIN_VDEC>; + clocks = <&topckgen CLK_TOP_SMI_MM>, + <&topckgen CLK_TOP_RG_VDEC>; + clock-names = "mm", "vdec"; + #power-domain-cells = <0>; + }; + + power-domain@MT8167_POWER_DOMAIN_ISP { + reg = <MT8167_POWER_DOMAIN_ISP>; + clocks = <&topckgen CLK_TOP_SMI_MM>; + clock-names = "mm"; + #power-domain-cells = <0>; + }; + + power-domain@MT8167_POWER_DOMAIN_MFG_ASYNC { + reg = <MT8167_POWER_DOMAIN_MFG_ASYNC>; + clocks = <&topckgen CLK_TOP_RG_AXI_MFG>, + <&topckgen CLK_TOP_RG_SLOW_MFG>; + clock-names = "axi_mfg", "mfg"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + mediatek,infracfg = <&infracfg>; + + power-domain@MT8167_POWER_DOMAIN_MFG_2D { + reg = <MT8167_POWER_DOMAIN_MFG_2D>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8167_POWER_DOMAIN_MFG { + reg = <MT8167_POWER_DOMAIN_MFG>; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + }; + }; + + power-domain@MT8167_POWER_DOMAIN_CONN { + reg = <MT8167_POWER_DOMAIN_CONN>; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + }; + }; + + imgsys: syscon@15000000 { + compatible = "mediatek,mt8167-imgsys", "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys: syscon@16000000 { + compatible = "mediatek,mt8167-vdecsys", "syscon"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + pio: pinctrl@1000b000 { + compatible = "mediatek,mt8167-pinctrl"; + reg = <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl>; + pins-are-numbered; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; + }; + + mmsys: mmsys@14000000 { + compatible = "mediatek,mt8167-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + }; + + smi_common: smi@14017000 { + compatible = "mediatek,mt8167-smi-common"; + reg = <0 0x14017000 0 0x1000>; + clocks = <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_COMMON>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + }; + + larb0: larb@14016000 { + compatible = "mediatek,mt8167-smi-larb"; + reg = <0 0x14016000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&mmsys CLK_MM_SMI_LARB0>, + <&mmsys CLK_MM_SMI_LARB0>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + }; + + larb1: larb@15001000 { + compatible = "mediatek,mt8167-smi-larb"; + reg = <0 0x15001000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&imgsys CLK_IMG_LARB1_SMI>, + <&imgsys CLK_IMG_LARB1_SMI>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8167_POWER_DOMAIN_ISP>; + }; + + larb2: larb@16010000 { + compatible = "mediatek,mt8167-smi-larb"; + reg = <0 0x16010000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&vdecsys CLK_VDEC_CKEN>, + <&vdecsys CLK_VDEC_LARB1_CKEN>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8167_POWER_DOMAIN_VDEC>; + }; + + iommu: m4u@10203000 { + compatible = "mediatek,mt8167-m4u"; + reg = <0 0x10203000 0 0x1000>; + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>; + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_LOW>; + #iommu-cells = <1>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts new file mode 100644 index 000000000..28433b94f --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2019 MediaTek Inc. + */ + +/dts-v1/; +#include "mt8173-elm-hana.dtsi" + +/ { + model = "Google Hanawl"; + compatible = "google,hana-rev7", "mediatek,mt8173"; +}; + +&cpu_thermal { + trips { + cpu_crit: cpu_crit0 { + temperature = <100000>; + type = "critical"; + }; + }; +}; + +&gpio_keys { + /delete-node/switch-tablet-mode; + /delete-node/switch-volume-down; + /delete-node/switch-volume-up; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts new file mode 100644 index 000000000..c23429675 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2016 MediaTek Inc. + */ + +/dts-v1/; +#include "mt8173-elm-hana.dtsi" + +/ { + model = "Google Hana"; + compatible = "google,hana-rev6", "google,hana-rev5", + "google,hana-rev4", "google,hana-rev3", + "google,hana", "mediatek,mt8173"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi new file mode 100644 index 000000000..bdcd35cec --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2016 MediaTek Inc. + */ + +#include "mt8173-elm.dtsi" + +&i2c0 { + clock-frequency = <200000>; +}; + +&i2c3 { + touchscreen2: touchscreen@34 { + compatible = "melfas,mip4_ts"; + reg = <0x34>; + interrupt-parent = <&pio>; + interrupts = <88 IRQ_TYPE_LEVEL_LOW>; + }; + + /* + * Lenovo 100e Chromebook 2nd Gen (MTK) and Lenovo 300e Chromebook 2nd + * Gen (MTK) are using synaptics touchscreen (hid-over-i2c driver) as a + * second source touchscreen. + */ + touchscreen3: touchscreen@20 { + compatible = "hid-over-i2c"; + reg = <0x20>; + hid-descr-addr = <0x0020>; + interrupt-parent = <&pio>; + interrupts = <88 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c4 { + /* + * Lenovo 100e Chromebook 2nd Gen (MTK) and Lenovo 300e Chromebook 2nd + * Gen (MTK) are using synaptics trackpad (hid-over-i2c driver) as a + * second source trackpad. + */ + trackpad2: trackpad@2c { + compatible = "hid-over-i2c"; + interrupt-parent = <&pio>; + interrupts = <117 IRQ_TYPE_LEVEL_LOW>; + reg = <0x2c>; + hid-descr-addr = <0x0020>; + wakeup-source; + }; +}; + +&mmc1 { + wp-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; +}; + +&pio { + hdmi_mux_pins: hdmi_mux_pins { + pins2 { + pinmux = <MT8173_PIN_98_URTS1__FUNC_GPIO98>; + bias-pull-up; + output-high; + }; + }; + + mmc1_pins_default: mmc1default { + pins_wp { + pinmux = <MT8173_PIN_42_DSI_TE__FUNC_GPIO42>; + input-enable; + bias-pull-up; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dts b/arch/arm64/boot/dts/mediatek/mt8173-elm.dts new file mode 100644 index 000000000..e9e4ac0b7 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2016 MediaTek Inc. + */ + +/dts-v1/; +#include "mt8173-elm.dtsi" + +/ { + model = "Google Elm"; + compatible = "google,elm-rev8", "google,elm-rev7", "google,elm-rev6", + "google,elm-rev5", "google,elm-rev4", "google,elm-rev3", + "google,elm", "mediatek,mt8173"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi new file mode 100644 index 000000000..e21feb85d --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -0,0 +1,1191 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2016 MediaTek Inc. + */ + +#include <dt-bindings/input/input.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/regulator/dlg,da9211-regulator.h> +#include <dt-bindings/gpio/gpio.h> +#include "mt8173.dtsi" + +/ { + aliases { + mmc0 = &mmc0; + mmc1 = &mmc1; + mmc2 = &mmc3; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 1000000>; + power-supply = <&bl_fixed_reg>; + enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_backlight_en_pins>; + status = "okay"; + }; + + bl_fixed_reg: fixedregulator2 { + compatible = "regulator-fixed"; + regulator-name = "bl_fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <1000>; + enable-active-high; + gpio = <&pio 32 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_fixed_pins>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pins>; + + switch-lid { + label = "Lid"; + gpios = <&pio 69 GPIO_ACTIVE_LOW>; + linux,code = <SW_LID>; + linux,input-type = <EV_SW>; + gpio-key,wakeup; + }; + + switch-power { + label = "Power"; + gpios = <&pio 14 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_POWER>; + debounce-interval = <30>; + gpio-key,wakeup; + }; + + switch-tablet-mode { + label = "Tablet_mode"; + gpios = <&pio 121 GPIO_ACTIVE_HIGH>; + linux,code = <SW_TABLET_MODE>; + linux,input-type = <EV_SW>; + gpio-key,wakeup; + }; + + switch-volume-down { + label = "Volume_down"; + gpios = <&pio 123 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + }; + + switch-volume-up { + label = "Volume_up"; + gpios = <&pio 124 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + }; + + panel: panel { + compatible = "lg,lp120up1"; + power-supply = <&panel_fixed_3v3>; + backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&ps8640_out>; + }; + }; + }; + + panel_fixed_3v3: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "PANEL_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pio 41 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_fixed_pins>; + }; + + ps8640_fixed_1v2: regulator2 { + compatible = "regulator-fixed"; + regulator-name = "PS8640_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <2000>; + enable-active-high; + regulator-boot-on; + gpio = <&pio 30 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&ps8640_fixed_pins>; + }; + + sdio_fixed_3v3: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 85 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio_fixed_3v3_pins>; + }; + + sound: sound { + compatible = "mediatek,mt8173-rt5650"; + mediatek,audio-codec = <&rt5650 &hdmi0>; + mediatek,platform = <&afe>; + pinctrl-names = "default"; + pinctrl-0 = <&aud_i2s2>; + + mediatek,mclk = <1>; + codec-capture { + sound-dai = <&rt5650 1>; + }; + }; + + hdmicon: connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + ddc-i2c-bus = <&hdmiddc0>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi0_out>; + }; + }; + }; +}; + +&mfg_async { + domain-supply = <&da9211_vgpu_reg>; +}; + +&cec { + status = "okay"; +}; + +&cpu0 { + proc-supply = <&mt6397_vpca15_reg>; +}; + +&cpu1 { + proc-supply = <&mt6397_vpca15_reg>; +}; + +&cpu2 { + proc-supply = <&da9211_vcpu_reg>; + sram-supply = <&mt6397_vsramca7_reg>; +}; + +&cpu3 { + proc-supply = <&da9211_vcpu_reg>; + sram-supply = <&mt6397_vsramca7_reg>; +}; + +&cpu_thermal { + sustainable-power = <4500>; /* milliwatts */ + trips { + threshold: trip-point0 { + temperature = <60000>; + }; + + target: trip-point1 { + temperature = <65000>; + }; + }; +}; + +&dsi0 { + status = "okay"; + ports { + port { + dsi0_out: endpoint { + remote-endpoint = <&ps8640_in>; + }; + }; + }; +}; + +&dpi0 { + status = "okay"; +}; + +&hdmi0 { + status = "okay"; + ports { + port@1 { + reg = <1>; + + hdmi0_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; +}; + +&hdmi_phy { + status = "okay"; + mediatek,ibias = <0xc>; +}; + +&i2c0 { + status = "okay"; + + rt5650: audio-codec@1a { + compatible = "realtek,rt5650"; + reg = <0x1a>; + avdd-supply = <&mt6397_vgp1_reg>; + cpvdd-supply = <&mt6397_vcama_reg>; + interrupt-parent = <&pio>; + interrupts = <3 IRQ_TYPE_EDGE_BOTH>; + pinctrl-names = "default"; + pinctrl-0 = <&rt5650_irq>; + #sound-dai-cells = <1>; + realtek,dmic1-data-pin = <2>; + realtek,jd-mode = <2>; + }; + + ps8640: edp-bridge@8 { + compatible = "parade,ps8640"; + reg = <0x8>; + powerdown-gpios = <&pio 127 GPIO_ACTIVE_LOW>; + reset-gpios = <&pio 115 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ps8640_pins>; + vdd12-supply = <&ps8640_fixed_1v2>; + vdd33-supply = <&mt6397_vgp2_reg>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ps8640_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + ps8640_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; +}; + +&i2c1 { + clock-frequency = <1500000>; + status = "okay"; + + da9211: da9211@68 { + compatible = "dlg,da9211"; + reg = <0x68>; + interrupt-parent = <&pio>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + + regulators { + da9211_vcpu_reg: BUCKA { + regulator-name = "VBUCKA"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1310000>; + regulator-min-microamp = <2000000>; + regulator-max-microamp = <4400000>; + regulator-ramp-delay = <10000>; + regulator-always-on; + regulator-allowed-modes = <DA9211_BUCK_MODE_SYNC + DA9211_BUCK_MODE_AUTO>; + }; + + da9211_vgpu_reg: BUCKB { + regulator-name = "VBUCKB"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1310000>; + regulator-min-microamp = <2000000>; + regulator-max-microamp = <3000000>; + regulator-ramp-delay = <10000>; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + + tpm: tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + powered-while-suspended; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + status = "okay"; + + touchscreen: touchscreen@10 { + compatible = "elan,ekth3500"; + reg = <0x10>; + interrupt-parent = <&pio>; + interrupts = <88 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c4 { + clock-frequency = <400000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_irq>; + + trackpad: trackpad@15 { + compatible = "elan,ekth3000"; + interrupt-parent = <&pio>; + interrupts = <117 IRQ_TYPE_LEVEL_LOW>; + reg = <0x15>; + vcc-supply = <&mt6397_vgp6_reg>; + wakeup-source; + }; +}; + +&mipi_tx0 { + status = "okay"; +}; + +&mmc0 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cap-mmc-hw-reset; + hs400-ds-delay = <0x14015>; + mediatek,hs200-cmd-int-delay = <30>; + mediatek,hs400-cmd-int-delay = <14>; + mediatek,hs400-cmd-resp-sel-rising; + vmmc-supply = <&mt6397_vemc_3v3_reg>; + vqmmc-supply = <&mt6397_vio18_reg>; + assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; + non-removable; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_uhs>; + bus-width = <4>; + max-frequency = <200000000>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + cd-gpios = <&pio 1 GPIO_ACTIVE_LOW>; + vmmc-supply = <&mt6397_vmch_reg>; + vqmmc-supply = <&mt6397_vmc_reg>; +}; + +&mmc3 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc3_pins_default>; + pinctrl-1 = <&mmc3_pins_uhs>; + bus-width = <4>; + max-frequency = <200000000>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + keep-power-in-suspend; + wakeup-source; + cap-sdio-irq; + vmmc-supply = <&sdio_fixed_3v3>; + vqmmc-supply = <&mt6397_vgp3_reg>; + non-removable; + cap-power-off-card; + + #address-cells = <1>; + #size-cells = <0>; + + btmrvl: btmrvl@2 { + compatible = "marvell,sd8897-bt"; + reg = <2>; + interrupt-parent = <&pio>; + interrupts = <119 IRQ_TYPE_LEVEL_LOW>; + marvell,wakeup-pin = /bits/ 16 <0x0d>; + marvell,wakeup-gap-ms = /bits/ 16 <0x64>; + }; + + mwifiex: mwifiex@1 { + compatible = "marvell,sd8897"; + reg = <1>; + interrupt-parent = <&pio>; + interrupts = <38 IRQ_TYPE_LEVEL_LOW>; + marvell,wakeup-pin = <3>; + }; +}; + +&nor_flash { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nor_gpio1_pins>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + }; +}; + +&pio { + gpio-line-names = "EC_INT_1V8", + "SD_CD_L", + "ALC5514_IRQ", + "ALC5650_IRQ", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it SFWP_B. + */ + "AP_FLASH_WP_L", + "SFIN", + "SFCS0", + "SFHOLD", + "SFOUT", + "SFCK", + "WRAP_EVENT_S_EINT10", + "PMU_INT", + "I2S2_WS_ALC5650", + "I2S2_BCK_ALC5650", + "PWR_BTN_1V8", + "DA9212_IRQ", + "IDDIG", + "WATCHDOG", + "CEC", + "HDMISCK", + "HDMISD", + "HTPLG", + "MSDC3_DAT0", + "MSDC3_DAT1", + "MSDC3_DAT2", + "MSDC3_DAT3", + "MSDC3_CLK", + "MSDC3_CMD", + "USB_C0_OC_FLAGB", + "USBA_OC1_L", + "PS8640_1V2_ENABLE", + "THERM_ALERT_N", + "PANEL_LCD_POWER_EN", + "ANX7688_CHIP_PD_C", + "EC_IN_RW_1V8", + "ANX7688_1V_EN_C", + "USB_DP_HPD_C", + "TPM_DAVINT_N", + "MARVELL8897_IRQ", + "EN_USB_A0_PWR", + "USBA_A0_OC_L", + "EN_PP3300_DX_EDP", + "", + "SOC_I2C2_1V8_SDA_400K", + "SOC_I2C2_1V8_SCL_400K", + "SOC_I2C0_1V8_SDA_400K", + "SOC_I2C0_1V8_SCL_400K", + "EMMC_ID1", + "EMMC_ID0", + "MEM_CONFIG3", + "EMMC_ID2", + "MEM_CONFIG1", + "MEM_CONFIG2", + "BRD_ID2", + "MEM_CONFIG0", + "BRD_ID0", + "BRD_ID1", + "EMMC_DAT0", + "EMMC_DAT1", + "EMMC_DAT2", + "EMMC_DAT3", + "EMMC_DAT4", + "EMMC_DAT5", + "EMMC_DAT6", + "EMMC_DAT7", + "EMMC_CLK", + "EMMC_CMD", + "EMMC_RCLK", + "PLT_RST_L", + "LID_OPEN_1V8_L", + "AUDIO_SPI_MISO_R", + "", + "AC_OK_1V8", + "SD_DATA0", + "SD_DATA1", + "SD_DATA2", + "SD_DATA3", + "SD_CLK", + "SD_CMD", + "PWRAP_SPI0_MI", + "PWRAP_SPI0_MO", + "PWRAP_SPI0_CK", + "PWRAP_SPI0_CSN", + "", + "", + "WIFI_PDN", + "RTC32K_1V8", + "DISP_PWM0", + "TOUCHSCREEN_INT_L", + "", + "SRCLKENA0", + "SRCLKENA1", + "PS8640_MODE_CONF", + "TOUCHSCREEN_RESET_R", + "PLATFORM_PROCHOT_L", + "PANEL_POWER_EN", + "REC_MODE_L", + "EC_FW_UPDATE_L", + "ACCEL2_INT_L", + "HDMI_DP_INT", + "ACCELGYRO3_INT_L", + "ACCELGYRO4_INT_L", + "SPI_EC_CLK", + "SPI_EC_MI", + "SPI_EC_MO", + "SPI_EC_CSN", + "SOC_I2C3_1V8_SDA_400K", + "SOC_I2C3_1V8_SCL_400K", + "", + "", + "", + "", + "", + "", + "", + "PS8640_SYSRSTN_1V8", + "APIN_MAX98090_DOUT2", + "TP_INT_1V8_L_R", + "RST_USB_HUB_R", + "BT_WAKE_L", + "ACCEL1_INT_L", + "TABLET_MODE_L", + "", + "V_UP_IN_L_R", + "V_DOWN_IN_L_R", + "SOC_I2C1_1V8_SDA_1M", + "SOC_I2C1_1V8_SCL_1M", + "PS8640_PDN_1V8", + "MAX98090_LRCLK", + "MAX98090_BCLK", + "MAX98090_MCLK", + "APOUT_MAX98090_DIN", + "APIN_MAX98090_DOUT", + "SOC_I2C4_1V8_SDA_400K", + "SOC_I2C4_1V8_SCL_400K"; + + aud_i2s2: aud_i2s2 { + pins1 { + pinmux = <MT8173_PIN_128_I2S0_LRCK__FUNC_I2S1_WS>, + <MT8173_PIN_129_I2S0_BCK__FUNC_I2S1_BCK>, + <MT8173_PIN_130_I2S0_MCK__FUNC_I2S1_MCK>, + <MT8173_PIN_131_I2S0_DATA0__FUNC_I2S1_DO_1>, + <MT8173_PIN_12_EINT12__FUNC_I2S2_WS>, + <MT8173_PIN_13_EINT13__FUNC_I2S2_BCK>, + <MT8173_PIN_132_I2S0_DATA1__FUNC_I2S2_DI_2>; + bias-pull-down; + }; + }; + + bl_fixed_pins: bl_fixed_pins { + pins1 { + pinmux = <MT8173_PIN_32_UTXD2__FUNC_GPIO32>; + output-low; + }; + }; + + bt_wake_pins: bt_wake_pins { + pins1 { + pinmux = <MT8173_PIN_119_KPROW0__FUNC_GPIO119>; + bias-pull-up; + }; + }; + + disp_pwm0_pins: disp_pwm0_pins { + pins1 { + pinmux = <MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0>; + output-low; + }; + }; + + gpio_keys_pins: gpio_keys_pins { + volume_pins { + pinmux = <MT8173_PIN_123_KPCOL1__FUNC_GPIO123>, + <MT8173_PIN_124_KPCOL2__FUNC_GPIO124>; + bias-pull-up; + }; + + tablet_mode_pins { + pinmux = <MT8173_PIN_121_KPROW2__FUNC_GPIO121>; + bias-pull-up; + }; + }; + + hdmi_mux_pins: hdmi_mux_pins { + pins1 { + pinmux = <MT8173_PIN_36_DAISYNC__FUNC_GPIO36>; + }; + }; + + i2c1_pins_a: i2c1 { + da9211_pins { + pinmux = <MT8173_PIN_15_EINT15__FUNC_GPIO15>; + bias-pull-up; + }; + }; + + mmc0_pins_default: mmc0default { + pins_cmd_dat { + pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>, + <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>, + <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>, + <MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3>, + <MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4>, + <MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5>, + <MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6>, + <MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>, + <MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>; + bias-pull-up; + }; + + pins_clk { + pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>; + bias-pull-down; + }; + + pins_rst { + pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>; + bias-pull-up; + }; + }; + + mmc1_pins_default: mmc1default { + pins_cmd_dat { + pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>, + <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>, + <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>, + <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>, + <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>; + input-enable; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_10>; + }; + + pins_clk { + pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>; + bias-pull-down; + drive-strength = <MTK_DRIVE_4mA>; + }; + + pins_insert { + pinmux = <MT8173_PIN_1_EINT1__FUNC_GPIO1>; + bias-pull-up; + }; + }; + + mmc3_pins_default: mmc3default { + pins_dat { + pinmux = <MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0>, + <MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1>, + <MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2>, + <MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3>; + input-enable; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_10>; + }; + + pins_cmd { + pinmux = <MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD>; + input-enable; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_10>; + }; + + pins_clk { + pinmux = <MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK>; + bias-pull-down; + drive-strength = <MTK_DRIVE_8mA>; + }; + }; + + mmc0_pins_uhs: mmc0 { + pins_cmd_dat { + pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>, + <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>, + <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>, + <MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3>, + <MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4>, + <MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5>, + <MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6>, + <MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>, + <MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>; + input-enable; + drive-strength = <MTK_DRIVE_6mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins_clk { + pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>; + drive-strength = <MTK_DRIVE_6mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_01>; + }; + + pins_ds { + pinmux = <MT8173_PIN_67_MSDC0_DSL__FUNC_MSDC0_DSL>; + drive-strength = <MTK_DRIVE_10mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_01>; + }; + + pins_rst { + pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>; + bias-pull-up; + }; + }; + + mmc1_pins_uhs: mmc1 { + pins_cmd_dat { + pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>, + <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>, + <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>, + <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>, + <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>; + input-enable; + drive-strength = <MTK_DRIVE_6mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_10>; + }; + + pins_clk { + pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + }; + + mmc3_pins_uhs: mmc3 { + pins_dat { + pinmux = <MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0>, + <MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1>, + <MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2>, + <MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3>; + input-enable; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_10>; + }; + + pins_cmd { + pinmux = <MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD>; + input-enable; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_10>; + }; + + pins_clk { + pinmux = <MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK>; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + }; + + nor_gpio1_pins: nor { + pins1 { + pinmux = <MT8173_PIN_6_EINT6__FUNC_SFCS0>, + <MT8173_PIN_7_EINT7__FUNC_SFHOLD>, + <MT8173_PIN_8_EINT8__FUNC_SFIN>; + input-enable; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up; + }; + + pins2 { + pinmux = <MT8173_PIN_5_EINT5__FUNC_SFOUT>; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up; + }; + + pins_clk { + pinmux = <MT8173_PIN_9_EINT9__FUNC_SFCK>; + input-enable; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up; + }; + }; + + panel_backlight_en_pins: panel_backlight_en_pins { + pins1 { + pinmux = <MT8173_PIN_95_PCM_TX__FUNC_GPIO95>; + }; + }; + + panel_fixed_pins: panel_fixed_pins { + pins1 { + pinmux = <MT8173_PIN_41_CMMCLK__FUNC_GPIO41>; + }; + }; + + ps8640_pins: ps8640_pins { + pins1 { + pinmux = <MT8173_PIN_92_PCM_CLK__FUNC_GPIO92>, + <MT8173_PIN_115_URTS0__FUNC_GPIO115>, + <MT8173_PIN_127_LCM_RST__FUNC_GPIO127>; + }; + }; + + ps8640_fixed_pins: ps8640_fixed_pins { + pins1 { + pinmux = <MT8173_PIN_30_URTS2__FUNC_GPIO30>; + }; + }; + + rt5650_irq: rt5650_irq { + pins1 { + pinmux = <MT8173_PIN_3_EINT3__FUNC_GPIO3>; + bias-pull-down; + }; + }; + + sdio_fixed_3v3_pins: sdio_fixed_3v3_pins { + pins1 { + pinmux = <MT8173_PIN_85_AUD_DAT_MOSI__FUNC_GPIO85>; + output-low; + }; + }; + + spi_pins_a: spi1 { + pins1 { + pinmux = <MT8173_PIN_0_EINT0__FUNC_GPIO0>; + bias-pull-up; + }; + + pins_spi { + pinmux = <MT8173_PIN_102_MSDC2_DAT2__FUNC_SPI_CK_1_>, + <MT8173_PIN_103_MSDC2_DAT3__FUNC_SPI_MI_1_>, + <MT8173_PIN_104_MSDC2_CLK__FUNC_SPI_MO_1_>, + <MT8173_PIN_105_MSDC2_CMD__FUNC_SPI_CS_1_>; + bias-disable; + }; + }; + + trackpad_irq: trackpad_irq { + pins1 { + pinmux = <MT8173_PIN_117_URXD3__FUNC_GPIO117>; + input-enable; + bias-pull-up; + }; + }; + + usb_pins: usb { + pins1 { + pinmux = <MT8173_PIN_101_MSDC2_DAT1__FUNC_GPIO101>; + output-high; + bias-disable; + }; + }; + + wifi_wake_pins: wifi_wake_pins { + pins1 { + pinmux = <MT8173_PIN_38_CONN_RST__FUNC_GPIO38>; + bias-pull-up; + }; + }; +}; + +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&disp_pwm0_pins>; + status = "okay"; +}; + +&pwrap { + pmic: mt6397 { + compatible = "mediatek,mt6397"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + + clock: mt6397clock { + compatible = "mediatek,mt6397-clk"; + #clock-cells = <1>; + }; + + pio6397: pinctrl { + compatible = "mediatek,mt6397-pinctrl"; + pins-are-numbered; + gpio-controller; + #gpio-cells = <2>; + }; + + regulator: mt6397regulator { + compatible = "mediatek,mt6397-regulator"; + + mt6397_vpca15_reg: buck_vpca15 { + regulator-compatible = "buck_vpca15"; + regulator-name = "vpca15"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + regulator-allowed-modes = <0 1>; + }; + + mt6397_vpca7_reg: buck_vpca7 { + regulator-compatible = "buck_vpca7"; + regulator-name = "vpca7"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <115>; + regulator-always-on; + }; + + mt6397_vsramca15_reg: buck_vsramca15 { + regulator-compatible = "buck_vsramca15"; + regulator-name = "vsramca15"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vsramca7_reg: buck_vsramca7 { + regulator-compatible = "buck_vsramca7"; + regulator-name = "vsramca7"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vcore_reg: buck_vcore { + regulator-compatible = "buck_vcore"; + regulator-name = "vcore"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vgpu_reg: buck_vgpu { + regulator-compatible = "buck_vgpu"; + regulator-name = "vgpu"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <115>; + }; + + mt6397_vdrm_reg: buck_vdrm { + regulator-compatible = "buck_vdrm"; + regulator-name = "vdrm"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1400000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vio18_reg: buck_vio18 { + regulator-compatible = "buck_vio18"; + regulator-name = "vio18"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vtcxo_reg: ldo_vtcxo { + regulator-compatible = "ldo_vtcxo"; + regulator-name = "vtcxo"; + regulator-always-on; + }; + + mt6397_va28_reg: ldo_va28 { + regulator-compatible = "ldo_va28"; + regulator-name = "va28"; + }; + + mt6397_vcama_reg: ldo_vcama { + regulator-compatible = "ldo_vcama"; + regulator-name = "vcama"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vio28_reg: ldo_vio28 { + regulator-compatible = "ldo_vio28"; + regulator-name = "vio28"; + regulator-always-on; + }; + + mt6397_vusb_reg: ldo_vusb { + regulator-compatible = "ldo_vusb"; + regulator-name = "vusb"; + }; + + mt6397_vmc_reg: ldo_vmc { + regulator-compatible = "ldo_vmc"; + regulator-name = "vmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vmch_reg: ldo_vmch { + regulator-compatible = "ldo_vmch"; + regulator-name = "vmch"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vemc_3v3_reg: ldo_vemc3v3 { + regulator-compatible = "ldo_vemc3v3"; + regulator-name = "vemc_3v3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp1_reg: ldo_vgp1 { + regulator-compatible = "ldo_vgp1"; + regulator-name = "vcamd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <240>; + }; + + mt6397_vgp2_reg: ldo_vgp2 { + regulator-compatible = "ldo_vgp2"; + regulator-name = "vcamio"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp3_reg: ldo_vgp3 { + regulator-compatible = "ldo_vgp3"; + regulator-name = "vcamaf"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp4_reg: ldo_vgp4 { + regulator-compatible = "ldo_vgp4"; + regulator-name = "vgp4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp5_reg: ldo_vgp5 { + regulator-compatible = "ldo_vgp5"; + regulator-name = "vgp5"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp6_reg: ldo_vgp6 { + regulator-compatible = "ldo_vgp6"; + regulator-name = "vgp6"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + regulator-always-on; + }; + + mt6397_vibr_reg: ldo_vibr { + regulator-compatible = "ldo_vibr"; + regulator-name = "vibr"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + }; + + rtc: mt6397rtc { + compatible = "mediatek,mt6397-rtc"; + }; + + syscfg_pctl_pmic: syscfg_pctl_pmic@c000 { + compatible = "mediatek,mt6397-pctl-pmic-syscfg", + "syscon"; + reg = <0 0x0000c000 0 0x0108>; + }; + }; +}; + +&spi { + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins_a>; + mediatek,pad-select = <1>; + status = "okay"; + /* clients */ + cros_ec: ec@0 { + compatible = "google,cros-ec-spi"; + reg = <0x0>; + spi-max-frequency = <12000000>; + interrupt-parent = <&pio>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + google,cros-ec-spi-msg-delay = <500>; + + i2c_tunnel: i2c-tunnel0 { + compatible = "google,cros-ec-i2c-tunnel"; + google,remote-bus = <0>; + #address-cells = <1>; + #size-cells = <0>; + + battery: sbs-battery@b { + compatible = "sbs,sbs-battery"; + reg = <0xb>; + sbs,i2c-retry-count = <2>; + sbs,poll-retry-count = <1>; + }; + }; + }; +}; + +&ssusb { + dr_mode = "host"; + wakeup-source; + vusb33-supply = <&mt6397_vusb_reg>; + status = "okay"; +}; + +&thermal { + bank0-supply = <&mt6397_vpca15_reg>; + bank1-supply = <&da9211_vcpu_reg>; +}; + +&uart0 { + status = "okay"; +}; + +&usb_host { + pinctrl-names = "default"; + pinctrl-0 = <&usb_pins>; + vusb33-supply = <&mt6397_vusb_reg>; + status = "okay"; +}; + +#include <arm/cros-ec-keyboard.dtsi> diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts new file mode 100644 index 000000000..49c718524 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts @@ -0,0 +1,536 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Eddie Huang <eddie.huang@mediatek.com> + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include "mt8173.dtsi" + +/ { + model = "MediaTek MT8173 evaluation board"; + compatible = "mediatek,mt8173-evb", "mediatek,mt8173"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; + + chosen { }; + + connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "d"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi0_out>; + }; + }; + }; + + extcon_usb: extcon_iddig { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&pio 16 GPIO_ACTIVE_HIGH>; + }; + + usb_p1_vbus: regulator-usb-p1 { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 130 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_p0_vbus: regulator-usb-p0 { + compatible = "regulator-fixed"; + regulator-name = "vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&mfg_async { + domain-supply = <&da9211_vgpu_reg>; +}; + +&cec { + status = "okay"; +}; + +&cpu0 { + proc-supply = <&mt6397_vpca15_reg>; +}; + +&cpu1 { + proc-supply = <&mt6397_vpca15_reg>; +}; + +&cpu2 { + proc-supply = <&da9211_vcpu_reg>; + sram-supply = <&mt6397_vsramca7_reg>; +}; + +&cpu3 { + proc-supply = <&da9211_vcpu_reg>; + sram-supply = <&mt6397_vsramca7_reg>; +}; + +&dpi0 { + status = "okay"; +}; + +&hdmi_phy { + status = "okay"; +}; + +&hdmi0 { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + hdmi0_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + + buck: da9211@68 { + compatible = "dlg,da9211"; + reg = <0x68>; + + regulators { + da9211_vcpu_reg: BUCKA { + regulator-name = "VBUCKA"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1310000>; + regulator-min-microamp = <2000000>; + regulator-max-microamp = <4400000>; + regulator-ramp-delay = <10000>; + regulator-always-on; + }; + + da9211_vgpu_reg: BUCKB { + regulator-name = "VBUCKB"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1310000>; + regulator-min-microamp = <2000000>; + regulator-max-microamp = <3000000>; + regulator-ramp-delay = <10000>; + }; + }; + }; +}; + +&mmc0 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <8>; + max-frequency = <50000000>; + cap-mmc-highspeed; + mediatek,hs200-cmd-int-delay = <26>; + mediatek,hs400-cmd-int-delay = <14>; + mediatek,hs400-cmd-resp-sel-rising; + vmmc-supply = <&mt6397_vemc_3v3_reg>; + vqmmc-supply = <&mt6397_vio18_reg>; + non-removable; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_uhs>; + bus-width = <4>; + max-frequency = <50000000>; + cap-sd-highspeed; + sd-uhs-sdr25; + cd-gpios = <&pio 132 0>; + vmmc-supply = <&mt6397_vmch_reg>; + vqmmc-supply = <&mt6397_vmc_reg>; +}; + +&pio { + disp_pwm0_pins: disp_pwm0_pins { + pins1 { + pinmux = <MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0>; + output-low; + }; + }; + + mmc0_pins_default: mmc0default { + pins_cmd_dat { + pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>, + <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>, + <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>, + <MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3>, + <MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4>, + <MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5>, + <MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6>, + <MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>, + <MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>; + input-enable; + bias-pull-up; + }; + + pins_clk { + pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>; + bias-pull-down; + }; + + pins_rst { + pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>; + bias-pull-up; + }; + }; + + mmc1_pins_default: mmc1default { + pins_cmd_dat { + pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>, + <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>, + <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>, + <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>, + <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>; + input-enable; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_10>; + }; + + pins_clk { + pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>; + bias-pull-down; + drive-strength = <MTK_DRIVE_4mA>; + }; + + pins_insert { + pinmux = <MT8173_PIN_132_I2S0_DATA1__FUNC_GPIO132>; + bias-pull-up; + }; + }; + + mmc0_pins_uhs: mmc0 { + pins_cmd_dat { + pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>, + <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>, + <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>, + <MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3>, + <MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4>, + <MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5>, + <MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6>, + <MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>, + <MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>; + input-enable; + drive-strength = <MTK_DRIVE_2mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins_clk { + pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>; + drive-strength = <MTK_DRIVE_2mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_01>; + }; + + pins_rst { + pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>; + bias-pull-up; + }; + }; + + mmc1_pins_uhs: mmc1 { + pins_cmd_dat { + pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>, + <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>, + <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>, + <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>, + <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>; + input-enable; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_10>; + }; + + pins_clk { + pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + }; + + usb_id_pins_float: usb_iddig_pull_up { + pins_iddig { + pinmux = <MT8173_PIN_16_IDDIG__FUNC_IDDIG>; + bias-pull-up; + }; + }; + + usb_id_pins_ground: usb_iddig_pull_down { + pins_iddig { + pinmux = <MT8173_PIN_16_IDDIG__FUNC_IDDIG>; + bias-pull-down; + }; + }; +}; + +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&disp_pwm0_pins>; + status = "okay"; +}; + +&pwrap { + /* Only MT8173 E1 needs USB power domain */ + power-domains = <&spm MT8173_POWER_DOMAIN_USB>; + + pmic: mt6397 { + compatible = "mediatek,mt6397"; + interrupt-parent = <&pio>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + + mt6397regulator: mt6397regulator { + compatible = "mediatek,mt6397-regulator"; + + mt6397_vpca15_reg: buck_vpca15 { + regulator-compatible = "buck_vpca15"; + regulator-name = "vpca15"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vpca7_reg: buck_vpca7 { + regulator-compatible = "buck_vpca7"; + regulator-name = "vpca7"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <115>; + }; + + mt6397_vsramca15_reg: buck_vsramca15 { + regulator-compatible = "buck_vsramca15"; + regulator-name = "vsramca15"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vsramca7_reg: buck_vsramca7 { + regulator-compatible = "buck_vsramca7"; + regulator-name = "vsramca7"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vcore_reg: buck_vcore { + regulator-compatible = "buck_vcore"; + regulator-name = "vcore"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vgpu_reg: buck_vgpu { + regulator-compatible = "buck_vgpu"; + regulator-name = "vgpu"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <115>; + }; + + mt6397_vdrm_reg: buck_vdrm { + regulator-compatible = "buck_vdrm"; + regulator-name = "vdrm"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1400000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vio18_reg: buck_vio18 { + regulator-compatible = "buck_vio18"; + regulator-name = "vio18"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vtcxo_reg: ldo_vtcxo { + regulator-compatible = "ldo_vtcxo"; + regulator-name = "vtcxo"; + regulator-always-on; + }; + + mt6397_va28_reg: ldo_va28 { + regulator-compatible = "ldo_va28"; + regulator-name = "va28"; + regulator-always-on; + }; + + mt6397_vcama_reg: ldo_vcama { + regulator-compatible = "ldo_vcama"; + regulator-name = "vcama"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vio28_reg: ldo_vio28 { + regulator-compatible = "ldo_vio28"; + regulator-name = "vio28"; + regulator-always-on; + }; + + mt6397_vusb_reg: ldo_vusb { + regulator-compatible = "ldo_vusb"; + regulator-name = "vusb"; + }; + + mt6397_vmc_reg: ldo_vmc { + regulator-compatible = "ldo_vmc"; + regulator-name = "vmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vmch_reg: ldo_vmch { + regulator-compatible = "ldo_vmch"; + regulator-name = "vmch"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vemc_3v3_reg: ldo_vemc3v3 { + regulator-compatible = "ldo_vemc3v3"; + regulator-name = "vemc_3v3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp1_reg: ldo_vgp1 { + regulator-compatible = "ldo_vgp1"; + regulator-name = "vcamd"; + regulator-min-microvolt = <1220000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <240>; + }; + + mt6397_vgp2_reg: ldo_vgp2 { + regulator-compatible = "ldo_vgp2"; + regulator-name = "vcamio"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp3_reg: ldo_vgp3 { + regulator-compatible = "ldo_vgp3"; + regulator-name = "vcamaf"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp4_reg: ldo_vgp4 { + regulator-compatible = "ldo_vgp4"; + regulator-name = "vgp4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp5_reg: ldo_vgp5 { + regulator-compatible = "ldo_vgp5"; + regulator-name = "vgp5"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp6_reg: ldo_vgp6 { + regulator-compatible = "ldo_vgp6"; + regulator-name = "vgp6"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vibr_reg: ldo_vibr { + regulator-compatible = "ldo_vibr"; + regulator-name = "vibr"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + }; + }; +}; + +&pio { + spi_pins_a: spi0 { + pins_spi { + pinmux = <MT8173_PIN_69_SPI_CK__FUNC_SPI_CK_0_>, + <MT8173_PIN_70_SPI_MI__FUNC_SPI_MI_0_>, + <MT8173_PIN_71_SPI_MO__FUNC_SPI_MO_0_>, + <MT8173_PIN_72_SPI_CS__FUNC_SPI_CS_0_>; + }; + }; +}; + +&spi { + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins_a>; + mediatek,pad-select = <0>; + status = "okay"; +}; + +&ssusb { + vusb33-supply = <&mt6397_vusb_reg>; + vbus-supply = <&usb_p0_vbus>; + extcon = <&extcon_usb>; + dr_mode = "otg"; + wakeup-source; + pinctrl-names = "default"; + pinctrl-0 = <&usb_id_pins_float>; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&usb_host { + vusb33-supply = <&mt6397_vusb_reg>; + vbus-supply = <&usb_p1_vbus>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt8173-pinfunc.h new file mode 100644 index 000000000..a5e308dc8 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8173-pinfunc.h @@ -0,0 +1,674 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com> + */ + +#ifndef __DTS_MT8173_PINFUNC_H +#define __DTS_MT8173_PINFUNC_H + +#include <dt-bindings/pinctrl/mt65xx.h> + +#define MT8173_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT8173_PIN_0_EINT0__FUNC_IRDA_PDN (MTK_PIN_NO(0) | 1) +#define MT8173_PIN_0_EINT0__FUNC_I2S1_WS (MTK_PIN_NO(0) | 2) +#define MT8173_PIN_0_EINT0__FUNC_AUD_SPDIF (MTK_PIN_NO(0) | 3) +#define MT8173_PIN_0_EINT0__FUNC_UTXD0 (MTK_PIN_NO(0) | 4) +#define MT8173_PIN_0_EINT0__FUNC_DBG_MON_A_20_ (MTK_PIN_NO(0) | 7) + +#define MT8173_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT8173_PIN_1_EINT1__FUNC_IRDA_RXD (MTK_PIN_NO(1) | 1) +#define MT8173_PIN_1_EINT1__FUNC_I2S1_BCK (MTK_PIN_NO(1) | 2) +#define MT8173_PIN_1_EINT1__FUNC_SDA5 (MTK_PIN_NO(1) | 3) +#define MT8173_PIN_1_EINT1__FUNC_URXD0 (MTK_PIN_NO(1) | 4) +#define MT8173_PIN_1_EINT1__FUNC_DBG_MON_A_21_ (MTK_PIN_NO(1) | 7) + +#define MT8173_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT8173_PIN_2_EINT2__FUNC_IRDA_TXD (MTK_PIN_NO(2) | 1) +#define MT8173_PIN_2_EINT2__FUNC_I2S1_MCK (MTK_PIN_NO(2) | 2) +#define MT8173_PIN_2_EINT2__FUNC_SCL5 (MTK_PIN_NO(2) | 3) +#define MT8173_PIN_2_EINT2__FUNC_UTXD3 (MTK_PIN_NO(2) | 4) +#define MT8173_PIN_2_EINT2__FUNC_DBG_MON_A_22_ (MTK_PIN_NO(2) | 7) + +#define MT8173_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT8173_PIN_3_EINT3__FUNC_DSI1_TE (MTK_PIN_NO(3) | 1) +#define MT8173_PIN_3_EINT3__FUNC_I2S1_DO_1 (MTK_PIN_NO(3) | 2) +#define MT8173_PIN_3_EINT3__FUNC_SDA3 (MTK_PIN_NO(3) | 3) +#define MT8173_PIN_3_EINT3__FUNC_URXD3 (MTK_PIN_NO(3) | 4) +#define MT8173_PIN_3_EINT3__FUNC_DBG_MON_A_23_ (MTK_PIN_NO(3) | 7) + +#define MT8173_PIN_4_EINT4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT8173_PIN_4_EINT4__FUNC_DISP_PWM1 (MTK_PIN_NO(4) | 1) +#define MT8173_PIN_4_EINT4__FUNC_I2S1_DO_2 (MTK_PIN_NO(4) | 2) +#define MT8173_PIN_4_EINT4__FUNC_SCL3 (MTK_PIN_NO(4) | 3) +#define MT8173_PIN_4_EINT4__FUNC_UCTS3 (MTK_PIN_NO(4) | 4) +#define MT8173_PIN_4_EINT4__FUNC_SFWP_B (MTK_PIN_NO(4) | 6) + +#define MT8173_PIN_5_EINT5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT8173_PIN_5_EINT5__FUNC_PCM1_CLK (MTK_PIN_NO(5) | 1) +#define MT8173_PIN_5_EINT5__FUNC_I2S2_WS (MTK_PIN_NO(5) | 2) +#define MT8173_PIN_5_EINT5__FUNC_SPI_CK_3_ (MTK_PIN_NO(5) | 3) +#define MT8173_PIN_5_EINT5__FUNC_URTS3 (MTK_PIN_NO(5) | 4) +#define MT8173_PIN_5_EINT5__FUNC_AP_MD32_JTAG_TMS (MTK_PIN_NO(5) | 5) +#define MT8173_PIN_5_EINT5__FUNC_SFOUT (MTK_PIN_NO(5) | 6) + +#define MT8173_PIN_6_EINT6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT8173_PIN_6_EINT6__FUNC_PCM1_SYNC (MTK_PIN_NO(6) | 1) +#define MT8173_PIN_6_EINT6__FUNC_I2S2_BCK (MTK_PIN_NO(6) | 2) +#define MT8173_PIN_6_EINT6__FUNC_SPI_MI_3_ (MTK_PIN_NO(6) | 3) +#define MT8173_PIN_6_EINT6__FUNC_AP_MD32_JTAG_TCK (MTK_PIN_NO(6) | 5) +#define MT8173_PIN_6_EINT6__FUNC_SFCS0 (MTK_PIN_NO(6) | 6) + +#define MT8173_PIN_7_EINT7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define MT8173_PIN_7_EINT7__FUNC_PCM1_DI (MTK_PIN_NO(7) | 1) +#define MT8173_PIN_7_EINT7__FUNC_I2S2_DI_1 (MTK_PIN_NO(7) | 2) +#define MT8173_PIN_7_EINT7__FUNC_SPI_MO_3_ (MTK_PIN_NO(7) | 3) +#define MT8173_PIN_7_EINT7__FUNC_AP_MD32_JTAG_TDI (MTK_PIN_NO(7) | 5) +#define MT8173_PIN_7_EINT7__FUNC_SFHOLD (MTK_PIN_NO(7) | 6) + +#define MT8173_PIN_8_EINT8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define MT8173_PIN_8_EINT8__FUNC_PCM1_DO (MTK_PIN_NO(8) | 1) +#define MT8173_PIN_8_EINT8__FUNC_I2S2_DI_2 (MTK_PIN_NO(8) | 2) +#define MT8173_PIN_8_EINT8__FUNC_SPI_CS_3_ (MTK_PIN_NO(8) | 3) +#define MT8173_PIN_8_EINT8__FUNC_AUD_SPDIF (MTK_PIN_NO(8) | 4) +#define MT8173_PIN_8_EINT8__FUNC_AP_MD32_JTAG_TDO (MTK_PIN_NO(8) | 5) +#define MT8173_PIN_8_EINT8__FUNC_SFIN (MTK_PIN_NO(8) | 6) + +#define MT8173_PIN_9_EINT9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define MT8173_PIN_9_EINT9__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(9) | 1) +#define MT8173_PIN_9_EINT9__FUNC_I2S2_MCK (MTK_PIN_NO(9) | 2) +#define MT8173_PIN_9_EINT9__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(9) | 4) +#define MT8173_PIN_9_EINT9__FUNC_AP_MD32_JTAG_TRST (MTK_PIN_NO(9) | 5) +#define MT8173_PIN_9_EINT9__FUNC_SFCK (MTK_PIN_NO(9) | 6) + +#define MT8173_PIN_10_EINT10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define MT8173_PIN_10_EINT10__FUNC_CLKM0 (MTK_PIN_NO(10) | 1) +#define MT8173_PIN_10_EINT10__FUNC_DSI1_TE (MTK_PIN_NO(10) | 2) +#define MT8173_PIN_10_EINT10__FUNC_DISP_PWM1 (MTK_PIN_NO(10) | 3) +#define MT8173_PIN_10_EINT10__FUNC_PWM4 (MTK_PIN_NO(10) | 4) +#define MT8173_PIN_10_EINT10__FUNC_IRDA_RXD (MTK_PIN_NO(10) | 5) + +#define MT8173_PIN_11_EINT11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define MT8173_PIN_11_EINT11__FUNC_CLKM1 (MTK_PIN_NO(11) | 1) +#define MT8173_PIN_11_EINT11__FUNC_I2S3_WS (MTK_PIN_NO(11) | 2) +#define MT8173_PIN_11_EINT11__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(11) | 3) +#define MT8173_PIN_11_EINT11__FUNC_PWM5 (MTK_PIN_NO(11) | 4) +#define MT8173_PIN_11_EINT11__FUNC_IRDA_TXD (MTK_PIN_NO(11) | 5) +#define MT8173_PIN_11_EINT11__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(11) | 6) +#define MT8173_PIN_11_EINT11__FUNC_DBG_MON_B_30_ (MTK_PIN_NO(11) | 7) + +#define MT8173_PIN_12_EINT12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define MT8173_PIN_12_EINT12__FUNC_CLKM2 (MTK_PIN_NO(12) | 1) +#define MT8173_PIN_12_EINT12__FUNC_I2S3_BCK (MTK_PIN_NO(12) | 2) +#define MT8173_PIN_12_EINT12__FUNC_SRCLKENA0 (MTK_PIN_NO(12) | 3) +#define MT8173_PIN_12_EINT12__FUNC_I2S2_WS (MTK_PIN_NO(12) | 5) +#define MT8173_PIN_12_EINT12__FUNC_DBG_MON_B_32_ (MTK_PIN_NO(12) | 7) + +#define MT8173_PIN_13_EINT13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define MT8173_PIN_13_EINT13__FUNC_CLKM3 (MTK_PIN_NO(13) | 1) +#define MT8173_PIN_13_EINT13__FUNC_I2S3_MCK (MTK_PIN_NO(13) | 2) +#define MT8173_PIN_13_EINT13__FUNC_SRCLKENA0 (MTK_PIN_NO(13) | 3) +#define MT8173_PIN_13_EINT13__FUNC_I2S2_BCK (MTK_PIN_NO(13) | 5) +#define MT8173_PIN_13_EINT13__FUNC_DBG_MON_A_32_ (MTK_PIN_NO(13) | 7) + +#define MT8173_PIN_14_EINT14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define MT8173_PIN_14_EINT14__FUNC_CMDAT0 (MTK_PIN_NO(14) | 1) +#define MT8173_PIN_14_EINT14__FUNC_CMCSD0 (MTK_PIN_NO(14) | 2) +#define MT8173_PIN_14_EINT14__FUNC_CLKM2 (MTK_PIN_NO(14) | 4) +#define MT8173_PIN_14_EINT14__FUNC_DBG_MON_B_6_ (MTK_PIN_NO(14) | 7) + +#define MT8173_PIN_15_EINT15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define MT8173_PIN_15_EINT15__FUNC_CMDAT1 (MTK_PIN_NO(15) | 1) +#define MT8173_PIN_15_EINT15__FUNC_CMCSD1 (MTK_PIN_NO(15) | 2) +#define MT8173_PIN_15_EINT15__FUNC_CMFLASH (MTK_PIN_NO(15) | 3) +#define MT8173_PIN_15_EINT15__FUNC_CLKM3 (MTK_PIN_NO(15) | 4) +#define MT8173_PIN_15_EINT15__FUNC_DBG_MON_B_29_ (MTK_PIN_NO(15) | 7) + +#define MT8173_PIN_16_IDDIG__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define MT8173_PIN_16_IDDIG__FUNC_IDDIG (MTK_PIN_NO(16) | 1) +#define MT8173_PIN_16_IDDIG__FUNC_CMFLASH (MTK_PIN_NO(16) | 2) +#define MT8173_PIN_16_IDDIG__FUNC_PWM5 (MTK_PIN_NO(16) | 4) + +#define MT8173_PIN_17_WATCHDOG__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define MT8173_PIN_17_WATCHDOG__FUNC_WATCHDOG_AO (MTK_PIN_NO(17) | 1) + +#define MT8173_PIN_18_CEC__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define MT8173_PIN_18_CEC__FUNC_CEC (MTK_PIN_NO(18) | 1) + +#define MT8173_PIN_19_HDMISCK__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define MT8173_PIN_19_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(19) | 1) +#define MT8173_PIN_19_HDMISCK__FUNC_HDCP_SCL (MTK_PIN_NO(19) | 2) + +#define MT8173_PIN_20_HDMISD__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define MT8173_PIN_20_HDMISD__FUNC_HDMISD (MTK_PIN_NO(20) | 1) +#define MT8173_PIN_20_HDMISD__FUNC_HDCP_SDA (MTK_PIN_NO(20) | 2) + +#define MT8173_PIN_21_HTPLG__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define MT8173_PIN_21_HTPLG__FUNC_HTPLG (MTK_PIN_NO(21) | 1) + +#define MT8173_PIN_22_MSDC3_DAT0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(22) | 1) + +#define MT8173_PIN_23_MSDC3_DAT1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(23) | 1) + +#define MT8173_PIN_24_MSDC3_DAT2__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(24) | 1) + +#define MT8173_PIN_25_MSDC3_DAT3__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(25) | 1) + +#define MT8173_PIN_26_MSDC3_CLK__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(26) | 1) + +#define MT8173_PIN_27_MSDC3_CMD__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(27) | 1) + +#define MT8173_PIN_28_MSDC3_DSL__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define MT8173_PIN_28_MSDC3_DSL__FUNC_MSDC3_DSL (MTK_PIN_NO(28) | 1) + +#define MT8173_PIN_29_UCTS2__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define MT8173_PIN_29_UCTS2__FUNC_UCTS2 (MTK_PIN_NO(29) | 1) + +#define MT8173_PIN_30_URTS2__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define MT8173_PIN_30_URTS2__FUNC_URTS2 (MTK_PIN_NO(30) | 1) + +#define MT8173_PIN_31_URXD2__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define MT8173_PIN_31_URXD2__FUNC_URXD2 (MTK_PIN_NO(31) | 1) +#define MT8173_PIN_31_URXD2__FUNC_UTXD2 (MTK_PIN_NO(31) | 2) + +#define MT8173_PIN_32_UTXD2__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define MT8173_PIN_32_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(32) | 1) +#define MT8173_PIN_32_UTXD2__FUNC_URXD2 (MTK_PIN_NO(32) | 2) + +#define MT8173_PIN_33_DAICLK__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define MT8173_PIN_33_DAICLK__FUNC_MRG_CLK (MTK_PIN_NO(33) | 1) +#define MT8173_PIN_33_DAICLK__FUNC_PCM0_CLK (MTK_PIN_NO(33) | 2) + +#define MT8173_PIN_34_DAIPCMIN__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define MT8173_PIN_34_DAIPCMIN__FUNC_MRG_DI (MTK_PIN_NO(34) | 1) +#define MT8173_PIN_34_DAIPCMIN__FUNC_PCM0_DI (MTK_PIN_NO(34) | 2) + +#define MT8173_PIN_35_DAIPCMOUT__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define MT8173_PIN_35_DAIPCMOUT__FUNC_MRG_DO (MTK_PIN_NO(35) | 1) +#define MT8173_PIN_35_DAIPCMOUT__FUNC_PCM0_DO (MTK_PIN_NO(35) | 2) + +#define MT8173_PIN_36_DAISYNC__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define MT8173_PIN_36_DAISYNC__FUNC_MRG_SYNC (MTK_PIN_NO(36) | 1) +#define MT8173_PIN_36_DAISYNC__FUNC_PCM0_SYNC (MTK_PIN_NO(36) | 2) + +#define MT8173_PIN_37_EINT16__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define MT8173_PIN_37_EINT16__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(37) | 1) +#define MT8173_PIN_37_EINT16__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(37) | 2) +#define MT8173_PIN_37_EINT16__FUNC_PWM0 (MTK_PIN_NO(37) | 3) +#define MT8173_PIN_37_EINT16__FUNC_PWM1 (MTK_PIN_NO(37) | 4) +#define MT8173_PIN_37_EINT16__FUNC_PWM2 (MTK_PIN_NO(37) | 5) +#define MT8173_PIN_37_EINT16__FUNC_CLKM0 (MTK_PIN_NO(37) | 6) + +#define MT8173_PIN_38_CONN_RST__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define MT8173_PIN_38_CONN_RST__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(38) | 1) +#define MT8173_PIN_38_CONN_RST__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(38) | 2) +#define MT8173_PIN_38_CONN_RST__FUNC_CLKM1 (MTK_PIN_NO(38) | 6) + +#define MT8173_PIN_39_CM2MCLK__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define MT8173_PIN_39_CM2MCLK__FUNC_CM2MCLK (MTK_PIN_NO(39) | 1) +#define MT8173_PIN_39_CM2MCLK__FUNC_CMCSD0 (MTK_PIN_NO(39) | 2) +#define MT8173_PIN_39_CM2MCLK__FUNC_DBG_MON_A_17_ (MTK_PIN_NO(39) | 7) + +#define MT8173_PIN_40_CMPCLK__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define MT8173_PIN_40_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(40) | 1) +#define MT8173_PIN_40_CMPCLK__FUNC_CMCSK (MTK_PIN_NO(40) | 2) +#define MT8173_PIN_40_CMPCLK__FUNC_CMCSD2 (MTK_PIN_NO(40) | 3) +#define MT8173_PIN_40_CMPCLK__FUNC_DBG_MON_A_18_ (MTK_PIN_NO(40) | 7) + +#define MT8173_PIN_41_CMMCLK__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define MT8173_PIN_41_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(41) | 1) +#define MT8173_PIN_41_CMMCLK__FUNC_DBG_MON_A_19_ (MTK_PIN_NO(41) | 7) + +#define MT8173_PIN_42_DSI_TE__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define MT8173_PIN_42_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(42) | 1) + +#define MT8173_PIN_43_SDA2__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define MT8173_PIN_43_SDA2__FUNC_SDA2 (MTK_PIN_NO(43) | 1) + +#define MT8173_PIN_44_SCL2__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define MT8173_PIN_44_SCL2__FUNC_SCL2 (MTK_PIN_NO(44) | 1) + +#define MT8173_PIN_45_SDA0__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define MT8173_PIN_45_SDA0__FUNC_SDA0 (MTK_PIN_NO(45) | 1) + +#define MT8173_PIN_46_SCL0__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define MT8173_PIN_46_SCL0__FUNC_SCL0 (MTK_PIN_NO(46) | 1) + +#define MT8173_PIN_47_RDN0_A__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define MT8173_PIN_47_RDN0_A__FUNC_CMDAT2 (MTK_PIN_NO(47) | 1) + +#define MT8173_PIN_48_RDP0_A__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define MT8173_PIN_48_RDP0_A__FUNC_CMDAT3 (MTK_PIN_NO(48) | 1) + +#define MT8173_PIN_49_RDN1_A__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define MT8173_PIN_49_RDN1_A__FUNC_CMDAT4 (MTK_PIN_NO(49) | 1) + +#define MT8173_PIN_50_RDP1_A__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define MT8173_PIN_50_RDP1_A__FUNC_CMDAT5 (MTK_PIN_NO(50) | 1) + +#define MT8173_PIN_51_RCN_A__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define MT8173_PIN_51_RCN_A__FUNC_CMDAT6 (MTK_PIN_NO(51) | 1) + +#define MT8173_PIN_52_RCP_A__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define MT8173_PIN_52_RCP_A__FUNC_CMDAT7 (MTK_PIN_NO(52) | 1) + +#define MT8173_PIN_53_RDN2_A__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define MT8173_PIN_53_RDN2_A__FUNC_CMDAT8 (MTK_PIN_NO(53) | 1) +#define MT8173_PIN_53_RDN2_A__FUNC_CMCSD3 (MTK_PIN_NO(53) | 2) + +#define MT8173_PIN_54_RDP2_A__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define MT8173_PIN_54_RDP2_A__FUNC_CMDAT9 (MTK_PIN_NO(54) | 1) +#define MT8173_PIN_54_RDP2_A__FUNC_CMCSD2 (MTK_PIN_NO(54) | 2) + +#define MT8173_PIN_55_RDN3_A__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define MT8173_PIN_55_RDN3_A__FUNC_CMHSYNC (MTK_PIN_NO(55) | 1) +#define MT8173_PIN_55_RDN3_A__FUNC_CMCSD1 (MTK_PIN_NO(55) | 2) + +#define MT8173_PIN_56_RDP3_A__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define MT8173_PIN_56_RDP3_A__FUNC_CMVSYNC (MTK_PIN_NO(56) | 1) +#define MT8173_PIN_56_RDP3_A__FUNC_CMCSD0 (MTK_PIN_NO(56) | 2) + +#define MT8173_PIN_57_MSDC0_DAT0__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(57) | 1) +#define MT8173_PIN_57_MSDC0_DAT0__FUNC_I2S1_WS (MTK_PIN_NO(57) | 2) +#define MT8173_PIN_57_MSDC0_DAT0__FUNC_DBG_MON_B_7_ (MTK_PIN_NO(57) | 7) + +#define MT8173_PIN_58_MSDC0_DAT1__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(58) | 1) +#define MT8173_PIN_58_MSDC0_DAT1__FUNC_I2S1_BCK (MTK_PIN_NO(58) | 2) +#define MT8173_PIN_58_MSDC0_DAT1__FUNC_DBG_MON_B_8_ (MTK_PIN_NO(58) | 7) + +#define MT8173_PIN_59_MSDC0_DAT2__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(59) | 1) +#define MT8173_PIN_59_MSDC0_DAT2__FUNC_I2S1_MCK (MTK_PIN_NO(59) | 2) +#define MT8173_PIN_59_MSDC0_DAT2__FUNC_DBG_MON_B_9_ (MTK_PIN_NO(59) | 7) + +#define MT8173_PIN_60_MSDC0_DAT3__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(60) | 1) +#define MT8173_PIN_60_MSDC0_DAT3__FUNC_I2S1_DO_1 (MTK_PIN_NO(60) | 2) +#define MT8173_PIN_60_MSDC0_DAT3__FUNC_DBG_MON_B_10_ (MTK_PIN_NO(60) | 7) + +#define MT8173_PIN_61_MSDC0_DAT4__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(61) | 1) +#define MT8173_PIN_61_MSDC0_DAT4__FUNC_I2S1_DO_2 (MTK_PIN_NO(61) | 2) +#define MT8173_PIN_61_MSDC0_DAT4__FUNC_DBG_MON_B_11_ (MTK_PIN_NO(61) | 7) + +#define MT8173_PIN_62_MSDC0_DAT5__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(62) | 1) +#define MT8173_PIN_62_MSDC0_DAT5__FUNC_I2S2_WS (MTK_PIN_NO(62) | 2) +#define MT8173_PIN_62_MSDC0_DAT5__FUNC_DBG_MON_B_12_ (MTK_PIN_NO(62) | 7) + +#define MT8173_PIN_63_MSDC0_DAT6__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(63) | 1) +#define MT8173_PIN_63_MSDC0_DAT6__FUNC_I2S2_BCK (MTK_PIN_NO(63) | 2) +#define MT8173_PIN_63_MSDC0_DAT6__FUNC_DBG_MON_B_13_ (MTK_PIN_NO(63) | 7) + +#define MT8173_PIN_64_MSDC0_DAT7__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(64) | 1) +#define MT8173_PIN_64_MSDC0_DAT7__FUNC_I2S2_DI_1 (MTK_PIN_NO(64) | 2) +#define MT8173_PIN_64_MSDC0_DAT7__FUNC_DBG_MON_B_14_ (MTK_PIN_NO(64) | 7) + +#define MT8173_PIN_65_MSDC0_CLK__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(65) | 1) +#define MT8173_PIN_65_MSDC0_CLK__FUNC_DBG_MON_B_16_ (MTK_PIN_NO(65) | 7) + +#define MT8173_PIN_66_MSDC0_CMD__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(66) | 1) +#define MT8173_PIN_66_MSDC0_CMD__FUNC_I2S2_DI_2 (MTK_PIN_NO(66) | 2) +#define MT8173_PIN_66_MSDC0_CMD__FUNC_DBG_MON_B_15_ (MTK_PIN_NO(66) | 7) + +#define MT8173_PIN_67_MSDC0_DSL__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define MT8173_PIN_67_MSDC0_DSL__FUNC_MSDC0_DSL (MTK_PIN_NO(67) | 1) +#define MT8173_PIN_67_MSDC0_DSL__FUNC_DBG_MON_B_17_ (MTK_PIN_NO(67) | 7) + +#define MT8173_PIN_68_MSDC0_RST___FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB (MTK_PIN_NO(68) | 1) +#define MT8173_PIN_68_MSDC0_RST___FUNC_I2S2_MCK (MTK_PIN_NO(68) | 2) +#define MT8173_PIN_68_MSDC0_RST___FUNC_DBG_MON_B_18_ (MTK_PIN_NO(68) | 7) + +#define MT8173_PIN_69_SPI_CK__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define MT8173_PIN_69_SPI_CK__FUNC_SPI_CK_0_ (MTK_PIN_NO(69) | 1) +#define MT8173_PIN_69_SPI_CK__FUNC_I2S3_DO_1 (MTK_PIN_NO(69) | 2) +#define MT8173_PIN_69_SPI_CK__FUNC_PWM0 (MTK_PIN_NO(69) | 3) +#define MT8173_PIN_69_SPI_CK__FUNC_PWM5 (MTK_PIN_NO(69) | 4) +#define MT8173_PIN_69_SPI_CK__FUNC_I2S2_MCK (MTK_PIN_NO(69) | 5) +#define MT8173_PIN_69_SPI_CK__FUNC_DBG_MON_B_19_ (MTK_PIN_NO(69) | 7) + +#define MT8173_PIN_70_SPI_MI__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define MT8173_PIN_70_SPI_MI__FUNC_SPI_MI_0_ (MTK_PIN_NO(70) | 1) +#define MT8173_PIN_70_SPI_MI__FUNC_I2S3_DO_2 (MTK_PIN_NO(70) | 2) +#define MT8173_PIN_70_SPI_MI__FUNC_PWM1 (MTK_PIN_NO(70) | 3) +#define MT8173_PIN_70_SPI_MI__FUNC_SPI_MO_0_ (MTK_PIN_NO(70) | 4) +#define MT8173_PIN_70_SPI_MI__FUNC_I2S2_DI_1 (MTK_PIN_NO(70) | 5) +#define MT8173_PIN_70_SPI_MI__FUNC_DSI1_TE (MTK_PIN_NO(70) | 6) +#define MT8173_PIN_70_SPI_MI__FUNC_DBG_MON_B_20_ (MTK_PIN_NO(70) | 7) + +#define MT8173_PIN_71_SPI_MO__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define MT8173_PIN_71_SPI_MO__FUNC_SPI_MO_0_ (MTK_PIN_NO(71) | 1) +#define MT8173_PIN_71_SPI_MO__FUNC_I2S3_DO_3 (MTK_PIN_NO(71) | 2) +#define MT8173_PIN_71_SPI_MO__FUNC_PWM2 (MTK_PIN_NO(71) | 3) +#define MT8173_PIN_71_SPI_MO__FUNC_SPI_MI_0_ (MTK_PIN_NO(71) | 4) +#define MT8173_PIN_71_SPI_MO__FUNC_I2S2_DI_2 (MTK_PIN_NO(71) | 5) +#define MT8173_PIN_71_SPI_MO__FUNC_DBG_MON_B_21_ (MTK_PIN_NO(71) | 7) + +#define MT8173_PIN_72_SPI_CS__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define MT8173_PIN_72_SPI_CS__FUNC_SPI_CS_0_ (MTK_PIN_NO(72) | 1) +#define MT8173_PIN_72_SPI_CS__FUNC_I2S3_DO_4 (MTK_PIN_NO(72) | 2) +#define MT8173_PIN_72_SPI_CS__FUNC_PWM3 (MTK_PIN_NO(72) | 3) +#define MT8173_PIN_72_SPI_CS__FUNC_PWM6 (MTK_PIN_NO(72) | 4) +#define MT8173_PIN_72_SPI_CS__FUNC_DISP_PWM1 (MTK_PIN_NO(72) | 5) +#define MT8173_PIN_72_SPI_CS__FUNC_DBG_MON_B_22_ (MTK_PIN_NO(72) | 7) + +#define MT8173_PIN_73_MSDC1_DAT0__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(73) | 1) +#define MT8173_PIN_73_MSDC1_DAT0__FUNC_DBG_MON_B_24_ (MTK_PIN_NO(73) | 7) + +#define MT8173_PIN_74_MSDC1_DAT1__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(74) | 1) +#define MT8173_PIN_74_MSDC1_DAT1__FUNC_DBG_MON_B_25_ (MTK_PIN_NO(74) | 7) + +#define MT8173_PIN_75_MSDC1_DAT2__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(75) | 1) +#define MT8173_PIN_75_MSDC1_DAT2__FUNC_DBG_MON_B_26_ (MTK_PIN_NO(75) | 7) + +#define MT8173_PIN_76_MSDC1_DAT3__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(76) | 1) +#define MT8173_PIN_76_MSDC1_DAT3__FUNC_DBG_MON_B_27_ (MTK_PIN_NO(76) | 7) + +#define MT8173_PIN_77_MSDC1_CLK__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(77) | 1) +#define MT8173_PIN_77_MSDC1_CLK__FUNC_DBG_MON_B_28_ (MTK_PIN_NO(77) | 7) + +#define MT8173_PIN_78_MSDC1_CMD__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(78) | 1) +#define MT8173_PIN_78_MSDC1_CMD__FUNC_DBG_MON_B_23_ (MTK_PIN_NO(78) | 7) + +#define MT8173_PIN_79_PWRAP_SPI0_MI__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define MT8173_PIN_79_PWRAP_SPI0_MI__FUNC_PWRAP_SPIMI (MTK_PIN_NO(79) | 1) +#define MT8173_PIN_79_PWRAP_SPI0_MI__FUNC_PWRAP_SPIMO (MTK_PIN_NO(79) | 2) + +#define MT8173_PIN_80_PWRAP_SPI0_MO__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define MT8173_PIN_80_PWRAP_SPI0_MO__FUNC_PWRAP_SPIMO (MTK_PIN_NO(80) | 1) +#define MT8173_PIN_80_PWRAP_SPI0_MO__FUNC_PWRAP_SPIMI (MTK_PIN_NO(80) | 2) + +#define MT8173_PIN_81_PWRAP_SPI0_CK__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define MT8173_PIN_81_PWRAP_SPI0_CK__FUNC_PWRAP_SPICK (MTK_PIN_NO(81) | 1) + +#define MT8173_PIN_82_PWRAP_SPI0_CSN__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define MT8173_PIN_82_PWRAP_SPI0_CSN__FUNC_PWRAP_SPICS (MTK_PIN_NO(82) | 1) + +#define MT8173_PIN_83_AUD_CLK_MOSI__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define MT8173_PIN_83_AUD_CLK_MOSI__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(83) | 1) + +#define MT8173_PIN_84_AUD_DAT_MISO__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define MT8173_PIN_84_AUD_DAT_MISO__FUNC_AUD_DAT_MISO (MTK_PIN_NO(84) | 1) +#define MT8173_PIN_84_AUD_DAT_MISO__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(84) | 2) + +#define MT8173_PIN_85_AUD_DAT_MOSI__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +#define MT8173_PIN_85_AUD_DAT_MOSI__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(85) | 1) +#define MT8173_PIN_85_AUD_DAT_MOSI__FUNC_AUD_DAT_MISO (MTK_PIN_NO(85) | 2) + +#define MT8173_PIN_86_RTC32K_CK__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +#define MT8173_PIN_86_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(86) | 1) + +#define MT8173_PIN_87_DISP_PWM0__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +#define MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0 (MTK_PIN_NO(87) | 1) +#define MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM1 (MTK_PIN_NO(87) | 2) +#define MT8173_PIN_87_DISP_PWM0__FUNC_DBG_MON_B_31_ (MTK_PIN_NO(87) | 7) + +#define MT8173_PIN_88_SRCLKENAI__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +#define MT8173_PIN_88_SRCLKENAI__FUNC_SRCLKENAI (MTK_PIN_NO(88) | 1) + +#define MT8173_PIN_89_SRCLKENAI2__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +#define MT8173_PIN_89_SRCLKENAI2__FUNC_SRCLKENAI2 (MTK_PIN_NO(89) | 1) + +#define MT8173_PIN_90_SRCLKENA0__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +#define MT8173_PIN_90_SRCLKENA0__FUNC_SRCLKENA0 (MTK_PIN_NO(90) | 1) + +#define MT8173_PIN_91_SRCLKENA1__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define MT8173_PIN_91_SRCLKENA1__FUNC_SRCLKENA1 (MTK_PIN_NO(91) | 1) + +#define MT8173_PIN_92_PCM_CLK__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define MT8173_PIN_92_PCM_CLK__FUNC_PCM1_CLK (MTK_PIN_NO(92) | 1) +#define MT8173_PIN_92_PCM_CLK__FUNC_I2S0_BCK (MTK_PIN_NO(92) | 2) +#define MT8173_PIN_92_PCM_CLK__FUNC_DBG_MON_A_24_ (MTK_PIN_NO(92) | 7) + +#define MT8173_PIN_93_PCM_SYNC__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define MT8173_PIN_93_PCM_SYNC__FUNC_PCM1_SYNC (MTK_PIN_NO(93) | 1) +#define MT8173_PIN_93_PCM_SYNC__FUNC_I2S0_WS (MTK_PIN_NO(93) | 2) +#define MT8173_PIN_93_PCM_SYNC__FUNC_DBG_MON_A_25_ (MTK_PIN_NO(93) | 7) + +#define MT8173_PIN_94_PCM_RX__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define MT8173_PIN_94_PCM_RX__FUNC_PCM1_DI (MTK_PIN_NO(94) | 1) +#define MT8173_PIN_94_PCM_RX__FUNC_I2S0_DI (MTK_PIN_NO(94) | 2) +#define MT8173_PIN_94_PCM_RX__FUNC_DBG_MON_A_26_ (MTK_PIN_NO(94) | 7) + +#define MT8173_PIN_95_PCM_TX__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +#define MT8173_PIN_95_PCM_TX__FUNC_PCM1_DO (MTK_PIN_NO(95) | 1) +#define MT8173_PIN_95_PCM_TX__FUNC_I2S0_DO (MTK_PIN_NO(95) | 2) +#define MT8173_PIN_95_PCM_TX__FUNC_DBG_MON_A_27_ (MTK_PIN_NO(95) | 7) + +#define MT8173_PIN_96_URXD1__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +#define MT8173_PIN_96_URXD1__FUNC_URXD1 (MTK_PIN_NO(96) | 1) +#define MT8173_PIN_96_URXD1__FUNC_UTXD1 (MTK_PIN_NO(96) | 2) +#define MT8173_PIN_96_URXD1__FUNC_DBG_MON_A_28_ (MTK_PIN_NO(96) | 7) + +#define MT8173_PIN_97_UTXD1__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +#define MT8173_PIN_97_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(97) | 1) +#define MT8173_PIN_97_UTXD1__FUNC_URXD1 (MTK_PIN_NO(97) | 2) +#define MT8173_PIN_97_UTXD1__FUNC_DBG_MON_A_29_ (MTK_PIN_NO(97) | 7) + +#define MT8173_PIN_98_URTS1__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +#define MT8173_PIN_98_URTS1__FUNC_URTS1 (MTK_PIN_NO(98) | 1) +#define MT8173_PIN_98_URTS1__FUNC_UCTS1 (MTK_PIN_NO(98) | 2) +#define MT8173_PIN_98_URTS1__FUNC_DBG_MON_A_30_ (MTK_PIN_NO(98) | 7) + +#define MT8173_PIN_99_UCTS1__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +#define MT8173_PIN_99_UCTS1__FUNC_UCTS1 (MTK_PIN_NO(99) | 1) +#define MT8173_PIN_99_UCTS1__FUNC_URTS1 (MTK_PIN_NO(99) | 2) +#define MT8173_PIN_99_UCTS1__FUNC_DBG_MON_A_31_ (MTK_PIN_NO(99) | 7) + +#define MT8173_PIN_100_MSDC2_DAT0__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define MT8173_PIN_100_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(100) | 1) +#define MT8173_PIN_100_MSDC2_DAT0__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(100) | 3) +#define MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5 (MTK_PIN_NO(100) | 4) +#define MT8173_PIN_100_MSDC2_DAT0__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(100) | 5) +#define MT8173_PIN_100_MSDC2_DAT0__FUNC_DBG_MON_B_0_ (MTK_PIN_NO(100) | 7) + +#define MT8173_PIN_101_MSDC2_DAT1__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define MT8173_PIN_101_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(101) | 1) +#define MT8173_PIN_101_MSDC2_DAT1__FUNC_AUD_SPDIF (MTK_PIN_NO(101) | 3) +#define MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5 (MTK_PIN_NO(101) | 4) +#define MT8173_PIN_101_MSDC2_DAT1__FUNC_DBG_MON_B_1_ (MTK_PIN_NO(101) | 7) + +#define MT8173_PIN_102_MSDC2_DAT2__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define MT8173_PIN_102_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(102) | 1) +#define MT8173_PIN_102_MSDC2_DAT2__FUNC_UTXD0 (MTK_PIN_NO(102) | 3) +#define MT8173_PIN_102_MSDC2_DAT2__FUNC_PWM0 (MTK_PIN_NO(102) | 5) +#define MT8173_PIN_102_MSDC2_DAT2__FUNC_SPI_CK_1_ (MTK_PIN_NO(102) | 6) +#define MT8173_PIN_102_MSDC2_DAT2__FUNC_DBG_MON_B_2_ (MTK_PIN_NO(102) | 7) + +#define MT8173_PIN_103_MSDC2_DAT3__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define MT8173_PIN_103_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(103) | 1) +#define MT8173_PIN_103_MSDC2_DAT3__FUNC_URXD0 (MTK_PIN_NO(103) | 3) +#define MT8173_PIN_103_MSDC2_DAT3__FUNC_PWM1 (MTK_PIN_NO(103) | 5) +#define MT8173_PIN_103_MSDC2_DAT3__FUNC_SPI_MI_1_ (MTK_PIN_NO(103) | 6) +#define MT8173_PIN_103_MSDC2_DAT3__FUNC_DBG_MON_B_3_ (MTK_PIN_NO(103) | 7) + +#define MT8173_PIN_104_MSDC2_CLK__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define MT8173_PIN_104_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(104) | 1) +#define MT8173_PIN_104_MSDC2_CLK__FUNC_UTXD3 (MTK_PIN_NO(104) | 3) +#define MT8173_PIN_104_MSDC2_CLK__FUNC_SDA3 (MTK_PIN_NO(104) | 4) +#define MT8173_PIN_104_MSDC2_CLK__FUNC_PWM2 (MTK_PIN_NO(104) | 5) +#define MT8173_PIN_104_MSDC2_CLK__FUNC_SPI_MO_1_ (MTK_PIN_NO(104) | 6) +#define MT8173_PIN_104_MSDC2_CLK__FUNC_DBG_MON_B_4_ (MTK_PIN_NO(104) | 7) + +#define MT8173_PIN_105_MSDC2_CMD__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define MT8173_PIN_105_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(105) | 1) +#define MT8173_PIN_105_MSDC2_CMD__FUNC_URXD3 (MTK_PIN_NO(105) | 3) +#define MT8173_PIN_105_MSDC2_CMD__FUNC_SCL3 (MTK_PIN_NO(105) | 4) +#define MT8173_PIN_105_MSDC2_CMD__FUNC_PWM3 (MTK_PIN_NO(105) | 5) +#define MT8173_PIN_105_MSDC2_CMD__FUNC_SPI_CS_1_ (MTK_PIN_NO(105) | 6) +#define MT8173_PIN_105_MSDC2_CMD__FUNC_DBG_MON_B_5_ (MTK_PIN_NO(105) | 7) + +#define MT8173_PIN_106_SDA3__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define MT8173_PIN_106_SDA3__FUNC_SDA3 (MTK_PIN_NO(106) | 1) + +#define MT8173_PIN_107_SCL3__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define MT8173_PIN_107_SCL3__FUNC_SCL3 (MTK_PIN_NO(107) | 1) + +#define MT8173_PIN_108_JTMS__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define MT8173_PIN_108_JTMS__FUNC_JTMS (MTK_PIN_NO(108) | 1) +#define MT8173_PIN_108_JTMS__FUNC_MFG_JTAG_TMS (MTK_PIN_NO(108) | 2) +#define MT8173_PIN_108_JTMS__FUNC_AP_MD32_JTAG_TMS (MTK_PIN_NO(108) | 5) +#define MT8173_PIN_108_JTMS__FUNC_DFD_TMS (MTK_PIN_NO(108) | 6) + +#define MT8173_PIN_109_JTCK__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define MT8173_PIN_109_JTCK__FUNC_JTCK (MTK_PIN_NO(109) | 1) +#define MT8173_PIN_109_JTCK__FUNC_MFG_JTAG_TCK (MTK_PIN_NO(109) | 2) +#define MT8173_PIN_109_JTCK__FUNC_AP_MD32_JTAG_TCK (MTK_PIN_NO(109) | 5) +#define MT8173_PIN_109_JTCK__FUNC_DFD_TCK (MTK_PIN_NO(109) | 6) + +#define MT8173_PIN_110_JTDI__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define MT8173_PIN_110_JTDI__FUNC_JTDI (MTK_PIN_NO(110) | 1) +#define MT8173_PIN_110_JTDI__FUNC_MFG_JTAG_TDI (MTK_PIN_NO(110) | 2) +#define MT8173_PIN_110_JTDI__FUNC_AP_MD32_JTAG_TDI (MTK_PIN_NO(110) | 5) +#define MT8173_PIN_110_JTDI__FUNC_DFD_TDI (MTK_PIN_NO(110) | 6) + +#define MT8173_PIN_111_JTDO__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define MT8173_PIN_111_JTDO__FUNC_JTDO (MTK_PIN_NO(111) | 1) +#define MT8173_PIN_111_JTDO__FUNC_MFG_JTAG_TDO (MTK_PIN_NO(111) | 2) +#define MT8173_PIN_111_JTDO__FUNC_AP_MD32_JTAG_TDO (MTK_PIN_NO(111) | 5) +#define MT8173_PIN_111_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(111) | 6) + +#define MT8173_PIN_112_JTRST_B__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define MT8173_PIN_112_JTRST_B__FUNC_JTRST_B (MTK_PIN_NO(112) | 1) +#define MT8173_PIN_112_JTRST_B__FUNC_MFG_JTAG_TRSTN (MTK_PIN_NO(112) | 2) +#define MT8173_PIN_112_JTRST_B__FUNC_AP_MD32_JTAG_TRST (MTK_PIN_NO(112) | 5) +#define MT8173_PIN_112_JTRST_B__FUNC_DFD_NTRST (MTK_PIN_NO(112) | 6) + +#define MT8173_PIN_113_URXD0__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define MT8173_PIN_113_URXD0__FUNC_URXD0 (MTK_PIN_NO(113) | 1) +#define MT8173_PIN_113_URXD0__FUNC_UTXD0 (MTK_PIN_NO(113) | 2) +#define MT8173_PIN_113_URXD0__FUNC_I2S2_WS (MTK_PIN_NO(113) | 6) +#define MT8173_PIN_113_URXD0__FUNC_DBG_MON_A_0_ (MTK_PIN_NO(113) | 7) + +#define MT8173_PIN_114_UTXD0__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define MT8173_PIN_114_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(114) | 1) +#define MT8173_PIN_114_UTXD0__FUNC_URXD0 (MTK_PIN_NO(114) | 2) +#define MT8173_PIN_114_UTXD0__FUNC_I2S2_BCK (MTK_PIN_NO(114) | 6) +#define MT8173_PIN_114_UTXD0__FUNC_DBG_MON_A_1_ (MTK_PIN_NO(114) | 7) + +#define MT8173_PIN_115_URTS0__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define MT8173_PIN_115_URTS0__FUNC_URTS0 (MTK_PIN_NO(115) | 1) +#define MT8173_PIN_115_URTS0__FUNC_UCTS0 (MTK_PIN_NO(115) | 2) +#define MT8173_PIN_115_URTS0__FUNC_I2S2_MCK (MTK_PIN_NO(115) | 6) +#define MT8173_PIN_115_URTS0__FUNC_DBG_MON_A_2_ (MTK_PIN_NO(115) | 7) + +#define MT8173_PIN_116_UCTS0__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define MT8173_PIN_116_UCTS0__FUNC_UCTS0 (MTK_PIN_NO(116) | 1) +#define MT8173_PIN_116_UCTS0__FUNC_URTS0 (MTK_PIN_NO(116) | 2) +#define MT8173_PIN_116_UCTS0__FUNC_I2S2_DI_1 (MTK_PIN_NO(116) | 6) +#define MT8173_PIN_116_UCTS0__FUNC_DBG_MON_A_3_ (MTK_PIN_NO(116) | 7) + +#define MT8173_PIN_117_URXD3__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define MT8173_PIN_117_URXD3__FUNC_URXD3 (MTK_PIN_NO(117) | 1) +#define MT8173_PIN_117_URXD3__FUNC_UTXD3 (MTK_PIN_NO(117) | 2) +#define MT8173_PIN_117_URXD3__FUNC_DBG_MON_A_9_ (MTK_PIN_NO(117) | 7) + +#define MT8173_PIN_118_UTXD3__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define MT8173_PIN_118_UTXD3__FUNC_UTXD3 (MTK_PIN_NO(118) | 1) +#define MT8173_PIN_118_UTXD3__FUNC_URXD3 (MTK_PIN_NO(118) | 2) +#define MT8173_PIN_118_UTXD3__FUNC_DBG_MON_A_10_ (MTK_PIN_NO(118) | 7) + +#define MT8173_PIN_119_KPROW0__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define MT8173_PIN_119_KPROW0__FUNC_KROW0 (MTK_PIN_NO(119) | 1) +#define MT8173_PIN_119_KPROW0__FUNC_DBG_MON_A_11_ (MTK_PIN_NO(119) | 7) + +#define MT8173_PIN_120_KPROW1__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define MT8173_PIN_120_KPROW1__FUNC_KROW1 (MTK_PIN_NO(120) | 1) +#define MT8173_PIN_120_KPROW1__FUNC_PWM6 (MTK_PIN_NO(120) | 3) +#define MT8173_PIN_120_KPROW1__FUNC_DBG_MON_A_12_ (MTK_PIN_NO(120) | 7) + +#define MT8173_PIN_121_KPROW2__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define MT8173_PIN_121_KPROW2__FUNC_KROW2 (MTK_PIN_NO(121) | 1) +#define MT8173_PIN_121_KPROW2__FUNC_IRDA_PDN (MTK_PIN_NO(121) | 2) +#define MT8173_PIN_121_KPROW2__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(121) | 3) +#define MT8173_PIN_121_KPROW2__FUNC_PWM4 (MTK_PIN_NO(121) | 4) +#define MT8173_PIN_121_KPROW2__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(121) | 5) +#define MT8173_PIN_121_KPROW2__FUNC_DBG_MON_A_13_ (MTK_PIN_NO(121) | 7) + +#define MT8173_PIN_122_KPCOL0__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define MT8173_PIN_122_KPCOL0__FUNC_KCOL0 (MTK_PIN_NO(122) | 1) +#define MT8173_PIN_122_KPCOL0__FUNC_DBG_MON_A_14_ (MTK_PIN_NO(122) | 7) + +#define MT8173_PIN_123_KPCOL1__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define MT8173_PIN_123_KPCOL1__FUNC_KCOL1 (MTK_PIN_NO(123) | 1) +#define MT8173_PIN_123_KPCOL1__FUNC_IRDA_RXD (MTK_PIN_NO(123) | 2) +#define MT8173_PIN_123_KPCOL1__FUNC_PWM5 (MTK_PIN_NO(123) | 3) +#define MT8173_PIN_123_KPCOL1__FUNC_DBG_MON_A_15_ (MTK_PIN_NO(123) | 7) + +#define MT8173_PIN_124_KPCOL2__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define MT8173_PIN_124_KPCOL2__FUNC_KCOL2 (MTK_PIN_NO(124) | 1) +#define MT8173_PIN_124_KPCOL2__FUNC_IRDA_TXD (MTK_PIN_NO(124) | 2) +#define MT8173_PIN_124_KPCOL2__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(124) | 3) +#define MT8173_PIN_124_KPCOL2__FUNC_PWM3 (MTK_PIN_NO(124) | 4) +#define MT8173_PIN_124_KPCOL2__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(124) | 5) +#define MT8173_PIN_124_KPCOL2__FUNC_DBG_MON_A_16_ (MTK_PIN_NO(124) | 7) + +#define MT8173_PIN_125_SDA1__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +#define MT8173_PIN_125_SDA1__FUNC_SDA1 (MTK_PIN_NO(125) | 1) + +#define MT8173_PIN_126_SCL1__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define MT8173_PIN_126_SCL1__FUNC_SCL1 (MTK_PIN_NO(126) | 1) + +#define MT8173_PIN_127_LCM_RST__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +#define MT8173_PIN_127_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(127) | 1) + +#define MT8173_PIN_128_I2S0_LRCK__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +#define MT8173_PIN_128_I2S0_LRCK__FUNC_I2S0_WS (MTK_PIN_NO(128) | 1) +#define MT8173_PIN_128_I2S0_LRCK__FUNC_I2S1_WS (MTK_PIN_NO(128) | 2) +#define MT8173_PIN_128_I2S0_LRCK__FUNC_I2S2_WS (MTK_PIN_NO(128) | 3) +#define MT8173_PIN_128_I2S0_LRCK__FUNC_SPI_CK_2_ (MTK_PIN_NO(128) | 5) +#define MT8173_PIN_128_I2S0_LRCK__FUNC_DBG_MON_A_4_ (MTK_PIN_NO(128) | 7) + +#define MT8173_PIN_129_I2S0_BCK__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +#define MT8173_PIN_129_I2S0_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(129) | 1) +#define MT8173_PIN_129_I2S0_BCK__FUNC_I2S1_BCK (MTK_PIN_NO(129) | 2) +#define MT8173_PIN_129_I2S0_BCK__FUNC_I2S2_BCK (MTK_PIN_NO(129) | 3) +#define MT8173_PIN_129_I2S0_BCK__FUNC_SPI_MI_2_ (MTK_PIN_NO(129) | 5) +#define MT8173_PIN_129_I2S0_BCK__FUNC_DBG_MON_A_5_ (MTK_PIN_NO(129) | 7) + +#define MT8173_PIN_130_I2S0_MCK__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +#define MT8173_PIN_130_I2S0_MCK__FUNC_I2S0_MCK (MTK_PIN_NO(130) | 1) +#define MT8173_PIN_130_I2S0_MCK__FUNC_I2S1_MCK (MTK_PIN_NO(130) | 2) +#define MT8173_PIN_130_I2S0_MCK__FUNC_I2S2_MCK (MTK_PIN_NO(130) | 3) +#define MT8173_PIN_130_I2S0_MCK__FUNC_SPI_MO_2_ (MTK_PIN_NO(130) | 5) +#define MT8173_PIN_130_I2S0_MCK__FUNC_DBG_MON_A_6_ (MTK_PIN_NO(130) | 7) + +#define MT8173_PIN_131_I2S0_DATA0__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +#define MT8173_PIN_131_I2S0_DATA0__FUNC_I2S0_DO (MTK_PIN_NO(131) | 1) +#define MT8173_PIN_131_I2S0_DATA0__FUNC_I2S1_DO_1 (MTK_PIN_NO(131) | 2) +#define MT8173_PIN_131_I2S0_DATA0__FUNC_I2S2_DI_1 (MTK_PIN_NO(131) | 3) +#define MT8173_PIN_131_I2S0_DATA0__FUNC_SPI_CS_2_ (MTK_PIN_NO(131) | 5) +#define MT8173_PIN_131_I2S0_DATA0__FUNC_DBG_MON_A_7_ (MTK_PIN_NO(131) | 7) + +#define MT8173_PIN_132_I2S0_DATA1__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +#define MT8173_PIN_132_I2S0_DATA1__FUNC_I2S0_DI (MTK_PIN_NO(132) | 1) +#define MT8173_PIN_132_I2S0_DATA1__FUNC_I2S1_DO_2 (MTK_PIN_NO(132) | 2) +#define MT8173_PIN_132_I2S0_DATA1__FUNC_I2S2_DI_2 (MTK_PIN_NO(132) | 3) +#define MT8173_PIN_132_I2S0_DATA1__FUNC_DBG_MON_A_8_ (MTK_PIN_NO(132) | 7) + +#define MT8173_PIN_133_SDA4__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +#define MT8173_PIN_133_SDA4__FUNC_SDA4 (MTK_PIN_NO(133) | 1) + +#define MT8173_PIN_134_SCL4__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +#define MT8173_PIN_134_SCL4__FUNC_SCL4 (MTK_PIN_NO(134) | 1) + +#endif /* __DTS_MT8173_PINFUNC_H */ diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi new file mode 100644 index 000000000..7640b5158 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -0,0 +1,1524 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Eddie Huang <eddie.huang@mediatek.com> + */ + +#include <dt-bindings/clock/mt8173-clk.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/memory/mt8173-larb-port.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/power/mt8173-power.h> +#include <dt-bindings/reset/mt8173-resets.h> +#include <dt-bindings/gce/mt8173-gce.h> +#include <dt-bindings/thermal/thermal.h> +#include "mt8173-pinfunc.h" + +/ { + compatible = "mediatek,mt8173"; + interrupt-parent = <&sysirq>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ovl0 = &ovl0; + ovl1 = &ovl1; + rdma0 = &rdma0; + rdma1 = &rdma1; + rdma2 = &rdma2; + wdma0 = &wdma0; + wdma1 = &wdma1; + color0 = &color0; + color1 = &color1; + split0 = &split0; + split1 = &split1; + dpi0 = &dpi0; + dsi0 = &dsi0; + dsi1 = &dsi1; + mdp-rdma0 = &mdp_rdma0; + mdp-rdma1 = &mdp_rdma1; + mdp-rsz0 = &mdp_rsz0; + mdp-rsz1 = &mdp_rsz1; + mdp-rsz2 = &mdp_rsz2; + mdp-wdma0 = &mdp_wdma0; + mdp-wrot0 = &mdp_wrot0; + mdp-wrot1 = &mdp_wrot1; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + opp-507000000 { + opp-hz = /bits/ 64 <507000000>; + opp-microvolt = <859000>; + }; + opp-702000000 { + opp-hz = /bits/ 64 <702000000>; + opp-microvolt = <908000>; + }; + opp-1001000000 { + opp-hz = /bits/ 64 <1001000000>; + opp-microvolt = <983000>; + }; + opp-1105000000 { + opp-hz = /bits/ 64 <1105000000>; + opp-microvolt = <1009000>; + }; + opp-1209000000 { + opp-hz = /bits/ 64 <1209000000>; + opp-microvolt = <1034000>; + }; + opp-1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <1057000>; + }; + opp-1508000000 { + opp-hz = /bits/ 64 <1508000000>; + opp-microvolt = <1109000>; + }; + opp-1703000000 { + opp-hz = /bits/ 64 <1703000000>; + opp-microvolt = <1125000>; + }; + }; + + cluster1_opp: opp-table-1 { + compatible = "operating-points-v2"; + opp-shared; + opp-507000000 { + opp-hz = /bits/ 64 <507000000>; + opp-microvolt = <828000>; + }; + opp-702000000 { + opp-hz = /bits/ 64 <702000000>; + opp-microvolt = <867000>; + }; + opp-1001000000 { + opp-hz = /bits/ 64 <1001000000>; + opp-microvolt = <927000>; + }; + opp-1209000000 { + opp-hz = /bits/ 64 <1209000000>; + opp-microvolt = <968000>; + }; + opp-1404000000 { + opp-hz = /bits/ 64 <1404000000>; + opp-microvolt = <1007000>; + }; + opp-1612000000 { + opp-hz = /bits/ 64 <1612000000>; + opp-microvolt = <1049000>; + }; + opp-1807000000 { + opp-hz = /bits/ 64 <1807000000>; + opp-microvolt = <1089000>; + }; + opp-2106000000 { + opp-hz = /bits/ 64 <2106000000>; + opp-microvolt = <1125000>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu2>; + }; + core1 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x000>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + #cooling-cells = <2>; + dynamic-power-coefficient = <263>; + clocks = <&infracfg CLK_INFRA_CA53SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + capacity-dmips-mhz = <740>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x001>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + #cooling-cells = <2>; + dynamic-power-coefficient = <263>; + clocks = <&infracfg CLK_INFRA_CA53SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + capacity-dmips-mhz = <740>; + }; + + cpu2: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + #cooling-cells = <2>; + dynamic-power-coefficient = <530>; + clocks = <&infracfg CLK_INFRA_CA72SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <1024>; + }; + + cpu3: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x101>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + #cooling-cells = <2>; + dynamic-power-coefficient = <530>; + clocks = <&infracfg CLK_INFRA_CA72SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <1024>; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + entry-latency-us = <639>; + exit-latency-us = <680>; + min-residency-us = <1088>; + arm,psci-suspend-param = <0x0010000>; + }; + }; + }; + + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + pmu_a72 { + compatible = "arm,cortex-a72-pmu"; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>; + interrupt-affinity = <&cpu2>, <&cpu3>; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; + method = "smc"; + cpu_suspend = <0x84000001>; + cpu_off = <0x84000002>; + cpu_on = <0x84000003>; + }; + + clk26m: oscillator0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + clk32k: oscillator1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + clock-output-names = "clk32k"; + }; + + cpum_ck: oscillator2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "cpum_ck"; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + + thermal-sensors = <&thermal>; + sustainable-power = <1500>; /* milliwatts */ + + trips { + threshold: trip-point0 { + temperature = <68000>; + hysteresis = <2000>; + type = "passive"; + }; + + target: trip-point1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit: cpu_crit0 { + temperature = <115000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + contribution = <3072>; + }; + map1 { + trip = <&target>; + cooling-device = <&cpu2 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + }; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + vpu_dma_reserved: vpu_dma_mem_region@b7000000 { + compatible = "shared-dma-pool"; + reg = <0 0xb7000000 0 0x500000>; + alignment = <0x1000>; + no-map; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + arm,no-tick-in-suspend; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + topckgen: clock-controller@10000000 { + compatible = "mediatek,mt8173-topckgen"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: power-controller@10001000 { + compatible = "mediatek,mt8173-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pericfg: power-controller@10003000 { + compatible = "mediatek,mt8173-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + syscfg_pctl_a: syscfg_pctl_a@10005000 { + compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; + reg = <0 0x10005000 0 0x1000>; + }; + + pio: pinctrl@1000b000 { + compatible = "mediatek,mt8173-pinctrl"; + reg = <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl_a>; + pins-are-numbered; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + + hdmi_pin: xxx { + + /*hdmi htplg pin*/ + pins1 { + pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>; + input-enable; + bias-pull-down; + }; + }; + + i2c0_pins_a: i2c0 { + pins1 { + pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, + <MT8173_PIN_46_SCL0__FUNC_SCL0>; + bias-disable; + }; + }; + + i2c1_pins_a: i2c1 { + pins1 { + pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, + <MT8173_PIN_126_SCL1__FUNC_SCL1>; + bias-disable; + }; + }; + + i2c2_pins_a: i2c2 { + pins1 { + pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, + <MT8173_PIN_44_SCL2__FUNC_SCL2>; + bias-disable; + }; + }; + + i2c3_pins_a: i2c3 { + pins1 { + pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, + <MT8173_PIN_107_SCL3__FUNC_SCL3>; + bias-disable; + }; + }; + + i2c4_pins_a: i2c4 { + pins1 { + pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, + <MT8173_PIN_134_SCL4__FUNC_SCL4>; + bias-disable; + }; + }; + + i2c6_pins_a: i2c6 { + pins1 { + pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, + <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; + bias-disable; + }; + }; + }; + + scpsys: syscon@10006000 { + compatible = "mediatek,mt8173-scpsys", "syscon", "simple-mfd"; + reg = <0 0x10006000 0 0x1000>; + + /* System Power Manager */ + spm: power-controller { + compatible = "mediatek,mt8173-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* power domains of the SoC */ + power-domain@MT8173_POWER_DOMAIN_VDEC { + reg = <MT8173_POWER_DOMAIN_VDEC>; + clocks = <&topckgen CLK_TOP_MM_SEL>; + clock-names = "mm"; + #power-domain-cells = <0>; + }; + power-domain@MT8173_POWER_DOMAIN_VENC { + reg = <MT8173_POWER_DOMAIN_VENC>; + clocks = <&topckgen CLK_TOP_MM_SEL>, + <&topckgen CLK_TOP_VENC_SEL>; + clock-names = "mm", "venc"; + #power-domain-cells = <0>; + }; + power-domain@MT8173_POWER_DOMAIN_ISP { + reg = <MT8173_POWER_DOMAIN_ISP>; + clocks = <&topckgen CLK_TOP_MM_SEL>; + clock-names = "mm"; + #power-domain-cells = <0>; + }; + power-domain@MT8173_POWER_DOMAIN_MM { + reg = <MT8173_POWER_DOMAIN_MM>; + clocks = <&topckgen CLK_TOP_MM_SEL>; + clock-names = "mm"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + power-domain@MT8173_POWER_DOMAIN_VENC_LT { + reg = <MT8173_POWER_DOMAIN_VENC_LT>; + clocks = <&topckgen CLK_TOP_MM_SEL>, + <&topckgen CLK_TOP_VENC_LT_SEL>; + clock-names = "mm", "venclt"; + #power-domain-cells = <0>; + }; + power-domain@MT8173_POWER_DOMAIN_AUDIO { + reg = <MT8173_POWER_DOMAIN_AUDIO>; + #power-domain-cells = <0>; + }; + power-domain@MT8173_POWER_DOMAIN_USB { + reg = <MT8173_POWER_DOMAIN_USB>; + #power-domain-cells = <0>; + }; + mfg_async: power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC { + reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>; + clocks = <&clk26m>; + clock-names = "mfg"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8173_POWER_DOMAIN_MFG_2D { + reg = <MT8173_POWER_DOMAIN_MFG_2D>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8173_POWER_DOMAIN_MFG { + reg = <MT8173_POWER_DOMAIN_MFG>; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + }; + }; + }; + }; + + watchdog: watchdog@10007000 { + compatible = "mediatek,mt8173-wdt", + "mediatek,mt6589-wdt"; + reg = <0 0x10007000 0 0x100>; + }; + + timer: timer@10008000 { + compatible = "mediatek,mt8173-timer", + "mediatek,mt6577-timer"; + reg = <0 0x10008000 0 0x1000>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_CLK_13M>, + <&topckgen CLK_TOP_RTC_SEL>; + }; + + pwrap: pwrap@1000d000 { + compatible = "mediatek,mt8173-pwrap"; + reg = <0 0x1000d000 0 0x1000>; + reg-names = "pwrap"; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; + reset-names = "pwrap"; + clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; + clock-names = "spi", "wrap"; + }; + + cec: cec@10013000 { + compatible = "mediatek,mt8173-cec"; + reg = <0 0x10013000 0 0xbc>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_CEC>; + status = "disabled"; + }; + + vpu: vpu@10020000 { + compatible = "mediatek,mt8173-vpu"; + reg = <0 0x10020000 0 0x30000>, + <0 0x10050000 0 0x100>; + reg-names = "tcm", "cfg_reg"; + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&topckgen CLK_TOP_SCP_SEL>; + clock-names = "main"; + memory-region = <&vpu_dma_reserved>; + }; + + sysirq: intpol-controller@10200620 { + compatible = "mediatek,mt8173-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10200620 0 0x20>; + }; + + iommu: iommu@10205000 { + compatible = "mediatek,mt8173-m4u"; + reg = <0 0x10205000 0 0x1000>; + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_M4U>; + clock-names = "bclk"; + mediatek,infracfg = <&infracfg>; + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, + <&larb3>, <&larb4>, <&larb5>; + #iommu-cells = <1>; + }; + + efuse: efuse@10206000 { + compatible = "mediatek,mt8173-efuse"; + reg = <0 0x10206000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + thermal_calibration: calib@528 { + reg = <0x528 0xc>; + }; + }; + + apmixedsys: clock-controller@10209000 { + compatible = "mediatek,mt8173-apmixedsys"; + reg = <0 0x10209000 0 0x1000>; + #clock-cells = <1>; + }; + + hdmi_phy: hdmi-phy@10209100 { + compatible = "mediatek,mt8173-hdmi-phy"; + reg = <0 0x10209100 0 0x24>; + clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; + clock-names = "pll_ref"; + clock-output-names = "hdmitx_dig_cts"; + mediatek,ibias = <0xa>; + mediatek,ibias_up = <0x1c>; + #clock-cells = <0>; + #phy-cells = <0>; + status = "disabled"; + }; + + gce: mailbox@10212000 { + compatible = "mediatek,mt8173-gce"; + reg = <0 0x10212000 0 0x1000>; + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_GCE>; + clock-names = "gce"; + #mbox-cells = <2>; + }; + + mipi_tx0: dsi-phy@10215000 { + compatible = "mediatek,mt8173-mipi-tx"; + reg = <0 0x10215000 0 0x1000>; + clocks = <&clk26m>; + clock-output-names = "mipi_tx0_pll"; + #clock-cells = <0>; + #phy-cells = <0>; + status = "disabled"; + }; + + mipi_tx1: dsi-phy@10216000 { + compatible = "mediatek,mt8173-mipi-tx"; + reg = <0 0x10216000 0 0x1000>; + clocks = <&clk26m>; + clock-output-names = "mipi_tx1_pll"; + #clock-cells = <0>; + #phy-cells = <0>; + status = "disabled"; + }; + + gic: interrupt-controller@10221000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x10221000 0 0x1000>, + <0 0x10222000 0 0x2000>, + <0 0x10224000 0 0x2000>, + <0 0x10226000 0 0x2000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + auxadc: auxadc@11001000 { + compatible = "mediatek,mt8173-auxadc"; + reg = <0 0x11001000 0 0x1000>; + clocks = <&pericfg CLK_PERI_AUXADC>; + clock-names = "main"; + #io-channel-cells = <1>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt8173-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt8173-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt8173-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x400>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart3: serial@11005000 { + compatible = "mediatek,mt8173-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11005000 0 0x400>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + i2c0: i2c@11007000 { + compatible = "mediatek,mt8173-i2c"; + reg = <0 0x11007000 0 0x70>, + <0 0x11000100 0 0x80>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C0>, + <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", "dma"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@11008000 { + compatible = "mediatek,mt8173-i2c"; + reg = <0 0x11008000 0 0x70>, + <0 0x11000180 0 0x80>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C1>, + <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", "dma"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11009000 { + compatible = "mediatek,mt8173-i2c"; + reg = <0 0x11009000 0 0x70>, + <0 0x11000200 0 0x80>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C2>, + <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", "dma"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi: spi@1100a000 { + compatible = "mediatek,mt8173-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100a000 0 0x1000>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&pericfg CLK_PERI_SPI0>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + thermal: thermal@1100b000 { + #thermal-sensor-cells = <0>; + compatible = "mediatek,mt8173-thermal"; + reg = <0 0x1100b000 0 0x1000>; + interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; + clock-names = "therm", "auxadc"; + resets = <&pericfg MT8173_PERI_THERM_SW_RST>; + mediatek,auxadc = <&auxadc>; + mediatek,apmixedsys = <&apmixedsys>; + nvmem-cells = <&thermal_calibration>; + nvmem-cell-names = "calibration-data"; + }; + + nor_flash: spi@1100d000 { + compatible = "mediatek,mt8173-nor"; + reg = <0 0x1100d000 0 0xe0>; + assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>; + assigned-clock-parents = <&clk26m>; + clocks = <&pericfg CLK_PERI_SPI>, + <&topckgen CLK_TOP_SPINFI_IFR_SEL>, + <&pericfg CLK_PERI_NFI>; + clock-names = "spi", "sf", "axi"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@11010000 { + compatible = "mediatek,mt8173-i2c"; + reg = <0 0x11010000 0 0x70>, + <0 0x11000280 0 0x80>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C3>, + <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", "dma"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins_a>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@11011000 { + compatible = "mediatek,mt8173-i2c"; + reg = <0 0x11011000 0 0x70>, + <0 0x11000300 0 0x80>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C4>, + <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", "dma"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_a>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hdmiddc0: i2c@11012000 { + compatible = "mediatek,mt8173-hdmi-ddc"; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; + reg = <0 0x11012000 0 0x1C>; + clocks = <&pericfg CLK_PERI_I2C5>; + clock-names = "ddc-i2c"; + }; + + i2c6: i2c@11013000 { + compatible = "mediatek,mt8173-i2c"; + reg = <0 0x11013000 0 0x70>, + <0 0x11000080 0 0x80>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C6>, + <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", "dma"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pins_a>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + afe: audio-controller@11220000 { + compatible = "mediatek,mt8173-afe-pcm"; + reg = <0 0x11220000 0 0x1000>; + interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; + power-domains = <&spm MT8173_POWER_DOMAIN_AUDIO>; + clocks = <&infracfg CLK_INFRA_AUDIO>, + <&topckgen CLK_TOP_AUDIO_SEL>, + <&topckgen CLK_TOP_AUD_INTBUS_SEL>, + <&topckgen CLK_TOP_APLL1_DIV0>, + <&topckgen CLK_TOP_APLL2_DIV0>, + <&topckgen CLK_TOP_I2S0_M_SEL>, + <&topckgen CLK_TOP_I2S1_M_SEL>, + <&topckgen CLK_TOP_I2S2_M_SEL>, + <&topckgen CLK_TOP_I2S3_M_SEL>, + <&topckgen CLK_TOP_I2S3_B_SEL>; + clock-names = "infra_sys_audio_clk", + "top_pdn_audio", + "top_pdn_aud_intbus", + "bck0", + "bck1", + "i2s0_m", + "i2s1_m", + "i2s2_m", + "i2s3_m", + "i2s3_b"; + assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, + <&topckgen CLK_TOP_AUD_2_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, + <&topckgen CLK_TOP_APLL2>; + }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt8173-mmc"; + reg = <0 0x11230000 0 0x1000>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_MSDC30_0>, + <&topckgen CLK_TOP_MSDC50_0_H_SEL>; + clock-names = "source", "hclk"; + status = "disabled"; + }; + + mmc1: mmc@11240000 { + compatible = "mediatek,mt8173-mmc"; + reg = <0 0x11240000 0 0x1000>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_MSDC30_1>, + <&topckgen CLK_TOP_AXI_SEL>; + clock-names = "source", "hclk"; + status = "disabled"; + }; + + mmc2: mmc@11250000 { + compatible = "mediatek,mt8173-mmc"; + reg = <0 0x11250000 0 0x1000>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_MSDC30_2>, + <&topckgen CLK_TOP_AXI_SEL>; + clock-names = "source", "hclk"; + status = "disabled"; + }; + + mmc3: mmc@11260000 { + compatible = "mediatek,mt8173-mmc"; + reg = <0 0x11260000 0 0x1000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_MSDC30_3>, + <&topckgen CLK_TOP_MSDC50_2_H_SEL>; + clock-names = "source", "hclk"; + status = "disabled"; + }; + + ssusb: usb@11271000 { + compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3"; + reg = <0 0x11271000 0 0x3000>, + <0 0x11280700 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>, + <&u2port1 PHY_TYPE_USB2>; + power-domains = <&spm MT8173_POWER_DOMAIN_USB>; + clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; + clock-names = "sys_ck", "ref_ck"; + mediatek,syscon-wakeup = <&pericfg 0x400 1>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb_host: usb@11270000 { + compatible = "mediatek,mt8173-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11270000 0 0x1000>; + reg-names = "mac"; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8173_POWER_DOMAIN_USB>; + clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; + clock-names = "sys_ck", "ref_ck"; + status = "disabled"; + }; + }; + + u3phy: t-phy@11290000 { + compatible = "mediatek,mt8173-u3phy"; + reg = <0 0x11290000 0 0x800>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "okay"; + + u2port0: usb-phy@11290800 { + reg = <0 0x11290800 0 0x100>; + clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u3port0: usb-phy@11290900 { + reg = <0 0x11290900 0 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u2port1: usb-phy@11291000 { + reg = <0 0x11291000 0 0x100>; + clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + + mmsys: syscon@14000000 { + compatible = "mediatek,mt8173-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; + assigned-clock-rates = <400000000>; + #clock-cells = <1>; + #reset-cells = <1>; + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; + }; + + mdp_rdma0: rdma@14001000 { + compatible = "mediatek,mt8173-mdp-rdma", + "mediatek,mt8173-mdp"; + reg = <0 0x14001000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_RDMA0>, + <&mmsys CLK_MM_MUTEX_32K>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + iommus = <&iommu M4U_PORT_MDP_RDMA0>; + mediatek,vpu = <&vpu>; + }; + + mdp_rdma1: rdma@14002000 { + compatible = "mediatek,mt8173-mdp-rdma"; + reg = <0 0x14002000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_RDMA1>, + <&mmsys CLK_MM_MUTEX_32K>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + iommus = <&iommu M4U_PORT_MDP_RDMA1>; + }; + + mdp_rsz0: rsz@14003000 { + compatible = "mediatek,mt8173-mdp-rsz"; + reg = <0 0x14003000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_RSZ0>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + }; + + mdp_rsz1: rsz@14004000 { + compatible = "mediatek,mt8173-mdp-rsz"; + reg = <0 0x14004000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_RSZ1>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + }; + + mdp_rsz2: rsz@14005000 { + compatible = "mediatek,mt8173-mdp-rsz"; + reg = <0 0x14005000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_RSZ2>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + }; + + mdp_wdma0: wdma@14006000 { + compatible = "mediatek,mt8173-mdp-wdma"; + reg = <0 0x14006000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_WDMA>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + iommus = <&iommu M4U_PORT_MDP_WDMA>; + }; + + mdp_wrot0: wrot@14007000 { + compatible = "mediatek,mt8173-mdp-wrot"; + reg = <0 0x14007000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_WROT0>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + iommus = <&iommu M4U_PORT_MDP_WROT0>; + }; + + mdp_wrot1: wrot@14008000 { + compatible = "mediatek,mt8173-mdp-wrot"; + reg = <0 0x14008000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_WROT1>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + iommus = <&iommu M4U_PORT_MDP_WROT1>; + }; + + ovl0: ovl@1400c000 { + compatible = "mediatek,mt8173-disp-ovl"; + reg = <0 0x1400c000 0 0x1000>; + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_OVL0>; + iommus = <&iommu M4U_PORT_DISP_OVL0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; + }; + + ovl1: ovl@1400d000 { + compatible = "mediatek,mt8173-disp-ovl"; + reg = <0 0x1400d000 0 0x1000>; + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_OVL1>; + iommus = <&iommu M4U_PORT_DISP_OVL1>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; + }; + + rdma0: rdma@1400e000 { + compatible = "mediatek,mt8173-disp-rdma"; + reg = <0 0x1400e000 0 0x1000>; + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_RDMA0>; + iommus = <&iommu M4U_PORT_DISP_RDMA0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; + }; + + rdma1: rdma@1400f000 { + compatible = "mediatek,mt8173-disp-rdma"; + reg = <0 0x1400f000 0 0x1000>; + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_RDMA1>; + iommus = <&iommu M4U_PORT_DISP_RDMA1>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; + }; + + rdma2: rdma@14010000 { + compatible = "mediatek,mt8173-disp-rdma"; + reg = <0 0x14010000 0 0x1000>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_RDMA2>; + iommus = <&iommu M4U_PORT_DISP_RDMA2>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; + }; + + wdma0: wdma@14011000 { + compatible = "mediatek,mt8173-disp-wdma"; + reg = <0 0x14011000 0 0x1000>; + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_WDMA0>; + iommus = <&iommu M4U_PORT_DISP_WDMA0>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; + }; + + wdma1: wdma@14012000 { + compatible = "mediatek,mt8173-disp-wdma"; + reg = <0 0x14012000 0 0x1000>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_WDMA1>; + iommus = <&iommu M4U_PORT_DISP_WDMA1>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; + }; + + color0: color@14013000 { + compatible = "mediatek,mt8173-disp-color"; + reg = <0 0x14013000 0 0x1000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_COLOR0>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>; + }; + + color1: color@14014000 { + compatible = "mediatek,mt8173-disp-color"; + reg = <0 0x14014000 0 0x1000>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_COLOR1>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; + }; + + aal@14015000 { + compatible = "mediatek,mt8173-disp-aal"; + reg = <0 0x14015000 0 0x1000>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_AAL>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; + }; + + gamma@14016000 { + compatible = "mediatek,mt8173-disp-gamma"; + reg = <0 0x14016000 0 0x1000>; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_GAMMA>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; + }; + + merge@14017000 { + compatible = "mediatek,mt8173-disp-merge"; + reg = <0 0x14017000 0 0x1000>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_MERGE>; + }; + + split0: split@14018000 { + compatible = "mediatek,mt8173-disp-split"; + reg = <0 0x14018000 0 0x1000>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_SPLIT0>; + }; + + split1: split@14019000 { + compatible = "mediatek,mt8173-disp-split"; + reg = <0 0x14019000 0 0x1000>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_SPLIT1>; + }; + + ufoe@1401a000 { + compatible = "mediatek,mt8173-disp-ufoe"; + reg = <0 0x1401a000 0 0x1000>; + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_UFOE>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>; + }; + + dsi0: dsi@1401b000 { + compatible = "mediatek,mt8173-dsi"; + reg = <0 0x1401b000 0 0x1000>; + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DSI0_ENGINE>, + <&mmsys CLK_MM_DSI0_DIGITAL>, + <&mipi_tx0>; + clock-names = "engine", "digital", "hs"; + resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>; + phys = <&mipi_tx0>; + phy-names = "dphy"; + status = "disabled"; + }; + + dsi1: dsi@1401c000 { + compatible = "mediatek,mt8173-dsi"; + reg = <0 0x1401c000 0 0x1000>; + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DSI1_ENGINE>, + <&mmsys CLK_MM_DSI1_DIGITAL>, + <&mipi_tx1>; + clock-names = "engine", "digital", "hs"; + phys = <&mipi_tx1>; + phy-names = "dphy"; + status = "disabled"; + }; + + dpi0: dpi@1401d000 { + compatible = "mediatek,mt8173-dpi"; + reg = <0 0x1401d000 0 0x1000>; + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DPI_PIXEL>, + <&mmsys CLK_MM_DPI_ENGINE>, + <&apmixedsys CLK_APMIXED_TVDPLL>; + clock-names = "pixel", "engine", "pll"; + status = "disabled"; + + port { + dpi0_out: endpoint { + remote-endpoint = <&hdmi0_in>; + }; + }; + }; + + pwm0: pwm@1401e000 { + compatible = "mediatek,mt8173-disp-pwm", + "mediatek,mt6595-disp-pwm"; + reg = <0 0x1401e000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&mmsys CLK_MM_DISP_PWM026M>, + <&mmsys CLK_MM_DISP_PWM0MM>; + clock-names = "main", "mm"; + status = "disabled"; + }; + + pwm1: pwm@1401f000 { + compatible = "mediatek,mt8173-disp-pwm", + "mediatek,mt6595-disp-pwm"; + reg = <0 0x1401f000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&mmsys CLK_MM_DISP_PWM126M>, + <&mmsys CLK_MM_DISP_PWM1MM>; + clock-names = "main", "mm"; + status = "disabled"; + }; + + mutex: mutex@14020000 { + compatible = "mediatek,mt8173-disp-mutex"; + reg = <0 0x14020000 0 0x1000>; + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_MUTEX_32K>; + mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>, + <CMDQ_EVENT_MUTEX1_STREAM_EOF>; + }; + + larb0: larb@14021000 { + compatible = "mediatek,mt8173-smi-larb"; + reg = <0 0x14021000 0 0x1000>; + mediatek,smi = <&smi_common>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_SMI_LARB0>, + <&mmsys CLK_MM_SMI_LARB0>; + clock-names = "apb", "smi"; + }; + + smi_common: smi@14022000 { + compatible = "mediatek,mt8173-smi-common"; + reg = <0 0x14022000 0 0x1000>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_COMMON>; + clock-names = "apb", "smi"; + }; + + od@14023000 { + compatible = "mediatek,mt8173-disp-od"; + reg = <0 0x14023000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_OD>; + mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>; + }; + + hdmi0: hdmi@14025000 { + compatible = "mediatek,mt8173-hdmi"; + reg = <0 0x14025000 0 0x400>; + interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_HDMI_PIXEL>, + <&mmsys CLK_MM_HDMI_PLLCK>, + <&mmsys CLK_MM_HDMI_AUDIO>, + <&mmsys CLK_MM_HDMI_SPDIF>; + clock-names = "pixel", "pll", "bclk", "spdif"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pin>; + phys = <&hdmi_phy>; + phy-names = "hdmi"; + mediatek,syscon-hdmi = <&mmsys 0x900>; + assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>; + assigned-clock-parents = <&hdmi_phy>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; + }; + }; + + larb4: larb@14027000 { + compatible = "mediatek,mt8173-smi-larb"; + reg = <0 0x14027000 0 0x1000>; + mediatek,smi = <&smi_common>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_SMI_LARB4>, + <&mmsys CLK_MM_SMI_LARB4>; + clock-names = "apb", "smi"; + }; + + imgsys: clock-controller@15000000 { + compatible = "mediatek,mt8173-imgsys", "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb2: larb@15001000 { + compatible = "mediatek,mt8173-smi-larb"; + reg = <0 0x15001000 0 0x1000>; + mediatek,smi = <&smi_common>; + power-domains = <&spm MT8173_POWER_DOMAIN_ISP>; + clocks = <&imgsys CLK_IMG_LARB2_SMI>, + <&imgsys CLK_IMG_LARB2_SMI>; + clock-names = "apb", "smi"; + }; + + vdecsys: clock-controller@16000000 { + compatible = "mediatek,mt8173-vdecsys", "syscon"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + vcodec_dec: vcodec@16000000 { + compatible = "mediatek,mt8173-vcodec-dec"; + reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */ + <0 0x16020000 0 0x1000>, /* VDEC_MISC */ + <0 0x16021000 0 0x800>, /* VDEC_LD */ + <0 0x16021800 0 0x800>, /* VDEC_TOP */ + <0 0x16022000 0 0x1000>, /* VDEC_CM */ + <0 0x16023000 0 0x1000>, /* VDEC_AD */ + <0 0x16024000 0 0x1000>, /* VDEC_AV */ + <0 0x16025000 0 0x1000>, /* VDEC_PP */ + <0 0x16026800 0 0x800>, /* VDEC_HWD */ + <0 0x16027000 0 0x800>, /* VDEC_HWQ */ + <0 0x16027800 0 0x800>, /* VDEC_HWB */ + <0 0x16028400 0 0x400>; /* VDEC_HWG */ + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>; + iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, + <&iommu M4U_PORT_HW_VDEC_PP_EXT>, + <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, + <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, + <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, + <&iommu M4U_PORT_HW_VDEC_UFO_EXT>, + <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, + <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; + mediatek,vpu = <&vpu>; + power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>; + clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, + <&topckgen CLK_TOP_UNIVPLL_D2>, + <&topckgen CLK_TOP_CCI400_SEL>, + <&topckgen CLK_TOP_VDEC_SEL>, + <&topckgen CLK_TOP_VCODECPLL>, + <&apmixedsys CLK_APMIXED_VENCPLL>, + <&topckgen CLK_TOP_VENC_LT_SEL>, + <&topckgen CLK_TOP_VCODECPLL_370P5>; + clock-names = "vcodecpll", + "univpll_d2", + "clk_cci400_sel", + "vdec_sel", + "vdecpll", + "vencpll", + "venc_lt_sel", + "vdec_bus_clk_src"; + assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>, + <&topckgen CLK_TOP_CCI400_SEL>, + <&topckgen CLK_TOP_VDEC_SEL>, + <&apmixedsys CLK_APMIXED_VCODECPLL>, + <&apmixedsys CLK_APMIXED_VENCPLL>; + assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>, + <&topckgen CLK_TOP_UNIVPLL_D2>, + <&topckgen CLK_TOP_VCODECPLL>; + assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>; + }; + + larb1: larb@16010000 { + compatible = "mediatek,mt8173-smi-larb"; + reg = <0 0x16010000 0 0x1000>; + mediatek,smi = <&smi_common>; + power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>; + clocks = <&vdecsys CLK_VDEC_CKEN>, + <&vdecsys CLK_VDEC_LARB_CKEN>; + clock-names = "apb", "smi"; + }; + + vencsys: clock-controller@18000000 { + compatible = "mediatek,mt8173-vencsys", "syscon"; + reg = <0 0x18000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb3: larb@18001000 { + compatible = "mediatek,mt8173-smi-larb"; + reg = <0 0x18001000 0 0x1000>; + mediatek,smi = <&smi_common>; + power-domains = <&spm MT8173_POWER_DOMAIN_VENC>; + clocks = <&vencsys CLK_VENC_CKE1>, + <&vencsys CLK_VENC_CKE0>; + clock-names = "apb", "smi"; + }; + + vcodec_enc_avc: vcodec@18002000 { + compatible = "mediatek,mt8173-vcodec-enc"; + reg = <0 0x18002000 0 0x1000>; /* VENC_SYS */ + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; + iommus = <&iommu M4U_PORT_VENC_RCPU>, + <&iommu M4U_PORT_VENC_REC>, + <&iommu M4U_PORT_VENC_BSDMA>, + <&iommu M4U_PORT_VENC_SV_COMV>, + <&iommu M4U_PORT_VENC_RD_COMV>, + <&iommu M4U_PORT_VENC_CUR_LUMA>, + <&iommu M4U_PORT_VENC_CUR_CHROMA>, + <&iommu M4U_PORT_VENC_REF_LUMA>, + <&iommu M4U_PORT_VENC_REF_CHROMA>, + <&iommu M4U_PORT_VENC_NBM_RDMA>, + <&iommu M4U_PORT_VENC_NBM_WDMA>; + mediatek,vpu = <&vpu>; + clocks = <&topckgen CLK_TOP_VENC_SEL>; + clock-names = "venc_sel"; + assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>; + power-domains = <&spm MT8173_POWER_DOMAIN_VENC>; + }; + + jpegdec: jpegdec@18004000 { + compatible = "mediatek,mt8173-jpgdec"; + reg = <0 0x18004000 0 0x1000>; + interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW>; + clocks = <&vencsys CLK_VENC_CKE0>, + <&vencsys CLK_VENC_CKE3>; + clock-names = "jpgdec-smi", + "jpgdec"; + power-domains = <&spm MT8173_POWER_DOMAIN_VENC>; + iommus = <&iommu M4U_PORT_JPGDEC_WDMA>, + <&iommu M4U_PORT_JPGDEC_BSDMA>; + }; + + vencltsys: clock-controller@19000000 { + compatible = "mediatek,mt8173-vencltsys", "syscon"; + reg = <0 0x19000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb5: larb@19001000 { + compatible = "mediatek,mt8173-smi-larb"; + reg = <0 0x19001000 0 0x1000>; + mediatek,smi = <&smi_common>; + power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>; + clocks = <&vencltsys CLK_VENCLT_CKE1>, + <&vencltsys CLK_VENCLT_CKE0>; + clock-names = "apb", "smi"; + }; + + vcodec_enc_vp8: vcodec@19002000 { + compatible = "mediatek,mt8173-vcodec-enc-vp8"; + reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ + interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; + iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>, + <&iommu M4U_PORT_VENC_REC_FRM_SET2>, + <&iommu M4U_PORT_VENC_BSDMA_SET2>, + <&iommu M4U_PORT_VENC_SV_COMA_SET2>, + <&iommu M4U_PORT_VENC_RD_COMA_SET2>, + <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, + <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, + <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, + <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; + mediatek,vpu = <&vpu>; + clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; + clock-names = "venc_lt_sel"; + assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; + assigned-clock-parents = + <&topckgen CLK_TOP_VCODECPLL_370P5>; + power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts new file mode 100644 index 000000000..2ca0da51e --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts @@ -0,0 +1,459 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2018 MediaTek Inc. + * Author: Ben Ho <ben.ho@mediatek.com> + * Erin Lo <erin.lo@mediatek.com> + */ + +/dts-v1/; +#include "mt8183.dtsi" +#include "mt6358.dtsi" + +/ { + model = "MediaTek MT8183 evaluation board"; + compatible = "mediatek,mt8183-evb", "mediatek,mt8183"; + + aliases { + serial0 = &uart0; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + scp_mem_reserved: memory@50000000 { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x2900000>; + no-map; + }; + }; + + thermal-sensor { + compatible = "murata,ncp03wf104"; + pullup-uv = <1800000>; + pullup-ohm = <390000>; + pulldown-ohm = <0>; + io-channels = <&auxadc 0>; + }; +}; + +&auxadc { + status = "okay"; +}; + +&gpu { + mali-supply = <&mt6358_vgpu_reg>; + sram-supply = <&mt6358_vsram_gpu_reg>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins_0>; + status = "okay"; + clock-frequency = <100000>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins_1>; + status = "okay"; + clock-frequency = <100000>; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins_2>; + status = "okay"; + clock-frequency = <100000>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins_3>; + status = "okay"; + clock-frequency = <100000>; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins_4>; + status = "okay"; + clock-frequency = <1000000>; +}; + +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins_5>; + status = "okay"; + clock-frequency = <1000000>; +}; + +&mmc0 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cap-mmc-hw-reset; + no-sdio; + no-sd; + hs400-ds-delay = <0x12814>; + vmmc-supply = <&mt6358_vemc_reg>; + vqmmc-supply = <&mt6358_vio18_reg>; + assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>; + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>; + non-removable; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_uhs>; + bus-width = <4>; + max-frequency = <200000000>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + cap-sdio-irq; + no-mmc; + no-sd; + vmmc-supply = <&mt6358_vmch_reg>; + vqmmc-supply = <&mt6358_vmc_reg>; + keep-power-in-suspend; + wakeup-source; + non-removable; +}; + +&pio { + i2c_pins_0: i2c0 { + pins_i2c { + pinmux = <PINMUX_GPIO82__FUNC_SDA0>, + <PINMUX_GPIO83__FUNC_SCL0>; + mediatek,pull-up-adv = <3>; + mediatek,drive-strength-adv = <00>; + }; + }; + + i2c_pins_1: i2c1 { + pins_i2c { + pinmux = <PINMUX_GPIO81__FUNC_SDA1>, + <PINMUX_GPIO84__FUNC_SCL1>; + mediatek,pull-up-adv = <3>; + mediatek,drive-strength-adv = <00>; + }; + }; + + i2c_pins_2: i2c2 { + pins_i2c { + pinmux = <PINMUX_GPIO103__FUNC_SCL2>, + <PINMUX_GPIO104__FUNC_SDA2>; + mediatek,pull-up-adv = <3>; + mediatek,drive-strength-adv = <00>; + }; + }; + + i2c_pins_3: i2c3 { + pins_i2c { + pinmux = <PINMUX_GPIO50__FUNC_SCL3>, + <PINMUX_GPIO51__FUNC_SDA3>; + mediatek,pull-up-adv = <3>; + mediatek,drive-strength-adv = <00>; + }; + }; + + i2c_pins_4: i2c4 { + pins_i2c { + pinmux = <PINMUX_GPIO105__FUNC_SCL4>, + <PINMUX_GPIO106__FUNC_SDA4>; + mediatek,pull-up-adv = <3>; + mediatek,drive-strength-adv = <00>; + }; + }; + + i2c_pins_5: i2c5 { + pins_i2c { + pinmux = <PINMUX_GPIO48__FUNC_SCL5>, + <PINMUX_GPIO49__FUNC_SDA5>; + mediatek,pull-up-adv = <3>; + mediatek,drive-strength-adv = <00>; + }; + }; + + spi_pins_0: spi0 { + pins_spi { + pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>, + <PINMUX_GPIO86__FUNC_SPI0_CSB>, + <PINMUX_GPIO87__FUNC_SPI0_MO>, + <PINMUX_GPIO88__FUNC_SPI0_CLK>; + bias-disable; + }; + }; + + mmc0_pins_default: mmc0default { + pins_cmd_dat { + pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, + <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, + <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, + <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, + <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, + <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, + <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, + <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, + <PINMUX_GPIO122__FUNC_MSDC0_CMD>; + input-enable; + bias-pull-up; + }; + + pins_clk { + pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; + bias-pull-down; + }; + + pins_rst { + pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; + bias-pull-up; + }; + }; + + mmc0_pins_uhs: mmc0 { + pins_cmd_dat { + pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, + <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, + <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, + <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, + <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, + <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, + <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, + <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, + <PINMUX_GPIO122__FUNC_MSDC0_CMD>; + input-enable; + drive-strength = <MTK_DRIVE_10mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins_clk { + pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; + drive-strength = <MTK_DRIVE_10mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins_ds { + pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>; + drive-strength = <MTK_DRIVE_10mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins_rst { + pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; + drive-strength = <MTK_DRIVE_10mA>; + bias-pull-up; + }; + }; + + mmc1_pins_default: mmc1default { + pins_cmd_dat { + pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, + <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, + <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, + <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, + <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; + input-enable; + bias-pull-up; + }; + + pins_clk { + pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; + input-enable; + bias-pull-down; + }; + + pins_pmu { + pinmux = <PINMUX_GPIO178__FUNC_GPIO178>, + <PINMUX_GPIO166__FUNC_GPIO166>; + output-high; + }; + }; + + mmc1_pins_uhs: mmc1 { + pins_cmd_dat { + pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, + <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, + <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, + <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, + <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; + drive-strength = <MTK_DRIVE_6mA>; + input-enable; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins_clk { + pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; + drive-strength = <MTK_DRIVE_6mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + input-enable; + }; + }; + + spi_pins_1: spi1 { + pins_spi { + pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>, + <PINMUX_GPIO162__FUNC_SPI1_A_CSB>, + <PINMUX_GPIO163__FUNC_SPI1_A_MO>, + <PINMUX_GPIO164__FUNC_SPI1_A_CLK>; + bias-disable; + }; + }; + + spi_pins_2: spi2 { + pins_spi { + pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>, + <PINMUX_GPIO1__FUNC_SPI2_MO>, + <PINMUX_GPIO2__FUNC_SPI2_CLK>, + <PINMUX_GPIO94__FUNC_SPI2_MI>; + bias-disable; + }; + }; + + spi_pins_3: spi3 { + pins_spi { + pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>, + <PINMUX_GPIO22__FUNC_SPI3_CSB>, + <PINMUX_GPIO23__FUNC_SPI3_MO>, + <PINMUX_GPIO24__FUNC_SPI3_CLK>; + bias-disable; + }; + }; + + spi_pins_4: spi4 { + pins_spi { + pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>, + <PINMUX_GPIO18__FUNC_SPI4_CSB>, + <PINMUX_GPIO19__FUNC_SPI4_MO>, + <PINMUX_GPIO20__FUNC_SPI4_CLK>; + bias-disable; + }; + }; + + spi_pins_5: spi5 { + pins_spi { + pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>, + <PINMUX_GPIO14__FUNC_SPI5_CSB>, + <PINMUX_GPIO15__FUNC_SPI5_MO>, + <PINMUX_GPIO16__FUNC_SPI5_CLK>; + bias-disable; + }; + }; + + pwm_pins_1: pwm1 { + pins_pwm { + pinmux = <PINMUX_GPIO90__FUNC_PWM_A>; + }; + }; +}; + +&mfg { + domain-supply = <&mt6358_vgpu_reg>; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins_0>; + mediatek,pad-select = <0>; + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins_1>; + mediatek,pad-select = <0>; + status = "okay"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins_2>; + mediatek,pad-select = <0>; + status = "okay"; +}; + +&spi3 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins_3>; + mediatek,pad-select = <0>; + status = "okay"; +}; + +&spi4 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins_4>; + mediatek,pad-select = <0>; + status = "okay"; +}; + +&spi5 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins_5>; + mediatek,pad-select = <0>; + status = "okay"; + +}; + +&cci { + proc-supply = <&mt6358_vproc12_reg>; +}; + +&cpu0 { + proc-supply = <&mt6358_vproc12_reg>; +}; + +&cpu1 { + proc-supply = <&mt6358_vproc12_reg>; +}; + +&cpu2 { + proc-supply = <&mt6358_vproc12_reg>; +}; + +&cpu3 { + proc-supply = <&mt6358_vproc12_reg>; +}; + +&cpu4 { + proc-supply = <&mt6358_vproc11_reg>; +}; + +&cpu5 { + proc-supply = <&mt6358_vproc11_reg>; +}; + +&cpu6 { + proc-supply = <&mt6358_vproc11_reg>; +}; + +&cpu7 { + proc-supply = <&mt6358_vproc11_reg>; +}; + +&uart0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; + pinctrl-0 = <&pwm_pins_1>; + pinctrl-names = "default"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219-max98357a.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219-max98357a.dtsi new file mode 100644 index 000000000..e4aeea459 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219-max98357a.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Google Kukui (and derivatives) da7219-max98357a sound card. + * + * Copyright 2019 Google LLC. + */ + +#include "mt8183-kukui-audio-da7219.dtsi" +#include "mt8183-kukui-audio-max98357a.dtsi" + +&sound { + compatible = "mediatek,mt8183_da7219_max98357"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219-rt1015p.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219-rt1015p.dtsi new file mode 100644 index 000000000..16ce5a361 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219-rt1015p.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Google Kukui (and derivatives) da7219-rt1015p sound card. + * + * Copyright 2020 Google LLC. + */ + +#include "mt8183-kukui-audio-da7219.dtsi" +#include "mt8183-kukui-audio-rt1015p.dtsi" + +&sound { + compatible = "mediatek,mt8183_da7219_rt1015p"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi new file mode 100644 index 000000000..2c69e7658 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Google Kukui (and derivatives) audio fragment for da7219. + * + * Copyright 2020 Google LLC. + */ + +&i2c5 { + da7219: da7219@1a { + pinctrl-names = "default"; + pinctrl-0 = <&da7219_pins>; + compatible = "dlg,da7219"; + reg = <0x1a>; + interrupt-parent = <&pio>; + interrupts = <165 IRQ_TYPE_LEVEL_LOW 165 0>; + + dlg,micbias-lvl = <2600>; + dlg,mic-amp-in-sel = "diff"; + VDD-supply = <&pp1800_alw>; + VDDMIC-supply = <&pp3300_alw>; + VDDIO-supply = <&pp1800_alw>; + + status = "okay"; + + da7219_aad { + dlg,adc-1bit-rpt = <1>; + dlg,btn-avg = <4>; + dlg,btn-cfg = <50>; + dlg,mic-det-thr = <500>; + dlg,jack-ins-deb = <20>; + dlg,jack-det-rate = "32ms_64ms"; + dlg,jack-rem-deb = <1>; + + dlg,a-d-btn-thr = <0xa>; + dlg,d-b-btn-thr = <0x16>; + dlg,b-c-btn-thr = <0x21>; + dlg,c-mic-btn-thr = <0x3E>; + }; + }; +}; + +&pio { + da7219_pins: da7219_pins { + pins1 { + pinmux = <PINMUX_GPIO165__FUNC_GPIO165>; + input-enable; + bias-pull-up; + }; + }; +}; + +&sound { + mediatek,headset-codec = <&da7219>; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-max98357a.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-max98357a.dtsi new file mode 100644 index 000000000..2b60967c0 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-max98357a.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Google Kukui (and derivatives) audio fragment for max98357a. + * + * Copyright 2020 Google LLC. + */ + +/ { + max98357a: max98357a { + compatible = "maxim,max98357a"; + sdmode-gpios = <&pio 175 0>; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-rt1015p.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-rt1015p.dtsi new file mode 100644 index 000000000..658a764fe --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-rt1015p.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Google Kukui (and derivatives) audio fragment for rt1015p. + * + * Copyright 2020 Google LLC. + */ + +/ { + rt1015p: rt1015p { + compatible = "realtek,rt1015p"; + sdb-gpios = <&pio 175 0>; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e-max98357a.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e-max98357a.dtsi new file mode 100644 index 000000000..260a5f561 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e-max98357a.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Google Kukui (and derivatives) ts3a227e-max98357a sound card. + * + * Copyright 2020 Google LLC. + */ + +#include "mt8183-kukui-audio-max98357a.dtsi" +#include "mt8183-kukui-audio-ts3a227e.dtsi" + +&sound { + compatible = "mediatek,mt8183_mt6358_ts3a227_max98357"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e-rt1015p.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e-rt1015p.dtsi new file mode 100644 index 000000000..2f7d1fa1c --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e-rt1015p.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Google Kukui (and derivatives) mt6358-ts3a227-rt1015p sound card. + * + * Copyright 2021 Google LLC. + */ + +#include "mt8183-kukui-audio-ts3a227e.dtsi" +#include "mt8183-kukui-audio-rt1015p.dtsi" + +&sound { + compatible = "mediatek,mt8183_mt6358_ts3a227_rt1015p"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e.dtsi new file mode 100644 index 000000000..0799c48ad --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Google Kukui (and derivatives) audio fragment for ts3a227e. + * + * Copyright 2019 Google LLC. + */ + +&i2c5 { + ts3a227e: ts3a227e@3b { + pinctrl-names = "default"; + pinctrl-0 = <&ts3a227e_pins>; + compatible = "ti,ts3a227e"; + reg = <0x3b>; + interrupt-parent = <&pio>; + interrupts = <157 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + }; +}; + +&pio { + ts3a227e_pins: ts3a227e_pins { + pins1 { + pinmux = <PINMUX_GPIO157__FUNC_GPIO157>; + input-enable; + bias-pull-up; + }; + }; +}; + +&sound { + mediatek,headset-codec = <&ts3a227e>; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts new file mode 100644 index 000000000..1a2ec0787 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi.dtsi" +#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi" + +/ { + model = "Google burnet board"; + compatible = "google,burnet", "mediatek,mt8183"; +}; + +&mt6358codec { + mediatek,dmic-mode = <1>; /* one-wire */ +}; + +&i2c0 { + touchscreen@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>; + + post-power-on-delay-ms = <200>; + hid-descr-addr = <0x0020>; + }; +}; + diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts new file mode 100644 index 000000000..072133fb0 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi.dtsi" +#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi" + +/ { + model = "Google cozmo board"; + compatible = "google,cozmo", "mediatek,mt8183"; +}; + +&i2c_tunnel { + google,remote-bus = <0>; +}; + +&i2c2 { + trackpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + hid-descr-addr = <0x20>; + + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_pins>; + + interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>; + + wakeup-source; + }; +}; + +&qca_wifi { + qcom,ath10k-calibration-variant = "GO_COZMO"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts new file mode 100644 index 000000000..0eca3ff86 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi.dtsi" +#include "mt8183-kukui-audio-da7219-max98357a.dtsi" + +/ { + model = "Google damu board"; + compatible = "google,damu", "mediatek,mt8183"; +}; + +&touchscreen { + status = "okay"; + + compatible = "hid-over-i2c"; + reg = <0x10>; + interrupt-parent = <&pio>; + interrupts = <155 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + + post-power-on-delay-ms = <10>; + hid-descr-addr = <0x0001>; +}; + +&qca_wifi { + qcom,ath10k-calibration-variant = "GO_DAMU"; +}; + diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts new file mode 100644 index 000000000..dec11a4eb --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi-fennel.dtsi" +#include "mt8183-kukui-audio-da7219-rt1015p.dtsi" + +/ { + model = "Google fennel sku1 board"; + compatible = "google,fennel-sku1", "google,fennel", "mediatek,mt8183"; + + pwmleds { + compatible = "pwm-leds"; + keyboard_backlight: keyboard-backlight { + label = "cros_ec::kbd_backlight"; + pwms = <&cros_ec_pwm 0>; + max-brightness = <1023>; + }; + }; +}; + +&cros_ec_pwm { + status = "okay"; +}; + +&touchscreen { + status = "okay"; + + compatible = "hid-over-i2c"; + reg = <0x10>; + interrupt-parent = <&pio>; + interrupts = <155 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + + post-power-on-delay-ms = <10>; + hid-descr-addr = <0x0001>; +}; + +&qca_wifi { + qcom,ath10k-calibration-variant = "GO_FENNEL"; +}; + diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts new file mode 100644 index 000000000..37e6e58f6 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi-fennel.dtsi" +#include "mt8183-kukui-audio-da7219-rt1015p.dtsi" + +/ { + model = "Google fennel sku6 board"; + compatible = "google,fennel-sku6", "google,fennel", "mediatek,mt8183"; +}; + +&touchscreen { + status = "okay"; + + compatible = "hid-over-i2c"; + reg = <0x10>; + interrupt-parent = <&pio>; + interrupts = <155 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + + post-power-on-delay-ms = <10>; + hid-descr-addr = <0x0001>; +}; + + +&qca_wifi { + qcom,ath10k-calibration-variant = "GO_FENNEL"; +}; + diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts new file mode 100644 index 000000000..0e0960400 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi-fennel.dtsi" +#include "mt8183-kukui-audio-ts3a227e-rt1015p.dtsi" + +/ { + model = "Google fennel sku7 board"; + compatible = "google,fennel-sku7", "google,fennel", "mediatek,mt8183"; +}; + +&touchscreen { + status = "okay"; + + compatible = "hid-over-i2c"; + reg = <0x10>; + interrupt-parent = <&pio>; + interrupts = <155 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + + post-power-on-delay-ms = <10>; + hid-descr-addr = <0x0001>; +}; + + +&qca_wifi { + qcom,ath10k-calibration-variant = "GO_FENNEL"; +}; + diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi new file mode 100644 index 000000000..bbe6c338f --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi.dtsi" + +&mt6358codec { + mediatek,dmic-mode = <1>; /* one-wire */ +}; + +&i2c2 { + trackpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + hid-descr-addr = <0x20>; + + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_pins>; + + interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>; + + wakeup-source; + }; +}; + diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts new file mode 100644 index 000000000..3fc5a6181 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi-fennel.dtsi" +#include "mt8183-kukui-audio-ts3a227e-rt1015p.dtsi" + +/ { + model = "Google fennel14 sku2 board"; + compatible = "google,fennel-sku2", "google,fennel", "mediatek,mt8183"; +}; + +&qca_wifi { + qcom,ath10k-calibration-variant = "GO_FENNEL14"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts new file mode 100644 index 000000000..23ad0b91e --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi-fennel.dtsi" +#include "mt8183-kukui-audio-da7219-rt1015p.dtsi" + +/ { + model = "Google fennel14 sku0 board"; + compatible = "google,fennel-sku0", "google,fennel", "mediatek,mt8183"; +}; + +&qca_wifi { + qcom,ath10k-calibration-variant = "GO_FENNEL14"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts new file mode 100644 index 000000000..bc2c57f0a --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi-juniper.dtsi" +#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi" + +/ { + model = "Google juniper sku16 board"; + compatible = "google,juniper-sku16", "google,juniper", "mediatek,mt8183"; +}; + diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper.dtsi new file mode 100644 index 000000000..078bc7656 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi.dtsi" + +&i2c2 { + trackpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + hid-descr-addr = <0x20>; + + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_pins>; + + interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>; + + wakeup-source; + }; +}; + +&qca_wifi { + qcom,ath10k-calibration-variant = "GO_JUNIPER"; +}; + diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts new file mode 100644 index 000000000..e5bd9191e --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi.dtsi" +#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi" + +/ { + model = "Google kappa board"; + compatible = "google,kappa", "mediatek,mt8183"; +}; + +&mt6358codec { + mediatek,dmic-mode = <1>; /* one-wire */ +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts new file mode 100644 index 000000000..8fa89db03 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi-juniper.dtsi" +#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi" + +/ { + model = "Google kenzo sku17 board"; + compatible = "google,juniper-sku17", "google,juniper", "mediatek,mt8183"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts new file mode 100644 index 000000000..89208b843 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi-willow.dtsi" +#include "mt8183-kukui-audio-da7219-max98357a.dtsi" + +/ { + model = "Google willow board sku0"; + compatible = "google,willow-sku0", "google,willow", "mediatek,mt8183"; +}; + diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts new file mode 100644 index 000000000..c7b20441d --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi-willow.dtsi" +#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi" + +/ { + model = "Google willow board sku1"; + compatible = "google,willow-sku1", "google,willow", "mediatek,mt8183"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow.dtsi new file mode 100644 index 000000000..76d335401 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-jacuzzi.dtsi" + +&i2c2 { + trackpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + hid-descr-addr = <0x20>; + + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_pins>; + + interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>; + + wakeup-source; + }; +}; + +&qca_wifi { + qcom,ath10k-calibration-variant = "GO_JUNIPER"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi new file mode 100644 index 000000000..dccf367c7 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi @@ -0,0 +1,483 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +#include "mt8183-kukui.dtsi" + +/ { + panel: panel { + compatible = "auo,b116xw03"; + power-supply = <&pp3300_panel>; + backlight = <&backlight_lcd0>; + + port { + panel_in: endpoint { + remote-endpoint = <&anx7625_out>; + }; + }; + }; + + pp1200_mipibrdg: pp1200-mipibrdg { + compatible = "regulator-fixed"; + regulator-name = "pp1200_mipibrdg"; + pinctrl-names = "default"; + pinctrl-0 = <&pp1200_mipibrdg_en>; + + enable-active-high; + regulator-boot-on; + + gpio = <&pio 54 GPIO_ACTIVE_HIGH>; + }; + + pp1800_mipibrdg: pp1800-mipibrdg { + compatible = "regulator-fixed"; + regulator-name = "pp1800_mipibrdg"; + pinctrl-names = "default"; + pinctrl-0 = <&pp1800_lcd_en>; + + enable-active-high; + regulator-boot-on; + + gpio = <&pio 36 GPIO_ACTIVE_HIGH>; + }; + + pp3300_panel: pp3300-panel { + compatible = "regulator-fixed"; + regulator-name = "pp3300_panel"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pp3300_panel_pins>; + + enable-active-high; + regulator-boot-on; + + gpio = <&pio 35 GPIO_ACTIVE_HIGH>; + }; + + vddio_mipibrdg: vddio-mipibrdg { + compatible = "regulator-fixed"; + regulator-name = "vddio_mipibrdg"; + pinctrl-names = "default"; + pinctrl-0 = <&vddio_mipibrdg_en>; + + enable-active-high; + regulator-boot-on; + + gpio = <&pio 37 GPIO_ACTIVE_HIGH>; + }; + + volume_buttons: volume-buttons { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&volume_button_pins>; + + button-volume-down { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + debounce-interval = <100>; + + gpios = <&pio 6 GPIO_ACTIVE_LOW>; + }; + + button-volume-up { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <100>; + + gpios = <&pio 5 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&cros_ec { + cros_ec_pwm: pwm { + compatible = "google,cros-ec-pwm"; + #pwm-cells = <1>; + status = "disabled"; + }; +}; + +&dsi0 { + status = "okay"; + /delete-property/#size-cells; + /delete-property/#address-cells; + /delete-node/panel@0; + ports { + port { + dsi_out: endpoint { + remote-endpoint = <&anx7625_in>; + }; + }; + }; +}; + +&i2c0 { + status = "okay"; + + touchscreen: touchscreen@10 { + compatible = "elan,ekth3500"; + reg = <0x10>; + + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + + interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&pio 156 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "okay"; + clock-frequency = <400000>; + + trackpad@15 { + compatible = "elan,ekth3000"; + reg = <0x15>; + + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_pins>; + + interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>; + + wakeup-source; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + status = "okay"; + clock-frequency = <100000>; + + anx_bridge: anx7625@58 { + compatible = "analogix,anx7625"; + reg = <0x58>; + pinctrl-names = "default"; + pinctrl-0 = <&anx7625_pins>; + panel_flags = <1>; + enable-gpios = <&pio 45 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 73 GPIO_ACTIVE_HIGH>; + vdd10-supply = <&pp1200_mipibrdg>; + vdd18-supply = <&pp1800_mipibrdg>; + vdd33-supply = <&vddio_mipibrdg>; + + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + + anx7625_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + anx7625_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&i2c_tunnel { + google,remote-bus = <2>; +}; + +&pio { + /* 192 lines */ + gpio-line-names = + "SPI_AP_EC_CS_L", + "SPI_AP_EC_MOSI", + "SPI_AP_EC_CLK", + "I2S3_DO", + "USB_PD_INT_ODL", + "", + "", + "", + "", + "IT6505_HPD_L", + "I2S3_TDM_D3", + "SOC_I2C6_1V8_SCL", + "SOC_I2C6_1V8_SDA", + "DPI_D0", + "DPI_D1", + "DPI_D2", + "DPI_D3", + "DPI_D4", + "DPI_D5", + "DPI_D6", + "DPI_D7", + "DPI_D8", + "DPI_D9", + "DPI_D10", + "DPI_D11", + "DPI_HSYNC", + "DPI_VSYNC", + "DPI_DE", + "DPI_CK", + "AP_MSDC1_CLK", + "AP_MSDC1_DAT3", + "AP_MSDC1_CMD", + "AP_MSDC1_DAT0", + "AP_MSDC1_DAT2", + "AP_MSDC1_DAT1", + "", + "", + "", + "", + "", + "", + "OTG_EN", + "DRVBUS", + "DISP_PWM", + "DSI_TE", + "LCM_RST_1V8", + "AP_CTS_WIFI_RTS", + "AP_RTS_WIFI_CTS", + "SOC_I2C5_1V8_SCL", + "SOC_I2C5_1V8_SDA", + "SOC_I2C3_1V8_SCL", + "SOC_I2C3_1V8_SDA", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SOC_I2C1_1V8_SDA", + "SOC_I2C0_1V8_SDA", + "SOC_I2C0_1V8_SCL", + "SOC_I2C1_1V8_SCL", + "AP_SPI_H1_MISO", + "AP_SPI_H1_CS_L", + "AP_SPI_H1_MOSI", + "AP_SPI_H1_CLK", + "I2S5_BCK", + "I2S5_LRCK", + "I2S5_DO", + "BOOTBLOCK_EN_L", + "MT8183_KPCOL0", + "SPI_AP_EC_MISO", + "UART_DBG_TX_AP_RX", + "UART_AP_TX_DBG_RX", + "I2S2_MCK", + "I2S2_BCK", + "CLK_5M_WCAM", + "CLK_2M_UCAM", + "I2S2_LRCK", + "I2S2_DI", + "SOC_I2C2_1V8_SCL", + "SOC_I2C2_1V8_SDA", + "SOC_I2C4_1V8_SCL", + "SOC_I2C4_1V8_SDA", + "", + "SCL8", + "SDA8", + "FCAM_PWDN_L", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "I2S_PMIC", + "I2S_PMIC", + "I2S_PMIC", + "I2S_PMIC", + "I2S_PMIC", + "I2S_PMIC", + "I2S_PMIC", + "I2S_PMIC", + "", + "", + "", + "", + "", + "", + /* + * AP_FLASH_WP_L is crossystem ABI. Rev1 schematics + * call it BIOS_FLASH_WP_R_L. + */ + "AP_FLASH_WP_L", + "EC_AP_INT_ODL", + "IT6505_INT_ODL", + "H1_INT_OD_L", + "", + "", + "", + "", + "", + "", + "", + "AP_SPI_FLASH_MISO", + "AP_SPI_FLASH_CS_L", + "AP_SPI_FLASH_MOSI", + "AP_SPI_FLASH_CLK", + "DA7219_IRQ", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + ""; + + pp1200_mipibrdg_en: pp1200-mipibrdg-en { + pins1 { + pinmux = <PINMUX_GPIO54__FUNC_GPIO54>; + output-low; + }; + }; + + pp1800_lcd_en: pp1800-lcd-en { + pins1 { + pinmux = <PINMUX_GPIO36__FUNC_GPIO36>; + output-low; + }; + }; + + pp3300_panel_pins: pp3300-panel-pins { + panel_3v3_enable: panel-3v3-enable { + pinmux = <PINMUX_GPIO35__FUNC_GPIO35>; + output-low; + }; + }; + + ppvarp_lcd_en: ppvarp-lcd-en { + pins1 { + pinmux = <PINMUX_GPIO66__FUNC_GPIO66>; + output-low; + }; + }; + + ppvarn_lcd_en: ppvarn-lcd-en { + pins1 { + pinmux = <PINMUX_GPIO166__FUNC_GPIO166>; + output-low; + }; + }; + + anx7625_pins: anx7625-pins { + pins1 { + pinmux = <PINMUX_GPIO45__FUNC_GPIO45>, + <PINMUX_GPIO73__FUNC_GPIO73>; + output-low; + }; + pins2 { + pinmux = <PINMUX_GPIO4__FUNC_GPIO4>; + input-enable; + bias-pull-up; + }; + }; + + touchscreen_pins: touchscreen-pins { + touch-int-odl { + pinmux = <PINMUX_GPIO155__FUNC_GPIO155>; + input-enable; + bias-pull-up; + }; + + touch-rst-l { + pinmux = <PINMUX_GPIO156__FUNC_GPIO156>; + output-high; + }; + }; + + trackpad_pins: trackpad-pins { + trackpad-int { + pinmux = <PINMUX_GPIO7__FUNC_GPIO7>; + input-enable; + bias-disable; /* pulled externally */ + }; + }; + + vddio_mipibrdg_en: vddio-mipibrdg-en { + pins1 { + pinmux = <PINMUX_GPIO37__FUNC_GPIO37>; + output-low; + }; + }; + + volume_button_pins: volume-button-pins { + voldn-btn-odl { + pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; + input-enable; + bias-pull-up; + }; + + volup-btn-odl { + pinmux = <PINMUX_GPIO5__FUNC_GPIO5>; + input-enable; + bias-pull-up; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts new file mode 100644 index 000000000..3a724e6f9 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-kakadu.dtsi" +#include "mt8183-kukui-audio-rt1015p.dtsi" + +/ { + model = "MediaTek kakadu board sku22"; + compatible = "google,kakadu-rev3-sku22", "google,kakadu-rev2-sku22", + "google,kakadu", "mediatek,mt8183"; +}; + +&sound { + compatible = "mediatek,mt8183_mt6358_ts3a227_rt1015p"; +}; + diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts new file mode 100644 index 000000000..89a139a0e --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui-kakadu.dtsi" +#include "mt8183-kukui-audio-da7219-rt1015p.dtsi" + +/ { + model = "MediaTek kakadu board"; + compatible = "google,kakadu-rev3", "google,kakadu-rev2", + "google,kakadu", "mediatek,mt8183"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi new file mode 100644 index 000000000..50a0dd36b --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi @@ -0,0 +1,382 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 Google LLC + */ + +#include "mt8183-kukui.dtsi" +#include <dt-bindings/input/gpio-keys.h> + +/ { + ppvarn_lcd: ppvarn-lcd { + compatible = "regulator-fixed"; + regulator-name = "ppvarn_lcd"; + pinctrl-names = "default"; + pinctrl-0 = <&ppvarn_lcd_en>; + + enable-active-high; + + gpio = <&pio 66 GPIO_ACTIVE_HIGH>; + }; + + ppvarp_lcd: ppvarp-lcd { + compatible = "regulator-fixed"; + regulator-name = "ppvarp_lcd"; + pinctrl-names = "default"; + pinctrl-0 = <&ppvarp_lcd_en>; + + enable-active-high; + + gpio = <&pio 166 GPIO_ACTIVE_HIGH>; + }; + + pp1800_lcd: pp1800-lcd { + compatible = "regulator-fixed"; + regulator-name = "pp1800_lcd"; + pinctrl-names = "default"; + pinctrl-0 = <&pp1800_lcd_en>; + + enable-active-high; + + gpio = <&pio 36 GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pen_eject>; + + switch-pen-insert { + label = "Pen Insert"; + /* Insert = low, eject = high */ + gpios = <&pio 6 GPIO_ACTIVE_LOW>; + linux,code = <SW_PEN_INSERTED>; + linux,input-type = <EV_SW>; + wakeup-event-action = <EV_ACT_DEASSERTED>; + wakeup-source; + }; + }; +}; + +&bluetooth { + firmware-name = "nvm_00440302_i2s_eu.bin"; +}; + +&i2c0 { + status = "okay"; + + touchscreen: touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + pinctrl-names = "default"; + pinctrl-0 = <&open_touch>; + + interrupt-parent = <&pio>; + interrupts = <155 IRQ_TYPE_EDGE_FALLING>; + + post-power-on-delay-ms = <10>; + hid-descr-addr = <0x0001>; + }; +}; + +&mt6358_vcama2_reg { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "okay"; + clock-frequency = <400000>; + vbus-supply = <&mt6358_vcamio_reg>; + + eeprom@58 { + compatible = "atmel,24c32"; + reg = <0x58>; + pagesize = <32>; + vcc-supply = <&mt6358_vcama2_reg>; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + status = "okay"; + clock-frequency = <400000>; + vbus-supply = <&mt6358_vcn18_reg>; + + eeprom@54 { + compatible = "atmel,24c32"; + reg = <0x54>; + pagesize = <32>; + vcc-supply = <&mt6358_vcn18_reg>; + }; +}; + +&mipi_tx0 { + drive-strength-microamp = <5800>; +}; + +&pio { + /* 192 lines */ + gpio-line-names = + "SPI_AP_EC_CS_L", + "SPI_AP_EC_MOSI", + "SPI_AP_EC_CLK", + "I2S3_DO", + "USB_PD_INT_ODL", + "", + "", + "", + "", + "IT6505_HPD_L", + "I2S3_TDM_D3", + "SOC_I2C6_1V8_SCL", + "SOC_I2C6_1V8_SDA", + "DPI_D0", + "DPI_D1", + "DPI_D2", + "DPI_D3", + "DPI_D4", + "DPI_D5", + "DPI_D6", + "DPI_D7", + "DPI_D8", + "DPI_D9", + "DPI_D10", + "DPI_D11", + "DPI_HSYNC", + "DPI_VSYNC", + "DPI_DE", + "DPI_CK", + "AP_MSDC1_CLK", + "AP_MSDC1_DAT3", + "AP_MSDC1_CMD", + "AP_MSDC1_DAT0", + "AP_MSDC1_DAT2", + "AP_MSDC1_DAT1", + "", + "", + "", + "", + "", + "", + "OTG_EN", + "DRVBUS", + "DISP_PWM", + "DSI_TE", + "LCM_RST_1V8", + "AP_CTS_WIFI_RTS", + "AP_RTS_WIFI_CTS", + "SOC_I2C5_1V8_SCL", + "SOC_I2C5_1V8_SDA", + "SOC_I2C3_1V8_SCL", + "SOC_I2C3_1V8_SDA", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SOC_I2C1_1V8_SDA", + "SOC_I2C0_1V8_SDA", + "SOC_I2C0_1V8_SCL", + "SOC_I2C1_1V8_SCL", + "AP_SPI_H1_MISO", + "AP_SPI_H1_CS_L", + "AP_SPI_H1_MOSI", + "AP_SPI_H1_CLK", + "I2S5_BCK", + "I2S5_LRCK", + "I2S5_DO", + "BOOTBLOCK_EN_L", + "MT8183_KPCOL0", + "SPI_AP_EC_MISO", + "UART_DBG_TX_AP_RX", + "UART_AP_TX_DBG_RX", + "I2S2_MCK", + "I2S2_BCK", + "CLK_5M_WCAM", + "CLK_2M_UCAM", + "I2S2_LRCK", + "I2S2_DI", + "SOC_I2C2_1V8_SCL", + "SOC_I2C2_1V8_SDA", + "SOC_I2C4_1V8_SCL", + "SOC_I2C4_1V8_SDA", + "", + "SCL8", + "SDA8", + "FCAM_PWDN_L", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "I2S_PMIC", + "I2S_PMIC", + "I2S_PMIC", + "I2S_PMIC", + "I2S_PMIC", + "I2S_PMIC", + "I2S_PMIC", + "I2S_PMIC", + "", + "", + "", + "", + "", + "", + /* + * AP_FLASH_WP_L is crossystem ABI. Rev1 schematics + * call it BIOS_FLASH_WP_R_L. + */ + "AP_FLASH_WP_L", + "EC_AP_INT_ODL", + "IT6505_INT_ODL", + "H1_INT_OD_L", + "", + "", + "", + "", + "", + "", + "", + "AP_SPI_FLASH_MISO", + "AP_SPI_FLASH_CS_L", + "AP_SPI_FLASH_MOSI", + "AP_SPI_FLASH_CLK", + "DA7219_IRQ", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + ""; + + ppvarp_lcd_en: ppvarp-lcd-en { + pins1 { + pinmux = <PINMUX_GPIO66__FUNC_GPIO66>; + output-low; + }; + }; + + ppvarn_lcd_en: ppvarn-lcd-en { + pins1 { + pinmux = <PINMUX_GPIO166__FUNC_GPIO166>; + output-low; + }; + }; + + pp1800_lcd_en: pp1800-lcd-en { + pins1 { + pinmux = <PINMUX_GPIO36__FUNC_GPIO36>; + output-low; + }; + }; + + open_touch: open_touch { + irq_pin { + pinmux = <PINMUX_GPIO155__FUNC_GPIO155>; + input-enable; + bias-pull-up; + }; + + rst_pin { + pinmux = <PINMUX_GPIO156__FUNC_GPIO156>; + + /* + * The pen driver doesn't currently support driving + * this reset line. By specifying output-high here + * we're relying on the fact that this pin has a default + * pulldown at boot (which makes sure the pen was in + * reset if it was powered) and then we set it high here + * to take it out of reset. Better would be if the pen + * driver could control this and we could remove + * "output-high" here. + */ + output-high; + }; + }; + + pen_eject: peneject { + pen_eject { + pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; + input-enable; + /* External pull-up. */ + bias-disable; + }; + }; +}; + +&qca_wifi { + qcom,ath10k-calibration-variant = "GO_KAKADU"; +}; + +&panel { + status = "okay"; + compatible = "boe,tv105wum-nw0"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts new file mode 100644 index 000000000..e3dd75bda --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + * + * SKU: 0x10 => 16 + * - bit 8: Camera: 0 (OV5695) + * - bits 7..4: Panel ID: 0x1 (AUO) + */ + +/dts-v1/; +#include "mt8183-kukui-kodama.dtsi" + +/ { + model = "MediaTek kodama sku16 board"; + compatible = "google,kodama-sku16", "google,kodama", "mediatek,mt8183"; +}; + +&panel { + status = "okay"; + compatible = "auo,b101uan08.3"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts new file mode 100644 index 000000000..d81935ae0 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 Google LLC + * + * SKU: 0x110 => 272 + * - bit 8: Camera: 1 (GC5035) + * - bits 7..4: Panel ID: 0x1 (AUO) + */ + +/dts-v1/; +#include "mt8183-kukui-kodama.dtsi" + +/ { + model = "MediaTek kodama sku272 board"; + compatible = "google,kodama-sku272", "google,kodama", "mediatek,mt8183"; +}; + +&panel { + status = "okay"; + compatible = "auo,b101uan08.3"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts new file mode 100644 index 000000000..f4082fbe0 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 Google LLC + * + * SKU: 0x120 => 288 + * - bit 8: Camera: 1 (GC5035) + * - bits 7..4: Panel ID: 0x2 (BOE) + */ + +/dts-v1/; +#include "mt8183-kukui-kodama.dtsi" + +/ { + model = "MediaTek kodama sku288 board"; + compatible = "google,kodama-sku288", "google,kodama", "mediatek,mt8183"; +}; + +&panel { + status = "okay"; + compatible = "boe,tv101wum-n53"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dts new file mode 100644 index 000000000..773935800 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + * + * SKU: 0x20 => 32 + * - bit 8: Camera: 0 (OV5695) + * - bits 7..4: Panel ID: 0x2 (BOE) + */ + +/dts-v1/; +#include "mt8183-kukui-kodama.dtsi" + +/ { + model = "MediaTek kodama sku32 board"; + compatible = "google,kodama-sku32", "google,kodama", "mediatek,mt8183"; +}; + +&panel { + status = "okay"; + compatible = "boe,tv101wum-n53"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi new file mode 100644 index 000000000..06f8c80bf --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi @@ -0,0 +1,348 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ + +/dts-v1/; +#include "mt8183-kukui.dtsi" +#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi" + +/ { + ppvarn_lcd: ppvarn-lcd { + compatible = "regulator-fixed"; + regulator-name = "ppvarn_lcd"; + pinctrl-names = "default"; + pinctrl-0 = <&ppvarn_lcd_en>; + + enable-active-high; + + gpio = <&pio 66 GPIO_ACTIVE_HIGH>; + }; + + ppvarp_lcd: ppvarp-lcd { + compatible = "regulator-fixed"; + regulator-name = "ppvarp_lcd"; + pinctrl-names = "default"; + pinctrl-0 = <&ppvarp_lcd_en>; + + enable-active-high; + + gpio = <&pio 166 GPIO_ACTIVE_HIGH>; + }; + + pp1800_lcd: pp1800-lcd { + compatible = "regulator-fixed"; + regulator-name = "pp1800_lcd"; + pinctrl-names = "default"; + pinctrl-0 = <&pp1800_lcd_en>; + + enable-active-high; + + gpio = <&pio 36 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c0 { + status = "okay"; + + touchscreen: touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + interrupt-parent = <&pio>; + interrupts = <155 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_default>; + + post-power-on-delay-ms = <10>; + hid-descr-addr = <0x0001>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "okay"; + clock-frequency = <400000>; + vbus-supply = <&mt6358_vcamio_reg>; + + eeprom@58 { + compatible = "atmel,24c64"; + reg = <0x58>; + pagesize = <32>; + vcc-supply = <&mt6358_vcamio_reg>; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + status = "okay"; + clock-frequency = <400000>; + vbus-supply = <&mt6358_vcn18_reg>; + + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + pagesize = <32>; + vcc-supply = <&mt6358_vcn18_reg>; + }; +}; + +&mt6358_vcama2_reg { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + +&pio { + /* 192 lines */ + gpio-line-names = + "SPI_AP_EC_CS_L", + "SPI_AP_EC_MOSI", + "SPI_AP_EC_CLK", + "I2S3_DO", + "USB_PD_INT_ODL", + "", + "", + "", + "", + "IT6505_HPD_L", + "I2S3_TDM_D3", + "SOC_I2C6_1V8_SCL", + "SOC_I2C6_1V8_SDA", + "DPI_D0", + "DPI_D1", + "DPI_D2", + "DPI_D3", + "DPI_D4", + "DPI_D5", + "DPI_D6", + "DPI_D7", + "DPI_D8", + "DPI_D9", + "DPI_D10", + "DPI_D11", + "DPI_HSYNC", + "DPI_VSYNC", + "DPI_DE", + "DPI_CK", + "AP_MSDC1_CLK", + "AP_MSDC1_DAT3", + "AP_MSDC1_CMD", + "AP_MSDC1_DAT0", + "AP_MSDC1_DAT2", + "AP_MSDC1_DAT1", + "", + "", + "", + "", + "", + "", + "OTG_EN", + "DRVBUS", + "DISP_PWM", + "DSI_TE", + "LCM_RST_1V8", + "AP_CTS_WIFI_RTS", + "AP_RTS_WIFI_CTS", + "SOC_I2C5_1V8_SCL", + "SOC_I2C5_1V8_SDA", + "SOC_I2C3_1V8_SCL", + "SOC_I2C3_1V8_SDA", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SOC_I2C1_1V8_SDA", + "SOC_I2C0_1V8_SDA", + "SOC_I2C0_1V8_SCL", + "SOC_I2C1_1V8_SCL", + "AP_SPI_H1_MISO", + "AP_SPI_H1_CS_L", + "AP_SPI_H1_MOSI", + "AP_SPI_H1_CLK", + "I2S5_BCK", + "I2S5_LRCK", + "I2S5_DO", + "BOOTBLOCK_EN_L", + "MT8183_KPCOL0", + "SPI_AP_EC_MISO", + "UART_DBG_TX_AP_RX", + "UART_AP_TX_DBG_RX", + "I2S2_MCK", + "I2S2_BCK", + "CLK_5M_WCAM", + "CLK_2M_UCAM", + "I2S2_LRCK", + "I2S2_DI", + "SOC_I2C2_1V8_SCL", + "SOC_I2C2_1V8_SDA", + "SOC_I2C4_1V8_SCL", + "SOC_I2C4_1V8_SDA", + "", + "SCL8", + "SDA8", + "FCAM_PWDN_L", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "I2S_PMIC", + "I2S_PMIC", + "I2S_PMIC", + "I2S_PMIC", + "I2S_PMIC", + "I2S_PMIC", + "I2S_PMIC", + "I2S_PMIC", + "", + "", + "", + "", + "", + "", + /* + * AP_FLASH_WP_L is crossystem ABI. Rev1 schematics + * call it BIOS_FLASH_WP_R_L. + */ + "AP_FLASH_WP_L", + "EC_AP_INT_ODL", + "IT6505_INT_ODL", + "H1_INT_OD_L", + "", + "", + "", + "", + "", + "", + "", + "AP_SPI_FLASH_MISO", + "AP_SPI_FLASH_CS_L", + "AP_SPI_FLASH_MOSI", + "AP_SPI_FLASH_CLK", + "DA7219_IRQ", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + ""; + + ppvarp_lcd_en: ppvarp-lcd-en { + pins1 { + pinmux = <PINMUX_GPIO66__FUNC_GPIO66>; + output-low; + }; + }; + + ppvarn_lcd_en: ppvarn-lcd-en { + pins1 { + pinmux = <PINMUX_GPIO166__FUNC_GPIO166>; + output-low; + }; + }; + + pp1800_lcd_en: pp1800-lcd-en { + pins1 { + pinmux = <PINMUX_GPIO36__FUNC_GPIO36>; + output-low; + }; + }; + + touch_default: touchdefault { + pin_irq { + pinmux = <PINMUX_GPIO155__FUNC_GPIO155>; + input-enable; + bias-pull-up; + }; + + touch_pin_reset: pin_reset { + pinmux = <PINMUX_GPIO156__FUNC_GPIO156>; + + /* + * The touchscreen driver doesn't currently support driving + * this reset line. By specifying output-high here + * we're relying on the fact that this pin has a default + * pulldown at boot (which makes sure the controller was in + * reset if it was powered) and then we set it high here + * to take it out of reset. Better would be if the touchscreen + * driver could control this and we could remove + * "output-high" here. + */ + output-high; + }; + }; +}; + +&qca_wifi { + qcom,ath10k-calibration-variant = "GO_KODAMA"; +}; + +&i2c_tunnel { + google,remote-bus = <2>; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts new file mode 100644 index 000000000..fb5ee91b6 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2019 Google LLC + * + * Device-tree for Krane sku0. + * + * SKU is a 8-bit value (0x00 == 0): + * - Bits 7..4: Panel ID: 0x0 (AUO) + * - Bits 3..0: SKU ID: 0x0 (default) + */ + +/dts-v1/; +#include "mt8183-kukui-krane.dtsi" + +/ { + model = "MediaTek krane sku0 board"; + compatible = "google,krane-sku0", "google,krane", "mediatek,mt8183"; +}; + +&panel { + status = "okay"; + compatible = "auo,kd101n80-45na"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts new file mode 100644 index 000000000..721d16f9c --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2019 Google LLC + * + * Device-tree for Krane sku176. + * + * SKU is a 8-bit value (0xb0 == 176): + * - Bits 7..4: Panel ID: 0xb (BOE) + * - Bits 3..0: SKU ID: 0x0 (default) + */ + +/dts-v1/; +#include "mt8183-kukui-krane.dtsi" + +/ { + model = "MediaTek krane sku176 board"; + compatible = "google,krane-sku176", "google,krane", "mediatek,mt8183"; +}; + +&panel { + status = "okay"; + compatible = "boe,tv101wum-nl6"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi new file mode 100644 index 000000000..a7b0cb3ff --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi @@ -0,0 +1,352 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2019 Google LLC + */ + +#include "mt8183-kukui.dtsi" +#include "mt8183-kukui-audio-max98357a.dtsi" + +/ { + ppvarn_lcd: ppvarn-lcd { + compatible = "regulator-fixed"; + regulator-name = "ppvarn_lcd"; + pinctrl-names = "default"; + pinctrl-0 = <&ppvarn_lcd_en>; + + enable-active-high; + + gpio = <&pio 66 GPIO_ACTIVE_HIGH>; + }; + + ppvarp_lcd: ppvarp-lcd { + compatible = "regulator-fixed"; + regulator-name = "ppvarp_lcd"; + pinctrl-names = "default"; + pinctrl-0 = <&ppvarp_lcd_en>; + + enable-active-high; + + gpio = <&pio 166 GPIO_ACTIVE_HIGH>; + }; + + pp1800_lcd: pp1800-lcd { + compatible = "regulator-fixed"; + regulator-name = "pp1800_lcd"; + pinctrl-names = "default"; + pinctrl-0 = <&pp1800_lcd_en>; + + enable-active-high; + + gpio = <&pio 36 GPIO_ACTIVE_HIGH>; + }; +}; + +&bluetooth { + firmware-name = "nvm_00440302_i2s_eu.bin"; +}; + +&i2c0 { + status = "okay"; + + touchscreen4: touchscreen@5d { + compatible = "hid-over-i2c"; + reg = <0x5d>; + pinctrl-names = "default"; + pinctrl-0 = <&open_touch>; + + interrupt-parent = <&pio>; + interrupts = <155 IRQ_TYPE_EDGE_FALLING>; + + post-power-on-delay-ms = <10>; + hid-descr-addr = <0x0001>; + }; +}; + +&mt6358_vcama2_reg { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "okay"; + clock-frequency = <400000>; + vbus-supply = <&mt6358_vcamio_reg>; + + eeprom@58 { + compatible = "atmel,24c32"; + reg = <0x58>; + pagesize = <32>; + vcc-supply = <&mt6358_vcama2_reg>; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + status = "okay"; + clock-frequency = <400000>; + vbus-supply = <&mt6358_vcn18_reg>; + + eeprom@54 { + compatible = "atmel,24c32"; + reg = <0x54>; + pagesize = <32>; + vcc-supply = <&mt6358_vcn18_reg>; + }; +}; + +&pio { + /* 192 lines */ + gpio-line-names = + "SPI_AP_EC_CS_L", + "SPI_AP_EC_MOSI", + "SPI_AP_EC_CLK", + "I2S3_DO", + "USB_PD_INT_ODL", + "", + "", + "", + "", + "IT6505_HPD_L", + "I2S3_TDM_D3", + "SOC_I2C6_1V8_SCL", + "SOC_I2C6_1V8_SDA", + "DPI_D0", + "DPI_D1", + "DPI_D2", + "DPI_D3", + "DPI_D4", + "DPI_D5", + "DPI_D6", + "DPI_D7", + "DPI_D8", + "DPI_D9", + "DPI_D10", + "DPI_D11", + "DPI_HSYNC", + "DPI_VSYNC", + "DPI_DE", + "DPI_CK", + "AP_MSDC1_CLK", + "AP_MSDC1_DAT3", + "AP_MSDC1_CMD", + "AP_MSDC1_DAT0", + "AP_MSDC1_DAT2", + "AP_MSDC1_DAT1", + "", + "", + "", + "", + "", + "", + "OTG_EN", + "DRVBUS", + "DISP_PWM", + "DSI_TE", + "LCM_RST_1V8", + "AP_CTS_WIFI_RTS", + "AP_RTS_WIFI_CTS", + "SOC_I2C5_1V8_SCL", + "SOC_I2C5_1V8_SDA", + "SOC_I2C3_1V8_SCL", + "SOC_I2C3_1V8_SDA", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SOC_I2C1_1V8_SDA", + "SOC_I2C0_1V8_SDA", + "SOC_I2C0_1V8_SCL", + "SOC_I2C1_1V8_SCL", + "AP_SPI_H1_MISO", + "AP_SPI_H1_CS_L", + "AP_SPI_H1_MOSI", + "AP_SPI_H1_CLK", + "I2S5_BCK", + "I2S5_LRCK", + "I2S5_DO", + "BOOTBLOCK_EN_L", + "MT8183_KPCOL0", + "SPI_AP_EC_MISO", + "UART_DBG_TX_AP_RX", + "UART_AP_TX_DBG_RX", + "I2S2_MCK", + "I2S2_BCK", + "CLK_5M_WCAM", + "CLK_2M_UCAM", + "I2S2_LRCK", + "I2S2_DI", + "SOC_I2C2_1V8_SCL", + "SOC_I2C2_1V8_SDA", + "SOC_I2C4_1V8_SCL", + "SOC_I2C4_1V8_SDA", + "", + "SCL8", + "SDA8", + "FCAM_PWDN_L", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "I2S_PMIC", + "I2S_PMIC", + "I2S_PMIC", + "I2S_PMIC", + "I2S_PMIC", + "I2S_PMIC", + "I2S_PMIC", + "I2S_PMIC", + "", + "", + "", + "", + "", + "", + /* + * AP_FLASH_WP_L is crossystem ABI. Rev1 schematics + * call it BIOS_FLASH_WP_R_L. + */ + "AP_FLASH_WP_L", + "EC_AP_INT_ODL", + "IT6505_INT_ODL", + "H1_INT_OD_L", + "", + "", + "", + "", + "", + "", + "", + "AP_SPI_FLASH_MISO", + "AP_SPI_FLASH_CS_L", + "AP_SPI_FLASH_MOSI", + "AP_SPI_FLASH_CLK", + "DA7219_IRQ", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + ""; + + ppvarp_lcd_en: ppvarp-lcd-en { + pins1 { + pinmux = <PINMUX_GPIO66__FUNC_GPIO66>; + output-low; + }; + }; + + ppvarn_lcd_en: ppvarn-lcd-en { + pins1 { + pinmux = <PINMUX_GPIO166__FUNC_GPIO166>; + output-low; + }; + }; + + pp1800_lcd_en: pp1800-lcd-en { + pins1 { + pinmux = <PINMUX_GPIO36__FUNC_GPIO36>; + output-low; + }; + }; + + open_touch: open_touch { + irq_pin { + pinmux = <PINMUX_GPIO155__FUNC_GPIO155>; + input-enable; + bias-pull-up; + }; + + rst_pin { + pinmux = <PINMUX_GPIO156__FUNC_GPIO156>; + + /* + * The pen driver doesn't currently support driving + * this reset line. By specifying output-high here + * we're relying on the fact that this pin has a default + * pulldown at boot (which makes sure the pen was in + * reset if it was powered) and then we set it high here + * to take it out of reset. Better would be if the pen + * driver could control this and we could remove + * "output-high" here. + */ + output-high; + }; + }; +}; + +&qca_wifi { + qcom,ath10k-calibration-variant = "LE_Krane"; +}; + +&sound { + compatible = "mediatek,mt8183_mt6358_ts3a227_max98357"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi new file mode 100644 index 000000000..a428a581c --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -0,0 +1,1003 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2018 MediaTek Inc. + * Author: Ben Ho <ben.ho@mediatek.com> + * Erin Lo <erin.lo@mediatek.com> + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include "mt8183.dtsi" +#include "mt6358.dtsi" + +/ { + aliases { + serial0 = &uart0; + mmc0 = &mmc0; + mmc1 = &mmc1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + backlight_lcd0: backlight_lcd0 { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 500000>; + power-supply = <&bl_pp5000>; + enable-gpios = <&pio 176 0>; + brightness-levels = <0 1023>; + num-interpolated-steps = <1023>; + default-brightness-level = <576>; + status = "okay"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; + + clk32k: oscillator1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "clk32k"; + }; + + it6505_pp18_reg: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "it6505_pp18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&pio 178 0>; + enable-active-high; + }; + + lcd_pp3300: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "lcd_pp3300"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + bl_pp5000: regulator2 { + compatible = "regulator-fixed"; + regulator-name = "bl_pp5000"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + mmc1_fixed_power: regulator3 { + compatible = "regulator-fixed"; + regulator-name = "mmc1_power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + mmc1_fixed_io: regulator4 { + compatible = "regulator-fixed"; + regulator-name = "mmc1_io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pp1800_alw: regulator5 { + compatible = "regulator-fixed"; + regulator-name = "pp1800_alw"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pp3300_alw: regulator6 { + compatible = "regulator-fixed"; + regulator-name = "pp3300_alw"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scp_mem_reserved: memory@50000000 { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x2900000>; + no-map; + }; + }; + + sound: mt8183-sound { + mediatek,platform = <&afe>; + pinctrl-names = "default", + "aud_tdm_out_on", + "aud_tdm_out_off"; + pinctrl-0 = <&aud_pins_default>; + pinctrl-1 = <&aud_pins_tdm_out_on>; + pinctrl-2 = <&aud_pins_tdm_out_off>; + status = "okay"; + }; + + btsco: bt-sco { + compatible = "linux,bt-sco"; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_pins_pwrseq>; + + /* Toggle WIFI_ENABLE to reset the chip. */ + reset-gpios = <&pio 119 1>; + }; + + wifi_wakeup: wifi-wakeup { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_pins_wakeup>; + + button-wowlan { + label = "Wake on WiFi"; + gpios = <&pio 113 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_WAKEUP>; + wakeup-source; + }; + }; + + tboard_thermistor1: thermal-sensor1 { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&auxadc 0>; + io-channel-names = "sensor-channel"; + temperature-lookup-table = < (-5000) 1553 + 0 1488 + 5000 1412 + 10000 1326 + 15000 1232 + 20000 1132 + 25000 1029 + 30000 925 + 35000 823 + 40000 726 + 45000 635 + 50000 552 + 55000 478 + 60000 411 + 65000 353 + 70000 303 + 75000 260 + 80000 222 + 85000 190 + 90000 163 + 95000 140 + 100000 121 + 105000 104 + 110000 90 + 115000 78 + 120000 67 + 125000 59>; + }; + + tboard_thermistor2: thermal-sensor2 { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&auxadc 1>; + io-channel-names = "sensor-channel"; + temperature-lookup-table = < (-5000) 1553 + 0 1488 + 5000 1412 + 10000 1326 + 15000 1232 + 20000 1132 + 25000 1029 + 30000 925 + 35000 823 + 40000 726 + 45000 635 + 50000 552 + 55000 478 + 60000 411 + 65000 353 + 70000 303 + 75000 260 + 80000 222 + 85000 190 + 90000 163 + 95000 140 + 100000 121 + 105000 104 + 110000 90 + 115000 78 + 120000 67 + 125000 59>; + }; +}; + +&afe { + i2s3-share = "I2S2"; + i2s0-share = "I2S5"; +}; + +&auxadc { + status = "okay"; +}; + +&cci { + proc-supply = <&mt6358_vproc12_reg>; +}; + +&cpu0 { + proc-supply = <&mt6358_vproc12_reg>; +}; + +&cpu1 { + proc-supply = <&mt6358_vproc12_reg>; +}; + +&cpu2 { + proc-supply = <&mt6358_vproc12_reg>; +}; + +&cpu3 { + proc-supply = <&mt6358_vproc12_reg>; +}; + +&cpu4 { + proc-supply = <&mt6358_vproc11_reg>; +}; + +&cpu5 { + proc-supply = <&mt6358_vproc11_reg>; +}; + +&cpu6 { + proc-supply = <&mt6358_vproc11_reg>; +}; + +&cpu7 { + proc-supply = <&mt6358_vproc11_reg>; +}; + +&dsi0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + panel: panel@0 { + /* compatible will be set in board dts */ + reg = <0>; + enable-gpios = <&pio 45 0>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_pins_default>; + avdd-supply = <&ppvarn_lcd>; + avee-supply = <&ppvarp_lcd>; + pp1800-supply = <&pp1800_lcd>; + backlight = <&backlight_lcd0>; + rotation = <270>; + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; + + ports { + port { + dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&gic { + mediatek,broken-save-restore-fw; +}; + +&gpu { + mali-supply = <&mt6358_vgpu_reg>; + sram-supply = <&mt6358_vsram_gpu_reg>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "okay"; + clock-frequency = <100000>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + status = "okay"; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; +}; + +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins>; + status = "okay"; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pins>; + status = "okay"; + clock-frequency = <100000>; +}; + +&mipi_tx0 { + status = "okay"; +}; + +&mmc0 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cap-mmc-hw-reset; + no-sdio; + no-sd; + hs400-ds-delay = <0x12814>; + vmmc-supply = <&mt6358_vemc_reg>; + vqmmc-supply = <&mt6358_vio18_reg>; + assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>; + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>; + non-removable; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_uhs>; + vmmc-supply = <&mmc1_fixed_power>; + vqmmc-supply = <&mmc1_fixed_io>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + max-frequency = <200000000>; + drv-type = <2>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + keep-power-in-suspend; + wakeup-source; + cap-sdio-irq; + non-removable; + no-mmc; + no-sd; + assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>; + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; + #address-cells = <1>; + #size-cells = <0>; + + qca_wifi: qca-wifi@1 { + compatible = "qcom,ath10k"; + reg = <1>; + }; +}; + +&mt6358_vdram2_reg { + regulator-always-on; +}; + +&mt6358codec { + Avdd-supply = <&mt6358_vaud28_reg>; +}; + +&mt6358_vsim1_reg { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; +}; + +&mt6358_vsim2_reg { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; +}; + +&pio { + aud_pins_default: audiopins { + pins-bus { + pinmux = <PINMUX_GPIO97__FUNC_I2S2_MCK>, + <PINMUX_GPIO98__FUNC_I2S2_BCK>, + <PINMUX_GPIO101__FUNC_I2S2_LRCK>, + <PINMUX_GPIO102__FUNC_I2S2_DI>, + <PINMUX_GPIO3__FUNC_I2S3_DO>, /*i2s to da7219/max98357*/ + <PINMUX_GPIO89__FUNC_I2S5_BCK>, + <PINMUX_GPIO90__FUNC_I2S5_LRCK>, + <PINMUX_GPIO91__FUNC_I2S5_DO>, + <PINMUX_GPIO174__FUNC_I2S0_DI>, /*i2s to wifi/bt*/ + <PINMUX_GPIO136__FUNC_AUD_CLK_MOSI>, + <PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI>, + <PINMUX_GPIO138__FUNC_AUD_DAT_MOSI0>, + <PINMUX_GPIO139__FUNC_AUD_DAT_MOSI1>, + <PINMUX_GPIO140__FUNC_AUD_CLK_MISO>, + <PINMUX_GPIO141__FUNC_AUD_SYNC_MISO>, + <PINMUX_GPIO142__FUNC_AUD_DAT_MISO0>, + <PINMUX_GPIO143__FUNC_AUD_DAT_MISO1>; /*mtkaif3.0*/ + }; + }; + + aud_pins_tdm_out_on: audiotdmouton { + pins-bus { + pinmux = <PINMUX_GPIO169__FUNC_TDM_BCK_2ND>, + <PINMUX_GPIO170__FUNC_TDM_LRCK_2ND>, + <PINMUX_GPIO171__FUNC_TDM_DATA0_2ND>, + <PINMUX_GPIO172__FUNC_TDM_DATA1_2ND>, + <PINMUX_GPIO173__FUNC_TDM_DATA2_2ND>, + <PINMUX_GPIO10__FUNC_TDM_DATA3>; /*8ch-i2s to it6505*/ + drive-strength = <MTK_DRIVE_6mA>; + }; + }; + + aud_pins_tdm_out_off: audiotdmoutoff { + pins-bus { + pinmux = <PINMUX_GPIO169__FUNC_GPIO169>, + <PINMUX_GPIO170__FUNC_GPIO170>, + <PINMUX_GPIO171__FUNC_GPIO171>, + <PINMUX_GPIO172__FUNC_GPIO172>, + <PINMUX_GPIO173__FUNC_GPIO173>, + <PINMUX_GPIO10__FUNC_GPIO10>; + input-enable; + bias-pull-down; + drive-strength = <MTK_DRIVE_2mA>; + }; + }; + + bt_pins: bt-pins { + pins-bt-en { + pinmux = <PINMUX_GPIO120__FUNC_GPIO120>; + output-low; + }; + }; + + ec_ap_int_odl: ec-ap-int-odl { + pins1 { + pinmux = <PINMUX_GPIO151__FUNC_GPIO151>; + input-enable; + bias-pull-up; + }; + }; + + h1_int_od_l: h1-int-od-l { + pins1 { + pinmux = <PINMUX_GPIO153__FUNC_GPIO153>; + input-enable; + }; + }; + + i2c0_pins: i2c0 { + pins-bus { + pinmux = <PINMUX_GPIO82__FUNC_SDA0>, + <PINMUX_GPIO83__FUNC_SCL0>; + mediatek,pull-up-adv = <3>; + mediatek,drive-strength-adv = <00>; + }; + }; + + i2c1_pins: i2c1 { + pins-bus { + pinmux = <PINMUX_GPIO81__FUNC_SDA1>, + <PINMUX_GPIO84__FUNC_SCL1>; + mediatek,pull-up-adv = <3>; + mediatek,drive-strength-adv = <00>; + }; + }; + + i2c2_pins: i2c2 { + pins-bus { + pinmux = <PINMUX_GPIO103__FUNC_SCL2>, + <PINMUX_GPIO104__FUNC_SDA2>; + bias-disable; + mediatek,drive-strength-adv = <00>; + }; + }; + + i2c3_pins: i2c3 { + pins-bus { + pinmux = <PINMUX_GPIO50__FUNC_SCL3>, + <PINMUX_GPIO51__FUNC_SDA3>; + mediatek,pull-up-adv = <3>; + mediatek,drive-strength-adv = <00>; + }; + }; + + i2c4_pins: i2c4 { + pins-bus { + pinmux = <PINMUX_GPIO105__FUNC_SCL4>, + <PINMUX_GPIO106__FUNC_SDA4>; + bias-disable; + mediatek,drive-strength-adv = <00>; + }; + }; + + i2c5_pins: i2c5 { + pins-bus { + pinmux = <PINMUX_GPIO48__FUNC_SCL5>, + <PINMUX_GPIO49__FUNC_SDA5>; + mediatek,pull-up-adv = <3>; + mediatek,drive-strength-adv = <00>; + }; + }; + + i2c6_pins: i2c6 { + pins-bus { + pinmux = <PINMUX_GPIO11__FUNC_SCL6>, + <PINMUX_GPIO12__FUNC_SDA6>; + bias-disable; + }; + }; + + mmc0_pins_default: mmc0-pins-default { + pins-cmd-dat { + pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, + <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, + <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, + <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, + <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, + <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, + <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, + <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, + <PINMUX_GPIO122__FUNC_MSDC0_CMD>; + input-enable; + drive-strength = <MTK_DRIVE_14mA>; + mediatek,pull-up-adv = <01>; + }; + + pins-clk { + pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; + drive-strength = <MTK_DRIVE_14mA>; + mediatek,pull-down-adv = <10>; + }; + + pins-rst { + pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; + drive-strength = <MTK_DRIVE_14mA>; + mediatek,pull-down-adv = <01>; + }; + }; + + mmc0_pins_uhs: mmc0-pins-uhs { + pins-cmd-dat { + pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, + <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, + <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, + <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, + <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, + <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, + <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, + <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, + <PINMUX_GPIO122__FUNC_MSDC0_CMD>; + input-enable; + drive-strength = <MTK_DRIVE_14mA>; + mediatek,pull-up-adv = <01>; + }; + + pins-clk { + pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; + drive-strength = <MTK_DRIVE_14mA>; + mediatek,pull-down-adv = <10>; + }; + + pins-ds { + pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>; + drive-strength = <MTK_DRIVE_14mA>; + mediatek,pull-down-adv = <10>; + }; + + pins-rst { + pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; + drive-strength = <MTK_DRIVE_14mA>; + mediatek,pull-up-adv = <01>; + }; + }; + + mmc1_pins_default: mmc1-pins-default { + pins-cmd-dat { + pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, + <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, + <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, + <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, + <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; + input-enable; + mediatek,pull-up-adv = <10>; + }; + + pins-clk { + pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; + input-enable; + mediatek,pull-down-adv = <10>; + }; + }; + + mmc1_pins_uhs: mmc1-pins-uhs { + pins-cmd-dat { + pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, + <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, + <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, + <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, + <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; + drive-strength = <MTK_DRIVE_6mA>; + input-enable; + mediatek,pull-up-adv = <10>; + }; + + pins-clk { + pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; + drive-strength = <MTK_DRIVE_8mA>; + mediatek,pull-down-adv = <10>; + input-enable; + }; + }; + + panel_pins_default: panel-pins-default { + panel-reset { + pinmux = <PINMUX_GPIO45__FUNC_GPIO45>; + output-low; + bias-pull-up; + }; + }; + + pwm0_pin_default: pwm0-pin-default { + pins1 { + pinmux = <PINMUX_GPIO176__FUNC_GPIO176>; + output-high; + bias-pull-up; + }; + pins2 { + pinmux = <PINMUX_GPIO43__FUNC_DISP_PWM>; + }; + }; + + scp_pins: scp { + pins-scp-uart { + pinmux = <PINMUX_GPIO110__FUNC_TP_URXD1_AO>, + <PINMUX_GPIO112__FUNC_TP_UTXD1_AO>; + }; + }; + + spi0_pins: spi0 { + pins-spi { + pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>, + <PINMUX_GPIO86__FUNC_GPIO86>, + <PINMUX_GPIO87__FUNC_SPI0_MO>, + <PINMUX_GPIO88__FUNC_SPI0_CLK>; + bias-disable; + }; + }; + + spi1_pins: spi1 { + pins-spi { + pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>, + <PINMUX_GPIO162__FUNC_SPI1_A_CSB>, + <PINMUX_GPIO163__FUNC_SPI1_A_MO>, + <PINMUX_GPIO164__FUNC_SPI1_A_CLK>; + bias-disable; + }; + }; + + spi2_pins: spi2 { + pins-spi { + pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>, + <PINMUX_GPIO1__FUNC_SPI2_MO>, + <PINMUX_GPIO2__FUNC_SPI2_CLK>; + bias-disable; + }; + pins-spi-mi { + pinmux = <PINMUX_GPIO94__FUNC_SPI2_MI>; + mediatek,pull-down-adv = <00>; + }; + }; + + spi3_pins: spi3 { + pins-spi { + pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>, + <PINMUX_GPIO22__FUNC_SPI3_CSB>, + <PINMUX_GPIO23__FUNC_SPI3_MO>, + <PINMUX_GPIO24__FUNC_SPI3_CLK>; + bias-disable; + }; + }; + + spi4_pins: spi4 { + pins-spi { + pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>, + <PINMUX_GPIO18__FUNC_SPI4_CSB>, + <PINMUX_GPIO19__FUNC_SPI4_MO>, + <PINMUX_GPIO20__FUNC_SPI4_CLK>; + bias-disable; + }; + }; + + spi5_pins: spi5 { + pins-spi { + pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>, + <PINMUX_GPIO14__FUNC_SPI5_CSB>, + <PINMUX_GPIO15__FUNC_SPI5_MO>, + <PINMUX_GPIO16__FUNC_SPI5_CLK>; + bias-disable; + }; + }; + + uart0_pins_default: uart0-pins-default { + pins-rx { + pinmux = <PINMUX_GPIO95__FUNC_URXD0>; + input-enable; + bias-pull-up; + }; + pins-tx { + pinmux = <PINMUX_GPIO96__FUNC_UTXD0>; + }; + }; + + uart1_pins_default: uart1-pins-default { + pins-rx { + pinmux = <PINMUX_GPIO121__FUNC_URXD1>; + input-enable; + bias-pull-up; + }; + pins-tx { + pinmux = <PINMUX_GPIO115__FUNC_UTXD1>; + }; + pins-rts { + pinmux = <PINMUX_GPIO47__FUNC_URTS1>; + output-enable; + }; + pins-cts { + pinmux = <PINMUX_GPIO46__FUNC_UCTS1>; + input-enable; + }; + }; + + uart1_pins_sleep: uart1-pins-sleep { + pins-rx { + pinmux = <PINMUX_GPIO121__FUNC_GPIO121>; + input-enable; + bias-pull-up; + }; + pins-tx { + pinmux = <PINMUX_GPIO115__FUNC_UTXD1>; + }; + pins-rts { + pinmux = <PINMUX_GPIO47__FUNC_URTS1>; + output-enable; + }; + pins-cts { + pinmux = <PINMUX_GPIO46__FUNC_UCTS1>; + input-enable; + }; + }; + + wifi_pins_pwrseq: wifi-pins-pwrseq { + pins-wifi-enable { + pinmux = <PINMUX_GPIO119__FUNC_GPIO119>; + output-low; + }; + }; + + wifi_pins_wakeup: wifi-pins-wakeup { + pins-wifi-wakeup { + pinmux = <PINMUX_GPIO113__FUNC_GPIO113>; + input-enable; + }; + }; +}; + +&pwm0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin_default>; +}; + +&scp { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&scp_pins>; + + cros_ec { + compatible = "google,cros-ec-rpmsg"; + mediatek,rpmsg-name = "cros-ec-rpmsg"; + }; +}; + +&mfg_async { + domain-supply = <&mt6358_vsram_gpu_reg>; +}; + +&mfg { + domain-supply = <&mt6358_vgpu_reg>; +}; + +&soc_data { + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + mediatek,pad-select = <0>; + status = "okay"; + cs-gpios = <&pio 86 GPIO_ACTIVE_LOW>; + + cr50@0 { + compatible = "google,cr50"; + reg = <0>; + spi-max-frequency = <1000000>; + pinctrl-names = "default"; + pinctrl-0 = <&h1_int_od_l>; + interrupt-parent = <&pio>; + interrupts = <153 IRQ_TYPE_EDGE_RISING>; + }; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + mediatek,pad-select = <0>; + status = "okay"; + + w25q64dw: flash@0 { + compatible = "winbond,w25q64dw", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + }; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins>; + mediatek,pad-select = <0>; + status = "okay"; + + cros_ec: cros-ec@0 { + compatible = "google,cros-ec-spi"; + reg = <0>; + spi-max-frequency = <3000000>; + interrupt-parent = <&pio>; + interrupts = <151 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ec_ap_int_odl>; + + i2c_tunnel: i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + google,remote-bus = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + usbc_extcon: extcon0 { + compatible = "google,extcon-usbc-cros-ec"; + google,usb-port-id = <0>; + }; + + cbas { + compatible = "google,cros-cbas"; + }; + + typec { + compatible = "google,cros-ec-typec"; + #address-cells = <1>; + #size-cells = <0>; + + usb_c0: connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "host"; + try-power-role = "sink"; + }; + }; + }; +}; + +&spi3 { + pinctrl-names = "default"; + pinctrl-0 = <&spi3_pins>; + mediatek,pad-select = <0>; + status = "disabled"; +}; + +&spi4 { + pinctrl-names = "default"; + pinctrl-0 = <&spi4_pins>; + mediatek,pad-select = <0>; + status = "disabled"; +}; + +&spi5 { + pinctrl-names = "default"; + pinctrl-0 = <&spi5_pins>; + mediatek,pad-select = <0>; + status = "disabled"; +}; + +&ssusb { + dr_mode = "host"; + wakeup-source; + vusb33-supply = <&mt6358_vusb_reg>; + status = "okay"; +}; + +&thermal_zones { + tboard1 { + polling-delay = <1000>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&tboard_thermistor1>; + }; + + tboard2 { + polling-delay = <1000>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&tboard_thermistor2>; + }; +}; + +&u3phy { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_default>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart1_pins_default>; + pinctrl-1 = <&uart1_pins_sleep>; + status = "okay"; + interrupts-extended = <&sysirq GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>, + <&pio 121 IRQ_TYPE_EDGE_FALLING>; + + bluetooth: bluetooth { + pinctrl-names = "default"; + pinctrl-0 = <&bt_pins>; + status = "okay"; + compatible = "qcom,qca6174-bt"; + enable-gpios = <&pio 120 0>; + clocks = <&clk32k>; + firmware-name = "nvm_00440302_i2s.bin"; + }; +}; + +&usb_host { + #address-cells = <1>; + #size-cells = <0>; + vusb33-supply = <&mt6358_vusb_reg>; + status = "okay"; + + hub@1 { + compatible = "usb5e3,610"; + reg = <1>; + }; +}; + +#include <arm/cros-ec-keyboard.dtsi> +#include <arm/cros-ec-sbs.dtsi> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts new file mode 100644 index 000000000..dd8d39861 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts @@ -0,0 +1,404 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 BayLibre, SAS. + * Author: Fabien Parent <fparent@baylibre.com> + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include "mt8183.dtsi" +#include "mt6358.dtsi" + +/ { + model = "Pumpkin MT8183"; + compatible = "mediatek,mt8183-pumpkin", "mediatek,mt8183"; + + aliases { + serial0 = &uart0; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scp_mem_reserved: scp_mem_region@50000000 { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x2900000>; + no-map; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-red { + label = "red"; + gpios = <&pio 155 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-green { + label = "green"; + gpios = <&pio 156 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + thermistor { + compatible = "murata,ncp03wf104"; + pullup-uv = <1800000>; + pullup-ohm = <390000>; + pulldown-ohm = <0>; + io-channels = <&auxadc 0>; + }; +}; + +&auxadc { + status = "okay"; +}; + +&gpu { + mali-supply = <&mt6358_vgpu_reg>; + sram-supply = <&mt6358_vsram_gpu_reg>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins_0>; + status = "okay"; + clock-frequency = <100000>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins_1>; + status = "okay"; + clock-frequency = <100000>; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins_2>; + status = "okay"; + clock-frequency = <100000>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins_3>; + status = "okay"; + clock-frequency = <100000>; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins_4>; + status = "okay"; + clock-frequency = <100000>; +}; + +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins_5>; + status = "okay"; + clock-frequency = <100000>; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pins>; + status = "okay"; + clock-frequency = <100000>; +}; + +&keyboard { + pinctrl-names = "default"; + pinctrl-0 = <&keyboard_pins>; + status = "okay"; + linux,keymap = <MATRIX_KEY(0x00, 0x00, KEY_VOLUMEDOWN) + MATRIX_KEY(0x01, 0x00, KEY_VOLUMEUP)>; + keypad,num-rows = <2>; + keypad,num-columns = <1>; + debounce-delay-ms = <32>; + mediatek,keys-per-group = <2>; +}; + +&mmc0 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cap-mmc-hw-reset; + no-sdio; + no-sd; + hs400-ds-delay = <0x12814>; + vmmc-supply = <&mt6358_vemc_reg>; + vqmmc-supply = <&mt6358_vio18_reg>; + assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>; + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>; + non-removable; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_uhs>; + bus-width = <4>; + max-frequency = <200000000>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + cap-sdio-irq; + no-mmc; + no-sd; + vmmc-supply = <&mt6358_vmch_reg>; + vqmmc-supply = <&mt6358_vmc_reg>; + keep-power-in-suspend; + wakeup-source; + non-removable; +}; + +&pio { + i2c_pins_0: i2c0 { + pins_i2c { + pinmux = <PINMUX_GPIO82__FUNC_SDA0>, + <PINMUX_GPIO83__FUNC_SCL0>; + mediatek,pull-up-adv = <3>; + mediatek,drive-strength-adv = <00>; + }; + }; + + i2c_pins_1: i2c1 { + pins_i2c { + pinmux = <PINMUX_GPIO81__FUNC_SDA1>, + <PINMUX_GPIO84__FUNC_SCL1>; + mediatek,pull-up-adv = <3>; + mediatek,drive-strength-adv = <00>; + }; + }; + + i2c_pins_2: i2c2 { + pins_i2c { + pinmux = <PINMUX_GPIO103__FUNC_SCL2>, + <PINMUX_GPIO104__FUNC_SDA2>; + mediatek,pull-up-adv = <3>; + mediatek,drive-strength-adv = <00>; + }; + }; + + i2c_pins_3: i2c3 { + pins_i2c { + pinmux = <PINMUX_GPIO50__FUNC_SCL3>, + <PINMUX_GPIO51__FUNC_SDA3>; + mediatek,pull-up-adv = <3>; + mediatek,drive-strength-adv = <00>; + }; + }; + + i2c_pins_4: i2c4 { + pins_i2c { + pinmux = <PINMUX_GPIO105__FUNC_SCL4>, + <PINMUX_GPIO106__FUNC_SDA4>; + mediatek,pull-up-adv = <3>; + mediatek,drive-strength-adv = <00>; + }; + }; + + i2c_pins_5: i2c5 { + pins_i2c { + pinmux = <PINMUX_GPIO48__FUNC_SCL5>, + <PINMUX_GPIO49__FUNC_SDA5>; + mediatek,pull-up-adv = <3>; + mediatek,drive-strength-adv = <00>; + }; + }; + + i2c6_pins: i2c6 { + pins_cmd_dat { + pinmux = <PINMUX_GPIO113__FUNC_SCL6>, + <PINMUX_GPIO114__FUNC_SDA6>; + mediatek,pull-up-adv = <3>; + }; + }; + + keyboard_pins: keyboard { + pins_keyboard { + pinmux = <PINMUX_GPIO91__FUNC_KPROW1>, + <PINMUX_GPIO92__FUNC_KPROW0>, + <PINMUX_GPIO93__FUNC_KPCOL0>; + }; + }; + + mmc0_pins_default: mmc0-pins-default { + pins_cmd_dat { + pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, + <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, + <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, + <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, + <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, + <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, + <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, + <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, + <PINMUX_GPIO122__FUNC_MSDC0_CMD>; + input-enable; + drive-strength = <MTK_DRIVE_14mA>; + mediatek,pull-up-adv = <01>; + }; + + pins_clk { + pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; + drive-strength = <MTK_DRIVE_14mA>; + mediatek,pull-down-adv = <10>; + }; + + pins_rst { + pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; + drive-strength = <MTK_DRIVE_14mA>; + mediatek,pull-down-adv = <01>; + }; + }; + + mmc0_pins_uhs: mmc0-pins-uhs { + pins_cmd_dat { + pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, + <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, + <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, + <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, + <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, + <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, + <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, + <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, + <PINMUX_GPIO122__FUNC_MSDC0_CMD>; + input-enable; + drive-strength = <MTK_DRIVE_14mA>; + mediatek,pull-up-adv = <01>; + }; + + pins_clk { + pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; + drive-strength = <MTK_DRIVE_14mA>; + mediatek,pull-down-adv = <10>; + }; + + pins_ds { + pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>; + drive-strength = <MTK_DRIVE_14mA>; + mediatek,pull-down-adv = <10>; + }; + + pins_rst { + pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; + drive-strength = <MTK_DRIVE_14mA>; + mediatek,pull-up-adv = <01>; + }; + }; + + mmc1_pins_default: mmc1-pins-default { + pins_cmd_dat { + pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, + <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, + <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, + <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, + <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; + input-enable; + mediatek,pull-up-adv = <10>; + }; + + pins_clk { + pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; + input-enable; + mediatek,pull-down-adv = <10>; + }; + + pins_pmu { + pinmux = <PINMUX_GPIO178__FUNC_GPIO178>; + output-high; + }; + }; + + mmc1_pins_uhs: mmc1-pins-uhs { + pins_cmd_dat { + pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, + <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, + <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, + <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, + <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; + drive-strength = <MTK_DRIVE_6mA>; + input-enable; + mediatek,pull-up-adv = <10>; + }; + + pins_clk { + pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; + drive-strength = <MTK_DRIVE_8mA>; + mediatek,pull-down-adv = <10>; + input-enable; + }; + }; +}; + +&mfg { + domain-supply = <&mt6358_vgpu_reg>; +}; + +&cpu0 { + proc-supply = <&mt6358_vproc12_reg>; +}; + +&cpu1 { + proc-supply = <&mt6358_vproc12_reg>; +}; + +&cpu2 { + proc-supply = <&mt6358_vproc12_reg>; +}; + +&cpu3 { + proc-supply = <&mt6358_vproc12_reg>; +}; + +&cpu4 { + proc-supply = <&mt6358_vproc11_reg>; +}; + +&cpu5 { + proc-supply = <&mt6358_vproc11_reg>; +}; + +&cpu6 { + proc-supply = <&mt6358_vproc11_reg>; +}; + +&cpu7 { + proc-supply = <&mt6358_vproc11_reg>; +}; + +&uart0 { + status = "okay"; +}; + +&scp { + status = "okay"; +}; + +&dsi0 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi new file mode 100644 index 000000000..d5d9b954c --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -0,0 +1,2036 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2018 MediaTek Inc. + * Author: Ben Ho <ben.ho@mediatek.com> + * Erin Lo <erin.lo@mediatek.com> + */ + +#include <dt-bindings/clock/mt8183-clk.h> +#include <dt-bindings/gce/mt8183-gce.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/memory/mt8183-larb-port.h> +#include <dt-bindings/power/mt8183-power.h> +#include <dt-bindings/reset/mt8183-resets.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/pinctrl/mt8183-pinfunc.h> + +/ { + compatible = "mediatek,mt8183"; + interrupt-parent = <&sysirq>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + ovl0 = &ovl0; + ovl-2l0 = &ovl_2l0; + ovl-2l1 = &ovl_2l1; + rdma0 = &rdma0; + rdma1 = &rdma1; + }; + + cluster0_opp: opp-table-cluster0 { + compatible = "operating-points-v2"; + opp-shared; + opp0-793000000 { + opp-hz = /bits/ 64 <793000000>; + opp-microvolt = <650000>; + required-opps = <&opp2_00>; + }; + opp0-910000000 { + opp-hz = /bits/ 64 <910000000>; + opp-microvolt = <687500>; + required-opps = <&opp2_01>; + }; + opp0-1014000000 { + opp-hz = /bits/ 64 <1014000000>; + opp-microvolt = <718750>; + required-opps = <&opp2_02>; + }; + opp0-1131000000 { + opp-hz = /bits/ 64 <1131000000>; + opp-microvolt = <756250>; + required-opps = <&opp2_03>; + }; + opp0-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-microvolt = <800000>; + required-opps = <&opp2_04>; + }; + opp0-1326000000 { + opp-hz = /bits/ 64 <1326000000>; + opp-microvolt = <818750>; + required-opps = <&opp2_05>; + }; + opp0-1417000000 { + opp-hz = /bits/ 64 <1417000000>; + opp-microvolt = <850000>; + required-opps = <&opp2_06>; + }; + opp0-1508000000 { + opp-hz = /bits/ 64 <1508000000>; + opp-microvolt = <868750>; + required-opps = <&opp2_07>; + }; + opp0-1586000000 { + opp-hz = /bits/ 64 <1586000000>; + opp-microvolt = <893750>; + required-opps = <&opp2_08>; + }; + opp0-1625000000 { + opp-hz = /bits/ 64 <1625000000>; + opp-microvolt = <906250>; + required-opps = <&opp2_09>; + }; + opp0-1677000000 { + opp-hz = /bits/ 64 <1677000000>; + opp-microvolt = <931250>; + required-opps = <&opp2_10>; + }; + opp0-1716000000 { + opp-hz = /bits/ 64 <1716000000>; + opp-microvolt = <943750>; + required-opps = <&opp2_11>; + }; + opp0-1781000000 { + opp-hz = /bits/ 64 <1781000000>; + opp-microvolt = <975000>; + required-opps = <&opp2_12>; + }; + opp0-1846000000 { + opp-hz = /bits/ 64 <1846000000>; + opp-microvolt = <1000000>; + required-opps = <&opp2_13>; + }; + opp0-1924000000 { + opp-hz = /bits/ 64 <1924000000>; + opp-microvolt = <1025000>; + required-opps = <&opp2_14>; + }; + opp0-1989000000 { + opp-hz = /bits/ 64 <1989000000>; + opp-microvolt = <1050000>; + required-opps = <&opp2_15>; + }; }; + + cluster1_opp: opp-table-cluster1 { + compatible = "operating-points-v2"; + opp-shared; + opp1-793000000 { + opp-hz = /bits/ 64 <793000000>; + opp-microvolt = <700000>; + required-opps = <&opp2_00>; + }; + opp1-910000000 { + opp-hz = /bits/ 64 <910000000>; + opp-microvolt = <725000>; + required-opps = <&opp2_01>; + }; + opp1-1014000000 { + opp-hz = /bits/ 64 <1014000000>; + opp-microvolt = <750000>; + required-opps = <&opp2_02>; + }; + opp1-1131000000 { + opp-hz = /bits/ 64 <1131000000>; + opp-microvolt = <775000>; + required-opps = <&opp2_03>; + }; + opp1-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-microvolt = <800000>; + required-opps = <&opp2_04>; + }; + opp1-1326000000 { + opp-hz = /bits/ 64 <1326000000>; + opp-microvolt = <825000>; + required-opps = <&opp2_05>; + }; + opp1-1417000000 { + opp-hz = /bits/ 64 <1417000000>; + opp-microvolt = <850000>; + required-opps = <&opp2_06>; + }; + opp1-1508000000 { + opp-hz = /bits/ 64 <1508000000>; + opp-microvolt = <875000>; + required-opps = <&opp2_07>; + }; + opp1-1586000000 { + opp-hz = /bits/ 64 <1586000000>; + opp-microvolt = <900000>; + required-opps = <&opp2_08>; + }; + opp1-1625000000 { + opp-hz = /bits/ 64 <1625000000>; + opp-microvolt = <912500>; + required-opps = <&opp2_09>; + }; + opp1-1677000000 { + opp-hz = /bits/ 64 <1677000000>; + opp-microvolt = <931250>; + required-opps = <&opp2_10>; + }; + opp1-1716000000 { + opp-hz = /bits/ 64 <1716000000>; + opp-microvolt = <950000>; + required-opps = <&opp2_11>; + }; + opp1-1781000000 { + opp-hz = /bits/ 64 <1781000000>; + opp-microvolt = <975000>; + required-opps = <&opp2_12>; + }; + opp1-1846000000 { + opp-hz = /bits/ 64 <1846000000>; + opp-microvolt = <1000000>; + required-opps = <&opp2_13>; + }; + opp1-1924000000 { + opp-hz = /bits/ 64 <1924000000>; + opp-microvolt = <1025000>; + required-opps = <&opp2_14>; + }; + opp1-1989000000 { + opp-hz = /bits/ 64 <1989000000>; + opp-microvolt = <1050000>; + required-opps = <&opp2_15>; + }; + }; + + cci_opp: opp-table-cci { + compatible = "operating-points-v2"; + opp-shared; + opp2_00: opp-273000000 { + opp-hz = /bits/ 64 <273000000>; + opp-microvolt = <650000>; + }; + opp2_01: opp-338000000 { + opp-hz = /bits/ 64 <338000000>; + opp-microvolt = <687500>; + }; + opp2_02: opp-403000000 { + opp-hz = /bits/ 64 <403000000>; + opp-microvolt = <718750>; + }; + opp2_03: opp-463000000 { + opp-hz = /bits/ 64 <463000000>; + opp-microvolt = <756250>; + }; + opp2_04: opp-546000000 { + opp-hz = /bits/ 64 <546000000>; + opp-microvolt = <800000>; + }; + opp2_05: opp-624000000 { + opp-hz = /bits/ 64 <624000000>; + opp-microvolt = <818750>; + }; + opp2_06: opp-689000000 { + opp-hz = /bits/ 64 <689000000>; + opp-microvolt = <850000>; + }; + opp2_07: opp-767000000 { + opp-hz = /bits/ 64 <767000000>; + opp-microvolt = <868750>; + }; + opp2_08: opp-845000000 { + opp-hz = /bits/ 64 <845000000>; + opp-microvolt = <893750>; + }; + opp2_09: opp-871000000 { + opp-hz = /bits/ 64 <871000000>; + opp-microvolt = <906250>; + }; + opp2_10: opp-923000000 { + opp-hz = /bits/ 64 <923000000>; + opp-microvolt = <931250>; + }; + opp2_11: opp-962000000 { + opp-hz = /bits/ 64 <962000000>; + opp-microvolt = <943750>; + }; + opp2_12: opp-1027000000 { + opp-hz = /bits/ 64 <1027000000>; + opp-microvolt = <975000>; + }; + opp2_13: opp-1092000000 { + opp-hz = /bits/ 64 <1092000000>; + opp-microvolt = <1000000>; + }; + opp2_14: opp-1144000000 { + opp-hz = /bits/ 64 <1144000000>; + opp-microvolt = <1025000>; + }; + opp2_15: opp-1196000000 { + opp-hz = /bits/ 64 <1196000000>; + opp-microvolt = <1050000>; + }; + }; + + cci: cci { + compatible = "mediatek,mt8183-cci"; + clocks = <&mcucfg CLK_MCU_BUS_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cci", "intermediate"; + operating-points-v2 = <&cci_opp>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x000>; + enable-method = "psci"; + capacity-dmips-mhz = <741>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; + clocks = <&mcucfg CLK_MCU_MP0_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + dynamic-power-coefficient = <84>; + #cooling-cells = <2>; + mediatek,cci = <&cci>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x001>; + enable-method = "psci"; + capacity-dmips-mhz = <741>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; + clocks = <&mcucfg CLK_MCU_MP0_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + dynamic-power-coefficient = <84>; + #cooling-cells = <2>; + mediatek,cci = <&cci>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x002>; + enable-method = "psci"; + capacity-dmips-mhz = <741>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; + clocks = <&mcucfg CLK_MCU_MP0_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + dynamic-power-coefficient = <84>; + #cooling-cells = <2>; + mediatek,cci = <&cci>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x003>; + enable-method = "psci"; + capacity-dmips-mhz = <741>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; + clocks = <&mcucfg CLK_MCU_MP0_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + dynamic-power-coefficient = <84>; + #cooling-cells = <2>; + mediatek,cci = <&cci>; + }; + + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; + clocks = <&mcucfg CLK_MCU_MP2_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster1_opp>; + dynamic-power-coefficient = <211>; + #cooling-cells = <2>; + mediatek,cci = <&cci>; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x101>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; + clocks = <&mcucfg CLK_MCU_MP2_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster1_opp>; + dynamic-power-coefficient = <211>; + #cooling-cells = <2>; + mediatek,cci = <&cci>; + }; + + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x102>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; + clocks = <&mcucfg CLK_MCU_MP2_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster1_opp>; + dynamic-power-coefficient = <211>; + #cooling-cells = <2>; + mediatek,cci = <&cci>; + }; + + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x103>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; + clocks = <&mcucfg CLK_MCU_MP2_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster1_opp>; + dynamic-power-coefficient = <211>; + #cooling-cells = <2>; + mediatek,cci = <&cci>; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x00010001>; + entry-latency-us = <200>; + exit-latency-us = <200>; + min-residency-us = <800>; + }; + + CLUSTER_SLEEP0: cluster-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x01010001>; + entry-latency-us = <250>; + exit-latency-us = <400>; + min-residency-us = <1000>; + }; + CLUSTER_SLEEP1: cluster-sleep-1 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x01010001>; + entry-latency-us = <250>; + exit-latency-us = <400>; + min-residency-us = <1300>; + }; + }; + }; + + gpu_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <625000>, <850000>; + }; + + opp-320000000 { + opp-hz = /bits/ 64 <320000000>; + opp-microvolt = <631250>, <850000>; + }; + + opp-340000000 { + opp-hz = /bits/ 64 <340000000>; + opp-microvolt = <637500>, <850000>; + }; + + opp-360000000 { + opp-hz = /bits/ 64 <360000000>; + opp-microvolt = <643750>, <850000>; + }; + + opp-380000000 { + opp-hz = /bits/ 64 <380000000>; + opp-microvolt = <650000>, <850000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <656250>, <850000>; + }; + + opp-420000000 { + opp-hz = /bits/ 64 <420000000>; + opp-microvolt = <662500>, <850000>; + }; + + opp-460000000 { + opp-hz = /bits/ 64 <460000000>; + opp-microvolt = <675000>, <850000>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <687500>, <850000>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + opp-microvolt = <700000>, <850000>; + }; + + opp-580000000 { + opp-hz = /bits/ 64 <580000000>; + opp-microvolt = <712500>, <850000>; + }; + + opp-620000000 { + opp-hz = /bits/ 64 <620000000>; + opp-microvolt = <725000>, <850000>; + }; + + opp-653000000 { + opp-hz = /bits/ 64 <653000000>; + opp-microvolt = <743750>, <850000>; + }; + + opp-698000000 { + opp-hz = /bits/ 64 <698000000>; + opp-microvolt = <768750>, <868750>; + }; + + opp-743000000 { + opp-hz = /bits/ 64 <743000000>; + opp-microvolt = <793750>, <893750>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <825000>, <925000>; + }; + }; + + pmu-a53 { + compatible = "arm,cortex-a53-pmu"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; + }; + + pmu-a73 { + compatible = "arm,cortex-a73-pmu"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + clk13m: fixed-factor-clock-13m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk26m>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "clk13m"; + }; + + clk26m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + soc_data: efuse@8000000 { + compatible = "mediatek,mt8183-efuse", + "mediatek,efuse"; + reg = <0 0x08000000 0 0x0010>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + }; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <4>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x40000>, /* GICD */ + <0 0x0c100000 0 0x200000>, /* GICR */ + <0 0x0c400000 0 0x2000>, /* GICC */ + <0 0x0c410000 0 0x1000>, /* GICH */ + <0 0x0c420000 0 0x2000>; /* GICV */ + + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; + }; + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; + }; + }; + }; + + mcucfg: syscon@c530000 { + compatible = "mediatek,mt8183-mcucfg", "syscon"; + reg = <0 0x0c530000 0 0x1000>; + #clock-cells = <1>; + }; + + sysirq: interrupt-controller@c530a80 { + compatible = "mediatek,mt8183-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x0c530a80 0 0x50>; + }; + + cpu_debug0: cpu-debug@d410000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xd410000 0x0 0x1000>; + clocks = <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names = "apb_pclk"; + cpu = <&cpu0>; + }; + + cpu_debug1: cpu-debug@d510000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xd510000 0x0 0x1000>; + clocks = <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names = "apb_pclk"; + cpu = <&cpu1>; + }; + + cpu_debug2: cpu-debug@d610000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xd610000 0x0 0x1000>; + clocks = <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names = "apb_pclk"; + cpu = <&cpu2>; + }; + + cpu_debug3: cpu-debug@d710000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xd710000 0x0 0x1000>; + clocks = <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names = "apb_pclk"; + cpu = <&cpu3>; + }; + + cpu_debug4: cpu-debug@d810000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xd810000 0x0 0x1000>; + clocks = <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names = "apb_pclk"; + cpu = <&cpu4>; + }; + + cpu_debug5: cpu-debug@d910000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xd910000 0x0 0x1000>; + clocks = <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names = "apb_pclk"; + cpu = <&cpu5>; + }; + + cpu_debug6: cpu-debug@da10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xda10000 0x0 0x1000>; + clocks = <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names = "apb_pclk"; + cpu = <&cpu6>; + }; + + cpu_debug7: cpu-debug@db10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xdb10000 0x0 0x1000>; + clocks = <&infracfg CLK_INFRA_DEBUGSYS>; + clock-names = "apb_pclk"; + cpu = <&cpu7>; + }; + + topckgen: syscon@10000000 { + compatible = "mediatek,mt8183-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: syscon@10001000 { + compatible = "mediatek,mt8183-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pericfg: syscon@10003000 { + compatible = "mediatek,mt8183-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + }; + + pio: pinctrl@10005000 { + compatible = "mediatek,mt8183-pinctrl"; + reg = <0 0x10005000 0 0x1000>, + <0 0x11f20000 0 0x1000>, + <0 0x11e80000 0 0x1000>, + <0 0x11e70000 0 0x1000>, + <0 0x11e90000 0 0x1000>, + <0 0x11d30000 0 0x1000>, + <0 0x11d20000 0 0x1000>, + <0 0x11c50000 0 0x1000>, + <0 0x11f30000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "iocfg0", "iocfg1", "iocfg2", + "iocfg3", "iocfg4", "iocfg5", + "iocfg6", "iocfg7", "iocfg8", + "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 192>; + interrupt-controller; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + }; + + scpsys: syscon@10006000 { + compatible = "mediatek,mt8183-scpsys", "syscon", "simple-mfd"; + reg = <0 0x10006000 0 0x1000>; + + /* System Power Manager */ + spm: power-controller { + compatible = "mediatek,mt8183-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* power domain of the SoC */ + power-domain@MT8183_POWER_DOMAIN_AUDIO { + reg = <MT8183_POWER_DOMAIN_AUDIO>; + clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>, + <&infracfg CLK_INFRA_AUDIO>, + <&infracfg CLK_INFRA_AUDIO_26M_BCLK>; + clock-names = "audio", "audio1", "audio2"; + #power-domain-cells = <0>; + }; + + power-domain@MT8183_POWER_DOMAIN_CONN { + reg = <MT8183_POWER_DOMAIN_CONN>; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + mfg_async: power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC { + reg = <MT8183_POWER_DOMAIN_MFG_ASYNC>; + clocks = <&topckgen CLK_TOP_MUX_MFG>; + clock-names = "mfg"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + mfg: power-domain@MT8183_POWER_DOMAIN_MFG { + reg = <MT8183_POWER_DOMAIN_MFG>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8183_POWER_DOMAIN_MFG_CORE0 { + reg = <MT8183_POWER_DOMAIN_MFG_CORE0>; + #power-domain-cells = <0>; + }; + + power-domain@MT8183_POWER_DOMAIN_MFG_CORE1 { + reg = <MT8183_POWER_DOMAIN_MFG_CORE1>; + #power-domain-cells = <0>; + }; + + power-domain@MT8183_POWER_DOMAIN_MFG_2D { + reg = <MT8183_POWER_DOMAIN_MFG_2D>; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + }; + }; + + power-domain@MT8183_POWER_DOMAIN_DISP { + reg = <MT8183_POWER_DOMAIN_DISP>; + clocks = <&topckgen CLK_TOP_MUX_MM>, + <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_LARB0>, + <&mmsys CLK_MM_SMI_LARB1>, + <&mmsys CLK_MM_GALS_COMM0>, + <&mmsys CLK_MM_GALS_COMM1>, + <&mmsys CLK_MM_GALS_CCU2MM>, + <&mmsys CLK_MM_GALS_IPU12MM>, + <&mmsys CLK_MM_GALS_IMG2MM>, + <&mmsys CLK_MM_GALS_CAM2MM>, + <&mmsys CLK_MM_GALS_IPU2MM>; + clock-names = "mm", "mm-0", "mm-1", "mm-2", "mm-3", + "mm-4", "mm-5", "mm-6", "mm-7", + "mm-8", "mm-9"; + mediatek,infracfg = <&infracfg>; + mediatek,smi = <&smi_common>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8183_POWER_DOMAIN_CAM { + reg = <MT8183_POWER_DOMAIN_CAM>; + clocks = <&topckgen CLK_TOP_MUX_CAM>, + <&camsys CLK_CAM_LARB6>, + <&camsys CLK_CAM_LARB3>, + <&camsys CLK_CAM_SENINF>, + <&camsys CLK_CAM_CAMSV0>, + <&camsys CLK_CAM_CAMSV1>, + <&camsys CLK_CAM_CAMSV2>, + <&camsys CLK_CAM_CCU>; + clock-names = "cam", "cam-0", "cam-1", + "cam-2", "cam-3", "cam-4", + "cam-5", "cam-6"; + mediatek,infracfg = <&infracfg>; + mediatek,smi = <&smi_common>; + #power-domain-cells = <0>; + }; + + power-domain@MT8183_POWER_DOMAIN_ISP { + reg = <MT8183_POWER_DOMAIN_ISP>; + clocks = <&topckgen CLK_TOP_MUX_IMG>, + <&imgsys CLK_IMG_LARB5>, + <&imgsys CLK_IMG_LARB2>; + clock-names = "isp", "isp-0", "isp-1"; + mediatek,infracfg = <&infracfg>; + mediatek,smi = <&smi_common>; + #power-domain-cells = <0>; + }; + + power-domain@MT8183_POWER_DOMAIN_VDEC { + reg = <MT8183_POWER_DOMAIN_VDEC>; + mediatek,smi = <&smi_common>; + #power-domain-cells = <0>; + }; + + power-domain@MT8183_POWER_DOMAIN_VENC { + reg = <MT8183_POWER_DOMAIN_VENC>; + mediatek,smi = <&smi_common>; + #power-domain-cells = <0>; + }; + + power-domain@MT8183_POWER_DOMAIN_VPU_TOP { + reg = <MT8183_POWER_DOMAIN_VPU_TOP>; + clocks = <&topckgen CLK_TOP_MUX_IPU_IF>, + <&topckgen CLK_TOP_MUX_DSP>, + <&ipu_conn CLK_IPU_CONN_IPU>, + <&ipu_conn CLK_IPU_CONN_AHB>, + <&ipu_conn CLK_IPU_CONN_AXI>, + <&ipu_conn CLK_IPU_CONN_ISP>, + <&ipu_conn CLK_IPU_CONN_CAM_ADL>, + <&ipu_conn CLK_IPU_CONN_IMG_ADL>; + clock-names = "vpu", "vpu1", "vpu-0", "vpu-1", + "vpu-2", "vpu-3", "vpu-4", "vpu-5"; + mediatek,infracfg = <&infracfg>; + mediatek,smi = <&smi_common>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8183_POWER_DOMAIN_VPU_CORE0 { + reg = <MT8183_POWER_DOMAIN_VPU_CORE0>; + clocks = <&topckgen CLK_TOP_MUX_DSP1>; + clock-names = "vpu2"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + power-domain@MT8183_POWER_DOMAIN_VPU_CORE1 { + reg = <MT8183_POWER_DOMAIN_VPU_CORE1>; + clocks = <&topckgen CLK_TOP_MUX_DSP2>; + clock-names = "vpu3"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + }; + }; + }; + }; + + watchdog: watchdog@10007000 { + compatible = "mediatek,mt8183-wdt"; + reg = <0 0x10007000 0 0x100>; + #reset-cells = <1>; + }; + + apmixedsys: syscon@1000c000 { + compatible = "mediatek,mt8183-apmixedsys", "syscon"; + reg = <0 0x1000c000 0 0x1000>; + #clock-cells = <1>; + }; + + pwrap: pwrap@1000d000 { + compatible = "mediatek,mt8183-pwrap"; + reg = <0 0x1000d000 0 0x1000>; + reg-names = "pwrap"; + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, + <&infracfg CLK_INFRA_PMIC_AP>; + clock-names = "spi", "wrap"; + }; + + keyboard: keyboard@10010000 { + compatible = "mediatek,mt6779-keypad"; + reg = <0 0x10010000 0 0x1000>; + interrupts = <GIC_SPI 186 IRQ_TYPE_EDGE_FALLING>; + clocks = <&clk26m>; + clock-names = "kpd"; + status = "disabled"; + }; + + scp: scp@10500000 { + compatible = "mediatek,mt8183-scp"; + reg = <0 0x10500000 0 0x80000>, + <0 0x105c0000 0 0x19080>; + reg-names = "sram", "cfg"; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg CLK_INFRA_SCPSYS>; + clock-names = "main"; + memory-region = <&scp_mem_reserved>; + status = "disabled"; + }; + + systimer: timer@10017000 { + compatible = "mediatek,mt8183-timer", + "mediatek,mt6765-timer"; + reg = <0 0x10017000 0 0x1000>; + interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk13m>; + }; + + iommu: iommu@10205000 { + compatible = "mediatek,mt8183-m4u"; + reg = <0 0x10205000 0 0x1000>; + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>; + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>, + <&larb4>, <&larb5>, <&larb6>; + #iommu-cells = <1>; + }; + + gce: mailbox@10238000 { + compatible = "mediatek,mt8183-gce"; + reg = <0 0x10238000 0 0x4000>; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>; + #mbox-cells = <2>; + clocks = <&infracfg CLK_INFRA_GCE>; + clock-names = "gce"; + }; + + auxadc: auxadc@11001000 { + compatible = "mediatek,mt8183-auxadc", + "mediatek,mt8173-auxadc"; + reg = <0 0x11001000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_AUXADC>; + clock-names = "main"; + #io-channel-cells = <1>; + status = "disabled"; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt8183-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x1000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt8183-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x1000>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt8183-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x1000>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + i2c6: i2c@11005000 { + compatible = "mediatek,mt8183-i2c"; + reg = <0 0x11005000 0 0x1000>, + <0 0x11000600 0 0x80>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_I2C6>, + <&infracfg CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c0: i2c@11007000 { + compatible = "mediatek,mt8183-i2c"; + reg = <0 0x11007000 0 0x1000>, + <0 0x11000080 0 0x80>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_I2C0>, + <&infracfg CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@11008000 { + compatible = "mediatek,mt8183-i2c"; + reg = <0 0x11008000 0 0x1000>, + <0 0x11000100 0 0x80>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_I2C1>, + <&infracfg CLK_INFRA_AP_DMA>, + <&infracfg CLK_INFRA_I2C1_ARBITER>; + clock-names = "main", "dma","arb"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11009000 { + compatible = "mediatek,mt8183-i2c"; + reg = <0 0x11009000 0 0x1000>, + <0 0x11000280 0 0x80>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_I2C2>, + <&infracfg CLK_INFRA_AP_DMA>, + <&infracfg CLK_INFRA_I2C2_ARBITER>; + clock-names = "main", "dma", "arb"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@1100a000 { + compatible = "mediatek,mt8183-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100a000 0 0x1000>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, + <&topckgen CLK_TOP_MUX_SPI>, + <&infracfg CLK_INFRA_SPI0>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + svs: svs@1100b000 { + compatible = "mediatek,mt8183-svs"; + reg = <0 0x1100b000 0 0x1000>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_THERM>; + clock-names = "main"; + nvmem-cells = <&svs_calibration>, + <&thermal_calibration>; + nvmem-cell-names = "svs-calibration-data", + "t-calibration-data"; + }; + + thermal: thermal@1100b000 { + #thermal-sensor-cells = <1>; + compatible = "mediatek,mt8183-thermal"; + reg = <0 0x1100b000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_THERM>, + <&infracfg CLK_INFRA_AUXADC>; + clock-names = "therm", "auxadc"; + resets = <&infracfg MT8183_INFRACFG_AO_THERM_SW_RST>; + interrupts = <0 76 IRQ_TYPE_LEVEL_LOW>; + mediatek,auxadc = <&auxadc>; + mediatek,apmixedsys = <&apmixedsys>; + nvmem-cells = <&thermal_calibration>; + nvmem-cell-names = "calibration-data"; + }; + + pwm0: pwm@1100e000 { + compatible = "mediatek,mt8183-disp-pwm"; + reg = <0 0x1100e000 0 0x1000>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + #pwm-cells = <2>; + clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>, + <&infracfg CLK_INFRA_DISP_PWM>; + clock-names = "main", "mm"; + }; + + pwm1: pwm@11006000 { + compatible = "mediatek,mt8183-pwm"; + reg = <0 0x11006000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&infracfg CLK_INFRA_PWM>, + <&infracfg CLK_INFRA_PWM_HCLK>, + <&infracfg CLK_INFRA_PWM1>, + <&infracfg CLK_INFRA_PWM2>, + <&infracfg CLK_INFRA_PWM3>, + <&infracfg CLK_INFRA_PWM4>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3", + "pwm4"; + }; + + i2c3: i2c@1100f000 { + compatible = "mediatek,mt8183-i2c"; + reg = <0 0x1100f000 0 0x1000>, + <0 0x11000400 0 0x80>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_I2C3>, + <&infracfg CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@11010000 { + compatible = "mediatek,mt8183-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11010000 0 0x1000>; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, + <&topckgen CLK_TOP_MUX_SPI>, + <&infracfg CLK_INFRA_SPI1>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + i2c1: i2c@11011000 { + compatible = "mediatek,mt8183-i2c"; + reg = <0 0x11011000 0 0x1000>, + <0 0x11000480 0 0x80>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_I2C4>, + <&infracfg CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@11012000 { + compatible = "mediatek,mt8183-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11012000 0 0x1000>; + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, + <&topckgen CLK_TOP_MUX_SPI>, + <&infracfg CLK_INFRA_SPI2>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi3: spi@11013000 { + compatible = "mediatek,mt8183-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11013000 0 0x1000>; + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, + <&topckgen CLK_TOP_MUX_SPI>, + <&infracfg CLK_INFRA_SPI3>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + i2c9: i2c@11014000 { + compatible = "mediatek,mt8183-i2c"; + reg = <0 0x11014000 0 0x1000>, + <0 0x11000180 0 0x80>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_I2C1_IMM>, + <&infracfg CLK_INFRA_AP_DMA>, + <&infracfg CLK_INFRA_I2C1_ARBITER>; + clock-names = "main", "dma", "arb"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c10: i2c@11015000 { + compatible = "mediatek,mt8183-i2c"; + reg = <0 0x11015000 0 0x1000>, + <0 0x11000300 0 0x80>; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_I2C2_IMM>, + <&infracfg CLK_INFRA_AP_DMA>, + <&infracfg CLK_INFRA_I2C2_ARBITER>; + clock-names = "main", "dma", "arb"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@11016000 { + compatible = "mediatek,mt8183-i2c"; + reg = <0 0x11016000 0 0x1000>, + <0 0x11000500 0 0x80>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_I2C5>, + <&infracfg CLK_INFRA_AP_DMA>, + <&infracfg CLK_INFRA_I2C5_ARBITER>; + clock-names = "main", "dma", "arb"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c11: i2c@11017000 { + compatible = "mediatek,mt8183-i2c"; + reg = <0 0x11017000 0 0x1000>, + <0 0x11000580 0 0x80>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_I2C5_IMM>, + <&infracfg CLK_INFRA_AP_DMA>, + <&infracfg CLK_INFRA_I2C5_ARBITER>; + clock-names = "main", "dma", "arb"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@11018000 { + compatible = "mediatek,mt8183-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11018000 0 0x1000>; + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, + <&topckgen CLK_TOP_MUX_SPI>, + <&infracfg CLK_INFRA_SPI4>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi5: spi@11019000 { + compatible = "mediatek,mt8183-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11019000 0 0x1000>; + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, + <&topckgen CLK_TOP_MUX_SPI>, + <&infracfg CLK_INFRA_SPI5>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + i2c7: i2c@1101a000 { + compatible = "mediatek,mt8183-i2c"; + reg = <0 0x1101a000 0 0x1000>, + <0 0x11000680 0 0x80>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_I2C7>, + <&infracfg CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@1101b000 { + compatible = "mediatek,mt8183-i2c"; + reg = <0 0x1101b000 0 0x1000>, + <0 0x11000700 0 0x80>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_I2C8>, + <&infracfg CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ssusb: usb@11201000 { + compatible = "mediatek,mt8183-mtu3", "mediatek,mtu3"; + reg = <0 0x11201000 0 0x2e00>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>; + clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, + <&infracfg CLK_INFRA_USB>; + clock-names = "sys_ck", "ref_ck"; + mediatek,syscon-wakeup = <&pericfg 0x420 101>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb_host: usb@11200000 { + compatible = "mediatek,mt8183-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x1000>; + reg-names = "mac"; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, + <&infracfg CLK_INFRA_USB>; + clock-names = "sys_ck", "ref_ck"; + status = "disabled"; + }; + }; + + audiosys: audio-controller@11220000 { + compatible = "mediatek,mt8183-audiosys", "syscon"; + reg = <0 0x11220000 0 0x1000>; + #clock-cells = <1>; + afe: mt8183-afe-pcm { + compatible = "mediatek,mt8183-audio"; + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>; + resets = <&watchdog MT8183_TOPRGU_AUDIO_SW_RST>; + reset-names = "audiosys"; + power-domains = + <&spm MT8183_POWER_DOMAIN_AUDIO>; + clocks = <&audiosys CLK_AUDIO_AFE>, + <&audiosys CLK_AUDIO_DAC>, + <&audiosys CLK_AUDIO_DAC_PREDIS>, + <&audiosys CLK_AUDIO_ADC>, + <&audiosys CLK_AUDIO_PDN_ADDA6_ADC>, + <&audiosys CLK_AUDIO_22M>, + <&audiosys CLK_AUDIO_24M>, + <&audiosys CLK_AUDIO_APLL_TUNER>, + <&audiosys CLK_AUDIO_APLL2_TUNER>, + <&audiosys CLK_AUDIO_I2S1>, + <&audiosys CLK_AUDIO_I2S2>, + <&audiosys CLK_AUDIO_I2S3>, + <&audiosys CLK_AUDIO_I2S4>, + <&audiosys CLK_AUDIO_TDM>, + <&audiosys CLK_AUDIO_TML>, + <&infracfg CLK_INFRA_AUDIO>, + <&infracfg CLK_INFRA_AUDIO_26M_BCLK>, + <&topckgen CLK_TOP_MUX_AUDIO>, + <&topckgen CLK_TOP_MUX_AUD_INTBUS>, + <&topckgen CLK_TOP_SYSPLL_D2_D4>, + <&topckgen CLK_TOP_MUX_AUD_1>, + <&topckgen CLK_TOP_APLL1_CK>, + <&topckgen CLK_TOP_MUX_AUD_2>, + <&topckgen CLK_TOP_APLL2_CK>, + <&topckgen CLK_TOP_MUX_AUD_ENG1>, + <&topckgen CLK_TOP_APLL1_D8>, + <&topckgen CLK_TOP_MUX_AUD_ENG2>, + <&topckgen CLK_TOP_APLL2_D8>, + <&topckgen CLK_TOP_MUX_APLL_I2S0>, + <&topckgen CLK_TOP_MUX_APLL_I2S1>, + <&topckgen CLK_TOP_MUX_APLL_I2S2>, + <&topckgen CLK_TOP_MUX_APLL_I2S3>, + <&topckgen CLK_TOP_MUX_APLL_I2S4>, + <&topckgen CLK_TOP_MUX_APLL_I2S5>, + <&topckgen CLK_TOP_APLL12_DIV0>, + <&topckgen CLK_TOP_APLL12_DIV1>, + <&topckgen CLK_TOP_APLL12_DIV2>, + <&topckgen CLK_TOP_APLL12_DIV3>, + <&topckgen CLK_TOP_APLL12_DIV4>, + <&topckgen CLK_TOP_APLL12_DIVB>, + /*<&topckgen CLK_TOP_APLL12_DIV5>,*/ + <&clk26m>; + clock-names = "aud_afe_clk", + "aud_dac_clk", + "aud_dac_predis_clk", + "aud_adc_clk", + "aud_adc_adda6_clk", + "aud_apll22m_clk", + "aud_apll24m_clk", + "aud_apll1_tuner_clk", + "aud_apll2_tuner_clk", + "aud_i2s1_bclk_sw", + "aud_i2s2_bclk_sw", + "aud_i2s3_bclk_sw", + "aud_i2s4_bclk_sw", + "aud_tdm_clk", + "aud_tml_clk", + "aud_infra_clk", + "mtkaif_26m_clk", + "top_mux_audio", + "top_mux_aud_intbus", + "top_syspll_d2_d4", + "top_mux_aud_1", + "top_apll1_ck", + "top_mux_aud_2", + "top_apll2_ck", + "top_mux_aud_eng1", + "top_apll1_d8", + "top_mux_aud_eng2", + "top_apll2_d8", + "top_i2s0_m_sel", + "top_i2s1_m_sel", + "top_i2s2_m_sel", + "top_i2s3_m_sel", + "top_i2s4_m_sel", + "top_i2s5_m_sel", + "top_apll12_div0", + "top_apll12_div1", + "top_apll12_div2", + "top_apll12_div3", + "top_apll12_div4", + "top_apll12_divb", + /*"top_apll12_div5",*/ + "top_clk26m_clk"; + }; + }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt8183-mmc"; + reg = <0 0x11230000 0 0x1000>, + <0 0x11f50000 0 0x1000>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>, + <&infracfg CLK_INFRA_MSDC0>, + <&infracfg CLK_INFRA_MSDC0_SCK>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + mmc1: mmc@11240000 { + compatible = "mediatek,mt8183-mmc"; + reg = <0 0x11240000 0 0x1000>, + <0 0x11e10000 0 0x1000>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>, + <&infracfg CLK_INFRA_MSDC1>, + <&infracfg CLK_INFRA_MSDC1_SCK>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + mipi_tx0: dsi-phy@11e50000 { + compatible = "mediatek,mt8183-mipi-tx"; + reg = <0 0x11e50000 0 0x1000>; + clocks = <&apmixedsys CLK_APMIXED_MIPID0_26M>; + #clock-cells = <0>; + #phy-cells = <0>; + clock-output-names = "mipi_tx0_pll"; + nvmem-cells = <&mipi_tx_calibration>; + nvmem-cell-names = "calibration-data"; + }; + + efuse: efuse@11f10000 { + compatible = "mediatek,mt8183-efuse", + "mediatek,efuse"; + reg = <0 0x11f10000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + thermal_calibration: calib@180 { + reg = <0x180 0xc>; + }; + + mipi_tx_calibration: calib@190 { + reg = <0x190 0xc>; + }; + + svs_calibration: calib@580 { + reg = <0x580 0x64>; + }; + }; + + u3phy: t-phy@11f40000 { + compatible = "mediatek,mt8183-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11f40000 0x1000>; + status = "okay"; + + u2port0: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + mediatek,discth = <15>; + status = "okay"; + }; + + u3port0: usb-phy@700 { + reg = <0x0700 0x900>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + + mfgcfg: syscon@13000000 { + compatible = "mediatek,mt8183-mfgcfg", "syscon"; + reg = <0 0x13000000 0 0x1000>; + #clock-cells = <1>; + }; + + gpu: gpu@13040000 { + compatible = "mediatek,mt8183-mali", "arm,mali-bifrost"; + reg = <0 0x13040000 0 0x4000>; + interrupts = + <GIC_SPI 280 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 279 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 278 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "job", "mmu", "gpu"; + + clocks = <&mfgcfg CLK_MFG_BG3D>; + + power-domains = + <&spm MT8183_POWER_DOMAIN_MFG_CORE0>, + <&spm MT8183_POWER_DOMAIN_MFG_CORE1>, + <&spm MT8183_POWER_DOMAIN_MFG_2D>; + power-domain-names = "core0", "core1", "core2"; + + operating-points-v2 = <&gpu_opp_table>; + }; + + mmsys: syscon@14000000 { + compatible = "mediatek,mt8183-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; + }; + + dma-controller0@14001000 { + compatible = "mediatek,mt8183-mdp3-rdma"; + reg = <0 0x14001000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>, + <CMDQ_EVENT_MDP_RDMA0_EOF>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_MDP_RDMA0>, + <&mmsys CLK_MM_MDP_RSZ1>; + iommus = <&iommu M4U_PORT_MDP_RDMA0>; + mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>, + <&gce 21 CMDQ_THR_PRIO_LOWEST 0>; + #dma-cells = <1>; + }; + + mdp3-rsz0@14003000 { + compatible = "mediatek,mt8183-mdp3-rsz"; + reg = <0 0x14003000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ0_SOF>, + <CMDQ_EVENT_MDP_RSZ0_EOF>; + clocks = <&mmsys CLK_MM_MDP_RSZ0>; + }; + + mdp3-rsz1@14004000 { + compatible = "mediatek,mt8183-mdp3-rsz"; + reg = <0 0x14004000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ1_SOF>, + <CMDQ_EVENT_MDP_RSZ1_EOF>; + clocks = <&mmsys CLK_MM_MDP_RSZ1>; + }; + + dma-controller@14005000 { + compatible = "mediatek,mt8183-mdp3-wrot"; + reg = <0 0x14005000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>, + <CMDQ_EVENT_MDP_WROT0_EOF>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_MDP_WROT0>; + iommus = <&iommu M4U_PORT_MDP_WROT0>; + #dma-cells = <1>; + }; + + mdp3-wdma@14006000 { + compatible = "mediatek,mt8183-mdp3-wdma"; + reg = <0 0x14006000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_MDP_WDMA0_SOF>, + <CMDQ_EVENT_MDP_WDMA0_EOF>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_MDP_WDMA0>; + iommus = <&iommu M4U_PORT_MDP_WDMA0>; + }; + + ovl0: ovl@14008000 { + compatible = "mediatek,mt8183-disp-ovl"; + reg = <0 0x14008000 0 0x1000>; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_OVL0>; + iommus = <&iommu M4U_PORT_DISP_OVL0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; + }; + + ovl_2l0: ovl@14009000 { + compatible = "mediatek,mt8183-disp-ovl-2l"; + reg = <0 0x14009000 0 0x1000>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; + iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; + }; + + ovl_2l1: ovl@1400a000 { + compatible = "mediatek,mt8183-disp-ovl-2l"; + reg = <0 0x1400a000 0 0x1000>; + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; + iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; + }; + + rdma0: rdma@1400b000 { + compatible = "mediatek,mt8183-disp-rdma"; + reg = <0 0x1400b000 0 0x1000>; + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_RDMA0>; + iommus = <&iommu M4U_PORT_DISP_RDMA0>; + mediatek,rdma-fifo-size = <5120>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; + }; + + rdma1: rdma@1400c000 { + compatible = "mediatek,mt8183-disp-rdma"; + reg = <0 0x1400c000 0 0x1000>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_RDMA1>; + iommus = <&iommu M4U_PORT_DISP_RDMA1>; + mediatek,rdma-fifo-size = <2048>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; + }; + + color0: color@1400e000 { + compatible = "mediatek,mt8183-disp-color", + "mediatek,mt8173-disp-color"; + reg = <0 0x1400e000 0 0x1000>; + interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_COLOR0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; + }; + + ccorr0: ccorr@1400f000 { + compatible = "mediatek,mt8183-disp-ccorr"; + reg = <0 0x1400f000 0 0x1000>; + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_CCORR0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; + }; + + aal0: aal@14010000 { + compatible = "mediatek,mt8183-disp-aal"; + reg = <0 0x14010000 0 0x1000>; + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_AAL0>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; + }; + + gamma0: gamma@14011000 { + compatible = "mediatek,mt8183-disp-gamma"; + reg = <0 0x14011000 0 0x1000>; + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_GAMMA0>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; + }; + + dither0: dither@14012000 { + compatible = "mediatek,mt8183-disp-dither"; + reg = <0 0x14012000 0 0x1000>; + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_DITHER0>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; + }; + + dsi0: dsi@14014000 { + compatible = "mediatek,mt8183-dsi"; + reg = <0 0x14014000 0 0x1000>; + interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DSI0_MM>, + <&mmsys CLK_MM_DSI0_IF>, + <&mipi_tx0>; + clock-names = "engine", "digital", "hs"; + resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>; + phys = <&mipi_tx0>; + phy-names = "dphy"; + }; + + mutex: mutex@14016000 { + compatible = "mediatek,mt8183-disp-mutex"; + reg = <0 0x14016000 0 0x1000>; + interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>, + <CMDQ_EVENT_MUTEX_STREAM_DONE1>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; + }; + + larb0: larb@14017000 { + compatible = "mediatek,mt8183-smi-larb"; + reg = <0 0x14017000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&mmsys CLK_MM_SMI_LARB0>, + <&mmsys CLK_MM_SMI_LARB0>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clock-names = "apb", "smi"; + }; + + smi_common: smi@14019000 { + compatible = "mediatek,mt8183-smi-common"; + reg = <0 0x14019000 0 0x1000>; + clocks = <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_GALS_COMM0>, + <&mmsys CLK_MM_GALS_COMM1>; + clock-names = "apb", "smi", "gals0", "gals1"; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + }; + + mdp3-ccorr@1401c000 { + compatible = "mediatek,mt8183-mdp3-ccorr"; + reg = <0 0x1401c000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_MDP_CCORR_SOF>, + <CMDQ_EVENT_MDP_CCORR_EOF>; + clocks = <&mmsys CLK_MM_MDP_CCORR>; + }; + + imgsys: syscon@15020000 { + compatible = "mediatek,mt8183-imgsys", "syscon"; + reg = <0 0x15020000 0 0x1000>; + #clock-cells = <1>; + }; + + larb5: larb@15021000 { + compatible = "mediatek,mt8183-smi-larb"; + reg = <0 0x15021000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&imgsys CLK_IMG_LARB5>, <&imgsys CLK_IMG_LARB5>, + <&mmsys CLK_MM_GALS_IMG2MM>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8183_POWER_DOMAIN_ISP>; + }; + + larb2: larb@1502f000 { + compatible = "mediatek,mt8183-smi-larb"; + reg = <0 0x1502f000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&imgsys CLK_IMG_LARB2>, <&imgsys CLK_IMG_LARB2>, + <&mmsys CLK_MM_GALS_IPU2MM>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8183_POWER_DOMAIN_ISP>; + }; + + vdecsys: syscon@16000000 { + compatible = "mediatek,mt8183-vdecsys", "syscon"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb1: larb@16010000 { + compatible = "mediatek,mt8183-smi-larb"; + reg = <0 0x16010000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&vdecsys CLK_VDEC_VDEC>, <&vdecsys CLK_VDEC_LARB1>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>; + }; + + vencsys: syscon@17000000 { + compatible = "mediatek,mt8183-vencsys", "syscon"; + reg = <0 0x17000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb4: larb@17010000 { + compatible = "mediatek,mt8183-smi-larb"; + reg = <0 0x17010000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&vencsys CLK_VENC_LARB>, + <&vencsys CLK_VENC_LARB>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; + }; + + venc_jpg: venc_jpg@17030000 { + compatible = "mediatek,mt8183-jpgenc", "mediatek,mtk-jpgenc"; + reg = <0 0x17030000 0 0x1000>; + interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>; + iommus = <&iommu M4U_PORT_JPGENC_RDMA>, + <&iommu M4U_PORT_JPGENC_BSDMA>; + power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; + clocks = <&vencsys CLK_VENC_JPGENC>; + clock-names = "jpgenc"; + }; + + ipu_conn: syscon@19000000 { + compatible = "mediatek,mt8183-ipu_conn", "syscon"; + reg = <0 0x19000000 0 0x1000>; + #clock-cells = <1>; + }; + + ipu_adl: syscon@19010000 { + compatible = "mediatek,mt8183-ipu_adl", "syscon"; + reg = <0 0x19010000 0 0x1000>; + #clock-cells = <1>; + }; + + ipu_core0: syscon@19180000 { + compatible = "mediatek,mt8183-ipu_core0", "syscon"; + reg = <0 0x19180000 0 0x1000>; + #clock-cells = <1>; + }; + + ipu_core1: syscon@19280000 { + compatible = "mediatek,mt8183-ipu_core1", "syscon"; + reg = <0 0x19280000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys: syscon@1a000000 { + compatible = "mediatek,mt8183-camsys", "syscon"; + reg = <0 0x1a000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb6: larb@1a001000 { + compatible = "mediatek,mt8183-smi-larb"; + reg = <0 0x1a001000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&camsys CLK_CAM_LARB6>, <&camsys CLK_CAM_LARB6>, + <&mmsys CLK_MM_GALS_CAM2MM>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8183_POWER_DOMAIN_CAM>; + }; + + larb3: larb@1a002000 { + compatible = "mediatek,mt8183-smi-larb"; + reg = <0 0x1a002000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&camsys CLK_CAM_LARB3>, <&camsys CLK_CAM_LARB3>, + <&mmsys CLK_MM_GALS_IPU12MM>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8183_POWER_DOMAIN_CAM>; + }; + }; + + thermal_zones: thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <100>; + polling-delay = <500>; + thermal-sensors = <&thermal 0>; + sustainable-power = <5000>; + + trips { + threshold: trip-point0 { + temperature = <68000>; + hysteresis = <2000>; + type = "passive"; + }; + + target: trip-point1 { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit: cpu-crit { + temperature = <115000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu1 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu2 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu3 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + contribution = <3072>; + }; + map1 { + trip = <&target>; + cooling-device = <&cpu4 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu5 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu6 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu7 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + }; + }; + + /* The tzts1 ~ tzts6 don't need to polling */ + /* The tzts1 ~ tzts6 don't need to thermal throttle */ + + tzts1: tzts1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&thermal 1>; + sustainable-power = <5000>; + trips {}; + cooling-maps {}; + }; + + tzts2: tzts2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&thermal 2>; + sustainable-power = <5000>; + trips {}; + cooling-maps {}; + }; + + tzts3: tzts3 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&thermal 3>; + sustainable-power = <5000>; + trips {}; + cooling-maps {}; + }; + + tzts4: tzts4 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&thermal 4>; + sustainable-power = <5000>; + trips {}; + cooling-maps {}; + }; + + tzts5: tzts5 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&thermal 5>; + sustainable-power = <5000>; + trips {}; + cooling-maps {}; + }; + + tztsABB: tztsABB { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&thermal 6>; + sustainable-power = <5000>; + trips {}; + cooling-maps {}; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts new file mode 100644 index 000000000..ed74a3617 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts @@ -0,0 +1,220 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (C) 2022 MediaTek Inc. + */ +/dts-v1/; +#include "mt8186.dtsi" + +/ { + model = "MediaTek MT8186 evaluation board"; + compatible = "mediatek,mt8186-evb", "mediatek,mt8186"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; +}; + +&i2c0 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; +}; + +&i2c1 { + status = "okay"; + + clock-frequency = <400000>; + i2c-scl-internal-delay-ns = <8000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; +}; + +&i2c2 { + status = "okay"; + + clock-frequency = <400000>; + i2c-scl-internal-delay-ns = <10000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; +}; + +&i2c3 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; +}; + +&i2c4 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; +}; + +&i2c5 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins>; +}; + +&i2c6 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pins>; +}; + +&i2c7 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_pins>; +}; + +&i2c8 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_pins>; +}; + +&i2c9 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c9_pins>; +}; + +&pio { + i2c0_pins: i2c0-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO128__FUNC_SDA0>, + <PINMUX_GPIO127__FUNC_SCL0>; + bias-disable; + drive-strength-microamp = <1000>; + input-enable; + }; + }; + + i2c1_pins: i2c1-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO130__FUNC_SDA1>, + <PINMUX_GPIO129__FUNC_SCL1>; + bias-disable; + drive-strength-microamp = <1000>; + input-enable; + }; + }; + + i2c2_pins: i2c2-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO132__FUNC_SDA2>, + <PINMUX_GPIO131__FUNC_SCL2>; + bias-disable; + drive-strength-microamp = <1000>; + input-enable; + }; + }; + + i2c3_pins: i2c3-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO134__FUNC_SDA3>, + <PINMUX_GPIO133__FUNC_SCL3>; + bias-disable; + drive-strength-microamp = <1000>; + input-enable; + }; + }; + + i2c4_pins: i2c4-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO136__FUNC_SDA4>, + <PINMUX_GPIO135__FUNC_SCL4>; + bias-disable; + drive-strength-microamp = <1000>; + input-enable; + }; + }; + + i2c5_pins: i2c5-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO138__FUNC_SDA5>, + <PINMUX_GPIO137__FUNC_SCL5>; + bias-disable; + drive-strength-microamp = <1000>; + input-enable; + }; + }; + + i2c6_pins: i2c6-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO140__FUNC_SDA6>, + <PINMUX_GPIO139__FUNC_SCL6>; + bias-pull-up = <MTK_PULL_SET_RSEL_001>; + drive-strength-microamp = <1000>; + input-enable; + }; + }; + + i2c7_pins: i2c7-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO142__FUNC_SDA7>, + <PINMUX_GPIO141__FUNC_SCL7>; + bias-disable; + drive-strength-microamp = <1000>; + input-enable; + }; + }; + + i2c8_pins: i2c8-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO144__FUNC_SDA8>, + <PINMUX_GPIO143__FUNC_SCL8>; + bias-disable; + drive-strength-microamp = <1000>; + input-enable; + }; + }; + + i2c9_pins: i2c9-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO146__FUNC_SDA9>, + <PINMUX_GPIO145__FUNC_SCL9>; + bias-pull-up = <MTK_PULL_SET_RSEL_001>; + drive-strength-microamp = <1000>; + input-enable; + }; + }; +}; + +&u3phy0 { + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi new file mode 100644 index 000000000..f88d660e4 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -0,0 +1,818 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com> + */ +/dts-v1/; +#include <dt-bindings/clock/mt8186-clk.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/mt8186-pinfunc.h> +#include <dt-bindings/power/mt8186-power.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/reset/mt8186-resets.h> + +/ { + compatible = "mediatek,mt8186"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + + core4 { + cpu = <&cpu4>; + }; + + core5 { + cpu = <&cpu5>; + }; + + core6 { + cpu = <&cpu6>; + }; + + core7 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x000>; + enable-method = "psci"; + clock-frequency = <2000000000>; + capacity-dmips-mhz = <382>; + cpu-idle-states = <&cpu_off_l &cluster_off_l>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + clock-frequency = <2000000000>; + capacity-dmips-mhz = <382>; + cpu-idle-states = <&cpu_off_l &cluster_off_l>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + clock-frequency = <2000000000>; + capacity-dmips-mhz = <382>; + cpu-idle-states = <&cpu_off_l &cluster_off_l>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + clock-frequency = <2000000000>; + capacity-dmips-mhz = <382>; + cpu-idle-states = <&cpu_off_l &cluster_off_l>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x400>; + enable-method = "psci"; + clock-frequency = <2000000000>; + capacity-dmips-mhz = <382>; + cpu-idle-states = <&cpu_off_l &cluster_off_l>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x500>; + enable-method = "psci"; + clock-frequency = <2000000000>; + capacity-dmips-mhz = <382>; + cpu-idle-states = <&cpu_off_l &cluster_off_l>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu6: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x600>; + enable-method = "psci"; + clock-frequency = <2050000000>; + capacity-dmips-mhz = <1024>; + cpu-idle-states = <&cpu_off_b &cluster_off_b>; + next-level-cache = <&l2_1>; + #cooling-cells = <2>; + }; + + cpu7: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x700>; + enable-method = "psci"; + clock-frequency = <2050000000>; + capacity-dmips-mhz = <1024>; + cpu-idle-states = <&cpu_off_b &cluster_off_b>; + next-level-cache = <&l2_1>; + #cooling-cells = <2>; + }; + + idle-states { + entry-method = "psci"; + + cpu_off_l: cpu-off-l { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x00010001>; + local-timer-stop; + entry-latency-us = <50>; + exit-latency-us = <100>; + min-residency-us = <1600>; + }; + + cpu_off_b: cpu-off-b { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x00010001>; + local-timer-stop; + entry-latency-us = <50>; + exit-latency-us = <100>; + min-residency-us = <1400>; + }; + + cluster_off_l: cluster-off-l { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x01010001>; + local-timer-stop; + entry-latency-us = <100>; + exit-latency-us = <250>; + min-residency-us = <2100>; + }; + + cluster_off_b: cluster-off-b { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x01010001>; + local-timer-stop; + entry-latency-us = <100>; + exit-latency-us = <250>; + min-residency-us = <1900>; + }; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + next-level-cache = <&l3_0>; + }; + + l2_1: l2-cache1 { + compatible = "cache"; + next-level-cache = <&l3_0>; + }; + + l3_0: l3-cache { + compatible = "cache"; + }; + }; + + clk13m: fixed-factor-clock-13m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk26m>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "clk13m"; + }; + + clk26m: oscillator-26m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + clk32k: oscillator-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "clk32k"; + }; + + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; + }; + + pmu-a76 { + compatible = "arm,cortex-a76-pmu"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <4>; + #redistributor-regions = <1>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x40000>, + <0 0x0c040000 0 0x200000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu6 &cpu7>; + }; + }; + }; + + mcusys: syscon@c53a000 { + compatible = "mediatek,mt8186-mcusys", "syscon"; + reg = <0 0xc53a000 0 0x1000>; + #clock-cells = <1>; + }; + + topckgen: syscon@10000000 { + compatible = "mediatek,mt8186-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg_ao: syscon@10001000 { + compatible = "mediatek,mt8186-infracfg_ao", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pericfg: syscon@10003000 { + compatible = "mediatek,mt8186-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + }; + + pio: pinctrl@10005000 { + compatible = "mediatek,mt8186-pinctrl"; + reg = <0 0x10005000 0 0x1000>, + <0 0x10002000 0 0x0200>, + <0 0x10002200 0 0x0200>, + <0 0x10002400 0 0x0200>, + <0 0x10002600 0 0x0200>, + <0 0x10002a00 0 0x0200>, + <0 0x10002c00 0 0x0200>, + <0 0x1000b000 0 0x1000>; + reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb", + "iocfg_bl", "iocfg_rb", "iocfg_rt", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 185>; + interrupt-controller; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; + #interrupt-cells = <2>; + }; + + watchdog: watchdog@10007000 { + compatible = "mediatek,mt8186-wdt"; + mediatek,disable-extrst; + reg = <0 0x10007000 0 0x1000>; + #reset-cells = <1>; + }; + + apmixedsys: syscon@1000c000 { + compatible = "mediatek,mt8186-apmixedsys", "syscon"; + reg = <0 0x1000c000 0 0x1000>; + #clock-cells = <1>; + }; + + pwrap: pwrap@1000d000 { + compatible = "mediatek,mt8186-pwrap", "syscon"; + reg = <0 0x1000d000 0 0x1000>; + reg-names = "pwrap"; + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, + <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; + clock-names = "spi", "wrap"; + }; + + systimer: timer@10017000 { + compatible = "mediatek,mt8186-timer", + "mediatek,mt6765-timer"; + reg = <0 0x10017000 0 0x1000>; + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&clk13m>; + }; + + scp: scp@10500000 { + compatible = "mediatek,mt8186-scp"; + reg = <0 0x10500000 0 0x40000>, + <0 0x105c0000 0 0x19080>; + reg-names = "sram", "cfg"; + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; + }; + + nor_flash: spi@11000000 { + compatible = "mediatek,mt8186-nor"; + reg = <0 0x11000000 0 0x1000>; + clocks = <&topckgen CLK_TOP_SPINOR>, + <&infracfg_ao CLK_INFRA_AO_SPINOR>, + <&infracfg_ao CLK_INFRA_AO_FLASHIF_133M>, + <&infracfg_ao CLK_INFRA_AO_FLASHIF_66M>; + clock-names = "spi", "sf", "axi", "axi_s"; + assigned-clocks = <&topckgen CLK_TOP_SPINOR>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>; + interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>; + status = "disabled"; + }; + + auxadc: adc@11001000 { + compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc"; + reg = <0 0x11001000 0 0x1000>; + #io-channel-cells = <1>; + clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; + clock-names = "main"; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt8186-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x1000>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt8186-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x1000>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + i2c0: i2c@11007000 { + compatible = "mediatek,mt8186-i2c"; + reg = <0 0x11007000 0 0x1000>, + <0 0x10200100 0 0x100>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@11008000 { + compatible = "mediatek,mt8186-i2c"; + reg = <0 0x11008000 0 0x1000>, + <0 0x10200200 0 0x100>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11009000 { + compatible = "mediatek,mt8186-i2c"; + reg = <0 0x11009000 0 0x1000>, + <0 0x10200300 0 0x180>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@1100f000 { + compatible = "mediatek,mt8186-i2c"; + reg = <0 0x1100f000 0 0x1000>, + <0 0x10200480 0 0x100>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@11011000 { + compatible = "mediatek,mt8186-i2c"; + reg = <0 0x11011000 0 0x1000>, + <0 0x10200580 0 0x180>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@11016000 { + compatible = "mediatek,mt8186-i2c"; + reg = <0 0x11016000 0 0x1000>, + <0 0x10200700 0 0x100>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@1100d000 { + compatible = "mediatek,mt8186-i2c"; + reg = <0 0x1100d000 0 0x1000>, + <0 0x10200800 0 0x100>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@11004000 { + compatible = "mediatek,mt8186-i2c"; + reg = <0 0x11004000 0 0x1000>, + <0 0x10200900 0 0x180>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@11005000 { + compatible = "mediatek,mt8186-i2c"; + reg = <0 0x11005000 0 0x1000>, + <0 0x10200A80 0 0x180>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@1100a000 { + compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100a000 0 0x1000>; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI0>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + pwm0: pwm@1100e000 { + compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm"; + reg = <0 0x1100e000 0 0x1000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; + #pwm-cells = <2>; + clocks = <&topckgen CLK_TOP_DISP_PWM>, + <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; + clock-names = "main", "mm"; + status = "disabled"; + }; + + spi1: spi@11010000 { + compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11010000 0 0x1000>; + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI1>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi2: spi@11012000 { + compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11012000 0 0x1000>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI2>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi3: spi@11013000 { + compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11013000 0 0x1000>; + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI3>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi4: spi@11014000 { + compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11014000 0 0x1000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI4>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi5: spi@11015000 { + compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11015000 0 0x1000>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI5>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + imp_iic_wrap: clock-controller@11017000 { + compatible = "mediatek,mt8186-imp_iic_wrap"; + reg = <0 0x11017000 0 0x1000>; + #clock-cells = <1>; + }; + + uart2: serial@11018000 { + compatible = "mediatek,mt8186-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11018000 0 0x1000>; + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + i2c9: i2c@11019000 { + compatible = "mediatek,mt8186-i2c"; + reg = <0 0x11019000 0 0x1000>, + <0 0x10200c00 0 0x180>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt8186-mmc", + "mediatek,mt8183-mmc"; + reg = <0 0x11230000 0 0x1000>, + <0 0x11cd0000 0 0x1000>; + clocks = <&topckgen CLK_TOP_MSDC50_0>, + <&infracfg_ao CLK_INFRA_AO_MSDC0>, + <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; + clock-names = "source", "hclk", "source_cg"; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; + assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>; + assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>; + status = "disabled"; + }; + + mmc1: mmc@11240000 { + compatible = "mediatek,mt8186-mmc", + "mediatek,mt8183-mmc"; + reg = <0 0x11240000 0 0x1000>, + <0 0x11c90000 0 0x1000>; + clocks = <&topckgen CLK_TOP_MSDC30_1>, + <&infracfg_ao CLK_INFRA_AO_MSDC1>, + <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; + clock-names = "source", "hclk", "source_cg"; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; + assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; + status = "disabled"; + }; + + u3phy0: t-phy@11c80000 { + compatible = "mediatek,mt8186-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x11c80000 0x1000>; + status = "disabled"; + + u2port1: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + }; + + u3port1: usb-phy@700 { + reg = <0x700 0x900>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + + u3phy1: t-phy@11ca0000 { + compatible = "mediatek,mt8186-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x11ca0000 0x1000>; + status = "disabled"; + + u2port0: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + mediatek,discth = <0x8>; + }; + }; + + efuse: efuse@11cb0000 { + compatible = "mediatek,mt8186-efuse", "mediatek,efuse"; + reg = <0 0x11cb0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + mipi_tx0: dsi-phy@11cc0000 { + compatible = "mediatek,mt8183-mipi-tx"; + reg = <0 0x11cc0000 0 0x1000>; + clocks = <&clk26m>; + #clock-cells = <0>; + #phy-cells = <0>; + clock-output-names = "mipi_tx0_pll"; + status = "disabled"; + }; + + mfgsys: clock-controller@13000000 { + compatible = "mediatek,mt8186-mfgsys"; + reg = <0 0x13000000 0 0x1000>; + #clock-cells = <1>; + }; + + mmsys: syscon@14000000 { + compatible = "mediatek,mt8186-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + wpesys: clock-controller@14020000 { + compatible = "mediatek,mt8186-wpesys"; + reg = <0 0x14020000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys1: clock-controller@15020000 { + compatible = "mediatek,mt8186-imgsys1"; + reg = <0 0x15020000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys2: clock-controller@15820000 { + compatible = "mediatek,mt8186-imgsys2"; + reg = <0 0x15820000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys: clock-controller@1602f000 { + compatible = "mediatek,mt8186-vdecsys"; + reg = <0 0x1602f000 0 0x1000>; + #clock-cells = <1>; + }; + + vencsys: clock-controller@17000000 { + compatible = "mediatek,mt8186-vencsys"; + reg = <0 0x17000000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys: clock-controller@1a000000 { + compatible = "mediatek,mt8186-camsys"; + reg = <0 0x1a000000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_rawa: clock-controller@1a04f000 { + compatible = "mediatek,mt8186-camsys_rawa"; + reg = <0 0x1a04f000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_rawb: clock-controller@1a06f000 { + compatible = "mediatek,mt8186-camsys_rawb"; + reg = <0 0x1a06f000 0 0x1000>; + #clock-cells = <1>; + }; + + mdpsys: clock-controller@1b000000 { + compatible = "mediatek,mt8186-mdpsys"; + reg = <0 0x1b000000 0 0x1000>; + #clock-cells = <1>; + }; + + ipesys: clock-controller@1c000000 { + compatible = "mediatek,mt8186-ipesys"; + reg = <0 0x1c000000 0 0x1000>; + #clock-cells = <1>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts new file mode 100644 index 000000000..1e9149194 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 Google LLC + */ +/dts-v1/; +#include "mt8192-asurada.dtsi" + +/ { + model = "Google Hayato rev1"; + compatible = "google,hayato-rev1", "google,hayato", "mediatek,mt8192"; +}; + +&keyboard_controller { + function-row-physmap = < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + linux,keymap = < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_FORWARD) + MATRIX_KEY(0x02, 0x02, KEY_REFRESH) + MATRIX_KEY(0x01, 0x02, KEY_FULL_SCREEN) + MATRIX_KEY(0x03, 0x04, KEY_SCALE) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + + CROS_STD_MAIN_KEYMAP + >; +}; + +&touchscreen { + compatible = "hid-over-i2c"; + post-power-on-delay-ms = <10>; + hid-descr-addr = <0x0001>; + vdd-supply = <&pp3300_u>; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts new file mode 100644 index 000000000..fa3d9573f --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Google LLC + */ +/dts-v1/; +#include "mt8192-asurada.dtsi" +#include <dt-bindings/leds/common.h> + +/ { + model = "Google Spherion (rev0 - 3)"; + compatible = "google,spherion-rev3", "google,spherion-rev2", + "google,spherion-rev1", "google,spherion-rev0", + "google,spherion", "mediatek,mt8192"; + + pwmleds { + compatible = "pwm-leds"; + + led { + function = LED_FUNCTION_KBD_BACKLIGHT; + color = <LED_COLOR_ID_WHITE>; + pwms = <&cros_ec_pwm 0>; + max-brightness = <1023>; + }; + }; +}; + +&cros_ec_pwm { + status = "okay"; +}; + +&keyboard_controller { + function-row-physmap = < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + linux,keymap = < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_FULL_SCREEN) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + + CROS_STD_MAIN_KEYMAP + >; +}; + +&touchscreen { + compatible = "elan,ekth3500"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi new file mode 100644 index 000000000..50367da93 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -0,0 +1,959 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2020 MediaTek Inc. + * Author: Seiya Wang <seiya.wang@mediatek.com> + */ +/dts-v1/; +#include "mt8192.dtsi" +#include "mt6359.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/spmi/spmi.h> + +/ { + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; + + /* system wide LDO 1.8V power rail */ + pp1800_ldo_g: regulator-1v8-g { + compatible = "regulator-fixed"; + regulator-name = "pp1800_ldo_g"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&pp3300_g>; + }; + + /* system wide switching 3.3V power rail */ + pp3300_g: regulator-3v3-g { + compatible = "regulator-fixed"; + regulator-name = "pp3300_g"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&ppvar_sys>; + }; + + /* system wide LDO 3.3V power rail */ + pp3300_ldo_z: regulator-3v3-z { + compatible = "regulator-fixed"; + regulator-name = "pp3300_ldo_z"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&ppvar_sys>; + }; + + /* separately switched 3.3V power rail */ + pp3300_u: regulator-3v3-u { + compatible = "regulator-fixed"; + regulator-name = "pp3300_u"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /* enable pin wired to GPIO controlled by EC */ + vin-supply = <&pp3300_g>; + }; + + pp3300_wlan: regulator-3v3-wlan { + compatible = "regulator-fixed"; + regulator-name = "pp3300_wlan"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pp3300_wlan_pins>; + enable-active-high; + gpio = <&pio 143 GPIO_ACTIVE_HIGH>; + }; + + /* system wide switching 5.0V power rail */ + pp5000_a: regulator-5v0-a { + compatible = "regulator-fixed"; + regulator-name = "pp5000_a"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&ppvar_sys>; + }; + + /* system wide semi-regulated power rail from battery or USB */ + ppvar_sys: regulator-var-sys { + compatible = "regulator-fixed"; + regulator-name = "ppvar_sys"; + regulator-always-on; + regulator-boot-on; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scp_mem_reserved: scp@50000000 { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x2900000>; + no-map; + }; + + wifi_restricted_dma_region: wifi@c0000000 { + compatible = "restricted-dma-pool"; + reg = <0 0xc0000000 0 0x4000000>; + }; + }; +}; + +&i2c0 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + touchscreen: touchscreen@10 { + reg = <0x10>; + interrupts-extended = <&pio 21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + }; +}; + +&i2c1 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; +}; + +&i2c2 { + status = "okay"; + + clock-frequency = <400000>; + clock-stretch-ns = <12600>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + trackpad@15 { + compatible = "elan,ekth3000"; + reg = <0x15>; + interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_pins>; + vcc-supply = <&pp3300_u>; + wakeup-source; + }; +}; + +&i2c3 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; +}; + +&i2c7 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_pins>; +}; + +&mmc0 { + status = "okay"; + + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_default_pins>; + pinctrl-1 = <&mmc0_uhs_pins>; + bus-width = <8>; + max-frequency = <200000000>; + vmmc-supply = <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply = <&mt6359_vufs_ldo_reg>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + supports-cqe; + cap-mmc-hw-reset; + mmc-hs400-enhanced-strobe; + hs400-ds-delay = <0x12814>; + no-sdio; + no-sd; + non-removable; +}; + +&mmc1 { + status = "okay"; + + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_default_pins>; + pinctrl-1 = <&mmc1_uhs_pins>; + bus-width = <4>; + max-frequency = <200000000>; + cd-gpios = <&pio 17 GPIO_ACTIVE_LOW>; + vmmc-supply = <&mt6360_ldo5_reg>; + vqmmc-supply = <&mt6360_ldo3_reg>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + no-sdio; + no-mmc; +}; + +/* for CORE */ +&mt6359_vgpu11_buck_reg { + regulator-always-on; +}; + +&mt6359_vgpu11_sshub_buck_reg { + regulator-always-on; + regulator-min-microvolt = <575000>; + regulator-max-microvolt = <575000>; +}; + +&mt6359_vrf12_ldo_reg { + regulator-always-on; +}; + +&mt6359_vufs_ldo_reg { + regulator-always-on; +}; + +&mt6359codec { + mediatek,dmic-mode = <1>; /* one-wire */ + mediatek,mic-type-0 = <2>; /* DMIC */ + mediatek,mic-type-2 = <2>; /* DMIC */ +}; + +&nor_flash { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&nor_flash_pins>; + assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6_D8>; + + flash@0 { + compatible = "winbond,w25q64jwm", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <2>; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + + pcie0: pcie@0,0 { + device_type = "pci"; + reg = <0x0000 0 0 0 0>; + num-lanes = <1>; + bus-range = <0x1 0x1>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi: wifi@0,0 { + reg = <0x10000 0 0 0 0x100000>, + <0x10000 0 0x100000 0 0x100000>; + memory-region = <&wifi_restricted_dma_region>; + }; + }; +}; + +&pio { + /* 220 lines */ + gpio-line-names = "I2S_DP_LRCK", + "IS_DP_BCLK", + "I2S_DP_MCLK", + "I2S_DP_DATAOUT", + "SAR0_INT_ODL", + "EC_AP_INT_ODL", + "EDPBRDG_INT_ODL", + "DPBRDG_INT_ODL", + "DPBRDG_PWREN", + "DPBRDG_RST_ODL", + "I2S_HP_MCLK", + "I2S_HP_BCK", + "I2S_HP_LRCK", + "I2S_HP_DATAIN", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it AP_FLASH_WP_ODL. + */ + "AP_FLASH_WP_L", + "TRACKPAD_INT_ODL", + "EC_AP_HPD_OD", + "SD_CD_ODL", + "HP_INT_ODL_ALC", + "EN_PP1000_DPBRDG", + "AP_GPIO20", + "TOUCH_INT_L_1V8", + "UART_BT_WAKE_ODL", + "AP_GPIO23", + "AP_SPI_FLASH_CS_L", + "AP_SPI_FLASH_CLK", + "EN_PP3300_DPBRDG_DX", + "AP_SPI_FLASH_MOSI", + "AP_SPI_FLASH_MISO", + "I2S_HP_DATAOUT", + "AP_GPIO30", + "I2S_SPKR_MCLK", + "I2S_SPKR_BCLK", + "I2S_SPKR_LRCK", + "I2S_SPKR_DATAIN", + "I2S_SPKR_DATAOUT", + "AP_SPI_H1_TPM_CLK", + "AP_SPI_H1_TPM_CS_L", + "AP_SPI_H1_TPM_MISO", + "AP_SPI_H1_TPM_MOSI", + "BL_PWM", + "EDPBRDG_PWREN", + "EDPBRDG_RST_ODL", + "EN_PP3300_HUB", + "HUB_RST_L", + "", + "", + "", + "", + "", + "", + "SD_CLK", + "SD_CMD", + "SD_DATA3", + "SD_DATA0", + "SD_DATA2", + "SD_DATA1", + "", + "", + "", + "", + "", + "", + "PCIE_WAKE_ODL", + "PCIE_RST_L", + "PCIE_CLKREQ_ODL", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SPMI_SCL", + "SPMI_SDA", + "AP_GOOD", + "UART_DBG_TX_AP_RX", + "UART_AP_TX_DBG_RX", + "UART_AP_TX_BT_RX", + "UART_BT_TX_AP_RX", + "MIPI_DPI_D0_R", + "MIPI_DPI_D1_R", + "MIPI_DPI_D2_R", + "MIPI_DPI_D3_R", + "MIPI_DPI_D4_R", + "MIPI_DPI_D5_R", + "MIPI_DPI_D6_R", + "MIPI_DPI_D7_R", + "MIPI_DPI_D8_R", + "MIPI_DPI_D9_R", + "MIPI_DPI_D10_R", + "", + "", + "MIPI_DPI_DE_R", + "MIPI_DPI_D11_R", + "MIPI_DPI_VSYNC_R", + "MIPI_DPI_CLK_R", + "MIPI_DPI_HSYNC_R", + "PCM_BT_DATAIN", + "PCM_BT_SYNC", + "PCM_BT_DATAOUT", + "PCM_BT_CLK", + "AP_I2C_AUDIO_SCL", + "AP_I2C_AUDIO_SDA", + "SCP_I2C_SCL", + "SCP_I2C_SDA", + "AP_I2C_WLAN_SCL", + "AP_I2C_WLAN_SDA", + "AP_I2C_DPBRDG_SCL", + "AP_I2C_DPBRDG_SDA", + "EN_PP1800_DPBRDG_DX", + "EN_PP3300_EDP_DX", + "EN_PP1800_EDPBRDG_DX", + "EN_PP1000_EDPBRDG", + "SCP_JTAG0_TDO", + "SCP_JTAG0_TDI", + "SCP_JTAG0_TMS", + "SCP_JTAG0_TCK", + "SCP_JTAG0_TRSTN", + "EN_PP3000_VMC_PMU", + "EN_PP3300_DISPLAY_DX", + "TOUCH_RST_L_1V8", + "TOUCH_REPORT_DISABLE", + "", + "", + "AP_I2C_TRACKPAD_SCL_1V8", + "AP_I2C_TRACKPAD_SDA_1V8", + "EN_PP3300_WLAN", + "BT_KILL_L", + "WIFI_KILL_L", + "SET_VMC_VOLT_AT_1V8", + "EN_SPK", + "AP_WARM_RST_REQ", + "", + "", + "EN_PP3000_SD_S3", + "AP_EDP_BKLTEN", + "", + "", + "", + "AP_SPI_EC_CLK", + "AP_SPI_EC_CS_L", + "AP_SPI_EC_MISO", + "AP_SPI_EC_MOSI", + "AP_I2C_EDPBRDG_SCL", + "AP_I2C_EDPBRDG_SDA", + "MT6315_PROC_INT", + "MT6315_GPU_INT", + "UART_SERVO_TX_SCP_RX", + "UART_SCP_TX_SERVO_RX", + "BT_RTS_AP_CTS", + "AP_RTS_BT_CTS", + "UART_AP_WAKE_BT_ODL", + "WLAN_ALERT_ODL", + "EC_IN_RW_ODL", + "H1_AP_INT_ODL", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "MSDC0_CMD", + "MSDC0_DAT0", + "MSDC0_DAT2", + "MSDC0_DAT4", + "MSDC0_DAT6", + "MSDC0_DAT1", + "MSDC0_DAT5", + "MSDC0_DAT7", + "MSDC0_DSL", + "MSDC0_CLK", + "MSDC0_DAT3", + "MSDC0_RST_L", + "SCP_VREQ_VAO", + "AUD_DAT_MOSI2", + "AUD_NLE_MOSI1", + "AUD_NLE_MOSI0", + "AUD_DAT_MISO2", + "AP_I2C_SAR_SDA", + "AP_I2C_SAR_SCL", + "AP_I2C_PWR_SCL", + "AP_I2C_PWR_SDA", + "AP_I2C_TS_SCL_1V8", + "AP_I2C_TS_SDA_1V8", + "SRCLKENA0", + "SRCLKENA1", + "AP_EC_WATCHDOG_L", + "PWRAP_SPI0_MI", + "PWRAP_SPI0_CSN", + "PWRAP_SPI0_MO", + "PWRAP_SPI0_CK", + "AP_RTC_CLK32K", + "AUD_CLK_MOSI", + "AUD_SYNC_MOSI", + "AUD_DAT_MOSI0", + "AUD_DAT_MOSI1", + "AUD_DAT_MISO0", + "AUD_DAT_MISO1"; + + cr50_int: cr50-irq-default-pins { + pins-gsc-ap-int-odl { + pinmux = <PINMUX_GPIO171__FUNC_GPIO171>; + input-enable; + }; + }; + + cros_ec_int: cros-ec-irq-default-pins { + pins-ec-ap-int-odl { + pinmux = <PINMUX_GPIO5__FUNC_GPIO5>; + input-enable; + bias-pull-up; + }; + }; + + i2c0_pins: i2c0-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO204__FUNC_SCL0>, + <PINMUX_GPIO205__FUNC_SDA0>; + bias-pull-up = <MTK_PULL_SET_RSEL_011>; + drive-strength-microamp = <1000>; + }; + }; + + i2c1_pins: i2c1-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO118__FUNC_SCL1>, + <PINMUX_GPIO119__FUNC_SDA1>; + bias-pull-up = <MTK_PULL_SET_RSEL_011>; + drive-strength-microamp = <1000>; + }; + }; + + i2c2_pins: i2c2-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO141__FUNC_SCL2>, + <PINMUX_GPIO142__FUNC_SDA2>; + bias-pull-up = <MTK_PULL_SET_RSEL_011>; + }; + }; + + i2c3_pins: i2c3-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO160__FUNC_SCL3>, + <PINMUX_GPIO161__FUNC_SDA3>; + bias-disable; + drive-strength-microamp = <1000>; + }; + }; + + i2c7_pins: i2c7-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO124__FUNC_SCL7>, + <PINMUX_GPIO125__FUNC_SDA7>; + bias-disable; + drive-strength-microamp = <1000>; + }; + }; + + mmc0_default_pins: mmc0-default-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, + <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, + <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, + <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, + <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, + <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, + <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, + <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, + <PINMUX_GPIO183__FUNC_MSDC0_CMD>; + input-enable; + drive-strength = <8>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-clk { + pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; + drive-strength = <8>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-rst { + pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; + drive-strength = <8>; + bias-pull-down = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>, + <PINMUX_GPIO188__FUNC_MSDC0_DAT1>, + <PINMUX_GPIO185__FUNC_MSDC0_DAT2>, + <PINMUX_GPIO193__FUNC_MSDC0_DAT3>, + <PINMUX_GPIO186__FUNC_MSDC0_DAT4>, + <PINMUX_GPIO189__FUNC_MSDC0_DAT5>, + <PINMUX_GPIO187__FUNC_MSDC0_DAT6>, + <PINMUX_GPIO190__FUNC_MSDC0_DAT7>, + <PINMUX_GPIO183__FUNC_MSDC0_CMD>; + input-enable; + drive-strength = <10>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-clk { + pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>; + drive-strength = <10>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-rst { + pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>; + drive-strength = <8>; + bias-pull-down = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-ds { + pinmux = <PINMUX_GPIO191__FUNC_MSDC0_DSL>; + drive-strength = <10>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + }; + + mmc1_default_pins: mmc1-default-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, + <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, + <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, + <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, + <PINMUX_GPIO52__FUNC_MSDC1_CMD>; + input-enable; + drive-strength = <8>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-clk { + pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; + drive-strength = <8>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-insert { + pinmux = <PINMUX_GPIO17__FUNC_GPIO17>; + input-enable; + bias-pull-up; + }; + }; + + mmc1_uhs_pins: mmc1-uhs-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>, + <PINMUX_GPIO56__FUNC_MSDC1_DAT1>, + <PINMUX_GPIO55__FUNC_MSDC1_DAT2>, + <PINMUX_GPIO53__FUNC_MSDC1_DAT3>, + <PINMUX_GPIO52__FUNC_MSDC1_CMD>; + input-enable; + drive-strength = <8>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-clk { + pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>; + input-enable; + drive-strength = <8>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + }; + + nor_flash_pins: nor-flash-default-pins { + pins-cs-io1 { + pinmux = <PINMUX_GPIO24__FUNC_SPINOR_CS>, + <PINMUX_GPIO28__FUNC_SPINOR_IO1>; + input-enable; + bias-pull-up; + drive-strength = <10>; + }; + + pins-io0 { + pinmux = <PINMUX_GPIO27__FUNC_SPINOR_IO0>; + bias-pull-up; + drive-strength = <10>; + }; + + pins-clk { + pinmux = <PINMUX_GPIO25__FUNC_SPINOR_CK>; + input-enable; + bias-pull-up; + drive-strength = <10>; + }; + }; + + pcie_pins: pcie-default-pins { + pins-pcie-wake { + pinmux = <PINMUX_GPIO63__FUNC_PCIE_WAKE_N>; + bias-pull-up; + }; + + pins-pcie-pereset { + pinmux = <PINMUX_GPIO64__FUNC_PCIE_PERESET_N>; + }; + + pins-pcie-clkreq { + pinmux = <PINMUX_GPIO65__FUNC_PCIE_CLKREQ_N>; + bias-pull-up; + }; + + pins-wifi-kill { + pinmux = <PINMUX_GPIO145__FUNC_GPIO145>; /* WIFI_KILL_L */ + output-high; + }; + }; + + pp3300_wlan_pins: pp3300-wlan-pins { + pins-pcie-en-pp3300-wlan { + pinmux = <PINMUX_GPIO143__FUNC_GPIO143>; + output-high; + }; + }; + + scp_pins: scp-pins { + pins-vreq-vao { + pinmux = <PINMUX_GPIO195__FUNC_SCP_VREQ_VAO>; + }; + }; + + spi1_pins: spi1-default-pins { + pins-cs-mosi-clk { + pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>, + <PINMUX_GPIO159__FUNC_SPI1_A_MO>, + <PINMUX_GPIO156__FUNC_SPI1_A_CLK>; + bias-disable; + }; + + pins-miso { + pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>; + bias-pull-down; + }; + }; + + spi5_pins: spi5-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO38__FUNC_SPI5_A_MI>, + <PINMUX_GPIO37__FUNC_GPIO37>, + <PINMUX_GPIO39__FUNC_SPI5_A_MO>, + <PINMUX_GPIO36__FUNC_SPI5_A_CLK>; + bias-disable; + }; + }; + + trackpad_pins: trackpad-default-pins { + pins-int-n { + pinmux = <PINMUX_GPIO15__FUNC_GPIO15>; + input-enable; + bias-pull-up = <MTK_PUPD_SET_R1R0_11>; + }; + }; + + touchscreen_pins: touchscreen-default-pins { + pins-irq { + pinmux = <PINMUX_GPIO21__FUNC_GPIO21>; + input-enable; + bias-pull-up; + }; + + pins-reset { + pinmux = <PINMUX_GPIO137__FUNC_GPIO137>; + output-high; + }; + + pins-report-sw { + pinmux = <PINMUX_GPIO138__FUNC_GPIO138>; + output-low; + }; + }; +}; + +&pmic { + interrupts-extended = <&pio 214 IRQ_TYPE_LEVEL_HIGH>; +}; + +&scp { + status = "okay"; + + firmware-name = "mediatek/mt8192/scp.img"; + memory-region = <&scp_mem_reserved>; + pinctrl-names = "default"; + pinctrl-0 = <&scp_pins>; + + cros-ec { + compatible = "google,cros-ec-rpmsg"; + mediatek,rpmsg-name = "cros-ec-rpmsg"; + }; +}; + +&spi1 { + status = "okay"; + + mediatek,pad-select = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + + cros_ec: ec@0 { + compatible = "google,cros-ec-spi"; + reg = <0>; + interrupts-extended = <&pio 5 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <3000000>; + pinctrl-names = "default"; + pinctrl-0 = <&cros_ec_int>; + + #address-cells = <1>; + #size-cells = <0>; + + base_detection: cbas { + compatible = "google,cros-cbas"; + }; + + cros_ec_pwm: pwm { + compatible = "google,cros-ec-pwm"; + #pwm-cells = <1>; + + status = "disabled"; + }; + + i2c_tunnel: i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + google,remote-bus = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mt6360_ldo3_reg: regulator@0 { + compatible = "google,cros-ec-regulator"; + reg = <0>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + mt6360_ldo5_reg: regulator@1 { + compatible = "google,cros-ec-regulator"; + reg = <1>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + typec { + compatible = "google,cros-ec-typec"; + #address-cells = <1>; + #size-cells = <0>; + + usb_c0: connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + label = "left"; + power-role = "dual"; + data-role = "host"; + try-power-role = "source"; + }; + + usb_c1: connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + label = "right"; + power-role = "dual"; + data-role = "host"; + try-power-role = "source"; + }; + }; + }; +}; + +&spi5 { + status = "okay"; + + cs-gpios = <&pio 37 GPIO_ACTIVE_LOW>; + mediatek,pad-select = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi5_pins>; + + cr50@0 { + compatible = "google,cr50"; + reg = <0>; + interrupts-extended = <&pio 171 IRQ_TYPE_EDGE_RISING>; + spi-max-frequency = <1000000>; + pinctrl-names = "default"; + pinctrl-0 = <&cr50_int>; + }; +}; + +&spmi { + #address-cells = <2>; + #size-cells = <0>; + + mt6315_6: pmic@6 { + compatible = "mediatek,mt6315-regulator"; + reg = <0x6 SPMI_USID>; + + regulators { + mt6315_6_vbuck1: vbuck1 { + regulator-compatible = "vbuck1"; + regulator-name = "Vbcpu"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + + mt6315_6_vbuck3: vbuck3 { + regulator-compatible = "vbuck3"; + regulator-name = "Vlcpu"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + }; + }; + + mt6315_7: pmic@7 { + compatible = "mediatek,mt6315-regulator"; + reg = <0x7 SPMI_USID>; + + regulators { + mt6315_7_vbuck1: vbuck1 { + regulator-compatible = "vbuck1"; + regulator-name = "Vgpu"; + regulator-min-microvolt = <606250>; + regulator-max-microvolt = <800000>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + }; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&xhci { + status = "okay"; + + wakeup-source; + vusb33-supply = <&pp3300_g>; + vbus-supply = <&pp5000_a>; +}; + +#include <arm/cros-ec-keyboard.dtsi> +#include <arm/cros-ec-sbs.dtsi> diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts new file mode 100644 index 000000000..808be492e --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2020 MediaTek Inc. + * Author: Seiya Wang <seiya.wang@mediatek.com> + */ +/dts-v1/; +#include "mt8192.dtsi" +#include "mt6359.dtsi" + +/ { + model = "MediaTek MT8192 evaluation board"; + compatible = "mediatek,mt8192-evb", "mediatek,mt8192"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi new file mode 100644 index 000000000..2f40c6cc4 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -0,0 +1,1671 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2020 MediaTek Inc. + * Author: Seiya Wang <seiya.wang@mediatek.com> + */ + +/dts-v1/; +#include <dt-bindings/clock/mt8192-clk.h> +#include <dt-bindings/gce/mt8192-gce.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/memory/mt8192-larb-port.h> +#include <dt-bindings/pinctrl/mt8192-pinfunc.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/power/mt8192-power.h> +#include <dt-bindings/reset/mt8192-resets.h> + +/ { + compatible = "mediatek,mt8192"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ovl0 = &ovl0; + ovl-2l0 = &ovl_2l0; + ovl-2l2 = &ovl_2l2; + rdma0 = &rdma0; + rdma4 = &rdma4; + }; + + clk13m: fixed-factor-clock-13m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk26m>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "clk13m"; + }; + + clk26m: oscillator0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + clk32k: oscillator1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "clk32k"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x000>; + enable-method = "psci"; + clock-frequency = <1701000000>; + cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; + next-level-cache = <&l2_0>; + performance-domains = <&performance 0>; + capacity-dmips-mhz = <427>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + clock-frequency = <1701000000>; + cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; + next-level-cache = <&l2_0>; + performance-domains = <&performance 0>; + capacity-dmips-mhz = <427>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + clock-frequency = <1701000000>; + cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; + next-level-cache = <&l2_0>; + performance-domains = <&performance 0>; + capacity-dmips-mhz = <427>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + clock-frequency = <1701000000>; + cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; + next-level-cache = <&l2_0>; + performance-domains = <&performance 0>; + capacity-dmips-mhz = <427>; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x400>; + enable-method = "psci"; + clock-frequency = <2171000000>; + cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; + next-level-cache = <&l2_1>; + performance-domains = <&performance 1>; + capacity-dmips-mhz = <1024>; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x500>; + enable-method = "psci"; + clock-frequency = <2171000000>; + cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; + next-level-cache = <&l2_1>; + performance-domains = <&performance 1>; + capacity-dmips-mhz = <1024>; + }; + + cpu6: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x600>; + enable-method = "psci"; + clock-frequency = <2171000000>; + cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; + next-level-cache = <&l2_1>; + performance-domains = <&performance 1>; + capacity-dmips-mhz = <1024>; + }; + + cpu7: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x700>; + enable-method = "psci"; + clock-frequency = <2171000000>; + cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; + next-level-cache = <&l2_1>; + performance-domains = <&performance 1>; + capacity-dmips-mhz = <1024>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + core4 { + cpu = <&cpu4>; + }; + core5 { + cpu = <&cpu5>; + }; + core6 { + cpu = <&cpu6>; + }; + core7 { + cpu = <&cpu7>; + }; + }; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + next-level-cache = <&l3_0>; + }; + + l2_1: l2-cache1 { + compatible = "cache"; + next-level-cache = <&l3_0>; + }; + + l3_0: l3-cache { + compatible = "cache"; + }; + + idle-states { + entry-method = "psci"; + cpu_sleep_l: cpu-sleep-l { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x00010001>; + local-timer-stop; + entry-latency-us = <55>; + exit-latency-us = <140>; + min-residency-us = <780>; + }; + cpu_sleep_b: cpu-sleep-b { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x00010001>; + local-timer-stop; + entry-latency-us = <35>; + exit-latency-us = <145>; + min-residency-us = <720>; + }; + cluster_sleep_l: cluster-sleep-l { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x01010002>; + local-timer-stop; + entry-latency-us = <60>; + exit-latency-us = <155>; + min-residency-us = <860>; + }; + cluster_sleep_b: cluster-sleep-b { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x01010002>; + local-timer-stop; + entry-latency-us = <40>; + exit-latency-us = <155>; + min-residency-us = <780>; + }; + }; + }; + + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; + }; + + pmu-a76 { + compatible = "arm,cortex-a76-pmu"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer: timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; + clock-frequency = <13000000>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + performance: performance-controller@11bc10 { + compatible = "mediatek,cpufreq-hw"; + reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; + #performance-domain-cells = <1>; + }; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <4>; + #redistributor-regions = <1>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x40000>, + <0 0x0c040000 0 0x200000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; + }; + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; + }; + }; + }; + + topckgen: syscon@10000000 { + compatible = "mediatek,mt8192-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: syscon@10001000 { + compatible = "mediatek,mt8192-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pericfg: syscon@10003000 { + compatible = "mediatek,mt8192-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + }; + + pio: pinctrl@10005000 { + compatible = "mediatek,mt8192-pinctrl"; + reg = <0 0x10005000 0 0x1000>, + <0 0x11c20000 0 0x1000>, + <0 0x11d10000 0 0x1000>, + <0 0x11d30000 0 0x1000>, + <0 0x11d40000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11e70000 0 0x1000>, + <0 0x11ea0000 0 0x1000>, + <0 0x11f20000 0 0x1000>, + <0 0x11f30000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", + "iocfg_bl", "iocfg_br", "iocfg_lm", + "iocfg_lb", "iocfg_rt", "iocfg_lt", + "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 220>; + interrupt-controller; + interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; + #interrupt-cells = <2>; + }; + + scpsys: syscon@10006000 { + compatible = "mediatek,mt8192-scpsys", "syscon", "simple-mfd"; + reg = <0 0x10006000 0 0x1000>; + + /* System Power Manager */ + spm: power-controller { + compatible = "mediatek,mt8192-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* power domain of the SoC */ + power-domain@MT8192_POWER_DOMAIN_AUDIO { + reg = <MT8192_POWER_DOMAIN_AUDIO>; + clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, + <&infracfg CLK_INFRA_AUDIO_26M_B>, + <&infracfg CLK_INFRA_AUDIO>; + clock-names = "audio", "audio1", "audio2"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_CONN { + reg = <MT8192_POWER_DOMAIN_CONN>; + clocks = <&infracfg CLK_INFRA_PMIC_CONN>; + clock-names = "conn"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_MFG0 { + reg = <MT8192_POWER_DOMAIN_MFG0>; + clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>; + clock-names = "mfg"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8192_POWER_DOMAIN_MFG1 { + reg = <MT8192_POWER_DOMAIN_MFG1>; + mediatek,infracfg = <&infracfg>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8192_POWER_DOMAIN_MFG2 { + reg = <MT8192_POWER_DOMAIN_MFG2>; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_MFG3 { + reg = <MT8192_POWER_DOMAIN_MFG3>; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_MFG4 { + reg = <MT8192_POWER_DOMAIN_MFG4>; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_MFG5 { + reg = <MT8192_POWER_DOMAIN_MFG5>; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_MFG6 { + reg = <MT8192_POWER_DOMAIN_MFG6>; + #power-domain-cells = <0>; + }; + }; + }; + + power-domain@MT8192_POWER_DOMAIN_DISP { + reg = <MT8192_POWER_DOMAIN_DISP>; + clocks = <&topckgen CLK_TOP_DISP_SEL>, + <&mmsys CLK_MM_SMI_INFRA>, + <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_GALS>, + <&mmsys CLK_MM_SMI_IOMMU>; + clock-names = "disp", "disp-0", "disp-1", "disp-2", + "disp-3"; + mediatek,infracfg = <&infracfg>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8192_POWER_DOMAIN_IPE { + reg = <MT8192_POWER_DOMAIN_IPE>; + clocks = <&topckgen CLK_TOP_IPE_SEL>, + <&ipesys CLK_IPE_LARB19>, + <&ipesys CLK_IPE_LARB20>, + <&ipesys CLK_IPE_SMI_SUBCOM>, + <&ipesys CLK_IPE_GALS>; + clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2", + "ipe-3"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_ISP { + reg = <MT8192_POWER_DOMAIN_ISP>; + clocks = <&topckgen CLK_TOP_IMG1_SEL>, + <&imgsys CLK_IMG_LARB9>, + <&imgsys CLK_IMG_GALS>; + clock-names = "isp", "isp-0", "isp-1"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_ISP2 { + reg = <MT8192_POWER_DOMAIN_ISP2>; + clocks = <&topckgen CLK_TOP_IMG2_SEL>, + <&imgsys2 CLK_IMG2_LARB11>, + <&imgsys2 CLK_IMG2_GALS>; + clock-names = "isp2", "isp2-0", "isp2-1"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_MDP { + reg = <MT8192_POWER_DOMAIN_MDP>; + clocks = <&topckgen CLK_TOP_MDP_SEL>, + <&mdpsys CLK_MDP_SMI0>; + clock-names = "mdp", "mdp-0"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_VENC { + reg = <MT8192_POWER_DOMAIN_VENC>; + clocks = <&topckgen CLK_TOP_VENC_SEL>, + <&vencsys CLK_VENC_SET1_VENC>; + clock-names = "venc", "venc-0"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_VDEC { + reg = <MT8192_POWER_DOMAIN_VDEC>; + clocks = <&topckgen CLK_TOP_VDEC_SEL>, + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>, + <&vdecsys_soc CLK_VDEC_SOC_LARB1>; + clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2"; + mediatek,infracfg = <&infracfg>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8192_POWER_DOMAIN_VDEC2 { + reg = <MT8192_POWER_DOMAIN_VDEC2>; + clocks = <&vdecsys CLK_VDEC_VDEC>, + <&vdecsys CLK_VDEC_LAT>, + <&vdecsys CLK_VDEC_LARB1>; + clock-names = "vdec2-0", "vdec2-1", + "vdec2-2"; + #power-domain-cells = <0>; + }; + }; + + power-domain@MT8192_POWER_DOMAIN_CAM { + reg = <MT8192_POWER_DOMAIN_CAM>; + clocks = <&topckgen CLK_TOP_CAM_SEL>, + <&camsys CLK_CAM_LARB13>, + <&camsys CLK_CAM_LARB14>, + <&camsys CLK_CAM_CCU_GALS>, + <&camsys CLK_CAM_CAM2MM_GALS>; + clock-names = "cam", "cam-0", "cam-1", "cam-2", + "cam-3"; + mediatek,infracfg = <&infracfg>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8192_POWER_DOMAIN_CAM_RAWA { + reg = <MT8192_POWER_DOMAIN_CAM_RAWA>; + clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>; + clock-names = "cam_rawa-0"; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_CAM_RAWB { + reg = <MT8192_POWER_DOMAIN_CAM_RAWB>; + clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>; + clock-names = "cam_rawb-0"; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_CAM_RAWC { + reg = <MT8192_POWER_DOMAIN_CAM_RAWC>; + clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>; + clock-names = "cam_rawc-0"; + #power-domain-cells = <0>; + }; + }; + }; + }; + }; + + watchdog: watchdog@10007000 { + compatible = "mediatek,mt8192-wdt"; + reg = <0 0x10007000 0 0x100>; + #reset-cells = <1>; + }; + + apmixedsys: syscon@1000c000 { + compatible = "mediatek,mt8192-apmixedsys", "syscon"; + reg = <0 0x1000c000 0 0x1000>; + #clock-cells = <1>; + }; + + systimer: timer@10017000 { + compatible = "mediatek,mt8192-timer", + "mediatek,mt6765-timer"; + reg = <0 0x10017000 0 0x1000>; + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&clk13m>; + }; + + pwrap: pwrap@10026000 { + compatible = "mediatek,mt6873-pwrap"; + reg = <0 0x10026000 0 0x1000>; + reg-names = "pwrap"; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&infracfg CLK_INFRA_PMIC_AP>, + <&infracfg CLK_INFRA_PMIC_TMR>; + clock-names = "spi", "wrap"; + assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; + }; + + spmi: spmi@10027000 { + compatible = "mediatek,mt6873-spmi"; + reg = <0 0x10027000 0 0x000e00>, + <0 0x10029000 0 0x000100>; + reg-names = "pmif", "spmimst"; + clocks = <&infracfg CLK_INFRA_PMIC_AP>, + <&infracfg CLK_INFRA_PMIC_TMR>, + <&topckgen CLK_TOP_SPMI_MST_SEL>; + clock-names = "pmif_sys_ck", + "pmif_tmr_ck", + "spmimst_clk_mux"; + assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; + }; + + gce: mailbox@10228000 { + compatible = "mediatek,mt8192-gce"; + reg = <0 0x10228000 0 0x4000>; + interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; + #mbox-cells = <2>; + clocks = <&infracfg CLK_INFRA_GCE>; + clock-names = "gce"; + }; + + scp_adsp: clock-controller@10720000 { + compatible = "mediatek,mt8192-scp_adsp"; + reg = <0 0x10720000 0 0x1000>; + #clock-cells = <1>; + /* power domain dependency not upstreamed */ + status = "fail"; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt8192-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x1000>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt8192-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x1000>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + imp_iic_wrap_c: clock-controller@11007000 { + compatible = "mediatek,mt8192-imp_iic_wrap_c"; + reg = <0 0x11007000 0 0x1000>; + #clock-cells = <1>; + }; + + spi0: spi@1100a000 { + compatible = "mediatek,mt8192-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100a000 0 0x1000>; + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI0>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + pwm0: pwm@1100e000 { + compatible = "mediatek,mt8183-disp-pwm"; + reg = <0 0x1100e000 0 0x1000>; + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>; + #pwm-cells = <2>; + clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>, + <&infracfg CLK_INFRA_DISP_PWM>; + clock-names = "main", "mm"; + status = "disabled"; + }; + + spi1: spi@11010000 { + compatible = "mediatek,mt8192-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11010000 0 0x1000>; + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI1>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi2: spi@11012000 { + compatible = "mediatek,mt8192-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11012000 0 0x1000>; + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI2>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi3: spi@11013000 { + compatible = "mediatek,mt8192-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11013000 0 0x1000>; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI3>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi4: spi@11018000 { + compatible = "mediatek,mt8192-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11018000 0 0x1000>; + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI4>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi5: spi@11019000 { + compatible = "mediatek,mt8192-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11019000 0 0x1000>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI5>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi6: spi@1101d000 { + compatible = "mediatek,mt8192-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1101d000 0 0x1000>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI6>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi7: spi@1101e000 { + compatible = "mediatek,mt8192-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1101e000 0 0x1000>; + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI7>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + scp: scp@10500000 { + compatible = "mediatek,mt8192-scp"; + reg = <0 0x10500000 0 0x100000>, + <0 0x10720000 0 0xe0000>, + <0 0x10700000 0 0x8000>; + reg-names = "sram", "cfg", "l1tcm"; + interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&infracfg CLK_INFRA_SCPSYS>; + clock-names = "main"; + status = "disabled"; + }; + + xhci: usb@11200000 { + compatible = "mediatek,mt8192-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x1000>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "host"; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>; + assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>, + <&topckgen CLK_TOP_SSUSB_XHCI_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&infracfg CLK_INFRA_SSUSB>, + <&apmixedsys CLK_APMIXED_USBPLL>, + <&clk26m>, + <&clk26m>, + <&infracfg CLK_INFRA_SSUSB_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", + "xhci_ck"; + wakeup-source; + mediatek,syscon-wakeup = <&pericfg 0x420 102>; + status = "disabled"; + }; + + audsys: syscon@11210000 { + compatible = "mediatek,mt8192-audsys", "syscon"; + reg = <0 0x11210000 0 0x2000>; + #clock-cells = <1>; + + afe: mt8192-afe-pcm { + compatible = "mediatek,mt8192-audio"; + interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>; + resets = <&watchdog 17>; + reset-names = "audiosys"; + mediatek,apmixedsys = <&apmixedsys>; + mediatek,infracfg = <&infracfg>; + mediatek,topckgen = <&topckgen>; + power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>; + clocks = <&audsys CLK_AUD_AFE>, + <&audsys CLK_AUD_DAC>, + <&audsys CLK_AUD_DAC_PREDIS>, + <&audsys CLK_AUD_ADC>, + <&audsys CLK_AUD_ADDA6_ADC>, + <&audsys CLK_AUD_22M>, + <&audsys CLK_AUD_24M>, + <&audsys CLK_AUD_APLL_TUNER>, + <&audsys CLK_AUD_APLL2_TUNER>, + <&audsys CLK_AUD_TDM>, + <&audsys CLK_AUD_TML>, + <&audsys CLK_AUD_NLE>, + <&audsys CLK_AUD_DAC_HIRES>, + <&audsys CLK_AUD_ADC_HIRES>, + <&audsys CLK_AUD_ADC_HIRES_TML>, + <&audsys CLK_AUD_ADDA6_ADC_HIRES>, + <&audsys CLK_AUD_3RD_DAC>, + <&audsys CLK_AUD_3RD_DAC_PREDIS>, + <&audsys CLK_AUD_3RD_DAC_TML>, + <&audsys CLK_AUD_3RD_DAC_HIRES>, + <&infracfg CLK_INFRA_AUDIO>, + <&infracfg CLK_INFRA_AUDIO_26M_B>, + <&topckgen CLK_TOP_AUDIO_SEL>, + <&topckgen CLK_TOP_AUD_INTBUS_SEL>, + <&topckgen CLK_TOP_MAINPLL_D4_D4>, + <&topckgen CLK_TOP_AUD_1_SEL>, + <&topckgen CLK_TOP_APLL1>, + <&topckgen CLK_TOP_AUD_2_SEL>, + <&topckgen CLK_TOP_APLL2>, + <&topckgen CLK_TOP_AUD_ENGEN1_SEL>, + <&topckgen CLK_TOP_APLL1_D4>, + <&topckgen CLK_TOP_AUD_ENGEN2_SEL>, + <&topckgen CLK_TOP_APLL2_D4>, + <&topckgen CLK_TOP_APLL_I2S0_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S1_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S2_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S3_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S4_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S5_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S6_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S7_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S8_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S9_M_SEL>, + <&topckgen CLK_TOP_APLL12_DIV0>, + <&topckgen CLK_TOP_APLL12_DIV1>, + <&topckgen CLK_TOP_APLL12_DIV2>, + <&topckgen CLK_TOP_APLL12_DIV3>, + <&topckgen CLK_TOP_APLL12_DIV4>, + <&topckgen CLK_TOP_APLL12_DIVB>, + <&topckgen CLK_TOP_APLL12_DIV5>, + <&topckgen CLK_TOP_APLL12_DIV6>, + <&topckgen CLK_TOP_APLL12_DIV7>, + <&topckgen CLK_TOP_APLL12_DIV8>, + <&topckgen CLK_TOP_APLL12_DIV9>, + <&topckgen CLK_TOP_AUDIO_H_SEL>, + <&clk26m>; + clock-names = "aud_afe_clk", + "aud_dac_clk", + "aud_dac_predis_clk", + "aud_adc_clk", + "aud_adda6_adc_clk", + "aud_apll22m_clk", + "aud_apll24m_clk", + "aud_apll1_tuner_clk", + "aud_apll2_tuner_clk", + "aud_tdm_clk", + "aud_tml_clk", + "aud_nle", + "aud_dac_hires_clk", + "aud_adc_hires_clk", + "aud_adc_hires_tml", + "aud_adda6_adc_hires_clk", + "aud_3rd_dac_clk", + "aud_3rd_dac_predis_clk", + "aud_3rd_dac_tml", + "aud_3rd_dac_hires_clk", + "aud_infra_clk", + "aud_infra_26m_clk", + "top_mux_audio", + "top_mux_audio_int", + "top_mainpll_d4_d4", + "top_mux_aud_1", + "top_apll1_ck", + "top_mux_aud_2", + "top_apll2_ck", + "top_mux_aud_eng1", + "top_apll1_d4", + "top_mux_aud_eng2", + "top_apll2_d4", + "top_i2s0_m_sel", + "top_i2s1_m_sel", + "top_i2s2_m_sel", + "top_i2s3_m_sel", + "top_i2s4_m_sel", + "top_i2s5_m_sel", + "top_i2s6_m_sel", + "top_i2s7_m_sel", + "top_i2s8_m_sel", + "top_i2s9_m_sel", + "top_apll12_div0", + "top_apll12_div1", + "top_apll12_div2", + "top_apll12_div3", + "top_apll12_div4", + "top_apll12_divb", + "top_apll12_div5", + "top_apll12_div6", + "top_apll12_div7", + "top_apll12_div8", + "top_apll12_div9", + "top_mux_audio_h", + "top_clk26m_clk"; + }; + }; + + pcie: pcie@11230000 { + compatible = "mediatek,mt8192-pcie"; + device_type = "pci"; + reg = <0 0x11230000 0 0x2000>; + reg-names = "pcie-mac"; + #address-cells = <3>; + #size-cells = <2>; + clocks = <&infracfg CLK_INFRA_PCIE_PL_P_250M>, + <&infracfg CLK_INFRA_PCIE_TL_26M>, + <&infracfg CLK_INFRA_PCIE_TL_96M>, + <&infracfg CLK_INFRA_PCIE_TL_32K>, + <&infracfg CLK_INFRA_PCIE_PERI_26M>, + <&infracfg CLK_INFRA_PCIE_TOP_H_133M>; + clock-names = "pl_250m", "tl_26m", "tl_96m", + "tl_32k", "peri_26m", "top_133m"; + assigned-clocks = <&topckgen CLK_TOP_TL_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>; + interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>, + <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + nor_flash: spi@11234000 { + compatible = "mediatek,mt8192-nor"; + reg = <0 0x11234000 0 0xe0>; + interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_SFLASH_SEL>, + <&infracfg CLK_INFRA_FLASHIF_SFLASH>, + <&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>; + clock-names = "spi", "sf", "axi"; + assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; + assigned-clock-parents = <&clk26m>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + efuse: efuse@11c10000 { + compatible = "mediatek,mt8192-efuse", "mediatek,efuse"; + reg = <0 0x11c10000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + lvts_e_data1: data1@1c0 { + reg = <0x1c0 0x58>; + }; + + svs_calibration: calib@580 { + reg = <0x580 0x68>; + }; + }; + + i2c3: i2c@11cb0000 { + compatible = "mediatek,mt8192-i2c"; + reg = <0 0x11cb0000 0 0x1000>, + <0 0x10217300 0 0x80>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>, + <&infracfg CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + imp_iic_wrap_e: clock-controller@11cb1000 { + compatible = "mediatek,mt8192-imp_iic_wrap_e"; + reg = <0 0x11cb1000 0 0x1000>; + #clock-cells = <1>; + }; + + i2c7: i2c@11d00000 { + compatible = "mediatek,mt8192-i2c"; + reg = <0 0x11d00000 0 0x1000>, + <0 0x10217600 0 0x180>; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, + <&infracfg CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@11d01000 { + compatible = "mediatek,mt8192-i2c"; + reg = <0 0x11d01000 0 0x1000>, + <0 0x10217780 0 0x180>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>, + <&infracfg CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c9: i2c@11d02000 { + compatible = "mediatek,mt8192-i2c"; + reg = <0 0x11d02000 0 0x1000>, + <0 0x10217900 0 0x180>; + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>, + <&infracfg CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + imp_iic_wrap_s: clock-controller@11d03000 { + compatible = "mediatek,mt8192-imp_iic_wrap_s"; + reg = <0 0x11d03000 0 0x1000>; + #clock-cells = <1>; + }; + + i2c1: i2c@11d20000 { + compatible = "mediatek,mt8192-i2c"; + reg = <0 0x11d20000 0 0x1000>, + <0 0x10217100 0 0x80>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>, + <&infracfg CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11d21000 { + compatible = "mediatek,mt8192-i2c"; + reg = <0 0x11d21000 0 0x1000>, + <0 0x10217180 0 0x180>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>, + <&infracfg CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@11d22000 { + compatible = "mediatek,mt8192-i2c"; + reg = <0 0x11d22000 0 0x1000>, + <0 0x10217380 0 0x180>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>, + <&infracfg CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + imp_iic_wrap_ws: clock-controller@11d23000 { + compatible = "mediatek,mt8192-imp_iic_wrap_ws"; + reg = <0 0x11d23000 0 0x1000>; + #clock-cells = <1>; + }; + + i2c5: i2c@11e00000 { + compatible = "mediatek,mt8192-i2c"; + reg = <0 0x11e00000 0 0x1000>, + <0 0x10217500 0 0x80>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>, + <&infracfg CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + imp_iic_wrap_w: clock-controller@11e01000 { + compatible = "mediatek,mt8192-imp_iic_wrap_w"; + reg = <0 0x11e01000 0 0x1000>; + #clock-cells = <1>; + }; + + u3phy0: t-phy@11e40000 { + compatible = "mediatek,mt8192-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x11e40000 0x1000>; + + u2port0: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + }; + + u3port0: usb-phy@700 { + reg = <0x700 0x900>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + + mipi_tx0: dsi-phy@11e50000 { + compatible = "mediatek,mt8183-mipi-tx"; + reg = <0 0x11e50000 0 0x1000>; + clocks = <&apmixedsys CLK_APMIXED_MIPID26M>; + #clock-cells = <0>; + #phy-cells = <0>; + clock-output-names = "mipi_tx0_pll"; + status = "disabled"; + }; + + i2c0: i2c@11f00000 { + compatible = "mediatek,mt8192-i2c"; + reg = <0 0x11f00000 0 0x1000>, + <0 0x10217080 0 0x80>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>, + <&infracfg CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@11f01000 { + compatible = "mediatek,mt8192-i2c"; + reg = <0 0x11f01000 0 0x1000>, + <0 0x10217580 0 0x80>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>, + <&infracfg CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + imp_iic_wrap_n: clock-controller@11f02000 { + compatible = "mediatek,mt8192-imp_iic_wrap_n"; + reg = <0 0x11f02000 0 0x1000>; + #clock-cells = <1>; + }; + + msdc_top: clock-controller@11f10000 { + compatible = "mediatek,mt8192-msdc_top"; + reg = <0 0x11f10000 0 0x1000>; + #clock-cells = <1>; + }; + + mmc0: mmc@11f60000 { + compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; + reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, + <&msdc_top CLK_MSDC_TOP_H_MST_0P>, + <&msdc_top CLK_MSDC_TOP_SRC_0P>, + <&msdc_top CLK_MSDC_TOP_P_CFG>, + <&msdc_top CLK_MSDC_TOP_P_MSDC0>, + <&msdc_top CLK_MSDC_TOP_AXI>, + <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; + clock-names = "source", "hclk", "source_cg", "sys_cg", + "pclk_cg", "axi_cg", "ahb_cg"; + status = "disabled"; + }; + + mmc1: mmc@11f70000 { + compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; + reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, + <&msdc_top CLK_MSDC_TOP_H_MST_1P>, + <&msdc_top CLK_MSDC_TOP_SRC_1P>, + <&msdc_top CLK_MSDC_TOP_P_CFG>, + <&msdc_top CLK_MSDC_TOP_P_MSDC1>, + <&msdc_top CLK_MSDC_TOP_AXI>, + <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; + clock-names = "source", "hclk", "source_cg", "sys_cg", + "pclk_cg", "axi_cg", "ahb_cg"; + status = "disabled"; + }; + + mfgcfg: clock-controller@13fbf000 { + compatible = "mediatek,mt8192-mfgcfg"; + reg = <0 0x13fbf000 0 0x1000>; + #clock-cells = <1>; + }; + + mmsys: syscon@14000000 { + compatible = "mediatek,mt8192-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; + }; + + mutex: mutex@14001000 { + compatible = "mediatek,mt8192-disp-mutex"; + reg = <0 0x14001000 0 0x1000>; + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&mmsys CLK_MM_DISP_MUTEX0>; + mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>, + <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + }; + + smi_common: smi@14002000 { + compatible = "mediatek,mt8192-smi-common"; + reg = <0 0x14002000 0 0x1000>; + clocks = <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_INFRA>, + <&mmsys CLK_MM_SMI_GALS>, + <&mmsys CLK_MM_SMI_GALS>; + clock-names = "apb", "smi", "gals0", "gals1"; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + }; + + larb0: larb@14003000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x14003000 0 0x1000>; + mediatek,larb-id = <0>; + mediatek,smi = <&smi_common>; + clocks = <&clk26m>, <&clk26m>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + }; + + larb1: larb@14004000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x14004000 0 0x1000>; + mediatek,larb-id = <1>; + mediatek,smi = <&smi_common>; + clocks = <&clk26m>, <&clk26m>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + }; + + ovl0: ovl@14005000 { + compatible = "mediatek,mt8192-disp-ovl"; + reg = <0 0x14005000 0 0x1000>; + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&mmsys CLK_MM_DISP_OVL0>; + iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>, + <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; + }; + + ovl_2l0: ovl@14006000 { + compatible = "mediatek,mt8192-disp-ovl-2l"; + reg = <0 0x14006000 0 0x1000>; + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; + iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; + }; + + rdma0: rdma@14007000 { + compatible = "mediatek,mt8192-disp-rdma", + "mediatek,mt8183-disp-rdma"; + reg = <0 0x14007000 0 0x1000>; + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&mmsys CLK_MM_DISP_RDMA0>; + iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>; + mediatek,rdma-fifo-size = <5120>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>; + }; + + color0: color@14009000 { + compatible = "mediatek,mt8192-disp-color", + "mediatek,mt8173-disp-color"; + reg = <0 0x14009000 0 0x1000>; + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_COLOR0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; + }; + + ccorr0: ccorr@1400a000 { + compatible = "mediatek,mt8192-disp-ccorr"; + reg = <0 0x1400a000 0 0x1000>; + interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_CCORR0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; + }; + + aal0: aal@1400b000 { + compatible = "mediatek,mt8192-disp-aal", + "mediatek,mt8183-disp-aal"; + reg = <0 0x1400b000 0 0x1000>; + interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_AAL0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; + }; + + gamma0: gamma@1400c000 { + compatible = "mediatek,mt8192-disp-gamma", + "mediatek,mt8183-disp-gamma"; + reg = <0 0x1400c000 0 0x1000>; + interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_GAMMA0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; + }; + + postmask0: postmask@1400d000 { + compatible = "mediatek,mt8192-disp-postmask"; + reg = <0 0x1400d000 0 0x1000>; + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; + }; + + dither0: dither@1400e000 { + compatible = "mediatek,mt8192-disp-dither", + "mediatek,mt8183-disp-dither"; + reg = <0 0x1400e000 0 0x1000>; + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_DITHER0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; + }; + + dsi0: dsi@14010000 { + compatible = "mediatek,mt8183-dsi"; + reg = <0 0x14010000 0 0x1000>; + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&mmsys CLK_MM_DSI0>, + <&mmsys CLK_MM_DSI_DSI0>, + <&mipi_tx0>; + clock-names = "engine", "digital", "hs"; + phys = <&mipi_tx0>; + phy-names = "dphy"; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>; + status = "disabled"; + + port { + dsi_out: endpoint { }; + }; + }; + + ovl_2l2: ovl@14014000 { + compatible = "mediatek,mt8192-disp-ovl-2l"; + reg = <0 0x14014000 0 0x1000>; + interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_OVL2_2L>; + iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; + }; + + rdma4: rdma@14015000 { + compatible = "mediatek,mt8192-disp-rdma", + "mediatek,mt8183-disp-rdma"; + reg = <0 0x14015000 0 0x1000>; + interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_RDMA4>; + iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>; + mediatek,rdma-fifo-size = <2048>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; + }; + + dpi0: dpi@14016000 { + compatible = "mediatek,mt8192-dpi"; + reg = <0 0x14016000 0 0x1000>; + interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&mmsys CLK_MM_DPI_DPI0>, + <&mmsys CLK_MM_DISP_DPI0>, + <&apmixedsys CLK_APMIXED_TVDPLL>; + clock-names = "pixel", "engine", "pll"; + status = "disabled"; + }; + + iommu0: m4u@1401d000 { + compatible = "mediatek,mt8192-m4u"; + reg = <0 0x1401d000 0 0x1000>; + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, + <&larb4>, <&larb5>, <&larb7>, + <&larb9>, <&larb11>, <&larb13>, + <&larb14>, <&larb16>, <&larb17>, + <&larb18>, <&larb19>, <&larb20>; + interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&mmsys CLK_MM_SMI_IOMMU>; + clock-names = "bclk"; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + #iommu-cells = <1>; + }; + + imgsys: clock-controller@15020000 { + compatible = "mediatek,mt8192-imgsys"; + reg = <0 0x15020000 0 0x1000>; + #clock-cells = <1>; + }; + + larb9: larb@1502e000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1502e000 0 0x1000>; + mediatek,larb-id = <9>; + mediatek,smi = <&smi_common>; + clocks = <&imgsys CLK_IMG_LARB9>, + <&imgsys CLK_IMG_LARB9>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_ISP>; + }; + + imgsys2: clock-controller@15820000 { + compatible = "mediatek,mt8192-imgsys2"; + reg = <0 0x15820000 0 0x1000>; + #clock-cells = <1>; + }; + + larb11: larb@1582e000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1582e000 0 0x1000>; + mediatek,larb-id = <11>; + mediatek,smi = <&smi_common>; + clocks = <&imgsys2 CLK_IMG2_LARB11>, + <&imgsys2 CLK_IMG2_LARB11>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>; + }; + + larb5: larb@1600d000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1600d000 0 0x1000>; + mediatek,larb-id = <5>; + mediatek,smi = <&smi_common>; + clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, + <&vdecsys_soc CLK_VDEC_SOC_LARB1>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; + }; + + vdecsys_soc: clock-controller@1600f000 { + compatible = "mediatek,mt8192-vdecsys_soc"; + reg = <0 0x1600f000 0 0x1000>; + #clock-cells = <1>; + }; + + larb4: larb@1602e000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1602e000 0 0x1000>; + mediatek,larb-id = <4>; + mediatek,smi = <&smi_common>; + clocks = <&vdecsys CLK_VDEC_SOC_LARB1>, + <&vdecsys CLK_VDEC_SOC_LARB1>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; + }; + + vdecsys: clock-controller@1602f000 { + compatible = "mediatek,mt8192-vdecsys"; + reg = <0 0x1602f000 0 0x1000>; + #clock-cells = <1>; + }; + + vencsys: clock-controller@17000000 { + compatible = "mediatek,mt8192-vencsys"; + reg = <0 0x17000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb7: larb@17010000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x17010000 0 0x1000>; + mediatek,larb-id = <7>; + mediatek,smi = <&smi_common>; + clocks = <&vencsys CLK_VENC_SET0_LARB>, + <&vencsys CLK_VENC_SET1_VENC>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; + }; + + vcodec_enc: vcodec@17020000 { + compatible = "mediatek,mt8192-vcodec-enc"; + reg = <0 0x17020000 0 0x2000>; + iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>, + <&iommu0 M4U_PORT_L7_VENC_REC>, + <&iommu0 M4U_PORT_L7_VENC_BSDMA>, + <&iommu0 M4U_PORT_L7_VENC_SV_COMV>, + <&iommu0 M4U_PORT_L7_VENC_RD_COMV>, + <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>, + <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>, + <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>, + <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>, + <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>, + <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>; + interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>; + mediatek,scp = <&scp>; + power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; + clocks = <&vencsys CLK_VENC_SET1_VENC>; + clock-names = "venc-set1"; + assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + }; + + camsys: clock-controller@1a000000 { + compatible = "mediatek,mt8192-camsys"; + reg = <0 0x1a000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb13: larb@1a001000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1a001000 0 0x1000>; + mediatek,larb-id = <13>; + mediatek,smi = <&smi_common>; + clocks = <&camsys CLK_CAM_CAM>, + <&camsys CLK_CAM_LARB13>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; + }; + + larb14: larb@1a002000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1a002000 0 0x1000>; + mediatek,larb-id = <14>; + mediatek,smi = <&smi_common>; + clocks = <&camsys CLK_CAM_CAM>, + <&camsys CLK_CAM_LARB14>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; + }; + + larb16: larb@1a00f000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1a00f000 0 0x1000>; + mediatek,larb-id = <16>; + mediatek,smi = <&smi_common>; + clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>, + <&camsys_rawa CLK_CAM_RAWA_LARBX>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>; + }; + + larb17: larb@1a010000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1a010000 0 0x1000>; + mediatek,larb-id = <17>; + mediatek,smi = <&smi_common>; + clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>, + <&camsys_rawb CLK_CAM_RAWB_LARBX>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>; + }; + + larb18: larb@1a011000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1a011000 0 0x1000>; + mediatek,larb-id = <18>; + mediatek,smi = <&smi_common>; + clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>, + <&camsys_rawc CLK_CAM_RAWC_CAM>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>; + }; + + camsys_rawa: clock-controller@1a04f000 { + compatible = "mediatek,mt8192-camsys_rawa"; + reg = <0 0x1a04f000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_rawb: clock-controller@1a06f000 { + compatible = "mediatek,mt8192-camsys_rawb"; + reg = <0 0x1a06f000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_rawc: clock-controller@1a08f000 { + compatible = "mediatek,mt8192-camsys_rawc"; + reg = <0 0x1a08f000 0 0x1000>; + #clock-cells = <1>; + }; + + ipesys: clock-controller@1b000000 { + compatible = "mediatek,mt8192-ipesys"; + reg = <0 0x1b000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb20: larb@1b00f000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1b00f000 0 0x1000>; + mediatek,larb-id = <20>; + mediatek,smi = <&smi_common>; + clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, + <&ipesys CLK_IPE_LARB20>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; + }; + + larb19: larb@1b10f000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1b10f000 0 0x1000>; + mediatek,larb-id = <19>; + mediatek,smi = <&smi_common>; + clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, + <&ipesys CLK_IPE_LARB19>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; + }; + + mdpsys: clock-controller@1f000000 { + compatible = "mediatek,mt8192-mdpsys"; + reg = <0 0x1f000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb2: larb@1f002000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1f002000 0 0x1000>; + mediatek,larb-id = <2>; + mediatek,smi = <&smi_common>; + clocks = <&mdpsys CLK_MDP_SMI0>, + <&mdpsys CLK_MDP_SMI0>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts new file mode 100644 index 000000000..3348ba69f --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + */ +/dts-v1/; +#include "mt8195-cherry.dtsi" + +/ { + model = "Acer Tomato (rev1) board"; + compatible = "google,tomato-rev1", "google,tomato", "mediatek,mt8195"; +}; + +&ts_10 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts new file mode 100644 index 000000000..4669e9d91 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + */ +/dts-v1/; +#include "mt8195-cherry.dtsi" + +/ { + model = "Acer Tomato (rev2) board"; + compatible = "google,tomato-rev2", "google,tomato", "mediatek,mt8195"; +}; + +&pio_default { + pins-low-power-hdmi-disable { + pinmux = <PINMUX_GPIO31__FUNC_GPIO31>, + <PINMUX_GPIO32__FUNC_GPIO32>, + <PINMUX_GPIO33__FUNC_GPIO33>, + <PINMUX_GPIO34__FUNC_GPIO34>, + <PINMUX_GPIO35__FUNC_GPIO35>; + input-enable; + bias-pull-down; + }; + + pins-low-power-pcie0-disable { + pinmux = <PINMUX_GPIO19__FUNC_GPIO19>, + <PINMUX_GPIO20__FUNC_GPIO20>, + <PINMUX_GPIO21__FUNC_GPIO21>; + input-enable; + bias-pull-down; + }; +}; + +&ts_10 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts new file mode 100644 index 000000000..5021edd02 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + */ +/dts-v1/; +#include "mt8195-cherry.dtsi" + +/ { + model = "Acer Tomato (rev3 - 4) board"; + compatible = "google,tomato-rev4", "google,tomato-rev3", + "google,tomato", "mediatek,mt8195"; +}; + +&pio_default { + pins-low-power-hdmi-disable { + pinmux = <PINMUX_GPIO31__FUNC_GPIO31>, + <PINMUX_GPIO32__FUNC_GPIO32>, + <PINMUX_GPIO33__FUNC_GPIO33>, + <PINMUX_GPIO34__FUNC_GPIO34>, + <PINMUX_GPIO35__FUNC_GPIO35>; + input-enable; + bias-pull-down; + }; + + pins-low-power-pcie0-disable { + pinmux = <PINMUX_GPIO19__FUNC_GPIO19>, + <PINMUX_GPIO20__FUNC_GPIO20>, + <PINMUX_GPIO21__FUNC_GPIO21>; + input-enable; + bias-pull-down; + }; +}; + +&ts_10 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi new file mode 100644 index 000000000..4b8a1c462 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -0,0 +1,958 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/spmi/spmi.h> +#include "mt8195.dtsi" +#include "mt6359.dtsi" + +/ { + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c7 = &i2c7; + mmc0 = &mmc0; + mmc1 = &mmc1; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; + + /* system wide LDO 3.3V power rail */ + pp3300_z5: regulator-pp3300-ldo-z5 { + compatible = "regulator-fixed"; + regulator-name = "pp3300_ldo_z5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&ppvar_sys>; + }; + + /* separately switched 3.3V power rail */ + pp3300_s3: regulator-pp3300-s3 { + compatible = "regulator-fixed"; + regulator-name = "pp3300_s3"; + /* automatically sequenced by PMIC EXT_PMIC_EN2 */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&pp3300_z2>; + }; + + /* system wide 3.3V power rail */ + pp3300_z2: regulator-pp3300-z2 { + compatible = "regulator-fixed"; + regulator-name = "pp3300_z2"; + /* EN pin tied to pp4200_z2, which is controlled by EC */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&ppvar_sys>; + }; + + /* system wide 4.2V power rail */ + pp4200_z2: regulator-pp4200-z2 { + compatible = "regulator-fixed"; + regulator-name = "pp4200_z2"; + /* controlled by EC */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + vin-supply = <&ppvar_sys>; + }; + + /* system wide switching 5.0V power rail */ + pp5000_s5: regulator-pp5000-s5 { + compatible = "regulator-fixed"; + regulator-name = "pp5000_s5"; + /* controlled by EC */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&ppvar_sys>; + }; + + /* system wide semi-regulated power rail from battery or USB */ + ppvar_sys: regulator-ppvar-sys { + compatible = "regulator-fixed"; + regulator-name = "ppvar_sys"; + regulator-always-on; + regulator-boot-on; + }; + + usb_vbus: regulator-5v0-usb-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scp_mem: memory@50000000 { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x2900000>; + no-map; + }; + }; +}; + +&i2c0 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; +}; + +&i2c1 { + status = "okay"; + + clock-frequency = <400000>; + i2c-scl-internal-delay-ns = <12500>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + trackpad@15 { + compatible = "elan,ekth3000"; + reg = <0x15>; + interrupts-extended = <&pio 6 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_pins>; + vcc-supply = <&pp3300_s3>; + wakeup-source; + }; +}; + +&i2c2 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; +}; + +&i2c3 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + + tpm@50 { + compatible = "google,cr50"; + reg = <0x50>; + interrupts-extended = <&pio 88 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&cr50_int>; + }; +}; + +&i2c4 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + + ts_10: touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + hid-descr-addr = <0x0001>; + interrupts-extended = <&pio 92 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + post-power-on-delay-ms = <10>; + vdd-supply = <&pp3300_s3>; + status = "disabled"; + }; +}; + +&i2c5 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins>; +}; + +&i2c7 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_pins>; + + pmic@34 { + #interrupt-cells = <2>; + compatible = "mediatek,mt6360"; + reg = <0x34>; + interrupt-controller; + interrupts-extended = <&pio 130 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "IRQB"; + pinctrl-names = "default"; + pinctrl-0 = <&subpmic_default>; + wakeup-source; + }; +}; + +&mmc0 { + status = "okay"; + + bus-width = <8>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + hs400-ds-delay = <0x14c11>; + max-frequency = <200000000>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + no-sdio; + no-sd; + non-removable; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + vmmc-supply = <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply = <&mt6359_vufs_ldo_reg>; +}; + +&mmc1 { + status = "okay"; + + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&pio 54 GPIO_ACTIVE_LOW>; + max-frequency = <200000000>; + no-mmc; + no-sdio; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_pins_default>, <&mmc1_pins_detect>; + pinctrl-1 = <&mmc1_pins_default>; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&mt_pmic_vmch_ldo_reg>; + vqmmc-supply = <&mt_pmic_vmc_ldo_reg>; +}; + +/* for CPU-L */ +&mt6359_vcore_buck_reg { + regulator-always-on; +}; + +/* for CORE */ +&mt6359_vgpu11_buck_reg { + regulator-always-on; +}; + +&mt6359_vgpu11_sshub_buck_reg { + regulator-always-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <550000>; +}; + +/* for CORE SRAM */ +&mt6359_vpu_buck_reg { + regulator-always-on; +}; + +&mt6359_vrf12_ldo_reg { + regulator-always-on; +}; + +/* for GPU SRAM */ +&mt6359_vsram_others_ldo_reg { + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; +}; + +&mt6359_vufs_ldo_reg { + regulator-always-on; +}; + +&nor_flash { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&nor_pins_default>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <2>; + }; +}; + +&pio { + mediatek,rsel-resistance-in-si-unit; + pinctrl-names = "default"; + pinctrl-0 = <&pio_default>; + + /* 144 lines */ + gpio-line-names = + "I2S_SPKR_MCLK", + "I2S_SPKR_DATAIN", + "I2S_SPKR_LRCK", + "I2S_SPKR_BCLK", + "EC_AP_INT_ODL", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it AP_FLASH_WP_ODL. + */ + "AP_FLASH_WP_L", + "TCHPAD_INT_ODL", + "EDP_HPD_1V8", + "AP_I2C_CAM_SDA", + "AP_I2C_CAM_SCL", + "AP_I2C_TCHPAD_SDA_1V8", + "AP_I2C_TCHPAD_SCL_1V8", + "AP_I2C_AUD_SDA", + "AP_I2C_AUD_SCL", + "AP_I2C_TPM_SDA_1V8", + "AP_I2C_TPM_SCL_1V8", + "AP_I2C_TCHSCR_SDA_1V8", + "AP_I2C_TCHSCR_SCL_1V8", + "EC_AP_HPD_OD", + "", + "PCIE_NVME_RST_L", + "PCIE_NVME_CLKREQ_ODL", + "PCIE_RST_1V8_L", + "PCIE_CLKREQ_1V8_ODL", + "PCIE_WAKE_1V8_ODL", + "CLK_24M_CAM0", + "CAM1_SEN_EN", + "AP_I2C_PWR_SCL_1V8", + "AP_I2C_PWR_SDA_1V8", + "AP_I2C_MISC_SCL", + "AP_I2C_MISC_SDA", + "EN_PP5000_HDMI_X", + "AP_HDMITX_HTPLG", + "", + "AP_HDMITX_SCL_1V8", + "AP_HDMITX_SDA_1V8", + "AP_RTC_CLK32K", + "AP_EC_WATCHDOG_L", + "SRCLKENA0", + "SRCLKENA1", + "PWRAP_SPI0_CS_L", + "PWRAP_SPI0_CK", + "PWRAP_SPI0_MOSI", + "PWRAP_SPI0_MISO", + "SPMI_SCL", + "SPMI_SDA", + "", + "", + "", + "I2S_HP_DATAIN", + "I2S_HP_MCLK", + "I2S_HP_BCK", + "I2S_HP_LRCK", + "I2S_HP_DATAOUT", + "SD_CD_ODL", + "EN_PP3300_DISP_X", + "TCHSCR_RST_1V8_L", + "TCHSCR_REPORT_DISABLE", + "EN_PP3300_WLAN_X", + "BT_KILL_1V8_L", + "I2S_SPKR_DATAOUT", + "WIFI_KILL_1V8_L", + "BEEP_ON", + "SCP_I2C_SENSOR_SCL_1V8", + "SCP_I2C_SENSOR_SDA_1V8", + "", + "", + "", + "", + "AUD_CLK_MOSI", + "AUD_SYNC_MOSI", + "AUD_DAT_MOSI0", + "AUD_DAT_MOSI1", + "AUD_DAT_MISO0", + "AUD_DAT_MISO1", + "AUD_DAT_MISO2", + "SCP_VREQ_VAO", + "AP_SPI_GSC_TPM_CLK", + "AP_SPI_GSC_TPM_MOSI", + "AP_SPI_GSC_TPM_CS_L", + "AP_SPI_GSC_TPM_MISO", + "EN_PP1000_CAM_X", + "AP_EDP_BKLTEN", + "", + "USB3_HUB_RST_L", + "", + "WLAN_ALERT_ODL", + "EC_IN_RW_ODL", + "GSC_AP_INT_ODL", + "HP_INT_ODL", + "CAM0_RST_L", + "CAM1_RST_L", + "TCHSCR_INT_1V8_L", + "CAM1_DET_L", + "RST_ALC1011_L", + "", + "", + "BL_PWM_1V8", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "EN_SPKR", + "AP_EC_WARM_RST_REQ", + "UART_SCP_TX_DBGCON_RX", + "UART_DBGCON_TX_SCP_RX", + "", + "", + "KPCOL0", + "", + "MT6315_GPU_INT", + "MT6315_PROC_BC_INT", + "SD_CMD", + "SD_CLK", + "SD_DAT0", + "SD_DAT1", + "SD_DAT2", + "SD_DAT3", + "EMMC_DAT7", + "EMMC_DAT6", + "EMMC_DAT5", + "EMMC_DAT4", + "EMMC_RSTB", + "EMMC_CMD", + "EMMC_CLK", + "EMMC_DAT3", + "EMMC_DAT2", + "EMMC_DAT1", + "EMMC_DAT0", + "EMMC_DSL", + "", + "", + "MT6360_INT_ODL", + "SCP_JTAG0_TRSTN", + "AP_SPI_EC_CS_L", + "AP_SPI_EC_CLK", + "AP_SPI_EC_MOSI", + "AP_SPI_EC_MISO", + "SCP_JTAG0_TMS", + "SCP_JTAG0_TCK", + "SCP_JTAG0_TDO", + "SCP_JTAG0_TDI", + "AP_SPI_FLASH_CS_L", + "AP_SPI_FLASH_CLK", + "AP_SPI_FLASH_MOSI", + "AP_SPI_FLASH_MISO"; + + cr50_int: cr50-irq-default-pins { + pins-gsc-ap-int-odl { + pinmux = <PINMUX_GPIO88__FUNC_GPIO88>; + input-enable; + }; + }; + + cros_ec_int: cros-ec-irq-default-pins { + pins-ec-ap-int-odl { + pinmux = <PINMUX_GPIO4__FUNC_GPIO4>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + input-enable; + }; + }; + + i2c0_pins: i2c0-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO8__FUNC_SDA0>, + <PINMUX_GPIO9__FUNC_SCL0>; + bias-disable; + drive-strength-microamp = <1000>; + }; + }; + + i2c1_pins: i2c1-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO10__FUNC_SDA1>, + <PINMUX_GPIO11__FUNC_SCL1>; + bias-pull-up = <1000>; + drive-strength-microamp = <1000>; + }; + }; + + i2c2_pins: i2c2-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO12__FUNC_SDA2>, + <PINMUX_GPIO13__FUNC_SCL2>; + bias-disable; + drive-strength-microamp = <1000>; + }; + }; + + i2c3_pins: i2c3-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO14__FUNC_SDA3>, + <PINMUX_GPIO15__FUNC_SCL3>; + bias-pull-up = <1000>; + drive-strength-microamp = <1000>; + }; + }; + + i2c4_pins: i2c4-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO16__FUNC_SDA4>, + <PINMUX_GPIO17__FUNC_SCL4>; + bias-pull-up = <1000>; + drive-strength = <4>; + }; + }; + + i2c5_pins: i2c5-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO29__FUNC_SCL5>, + <PINMUX_GPIO30__FUNC_SDA5>; + bias-disable; + drive-strength-microamp = <1000>; + }; + }; + + i2c7_pins: i2c7-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO27__FUNC_SCL7>, + <PINMUX_GPIO28__FUNC_SDA7>; + bias-disable; + }; + }; + + mmc0_pins_default: mmc0-default-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, + <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, + <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, + <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, + <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, + <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, + <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, + <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, + <PINMUX_GPIO121__FUNC_MSDC0_CMD>; + input-enable; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-clk { + pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; + drive-strength = <6>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-rst { + pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + mmc0_pins_uhs: mmc0-uhs-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, + <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, + <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, + <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, + <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, + <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, + <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, + <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, + <PINMUX_GPIO121__FUNC_MSDC0_CMD>; + input-enable; + drive-strength = <8>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-clk { + pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; + drive-strength = <8>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-ds { + pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>; + drive-strength = <8>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-rst { + pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; + drive-strength = <8>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + mmc1_pins_detect: mmc1-detect-pins { + pins-insert { + pinmux = <PINMUX_GPIO54__FUNC_GPIO54>; + bias-pull-up; + }; + }; + + mmc1_pins_default: mmc1-default-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>, + <PINMUX_GPIO112__FUNC_MSDC1_DAT0>, + <PINMUX_GPIO113__FUNC_MSDC1_DAT1>, + <PINMUX_GPIO114__FUNC_MSDC1_DAT2>, + <PINMUX_GPIO115__FUNC_MSDC1_DAT3>; + input-enable; + drive-strength = <8>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-clk { + pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>; + drive-strength = <8>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + }; + + nor_pins_default: nor-default-pins { + pins-ck-io { + pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>, + <PINMUX_GPIO141__FUNC_SPINOR_CK>, + <PINMUX_GPIO143__FUNC_SPINOR_IO1>; + drive-strength = <6>; + bias-pull-down; + }; + + pins-cs { + pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>; + drive-strength = <6>; + bias-pull-up; + }; + }; + + pio_default: pio-default-pins { + pins-wifi-enable { + pinmux = <PINMUX_GPIO58__FUNC_GPIO58>; + output-high; + drive-strength = <14>; + }; + + pins-low-power-pd { + pinmux = <PINMUX_GPIO25__FUNC_GPIO25>, + <PINMUX_GPIO26__FUNC_GPIO26>, + <PINMUX_GPIO46__FUNC_GPIO46>, + <PINMUX_GPIO47__FUNC_GPIO47>, + <PINMUX_GPIO48__FUNC_GPIO48>, + <PINMUX_GPIO65__FUNC_GPIO65>, + <PINMUX_GPIO66__FUNC_GPIO66>, + <PINMUX_GPIO67__FUNC_GPIO67>, + <PINMUX_GPIO68__FUNC_GPIO68>, + <PINMUX_GPIO128__FUNC_GPIO128>, + <PINMUX_GPIO129__FUNC_GPIO129>; + input-enable; + bias-pull-down; + }; + + pins-low-power-pupd { + pinmux = <PINMUX_GPIO77__FUNC_GPIO77>, + <PINMUX_GPIO78__FUNC_GPIO78>, + <PINMUX_GPIO79__FUNC_GPIO79>, + <PINMUX_GPIO80__FUNC_GPIO80>, + <PINMUX_GPIO83__FUNC_GPIO83>, + <PINMUX_GPIO85__FUNC_GPIO85>, + <PINMUX_GPIO90__FUNC_GPIO90>, + <PINMUX_GPIO91__FUNC_GPIO91>, + <PINMUX_GPIO93__FUNC_GPIO93>, + <PINMUX_GPIO94__FUNC_GPIO94>, + <PINMUX_GPIO95__FUNC_GPIO95>, + <PINMUX_GPIO96__FUNC_GPIO96>, + <PINMUX_GPIO104__FUNC_GPIO104>, + <PINMUX_GPIO105__FUNC_GPIO105>, + <PINMUX_GPIO107__FUNC_GPIO107>; + input-enable; + bias-pull-down = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + scp_pins: scp-default-pins { + pins-vreq { + pinmux = <PINMUX_GPIO76__FUNC_SCP_VREQ_VAO>; + bias-disable; + input-enable; + }; + }; + + spi0_pins: spi0-default-pins { + pins-cs-mosi-clk { + pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>, + <PINMUX_GPIO134__FUNC_SPIM0_MO>, + <PINMUX_GPIO133__FUNC_SPIM0_CLK>; + bias-disable; + }; + + pins-miso { + pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>; + bias-pull-down; + }; + }; + + subpmic_default: subpmic-default-pins { + subpmic_pin_irq: pins-subpmic-int-n { + pinmux = <PINMUX_GPIO130__FUNC_GPIO130>; + input-enable; + bias-pull-up; + }; + }; + + trackpad_pins: trackpad-default-pins { + pins-int-n { + pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; + input-enable; + bias-pull-up; + }; + }; + + touchscreen_pins: touchscreen-default-pins { + pins-int-n { + pinmux = <PINMUX_GPIO92__FUNC_GPIO92>; + input-enable; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + pins-rst { + pinmux = <PINMUX_GPIO56__FUNC_GPIO56>; + output-high; + }; + pins-report-sw { + pinmux = <PINMUX_GPIO57__FUNC_GPIO57>; + output-low; + }; + }; +}; + +&pmic { + interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; +}; + +&scp { + status = "okay"; + + firmware-name = "mediatek/mt8195/scp.img"; + memory-region = <&scp_mem>; + pinctrl-names = "default"; + pinctrl-0 = <&scp_pins>; + + cros-ec-rpmsg { + compatible = "google,cros-ec-rpmsg"; + mediatek,rpmsg-name = "cros-ec-rpmsg"; + }; +}; + +&spi0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + mediatek,pad-select = <0>; + + cros_ec: ec@0 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "google,cros-ec-spi"; + reg = <0>; + interrupts-extended = <&pio 4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cros_ec_int>; + spi-max-frequency = <3000000>; + + keyboard-backlight { + compatible = "google,cros-kbd-led-backlight"; + }; + + i2c_tunnel: i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + google,remote-bus = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mt_pmic_vmc_ldo_reg: regulator@0 { + compatible = "google,cros-ec-regulator"; + reg = <0>; + regulator-name = "mt_pmic_vmc_ldo"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + }; + + mt_pmic_vmch_ldo_reg: regulator@1 { + compatible = "google,cros-ec-regulator"; + reg = <1>; + regulator-name = "mt_pmic_vmch_ldo"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3600000>; + }; + + typec { + compatible = "google,cros-ec-typec"; + #address-cells = <1>; + #size-cells = <0>; + + usb_c0: connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "host"; + try-power-role = "source"; + }; + + usb_c1: connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "host"; + try-power-role = "source"; + }; + }; + }; +}; + +&spmi { + #address-cells = <2>; + #size-cells = <0>; + + mt6315@6 { + compatible = "mediatek,mt6315-regulator"; + reg = <0x6 SPMI_USID>; + + regulators { + mt6315_6_vbuck1: vbuck1 { + regulator-compatible = "vbuck1"; + regulator-name = "Vbcpu"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-ramp-delay = <6250>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + }; + }; + + mt6315@7 { + compatible = "mediatek,mt6315-regulator"; + reg = <0x7 SPMI_USID>; + + regulators { + mt6315_7_vbuck1: vbuck1 { + regulator-compatible = "vbuck1"; + regulator-name = "Vgpu"; + regulator-min-microvolt = <625000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-ramp-delay = <6250>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + }; + }; +}; + +&u3phy0 { + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&u3phy2 { + status = "okay"; +}; + +&u3phy3 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&xhci0 { + status = "okay"; + + vusb33-supply = <&mt6359_vusb_ldo_reg>; + vbus-supply = <&usb_vbus>; +}; + +&xhci1 { + status = "okay"; + + vusb33-supply = <&mt6359_vusb_ldo_reg>; + vbus-supply = <&usb_vbus>; +}; + +&xhci2 { + status = "okay"; + + vusb33-supply = <&mt6359_vusb_ldo_reg>; + vbus-supply = <&usb_vbus>; +}; + +&xhci3 { + status = "okay"; + + /* MT7921's USB Bluetooth has issues with USB2 LPM */ + usb2-lpm-disable; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + vbus-supply = <&usb_vbus>; +}; + +#include <arm/cros-ec-keyboard.dtsi> +#include <arm/cros-ec-sbs.dtsi> + +&keyboard_controller { + function-row-physmap = < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + + linux,keymap = < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + + CROS_STD_MAIN_KEYMAP + >; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts new file mode 100644 index 000000000..5117b2e79 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts @@ -0,0 +1,473 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 BayLibre, SAS. + * Author: Fabien Parent <fparent@baylibre.com> + */ +/dts-v1/; + +#include "mt8195.dtsi" +#include "mt6359.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/mt8195-pinfunc.h> +#include <dt-bindings/regulator/mediatek,mt6360-regulator.h> + +/ { + model = "MediaTek MT8195 demo board"; + compatible = "mediatek,mt8195-demo", "mediatek,mt8195"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pins>; + + key-0 { + gpios = <&pio 106 GPIO_ACTIVE_LOW>; + label = "volume_up"; + linux,code = <KEY_VOLUMEUP>; + wakeup-source; + debounce-interval = <15>; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0x2 0x00000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg = <0 0x43200000 0 0x00c00000>; + }; + + scp_mem: memory@50000000 { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x2900000>; + no-map; + }; + + vpu_mem: memory@53000000 { + compatible = "shared-dma-pool"; + reg = <0 0x53000000 0 0x1400000>; /* 20 MB */ + }; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_mem: memory@54600000 { + no-map; + reg = <0 0x54600000 0x0 0x200000>; + }; + + snd_dma_mem: memory@60000000 { + compatible = "shared-dma-pool"; + reg = <0 0x60000000 0 0x1100000>; + no-map; + }; + + apu_mem: memory@62000000 { + compatible = "shared-dma-pool"; + reg = <0 0x62000000 0 0x1400000>; /* 20 MB */ + }; + }; +}; + +&i2c6 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c6_pins>; + pinctrl-names = "default"; + status = "okay"; + + mt6360: pmic@34 { + compatible = "mediatek,mt6360"; + reg = <0x34>; + interrupt-controller; + interrupts-extended = <&pio 101 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "IRQB"; + + charger { + compatible = "mediatek,mt6360-chg"; + richtek,vinovp-microvolt = <14500000>; + + otg_vbus_regulator: usb-otg-vbus-regulator { + regulator-compatible = "usb-otg-vbus"; + regulator-name = "usb-otg-vbus"; + regulator-min-microvolt = <4425000>; + regulator-max-microvolt = <5825000>; + }; + }; + + regulator { + compatible = "mediatek,mt6360-regulator"; + LDO_VIN3-supply = <&mt6360_buck2>; + + mt6360_buck1: buck1 { + regulator-compatible = "BUCK1"; + regulator-name = "mt6360,buck1"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1300000>; + regulator-allowed-modes = <MT6360_OPMODE_NORMAL + MT6360_OPMODE_LP + MT6360_OPMODE_ULP>; + regulator-always-on; + }; + + mt6360_buck2: buck2 { + regulator-compatible = "BUCK2"; + regulator-name = "mt6360,buck2"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1300000>; + regulator-allowed-modes = <MT6360_OPMODE_NORMAL + MT6360_OPMODE_LP + MT6360_OPMODE_ULP>; + regulator-always-on; + }; + + mt6360_ldo1: ldo1 { + regulator-compatible = "LDO1"; + regulator-name = "mt6360,ldo1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-allowed-modes = <MT6360_OPMODE_NORMAL + MT6360_OPMODE_LP>; + }; + + mt6360_ldo2: ldo2 { + regulator-compatible = "LDO2"; + regulator-name = "mt6360,ldo2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-allowed-modes = <MT6360_OPMODE_NORMAL + MT6360_OPMODE_LP>; + }; + + mt6360_ldo3: ldo3 { + regulator-compatible = "LDO3"; + regulator-name = "mt6360,ldo3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-allowed-modes = <MT6360_OPMODE_NORMAL + MT6360_OPMODE_LP>; + }; + + mt6360_ldo5: ldo5 { + regulator-compatible = "LDO5"; + regulator-name = "mt6360,ldo5"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3600000>; + regulator-allowed-modes = <MT6360_OPMODE_NORMAL + MT6360_OPMODE_LP>; + }; + + mt6360_ldo6: ldo6 { + regulator-compatible = "LDO6"; + regulator-name = "mt6360,ldo6"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2100000>; + regulator-allowed-modes = <MT6360_OPMODE_NORMAL + MT6360_OPMODE_LP>; + }; + + mt6360_ldo7: ldo7 { + regulator-compatible = "LDO7"; + regulator-name = "mt6360,ldo7"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2100000>; + regulator-allowed-modes = <MT6360_OPMODE_NORMAL + MT6360_OPMODE_LP>; + regulator-always-on; + }; + }; + }; +}; + +&mmc0 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_default_pins>; + pinctrl-1 = <&mmc0_uhs_pins>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cap-mmc-hw-reset; + no-sdio; + no-sd; + hs400-ds-delay = <0x14c11>; + vmmc-supply = <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply = <&mt6359_vufs_ldo_reg>; + non-removable; +}; + +&mmc1 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_default_pins>; + pinctrl-1 = <&mmc1_uhs_pins>; + cd-gpios = <&pio 129 GPIO_ACTIVE_LOW>; + bus-width = <4>; + max-frequency = <200000000>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&mt6360_ldo5>; + vqmmc-supply = <&mt6360_ldo3>; + status = "okay"; +}; + +&mt6359_vbbck_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcore_buck_reg { + regulator-always-on; +}; + +&mt6359_vgpu11_buck_reg { + regulator-always-on; +}; + +&mt6359_vproc1_buck_reg { + regulator-always-on; +}; + +&mt6359_vproc2_buck_reg { + regulator-always-on; +}; + +&mt6359_vpu_buck_reg { + regulator-always-on; +}; + +&mt6359_vrf12_ldo_reg { + regulator-always-on; +}; + +&mt6359_vsram_md_ldo_reg { + regulator-always-on; +}; + +&mt6359_vsram_others_ldo_reg { + regulator-always-on; +}; + +&pio { + gpio_keys_pins: gpio-keys-pins { + pins { + pinmux = <PINMUX_GPIO106__FUNC_GPIO106>; + input-enable; + }; + }; + + i2c6_pins: i2c6-pins { + pins { + pinmux = <PINMUX_GPIO25__FUNC_SDA6>, + <PINMUX_GPIO26__FUNC_SCL6>; + bias-pull-up; + }; + }; + + mmc0_default_pins: mmc0-default-pins { + pins-clk { + pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; + drive-strength = <MTK_DRIVE_6mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, + <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, + <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, + <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, + <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, + <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, + <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, + <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, + <PINMUX_GPIO121__FUNC_MSDC0_CMD>; + input-enable; + drive-strength = <MTK_DRIVE_6mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-rst { + pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; + drive-strength = <MTK_DRIVE_6mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + pins-clk { + pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, + <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, + <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, + <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, + <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, + <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, + <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, + <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, + <PINMUX_GPIO121__FUNC_MSDC0_CMD>; + input-enable; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-ds { + pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-rst { + pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + mmc1_default_pins: mmc1-default-pins { + pins-clk { + pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>, + <PINMUX_GPIO112__FUNC_MSDC1_DAT0>, + <PINMUX_GPIO113__FUNC_MSDC1_DAT1>, + <PINMUX_GPIO114__FUNC_MSDC1_DAT2>, + <PINMUX_GPIO115__FUNC_MSDC1_DAT3>; + input-enable; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-insert { + pinmux = <PINMUX_GPIO129__FUNC_GPIO129>; + bias-pull-up; + }; + }; + + mmc1_uhs_pins: mmc1-uhs-pins { + pins-clk { + pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>, + <PINMUX_GPIO112__FUNC_MSDC1_DAT0>, + <PINMUX_GPIO113__FUNC_MSDC1_DAT1>, + <PINMUX_GPIO114__FUNC_MSDC1_DAT2>, + <PINMUX_GPIO115__FUNC_MSDC1_DAT3>; + input-enable; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + uart0_pins: uart0-pins { + pins { + pinmux = <PINMUX_GPIO98__FUNC_UTXD0>, + <PINMUX_GPIO99__FUNC_URXD0>; + }; + }; + + uart1_pins: uart1-pins { + pins { + pinmux = <PINMUX_GPIO102__FUNC_UTXD1>, + <PINMUX_GPIO103__FUNC_URXD1>; + }; + }; +}; + + +&pmic { + interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + +&u3phy0 { + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&u3phy2 { + status = "okay"; +}; + +&u3phy3 { + status = "okay"; +}; + +&xhci0 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + vbus-supply = <&otg_vbus_regulator>; + status = "okay"; +}; + +&xhci1 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&xhci2 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&xhci3 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts new file mode 100644 index 000000000..690dc7717 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts @@ -0,0 +1,181 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Seiya Wang <seiya.wang@mediatek.com> + */ +/dts-v1/; +#include "mt8195.dtsi" + +/ { + model = "MediaTek MT8195 evaluation board"; + compatible = "mediatek,mt8195-evb", "mediatek,mt8195"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; +}; + +&auxadc { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pin>; + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pin>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pin>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pin>; + clock-frequency = <400000>; + status = "okay"; +}; + +&nor_flash { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nor_pins_default>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + }; +}; + +&pio { + i2c0_pin: i2c0-pins { + pins { + pinmux = <PINMUX_GPIO8__FUNC_SDA0>, + <PINMUX_GPIO9__FUNC_SCL0>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + mediatek,drive-strength-adv = <0>; + drive-strength = <6>; + }; + }; + + i2c1_pin: i2c1-pins { + pins { + pinmux = <PINMUX_GPIO10__FUNC_SDA1>, + <PINMUX_GPIO11__FUNC_SCL1>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + mediatek,drive-strength-adv = <0>; + drive-strength = <6>; + }; + }; + + i2c4_pin: i2c4-pins { + pins { + pinmux = <PINMUX_GPIO16__FUNC_SDA4>, + <PINMUX_GPIO17__FUNC_SCL4>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + mediatek,drive-strength-adv = <7>; + }; + }; + + i2c6_pin: i2c6-pins { + pins { + pinmux = <PINMUX_GPIO25__FUNC_SDA6>, + <PINMUX_GPIO26__FUNC_SCL6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + i2c7_pin: i2c7-pins { + pins { + pinmux = <PINMUX_GPIO27__FUNC_SCL7>, + <PINMUX_GPIO28__FUNC_SDA7>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + nor_pins_default: nor-pins { + pins0 { + pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>, + <PINMUX_GPIO141__FUNC_SPINOR_CK>, + <PINMUX_GPIO143__FUNC_SPINOR_IO1>; + bias-pull-down; + }; + + pins1 { + pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>, + <PINMUX_GPIO130__FUNC_SPINOR_IO2>, + <PINMUX_GPIO131__FUNC_SPINOR_IO3>; + bias-pull-up; + }; + }; + + uart0_pin: uart0-pins { + pins { + pinmux = <PINMUX_GPIO98__FUNC_UTXD0>, + <PINMUX_GPIO99__FUNC_URXD0>; + }; + }; +}; + +&u3phy0 { + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&u3phy2 { + status = "okay"; +}; + +&u3phy3 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pin>; + status = "okay"; +}; + +&xhci0 { + status = "okay"; +}; + +&xhci1 { + status = "okay"; +}; + +&xhci2 { + status = "okay"; +}; + +&xhci3 { + /* This controller is connected with a BT device. + * Disable usb2 lpm to prevent known issues. + */ + usb2-lpm-disable; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi new file mode 100644 index 000000000..414cbe345 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -0,0 +1,2171 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Seiya Wang <seiya.wang@mediatek.com> + */ + +/dts-v1/; +#include <dt-bindings/clock/mt8195-clk.h> +#include <dt-bindings/gce/mt8195-gce.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/memory/mt8195-memory-port.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/pinctrl/mt8195-pinfunc.h> +#include <dt-bindings/power/mt8195-power.h> + +/ { + compatible = "mediatek,mt8195"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + gce0 = &gce0; + gce1 = &gce1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x000>; + enable-method = "psci"; + performance-domains = <&performance 0>; + clock-frequency = <1701000000>; + capacity-dmips-mhz = <308>; + cpu-idle-states = <&cpu_off_l &cluster_off_l>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + performance-domains = <&performance 0>; + clock-frequency = <1701000000>; + capacity-dmips-mhz = <308>; + cpu-idle-states = <&cpu_off_l &cluster_off_l>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + performance-domains = <&performance 0>; + clock-frequency = <1701000000>; + capacity-dmips-mhz = <308>; + cpu-idle-states = <&cpu_off_l &cluster_off_l>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + performance-domains = <&performance 0>; + clock-frequency = <1701000000>; + capacity-dmips-mhz = <308>; + cpu-idle-states = <&cpu_off_l &cluster_off_l>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x400>; + enable-method = "psci"; + performance-domains = <&performance 1>; + clock-frequency = <2171000000>; + capacity-dmips-mhz = <1024>; + cpu-idle-states = <&cpu_off_b &cluster_off_b>; + next-level-cache = <&l2_1>; + #cooling-cells = <2>; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x500>; + enable-method = "psci"; + performance-domains = <&performance 1>; + clock-frequency = <2171000000>; + capacity-dmips-mhz = <1024>; + cpu-idle-states = <&cpu_off_b &cluster_off_b>; + next-level-cache = <&l2_1>; + #cooling-cells = <2>; + }; + + cpu6: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x600>; + enable-method = "psci"; + performance-domains = <&performance 1>; + clock-frequency = <2171000000>; + capacity-dmips-mhz = <1024>; + cpu-idle-states = <&cpu_off_b &cluster_off_b>; + next-level-cache = <&l2_1>; + #cooling-cells = <2>; + }; + + cpu7: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x700>; + enable-method = "psci"; + performance-domains = <&performance 1>; + clock-frequency = <2171000000>; + capacity-dmips-mhz = <1024>; + cpu-idle-states = <&cpu_off_b &cluster_off_b>; + next-level-cache = <&l2_1>; + #cooling-cells = <2>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + + core4 { + cpu = <&cpu4>; + }; + + core5 { + cpu = <&cpu5>; + }; + + core6 { + cpu = <&cpu6>; + }; + + core7 { + cpu = <&cpu7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + cpu_off_l: cpu-off-l { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x00010001>; + local-timer-stop; + entry-latency-us = <50>; + exit-latency-us = <95>; + min-residency-us = <580>; + }; + + cpu_off_b: cpu-off-b { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x00010001>; + local-timer-stop; + entry-latency-us = <45>; + exit-latency-us = <140>; + min-residency-us = <740>; + }; + + cluster_off_l: cluster-off-l { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x01010002>; + local-timer-stop; + entry-latency-us = <55>; + exit-latency-us = <155>; + min-residency-us = <840>; + }; + + cluster_off_b: cluster-off-b { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x01010002>; + local-timer-stop; + entry-latency-us = <50>; + exit-latency-us = <200>; + min-residency-us = <1000>; + }; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + next-level-cache = <&l3_0>; + }; + + l2_1: l2-cache1 { + compatible = "cache"; + next-level-cache = <&l3_0>; + }; + + l3_0: l3-cache { + compatible = "cache"; + }; + }; + + dsu-pmu { + compatible = "arm,dsu-pmu"; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; + cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, + <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + status = "fail"; + }; + + dmic_codec: dmic-codec { + compatible = "dmic-codec"; + num-channels = <2>; + wakeup-delay-ms = <50>; + }; + + sound: mt8195-sound { + mediatek,platform = <&afe>; + status = "disabled"; + }; + + clk13m: fixed-factor-clock-13m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk26m>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "clk13m"; + }; + + clk26m: oscillator-26m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + clk32k: oscillator-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "clk32k"; + }; + + performance: performance-controller@11bc10 { + compatible = "mediatek,cpufreq-hw"; + reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; + #performance-domain-cells = <1>; + }; + + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; + }; + + pmu-a78 { + compatible = "arm,cortex-a78-pmu"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer: timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <4>; + #redistributor-regions = <1>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x40000>, + <0 0x0c040000 0 0x200000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; + }; + }; + }; + + topckgen: syscon@10000000 { + compatible = "mediatek,mt8195-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg_ao: syscon@10001000 { + compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pericfg: syscon@10003000 { + compatible = "mediatek,mt8195-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + }; + + pio: pinctrl@10005000 { + compatible = "mediatek,mt8195-pinctrl"; + reg = <0 0x10005000 0 0x1000>, + <0 0x11d10000 0 0x1000>, + <0 0x11d30000 0 0x1000>, + <0 0x11d40000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11eb0000 0 0x1000>, + <0 0x11f40000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", + "iocfg_br", "iocfg_lm", "iocfg_rb", + "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 144>; + interrupt-controller; + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>; + #interrupt-cells = <2>; + }; + + scpsys: syscon@10006000 { + compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd"; + reg = <0 0x10006000 0 0x1000>; + + /* System Power Manager */ + spm: power-controller { + compatible = "mediatek,mt8195-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* power domain of the SoC */ + mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 { + reg = <MT8195_POWER_DOMAIN_MFG0>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8195_POWER_DOMAIN_MFG1 { + reg = <MT8195_POWER_DOMAIN_MFG1>; + clocks = <&apmixedsys CLK_APMIXED_MFGPLL>; + clock-names = "mfg"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8195_POWER_DOMAIN_MFG2 { + reg = <MT8195_POWER_DOMAIN_MFG2>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_MFG3 { + reg = <MT8195_POWER_DOMAIN_MFG3>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_MFG4 { + reg = <MT8195_POWER_DOMAIN_MFG4>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_MFG5 { + reg = <MT8195_POWER_DOMAIN_MFG5>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_MFG6 { + reg = <MT8195_POWER_DOMAIN_MFG6>; + #power-domain-cells = <0>; + }; + }; + }; + + power-domain@MT8195_POWER_DOMAIN_VPPSYS0 { + reg = <MT8195_POWER_DOMAIN_VPPSYS0>; + clocks = <&topckgen CLK_TOP_VPP>, + <&topckgen CLK_TOP_CAM>, + <&topckgen CLK_TOP_CCU>, + <&topckgen CLK_TOP_IMG>, + <&topckgen CLK_TOP_VENC>, + <&topckgen CLK_TOP_VDEC>, + <&topckgen CLK_TOP_WPE_VPP>, + <&topckgen CLK_TOP_CFG_VPP0>, + <&vppsys0 CLK_VPP0_SMI_COMMON>, + <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>, + <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>, + <&vppsys0 CLK_VPP0_GALS_VENCSYS>, + <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>, + <&vppsys0 CLK_VPP0_GALS_INFRA>, + <&vppsys0 CLK_VPP0_GALS_CAMSYS>, + <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>, + <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>, + <&vppsys0 CLK_VPP0_SMI_REORDER>, + <&vppsys0 CLK_VPP0_SMI_IOMMU>, + <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>, + <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, + <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>, + <&vppsys0 CLK_VPP0_SMI_RSI>, + <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, + <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, + <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, + <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; + clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3", + "vppsys4", "vppsys5", "vppsys6", "vppsys7", + "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3", + "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7", + "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11", + "vppsys0-12", "vppsys0-13", "vppsys0-14", + "vppsys0-15", "vppsys0-16", "vppsys0-17", + "vppsys0-18"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8195_POWER_DOMAIN_VDEC1 { + reg = <MT8195_POWER_DOMAIN_VDEC1>; + clocks = <&vdecsys CLK_VDEC_LARB1>; + clock-names = "vdec1-0"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 { + reg = <MT8195_POWER_DOMAIN_VENC_CORE1>; + clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>; + clock-names = "venc1-larb"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_VDOSYS0 { + reg = <MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&topckgen CLK_TOP_CFG_VDO0>, + <&vdosys0 CLK_VDO0_SMI_GALS>, + <&vdosys0 CLK_VDO0_SMI_COMMON>, + <&vdosys0 CLK_VDO0_SMI_EMI>, + <&vdosys0 CLK_VDO0_SMI_IOMMU>, + <&vdosys0 CLK_VDO0_SMI_LARB>, + <&vdosys0 CLK_VDO0_SMI_RSI>; + clock-names = "vdosys0", "vdosys0-0", "vdosys0-1", + "vdosys0-2", "vdosys0-3", + "vdosys0-4", "vdosys0-5"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8195_POWER_DOMAIN_VPPSYS1 { + reg = <MT8195_POWER_DOMAIN_VPPSYS1>; + clocks = <&topckgen CLK_TOP_CFG_VPP1>, + <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, + <&vppsys1 CLK_VPP1_VPPSYS1_LARB>; + clock-names = "vppsys1", "vppsys1-0", + "vppsys1-1"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_WPESYS { + reg = <MT8195_POWER_DOMAIN_WPESYS>; + clocks = <&wpesys CLK_WPE_SMI_LARB7>, + <&wpesys CLK_WPE_SMI_LARB8>, + <&wpesys CLK_WPE_SMI_LARB7_P>, + <&wpesys CLK_WPE_SMI_LARB8_P>; + clock-names = "wepsys-0", "wepsys-1", "wepsys-2", + "wepsys-3"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_VDEC0 { + reg = <MT8195_POWER_DOMAIN_VDEC0>; + clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>; + clock-names = "vdec0-0"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_VDEC2 { + reg = <MT8195_POWER_DOMAIN_VDEC2>; + clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; + clock-names = "vdec2-0"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_VENC { + reg = <MT8195_POWER_DOMAIN_VENC>; + clocks = <&vencsys CLK_VENC_LARB>; + clock-names = "venc0-larb"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_VDOSYS1 { + reg = <MT8195_POWER_DOMAIN_VDOSYS1>; + clocks = <&topckgen CLK_TOP_CFG_VDO1>, + <&vdosys1 CLK_VDO1_SMI_LARB2>, + <&vdosys1 CLK_VDO1_SMI_LARB3>, + <&vdosys1 CLK_VDO1_GALS>; + clock-names = "vdosys1", "vdosys1-0", + "vdosys1-1", "vdosys1-2"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8195_POWER_DOMAIN_DP_TX { + reg = <MT8195_POWER_DOMAIN_DP_TX>; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_EPD_TX { + reg = <MT8195_POWER_DOMAIN_EPD_TX>; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_HDMI_TX { + reg = <MT8195_POWER_DOMAIN_HDMI_TX>; + clocks = <&topckgen CLK_TOP_HDMI_APB>; + clock-names = "hdmi_tx"; + #power-domain-cells = <0>; + }; + }; + + power-domain@MT8195_POWER_DOMAIN_IMG { + reg = <MT8195_POWER_DOMAIN_IMG>; + clocks = <&imgsys CLK_IMG_LARB9>, + <&imgsys CLK_IMG_GALS>; + clock-names = "img-0", "img-1"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8195_POWER_DOMAIN_DIP { + reg = <MT8195_POWER_DOMAIN_DIP>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_IPE { + reg = <MT8195_POWER_DOMAIN_IPE>; + clocks = <&topckgen CLK_TOP_IPE>, + <&imgsys CLK_IMG_IPE>, + <&ipesys CLK_IPE_SMI_LARB12>; + clock-names = "ipe", "ipe-0", "ipe-1"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + }; + + power-domain@MT8195_POWER_DOMAIN_CAM { + reg = <MT8195_POWER_DOMAIN_CAM>; + clocks = <&camsys CLK_CAM_LARB13>, + <&camsys CLK_CAM_LARB14>, + <&camsys CLK_CAM_CAM2MM0_GALS>, + <&camsys CLK_CAM_CAM2MM1_GALS>, + <&camsys CLK_CAM_CAM2SYS_GALS>; + clock-names = "cam-0", "cam-1", "cam-2", "cam-3", + "cam-4"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8195_POWER_DOMAIN_CAM_RAWA { + reg = <MT8195_POWER_DOMAIN_CAM_RAWA>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_CAM_RAWB { + reg = <MT8195_POWER_DOMAIN_CAM_RAWB>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_CAM_MRAW { + reg = <MT8195_POWER_DOMAIN_CAM_MRAW>; + #power-domain-cells = <0>; + }; + }; + }; + }; + + power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 { + reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 { + reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_PCIE_PHY { + reg = <MT8195_POWER_DOMAIN_PCIE_PHY>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY { + reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP { + reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>; + clocks = <&topckgen CLK_TOP_SENINF>, + <&topckgen CLK_TOP_SENINF2>; + clock-names = "csi_rx_top", "csi_rx_top1"; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_ETHER { + reg = <MT8195_POWER_DOMAIN_ETHER>; + clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; + clock-names = "ether"; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_ADSP { + reg = <MT8195_POWER_DOMAIN_ADSP>; + clocks = <&topckgen CLK_TOP_ADSP>, + <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>; + clock-names = "adsp", "adsp1"; + #address-cells = <1>; + #size-cells = <0>; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <1>; + + power-domain@MT8195_POWER_DOMAIN_AUDIO { + reg = <MT8195_POWER_DOMAIN_AUDIO>; + clocks = <&topckgen CLK_TOP_A1SYS_HP>, + <&topckgen CLK_TOP_AUD_INTBUS>, + <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, + <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>; + clock-names = "audio", "audio1", "audio2", + "audio3"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + }; + }; + }; + + watchdog: watchdog@10007000 { + compatible = "mediatek,mt8195-wdt"; + mediatek,disable-extrst; + reg = <0 0x10007000 0 0x100>; + #reset-cells = <1>; + }; + + apmixedsys: syscon@1000c000 { + compatible = "mediatek,mt8195-apmixedsys", "syscon"; + reg = <0 0x1000c000 0 0x1000>; + #clock-cells = <1>; + }; + + systimer: timer@10017000 { + compatible = "mediatek,mt8195-timer", + "mediatek,mt6765-timer"; + reg = <0 0x10017000 0 0x1000>; + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&clk13m>; + }; + + pwrap: pwrap@10024000 { + compatible = "mediatek,mt8195-pwrap", "syscon"; + reg = <0 0x10024000 0 0x1000>; + reg-names = "pwrap"; + interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, + <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; + clock-names = "spi", "wrap"; + assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; + assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; + }; + + spmi: spmi@10027000 { + compatible = "mediatek,mt8195-spmi"; + reg = <0 0x10027000 0 0x000e00>, + <0 0x10029000 0 0x000100>; + reg-names = "pmif", "spmimst"; + clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, + <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, + <&topckgen CLK_TOP_SPMI_M_MST>; + clock-names = "pmif_sys_ck", + "pmif_tmr_ck", + "spmimst_clk_mux"; + assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; + assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; + }; + + iommu_infra: infra-iommu@10315000 { + compatible = "mediatek,mt8195-iommu-infra"; + reg = <0 0x10315000 0 0x5000>; + interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0>; + #iommu-cells = <1>; + }; + + gce0: mailbox@10320000 { + compatible = "mediatek,mt8195-gce"; + reg = <0 0x10320000 0 0x4000>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; + #mbox-cells = <2>; + clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; + }; + + gce1: mailbox@10330000 { + compatible = "mediatek,mt8195-gce"; + reg = <0 0x10330000 0 0x4000>; + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>; + #mbox-cells = <2>; + clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; + }; + + scp: scp@10500000 { + compatible = "mediatek,mt8195-scp"; + reg = <0 0x10500000 0 0x100000>, + <0 0x10720000 0 0xe0000>, + <0 0x10700000 0 0x8000>; + reg-names = "sram", "cfg", "l1tcm"; + interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; + status = "disabled"; + }; + + scp_adsp: clock-controller@10720000 { + compatible = "mediatek,mt8195-scp_adsp"; + reg = <0 0x10720000 0 0x1000>; + #clock-cells = <1>; + }; + + adsp: dsp@10803000 { + compatible = "mediatek,mt8195-dsp"; + reg = <0 0x10803000 0 0x1000>, + <0 0x10840000 0 0x40000>; + reg-names = "cfg", "sram"; + clocks = <&topckgen CLK_TOP_ADSP>, + <&clk26m>, + <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, + <&topckgen CLK_TOP_MAINPLL_D7_D2>, + <&scp_adsp CLK_SCP_ADSP_AUDIODSP>, + <&topckgen CLK_TOP_AUDIO_H>; + clock-names = "adsp_sel", + "clk26m_ck", + "audio_local_bus", + "mainpll_d7_d2", + "scp_adsp_audiodsp", + "audio_h"; + power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>; + mbox-names = "rx", "tx"; + mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; + status = "disabled"; + }; + + adsp_mailbox0: mailbox@10816000 { + compatible = "mediatek,mt8195-adsp-mbox"; + #mbox-cells = <0>; + reg = <0 0x10816000 0 0x1000>; + interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>; + }; + + adsp_mailbox1: mailbox@10817000 { + compatible = "mediatek,mt8195-adsp-mbox"; + #mbox-cells = <0>; + reg = <0 0x10817000 0 0x1000>; + interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>; + }; + + afe: mt8195-afe-pcm@10890000 { + compatible = "mediatek,mt8195-audio"; + reg = <0 0x10890000 0 0x10000>; + mediatek,topckgen = <&topckgen>; + power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>; + interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>; + resets = <&watchdog 14>; + reset-names = "audiosys"; + clocks = <&clk26m>, + <&apmixedsys CLK_APMIXED_APLL1>, + <&apmixedsys CLK_APMIXED_APLL2>, + <&topckgen CLK_TOP_APLL12_DIV0>, + <&topckgen CLK_TOP_APLL12_DIV1>, + <&topckgen CLK_TOP_APLL12_DIV2>, + <&topckgen CLK_TOP_APLL12_DIV3>, + <&topckgen CLK_TOP_APLL12_DIV9>, + <&topckgen CLK_TOP_A1SYS_HP>, + <&topckgen CLK_TOP_AUD_INTBUS>, + <&topckgen CLK_TOP_AUDIO_H>, + <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, + <&topckgen CLK_TOP_DPTX_MCK>, + <&topckgen CLK_TOP_I2SO1_MCK>, + <&topckgen CLK_TOP_I2SO2_MCK>, + <&topckgen CLK_TOP_I2SI1_MCK>, + <&topckgen CLK_TOP_I2SI2_MCK>, + <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>, + <&scp_adsp CLK_SCP_ADSP_AUDIODSP>; + clock-names = "clk26m", + "apll1_ck", + "apll2_ck", + "apll12_div0", + "apll12_div1", + "apll12_div2", + "apll12_div3", + "apll12_div9", + "a1sys_hp_sel", + "aud_intbus_sel", + "audio_h_sel", + "audio_local_bus_sel", + "dptx_m_sel", + "i2so1_m_sel", + "i2so2_m_sel", + "i2si1_m_sel", + "i2si2_m_sel", + "infra_ao_audio_26m_b", + "scp_adsp_audiodsp"; + status = "disabled"; + }; + + uart0: serial@11001100 { + compatible = "mediatek,mt8195-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11001100 0 0x100>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11001200 { + compatible = "mediatek,mt8195-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11001200 0 0x100>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart2: serial@11001300 { + compatible = "mediatek,mt8195-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11001300 0 0x100>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart3: serial@11001400 { + compatible = "mediatek,mt8195-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11001400 0 0x100>; + interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart4: serial@11001500 { + compatible = "mediatek,mt8195-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11001500 0 0x100>; + interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart5: serial@11001600 { + compatible = "mediatek,mt8195-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11001600 0 0x100>; + interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + auxadc: auxadc@11002000 { + compatible = "mediatek,mt8195-auxadc", + "mediatek,mt8173-auxadc"; + reg = <0 0x11002000 0 0x1000>; + clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; + clock-names = "main"; + #io-channel-cells = <1>; + status = "disabled"; + }; + + pericfg_ao: syscon@11003000 { + compatible = "mediatek,mt8195-pericfg_ao", "syscon"; + reg = <0 0x11003000 0 0x1000>; + #clock-cells = <1>; + }; + + spi0: spi@1100a000 { + compatible = "mediatek,mt8195-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100a000 0 0x1000>; + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI0>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi1: spi@11010000 { + compatible = "mediatek,mt8195-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11010000 0 0x1000>; + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI1>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi2: spi@11012000 { + compatible = "mediatek,mt8195-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11012000 0 0x1000>; + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI2>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi3: spi@11013000 { + compatible = "mediatek,mt8195-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11013000 0 0x1000>; + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI3>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi4: spi@11018000 { + compatible = "mediatek,mt8195-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11018000 0 0x1000>; + interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI4>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi5: spi@11019000 { + compatible = "mediatek,mt8195-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11019000 0 0x1000>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI5>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spis0: spi@1101d000 { + compatible = "mediatek,mt8195-spi-slave"; + reg = <0 0x1101d000 0 0x1000>; + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>; + clock-names = "spi"; + assigned-clocks = <&topckgen CLK_TOP_SPIS>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; + status = "disabled"; + }; + + spis1: spi@1101e000 { + compatible = "mediatek,mt8195-spi-slave"; + reg = <0 0x1101e000 0 0x1000>; + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>; + clock-names = "spi"; + assigned-clocks = <&topckgen CLK_TOP_SPIS>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; + status = "disabled"; + }; + + xhci0: usb@11200000 { + compatible = "mediatek,mt8195-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x1000>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>; + assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, + <&topckgen CLK_TOP_SSUSB_XHCI>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, + <&topckgen CLK_TOP_SSUSB_REF>, + <&apmixedsys CLK_APMIXED_USB1PLL>, + <&clk26m>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", + "xhci_ck"; + mediatek,syscon-wakeup = <&pericfg 0x400 103>; + wakeup-source; + status = "disabled"; + }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt8195-mmc", + "mediatek,mt8183-mmc"; + reg = <0 0x11230000 0 0x10000>, + <0 0x11f50000 0 0x1000>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_MSDC50_0>, + <&infracfg_ao CLK_INFRA_AO_MSDC0>, + <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + mmc1: mmc@11240000 { + compatible = "mediatek,mt8195-mmc", + "mediatek,mt8183-mmc"; + reg = <0 0x11240000 0 0x1000>, + <0 0x11c70000 0 0x1000>; + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_MSDC30_1>, + <&infracfg_ao CLK_INFRA_AO_MSDC1>, + <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; + clock-names = "source", "hclk", "source_cg"; + assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; + status = "disabled"; + }; + + mmc2: mmc@11250000 { + compatible = "mediatek,mt8195-mmc", + "mediatek,mt8183-mmc"; + reg = <0 0x11250000 0 0x1000>, + <0 0x11e60000 0 0x1000>; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_MSDC30_2>, + <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>, + <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>; + clock-names = "source", "hclk", "source_cg"; + assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>; + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; + status = "disabled"; + }; + + xhci1: usb@11290000 { + compatible = "mediatek,mt8195-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11290000 0 0x1000>, + <0 0x11293e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>; + phys = <&u2port1 PHY_TYPE_USB2>; + assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>, + <&topckgen CLK_TOP_SSUSB_XHCI_1P>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>, + <&topckgen CLK_TOP_SSUSB_P1_REF>, + <&apmixedsys CLK_APMIXED_USB1PLL>, + <&clk26m>, + <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", + "xhci_ck"; + mediatek,syscon-wakeup = <&pericfg 0x400 104>; + wakeup-source; + status = "disabled"; + }; + + xhci2: usb@112a0000 { + compatible = "mediatek,mt8195-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x112a0000 0 0x1000>, + <0 0x112a3e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; + phys = <&u2port2 PHY_TYPE_USB2>; + assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>, + <&topckgen CLK_TOP_SSUSB_XHCI_2P>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, + <&topckgen CLK_TOP_SSUSB_P2_REF>, + <&clk26m>, + <&clk26m>, + <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", + "xhci_ck"; + mediatek,syscon-wakeup = <&pericfg 0x400 105>; + wakeup-source; + status = "disabled"; + }; + + xhci3: usb@112b0000 { + compatible = "mediatek,mt8195-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x112b0000 0 0x1000>, + <0 0x112b3e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; + phys = <&u2port3 PHY_TYPE_USB2>; + assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>, + <&topckgen CLK_TOP_SSUSB_XHCI_3P>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, + <&topckgen CLK_TOP_SSUSB_P3_REF>, + <&clk26m>, + <&clk26m>, + <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", + "xhci_ck"; + mediatek,syscon-wakeup = <&pericfg 0x400 106>; + wakeup-source; + status = "disabled"; + }; + + nor_flash: spi@1132c000 { + compatible = "mediatek,mt8195-nor", + "mediatek,mt8173-nor"; + reg = <0 0x1132c000 0 0x1000>; + interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen CLK_TOP_SPINOR>, + <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>, + <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; + clock-names = "spi", "sf", "axi"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + efuse: efuse@11c10000 { + compatible = "mediatek,mt8195-efuse", "mediatek,efuse"; + reg = <0 0x11c10000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + u3_tx_imp_p0: usb3-tx-imp@184,1 { + reg = <0x184 0x1>; + bits = <0 5>; + }; + u3_rx_imp_p0: usb3-rx-imp@184,2 { + reg = <0x184 0x2>; + bits = <5 5>; + }; + u3_intr_p0: usb3-intr@185 { + reg = <0x185 0x1>; + bits = <2 6>; + }; + comb_tx_imp_p1: usb3-tx-imp@186,1 { + reg = <0x186 0x1>; + bits = <0 5>; + }; + comb_rx_imp_p1: usb3-rx-imp@186,2 { + reg = <0x186 0x2>; + bits = <5 5>; + }; + comb_intr_p1: usb3-intr@187 { + reg = <0x187 0x1>; + bits = <2 6>; + }; + u2_intr_p0: usb2-intr-p0@188,1 { + reg = <0x188 0x1>; + bits = <0 5>; + }; + u2_intr_p1: usb2-intr-p1@188,2 { + reg = <0x188 0x2>; + bits = <5 5>; + }; + u2_intr_p2: usb2-intr-p2@189,1 { + reg = <0x189 0x1>; + bits = <2 5>; + }; + u2_intr_p3: usb2-intr-p3@189,2 { + reg = <0x189 0x2>; + bits = <7 5>; + }; + }; + + u3phy2: t-phy@11c40000 { + compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11c40000 0x700>; + status = "disabled"; + + u2port2: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + + u3phy3: t-phy@11c50000 { + compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11c50000 0x700>; + status = "disabled"; + + u2port3: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + + i2c5: i2c@11d00000 { + compatible = "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg = <0 0x11d00000 0 0x1000>, + <0 0x10220580 0 0x80>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>; + clock-div = <1>; + clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@11d01000 { + compatible = "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg = <0 0x11d01000 0 0x1000>, + <0 0x10220600 0 0x80>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; + clock-div = <1>; + clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@11d02000 { + compatible = "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg = <0 0x11d02000 0 0x1000>, + <0 0x10220680 0 0x80>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; + clock-div = <1>; + clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + imp_iic_wrap_s: clock-controller@11d03000 { + compatible = "mediatek,mt8195-imp_iic_wrap_s"; + reg = <0 0x11d03000 0 0x1000>; + #clock-cells = <1>; + }; + + i2c0: i2c@11e00000 { + compatible = "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg = <0 0x11e00000 0 0x1000>, + <0 0x10220080 0 0x80>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>; + clock-div = <1>; + clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@11e01000 { + compatible = "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg = <0 0x11e01000 0 0x1000>, + <0 0x10220200 0 0x80>; + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>; + clock-div = <1>; + clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11e02000 { + compatible = "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg = <0 0x11e02000 0 0x1000>, + <0 0x10220380 0 0x80>; + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; + clock-div = <1>; + clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@11e03000 { + compatible = "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg = <0 0x11e03000 0 0x1000>, + <0 0x10220480 0 0x80>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; + clock-div = <1>; + clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@11e04000 { + compatible = "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg = <0 0x11e04000 0 0x1000>, + <0 0x10220500 0 0x80>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>; + clock-div = <1>; + clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + imp_iic_wrap_w: clock-controller@11e05000 { + compatible = "mediatek,mt8195-imp_iic_wrap_w"; + reg = <0 0x11e05000 0 0x1000>; + #clock-cells = <1>; + }; + + u3phy1: t-phy@11e30000 { + compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11e30000 0xe00>; + power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; + status = "disabled"; + + u2port1: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>, + <&clk26m>; + clock-names = "ref", "da_ref"; + #phy-cells = <1>; + }; + + u3port1: usb-phy@700 { + reg = <0x700 0x700>; + clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, + <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; + clock-names = "ref", "da_ref"; + nvmem-cells = <&comb_intr_p1>, + <&comb_rx_imp_p1>, + <&comb_tx_imp_p1>; + nvmem-cell-names = "intr", "rx_imp", "tx_imp"; + #phy-cells = <1>; + }; + }; + + u3phy0: t-phy@11e40000 { + compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11e40000 0xe00>; + status = "disabled"; + + u2port0: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>, + <&clk26m>; + clock-names = "ref", "da_ref"; + #phy-cells = <1>; + }; + + u3port0: usb-phy@700 { + reg = <0x700 0x700>; + clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, + <&topckgen CLK_TOP_SSUSB_PHY_REF>; + clock-names = "ref", "da_ref"; + nvmem-cells = <&u3_intr_p0>, + <&u3_rx_imp_p0>, + <&u3_tx_imp_p0>; + nvmem-cell-names = "intr", "rx_imp", "tx_imp"; + #phy-cells = <1>; + }; + }; + + ufsphy: ufs-phy@11fa0000 { + compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; + reg = <0 0x11fa0000 0 0xc000>; + clocks = <&clk26m>, <&clk26m>; + clock-names = "unipro", "mp"; + #phy-cells = <0>; + status = "disabled"; + }; + + mfgcfg: clock-controller@13fbf000 { + compatible = "mediatek,mt8195-mfgcfg"; + reg = <0 0x13fbf000 0 0x1000>; + #clock-cells = <1>; + }; + + vppsys0: clock-controller@14000000 { + compatible = "mediatek,mt8195-vppsys0"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + }; + + smi_sub_common_vpp0_vpp1_2x1: smi@14010000 { + compatible = "mediatek,mt8195-smi-sub-common"; + reg = <0 0x14010000 0 0x1000>; + clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, + <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, + <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; + clock-names = "apb", "smi", "gals0"; + mediatek,smi = <&smi_common_vpp>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + smi_sub_common_vdec_vpp0_2x1: smi@14011000 { + compatible = "mediatek,mt8195-smi-sub-common"; + reg = <0 0x14011000 0 0x1000>; + clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, + <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, + <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>; + clock-names = "apb", "smi", "gals0"; + mediatek,smi = <&smi_common_vpp>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + smi_common_vpp: smi@14012000 { + compatible = "mediatek,mt8195-smi-common-vpp"; + reg = <0 0x14012000 0 0x1000>; + clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, + <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, + <&vppsys0 CLK_VPP0_SMI_RSI>, + <&vppsys0 CLK_VPP0_SMI_RSI>; + clock-names = "apb", "smi", "gals0", "gals1"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + larb4: larb@14013000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x14013000 0 0x1000>; + mediatek,larb-id = <4>; + mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; + clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, + <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + iommu_vpp: iommu@14018000 { + compatible = "mediatek,mt8195-iommu-vpp"; + reg = <0 0x14018000 0 0x1000>; + mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8 + &larb12 &larb14 &larb16 &larb18 + &larb20 &larb22 &larb23 &larb26 + &larb27>; + interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>; + clock-names = "bclk"; + #iommu-cells = <1>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + wpesys: clock-controller@14e00000 { + compatible = "mediatek,mt8195-wpesys"; + reg = <0 0x14e00000 0 0x1000>; + #clock-cells = <1>; + }; + + wpesys_vpp0: clock-controller@14e02000 { + compatible = "mediatek,mt8195-wpesys_vpp0"; + reg = <0 0x14e02000 0 0x1000>; + #clock-cells = <1>; + }; + + wpesys_vpp1: clock-controller@14e03000 { + compatible = "mediatek,mt8195-wpesys_vpp1"; + reg = <0 0x14e03000 0 0x1000>; + #clock-cells = <1>; + }; + + larb7: larb@14e04000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x14e04000 0 0x1000>; + mediatek,larb-id = <7>; + mediatek,smi = <&smi_common_vdo>; + clocks = <&wpesys CLK_WPE_SMI_LARB7>, + <&wpesys CLK_WPE_SMI_LARB7>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; + }; + + larb8: larb@14e05000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x14e05000 0 0x1000>; + mediatek,larb-id = <8>; + mediatek,smi = <&smi_common_vpp>; + clocks = <&wpesys CLK_WPE_SMI_LARB8>, + <&wpesys CLK_WPE_SMI_LARB8>, + <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; + }; + + vppsys1: clock-controller@14f00000 { + compatible = "mediatek,mt8195-vppsys1"; + reg = <0 0x14f00000 0 0x1000>; + #clock-cells = <1>; + }; + + larb5: larb@14f02000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x14f02000 0 0x1000>; + mediatek,larb-id = <5>; + mediatek,smi = <&smi_common_vdo>; + clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, + <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, + <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + larb6: larb@14f03000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x14f03000 0 0x1000>; + mediatek,larb-id = <6>; + mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; + clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, + <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, + <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + imgsys: clock-controller@15000000 { + compatible = "mediatek,mt8195-imgsys"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb9: larb@15001000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x15001000 0 0x1000>; + mediatek,larb-id = <9>; + mediatek,smi = <&smi_sub_common_img1_3x1>; + clocks = <&imgsys CLK_IMG_LARB9>, + <&imgsys CLK_IMG_LARB9>, + <&imgsys CLK_IMG_GALS>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; + }; + + smi_sub_common_img0_3x1: smi@15002000 { + compatible = "mediatek,mt8195-smi-sub-common"; + reg = <0 0x15002000 0 0x1000>; + clocks = <&imgsys CLK_IMG_IPE>, + <&imgsys CLK_IMG_IPE>, + <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; + clock-names = "apb", "smi", "gals0"; + mediatek,smi = <&smi_common_vpp>; + power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; + }; + + smi_sub_common_img1_3x1: smi@15003000 { + compatible = "mediatek,mt8195-smi-sub-common"; + reg = <0 0x15003000 0 0x1000>; + clocks = <&imgsys CLK_IMG_LARB9>, + <&imgsys CLK_IMG_LARB9>, + <&imgsys CLK_IMG_GALS>; + clock-names = "apb", "smi", "gals0"; + mediatek,smi = <&smi_common_vdo>; + power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; + }; + + imgsys1_dip_top: clock-controller@15110000 { + compatible = "mediatek,mt8195-imgsys1_dip_top"; + reg = <0 0x15110000 0 0x1000>; + #clock-cells = <1>; + }; + + larb10: larb@15120000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x15120000 0 0x1000>; + mediatek,larb-id = <10>; + mediatek,smi = <&smi_sub_common_img1_3x1>; + clocks = <&imgsys CLK_IMG_DIP0>, + <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; + }; + + imgsys1_dip_nr: clock-controller@15130000 { + compatible = "mediatek,mt8195-imgsys1_dip_nr"; + reg = <0 0x15130000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys1_wpe: clock-controller@15220000 { + compatible = "mediatek,mt8195-imgsys1_wpe"; + reg = <0 0x15220000 0 0x1000>; + #clock-cells = <1>; + }; + + larb11: larb@15230000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x15230000 0 0x1000>; + mediatek,larb-id = <11>; + mediatek,smi = <&smi_sub_common_img1_3x1>; + clocks = <&imgsys CLK_IMG_WPE0>, + <&imgsys1_wpe CLK_IMG1_WPE_LARB11>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; + }; + + ipesys: clock-controller@15330000 { + compatible = "mediatek,mt8195-ipesys"; + reg = <0 0x15330000 0 0x1000>; + #clock-cells = <1>; + }; + + larb12: larb@15340000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x15340000 0 0x1000>; + mediatek,larb-id = <12>; + mediatek,smi = <&smi_sub_common_img0_3x1>; + clocks = <&ipesys CLK_IPE_SMI_LARB12>, + <&ipesys CLK_IPE_SMI_LARB12>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_IPE>; + }; + + camsys: clock-controller@16000000 { + compatible = "mediatek,mt8195-camsys"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb13: larb@16001000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x16001000 0 0x1000>; + mediatek,larb-id = <13>; + mediatek,smi = <&smi_sub_common_cam_4x1>; + clocks = <&camsys CLK_CAM_LARB13>, + <&camsys CLK_CAM_LARB13>, + <&camsys CLK_CAM_CAM2MM0_GALS>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; + }; + + larb14: larb@16002000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x16002000 0 0x1000>; + mediatek,larb-id = <14>; + mediatek,smi = <&smi_sub_common_cam_7x1>; + clocks = <&camsys CLK_CAM_LARB14>, + <&camsys CLK_CAM_LARB14>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; + }; + + smi_sub_common_cam_4x1: smi@16004000 { + compatible = "mediatek,mt8195-smi-sub-common"; + reg = <0 0x16004000 0 0x1000>; + clocks = <&camsys CLK_CAM_LARB13>, + <&camsys CLK_CAM_LARB13>, + <&camsys CLK_CAM_CAM2MM0_GALS>; + clock-names = "apb", "smi", "gals0"; + mediatek,smi = <&smi_common_vdo>; + power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; + }; + + smi_sub_common_cam_7x1: smi@16005000 { + compatible = "mediatek,mt8195-smi-sub-common"; + reg = <0 0x16005000 0 0x1000>; + clocks = <&camsys CLK_CAM_LARB14>, + <&camsys CLK_CAM_CAM2MM1_GALS>, + <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; + clock-names = "apb", "smi", "gals0"; + mediatek,smi = <&smi_common_vpp>; + power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; + }; + + larb16: larb@16012000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x16012000 0 0x1000>; + mediatek,larb-id = <16>; + mediatek,smi = <&smi_sub_common_cam_7x1>; + clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>, + <&camsys_rawa CLK_CAM_RAWA_LARBX>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; + }; + + larb17: larb@16013000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x16013000 0 0x1000>; + mediatek,larb-id = <17>; + mediatek,smi = <&smi_sub_common_cam_4x1>; + clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>, + <&camsys_yuva CLK_CAM_YUVA_LARBX>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; + }; + + larb27: larb@16014000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x16014000 0 0x1000>; + mediatek,larb-id = <27>; + mediatek,smi = <&smi_sub_common_cam_7x1>; + clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>, + <&camsys_rawb CLK_CAM_RAWB_LARBX>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; + }; + + larb28: larb@16015000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x16015000 0 0x1000>; + mediatek,larb-id = <28>; + mediatek,smi = <&smi_sub_common_cam_4x1>; + clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>, + <&camsys_yuvb CLK_CAM_YUVB_LARBX>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; + }; + + camsys_rawa: clock-controller@1604f000 { + compatible = "mediatek,mt8195-camsys_rawa"; + reg = <0 0x1604f000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_yuva: clock-controller@1606f000 { + compatible = "mediatek,mt8195-camsys_yuva"; + reg = <0 0x1606f000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_rawb: clock-controller@1608f000 { + compatible = "mediatek,mt8195-camsys_rawb"; + reg = <0 0x1608f000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_yuvb: clock-controller@160af000 { + compatible = "mediatek,mt8195-camsys_yuvb"; + reg = <0 0x160af000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_mraw: clock-controller@16140000 { + compatible = "mediatek,mt8195-camsys_mraw"; + reg = <0 0x16140000 0 0x1000>; + #clock-cells = <1>; + }; + + larb25: larb@16141000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x16141000 0 0x1000>; + mediatek,larb-id = <25>; + mediatek,smi = <&smi_sub_common_cam_4x1>; + clocks = <&camsys CLK_CAM_LARB13>, + <&camsys_mraw CLK_CAM_MRAW_LARBX>, + <&camsys CLK_CAM_CAM2MM0_GALS>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; + }; + + larb26: larb@16142000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x16142000 0 0x1000>; + mediatek,larb-id = <26>; + mediatek,smi = <&smi_sub_common_cam_7x1>; + clocks = <&camsys_mraw CLK_CAM_MRAW_LARBX>, + <&camsys_mraw CLK_CAM_MRAW_LARBX>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; + + }; + + ccusys: clock-controller@17200000 { + compatible = "mediatek,mt8195-ccusys"; + reg = <0 0x17200000 0 0x1000>; + #clock-cells = <1>; + }; + + larb18: larb@17201000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x17201000 0 0x1000>; + mediatek,larb-id = <18>; + mediatek,smi = <&smi_sub_common_cam_7x1>; + clocks = <&ccusys CLK_CCU_LARB18>, + <&ccusys CLK_CCU_LARB18>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; + }; + + larb24: larb@1800d000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x1800d000 0 0x1000>; + mediatek,larb-id = <24>; + mediatek,smi = <&smi_common_vdo>; + clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, + <&vdecsys_soc CLK_VDEC_SOC_LARB1>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; + }; + + larb23: larb@1800e000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x1800e000 0 0x1000>; + mediatek,larb-id = <23>; + mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; + clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, + <&vdecsys_soc CLK_VDEC_SOC_LARB1>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; + }; + + vdecsys_soc: clock-controller@1800f000 { + compatible = "mediatek,mt8195-vdecsys_soc"; + reg = <0 0x1800f000 0 0x1000>; + #clock-cells = <1>; + }; + + larb21: larb@1802e000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x1802e000 0 0x1000>; + mediatek,larb-id = <21>; + mediatek,smi = <&smi_common_vdo>; + clocks = <&vdecsys CLK_VDEC_LARB1>, + <&vdecsys CLK_VDEC_LARB1>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; + }; + + vdecsys: clock-controller@1802f000 { + compatible = "mediatek,mt8195-vdecsys"; + reg = <0 0x1802f000 0 0x1000>; + #clock-cells = <1>; + }; + + larb22: larb@1803e000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x1803e000 0 0x1000>; + mediatek,larb-id = <22>; + mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; + clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, + <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; + }; + + vdecsys_core1: clock-controller@1803f000 { + compatible = "mediatek,mt8195-vdecsys_core1"; + reg = <0 0x1803f000 0 0x1000>; + #clock-cells = <1>; + }; + + apusys_pll: clock-controller@190f3000 { + compatible = "mediatek,mt8195-apusys_pll"; + reg = <0 0x190f3000 0 0x1000>; + #clock-cells = <1>; + }; + + vencsys: clock-controller@1a000000 { + compatible = "mediatek,mt8195-vencsys"; + reg = <0 0x1a000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb19: larb@1a010000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x1a010000 0 0x1000>; + mediatek,larb-id = <19>; + mediatek,smi = <&smi_common_vdo>; + clocks = <&vencsys CLK_VENC_VENC>, + <&vencsys CLK_VENC_GALS>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; + }; + + vencsys_core1: clock-controller@1b000000 { + compatible = "mediatek,mt8195-vencsys_core1"; + reg = <0 0x1b000000 0 0x1000>; + #clock-cells = <1>; + }; + + vdosys0: syscon@1c01a000 { + compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon"; + reg = <0 0x1c01a000 0 0x1000>; + mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; + #clock-cells = <1>; + }; + + larb20: larb@1b010000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x1b010000 0 0x1000>; + mediatek,larb-id = <20>; + mediatek,smi = <&smi_common_vpp>; + clocks = <&vencsys_core1 CLK_VENC_CORE1_VENC>, + <&vencsys_core1 CLK_VENC_CORE1_GALS>, + <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; + }; + + ovl0: ovl@1c000000 { + compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl"; + reg = <0 0x1c000000 0 0x1000>; + interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; + iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; + }; + + rdma0: rdma@1c002000 { + compatible = "mediatek,mt8195-disp-rdma"; + reg = <0 0x1c002000 0 0x1000>; + interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; + iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; + }; + + color0: color@1c003000 { + compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color"; + reg = <0 0x1c003000 0 0x1000>; + interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; + }; + + ccorr0: ccorr@1c004000 { + compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr"; + reg = <0 0x1c004000 0 0x1000>; + interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; + }; + + aal0: aal@1c005000 { + compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal"; + reg = <0 0x1c005000 0 0x1000>; + interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; + }; + + gamma0: gamma@1c006000 { + compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma"; + reg = <0 0x1c006000 0 0x1000>; + interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; + }; + + dither0: dither@1c007000 { + compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither"; + reg = <0 0x1c007000 0 0x1000>; + interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; + }; + + dsc0: dsc@1c009000 { + compatible = "mediatek,mt8195-disp-dsc"; + reg = <0 0x1c009000 0 0x1000>; + interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>; + }; + + merge0: merge@1c014000 { + compatible = "mediatek,mt8195-disp-merge"; + reg = <0 0x1c014000 0 0x1000>; + interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; + }; + + mutex: mutex@1c016000 { + compatible = "mediatek,mt8195-disp-mutex"; + reg = <0 0x1c016000 0 0x1000>; + interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; + mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>; + }; + + larb0: larb@1c018000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x1c018000 0 0x1000>; + mediatek,larb-id = <0>; + mediatek,smi = <&smi_common_vdo>; + clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, + <&vdosys0 CLK_VDO0_SMI_LARB>, + <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + }; + + larb1: larb@1c019000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x1c019000 0 0x1000>; + mediatek,larb-id = <1>; + mediatek,smi = <&smi_common_vpp>; + clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, + <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>, + <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + }; + + vdosys1: syscon@1c100000 { + compatible = "mediatek,mt8195-vdosys1", "syscon"; + reg = <0 0x1c100000 0 0x1000>; + #clock-cells = <1>; + }; + + smi_common_vdo: smi@1c01b000 { + compatible = "mediatek,mt8195-smi-common-vdo"; + reg = <0 0x1c01b000 0 0x1000>; + clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>, + <&vdosys0 CLK_VDO0_SMI_EMI>, + <&vdosys0 CLK_VDO0_SMI_RSI>, + <&vdosys0 CLK_VDO0_SMI_GALS>; + clock-names = "apb", "smi", "gals0", "gals1"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + + }; + + iommu_vdo: iommu@1c01f000 { + compatible = "mediatek,mt8195-iommu-vdo"; + reg = <0 0x1c01f000 0 0x1000>; + mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9 + &larb10 &larb11 &larb13 &larb17 + &larb19 &larb21 &larb24 &larb25 + &larb28>; + interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>; + #iommu-cells = <1>; + clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>; + clock-names = "bclk"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + }; + + larb2: larb@1c102000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x1c102000 0 0x1000>; + mediatek,larb-id = <2>; + mediatek,smi = <&smi_common_vdo>; + clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>, + <&vdosys1 CLK_VDO1_SMI_LARB2>, + <&vdosys1 CLK_VDO1_GALS>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + }; + + larb3: larb@1c103000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x1c103000 0 0x1000>; + mediatek,larb-id = <3>; + mediatek,smi = <&smi_common_vpp>; + clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>, + <&vdosys1 CLK_VDO1_GALS>, + <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8516-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt8516-pinfunc.h new file mode 100644 index 000000000..73339bb48 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8516-pinfunc.h @@ -0,0 +1,663 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + */ +#ifndef __DTS_MT8516_PINFUNC_H +#define __DTS_MT8516_PINFUNC_H + +#include <dt-bindings/pinctrl/mt65xx.h> + +#define MT8516_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT8516_PIN_0_EINT0__FUNC_PWM_B (MTK_PIN_NO(0) | 1) +#define MT8516_PIN_0_EINT0__FUNC_I2S2_BCK (MTK_PIN_NO(0) | 3) +#define MT8516_PIN_0_EINT0__FUNC_EXT_TXD0 (MTK_PIN_NO(0) | 4) +#define MT8516_PIN_0_EINT0__FUNC_SQICS (MTK_PIN_NO(0) | 6) +#define MT8516_PIN_0_EINT0__FUNC_DBG_MON_A_6 (MTK_PIN_NO(0) | 7) + +#define MT8516_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT8516_PIN_1_EINT1__FUNC_PWM_C (MTK_PIN_NO(1) | 1) +#define MT8516_PIN_1_EINT1__FUNC_I2S2_DI (MTK_PIN_NO(1) | 3) +#define MT8516_PIN_1_EINT1__FUNC_EXT_TXD1 (MTK_PIN_NO(1) | 4) +#define MT8516_PIN_1_EINT1__FUNC_CONN_MCU_TDO (MTK_PIN_NO(1) | 5) +#define MT8516_PIN_1_EINT1__FUNC_SQISO (MTK_PIN_NO(1) | 6) +#define MT8516_PIN_1_EINT1__FUNC_DBG_MON_A_7 (MTK_PIN_NO(1) | 7) + +#define MT8516_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT8516_PIN_2_EINT2__FUNC_CLKM0 (MTK_PIN_NO(2) | 1) +#define MT8516_PIN_2_EINT2__FUNC_I2S2_LRCK (MTK_PIN_NO(2) | 3) +#define MT8516_PIN_2_EINT2__FUNC_EXT_TXD2 (MTK_PIN_NO(2) | 4) +#define MT8516_PIN_2_EINT2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(2) | 5) +#define MT8516_PIN_2_EINT2__FUNC_SQISI (MTK_PIN_NO(2) | 6) +#define MT8516_PIN_2_EINT2__FUNC_DBG_MON_A_8 (MTK_PIN_NO(2) | 7) + +#define MT8516_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT8516_PIN_3_EINT3__FUNC_CLKM1 (MTK_PIN_NO(3) | 1) +#define MT8516_PIN_3_EINT3__FUNC_SPI_MI (MTK_PIN_NO(3) | 3) +#define MT8516_PIN_3_EINT3__FUNC_EXT_TXD3 (MTK_PIN_NO(3) | 4) +#define MT8516_PIN_3_EINT3__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(3) | 5) +#define MT8516_PIN_3_EINT3__FUNC_SQIWP (MTK_PIN_NO(3) | 6) +#define MT8516_PIN_3_EINT3__FUNC_DBG_MON_A_9 (MTK_PIN_NO(3) | 7) + +#define MT8516_PIN_4_EINT4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT8516_PIN_4_EINT4__FUNC_CLKM2 (MTK_PIN_NO(4) | 1) +#define MT8516_PIN_4_EINT4__FUNC_SPI_MO (MTK_PIN_NO(4) | 3) +#define MT8516_PIN_4_EINT4__FUNC_EXT_TXC (MTK_PIN_NO(4) | 4) +#define MT8516_PIN_4_EINT4__FUNC_CONN_MCU_TCK (MTK_PIN_NO(4) | 5) +#define MT8516_PIN_4_EINT4__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(4) | 6) +#define MT8516_PIN_4_EINT4__FUNC_DBG_MON_A_10 (MTK_PIN_NO(4) | 7) + +#define MT8516_PIN_5_EINT5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT8516_PIN_5_EINT5__FUNC_UCTS2 (MTK_PIN_NO(5) | 1) +#define MT8516_PIN_5_EINT5__FUNC_SPI_CSB (MTK_PIN_NO(5) | 3) +#define MT8516_PIN_5_EINT5__FUNC_EXT_RXER (MTK_PIN_NO(5) | 4) +#define MT8516_PIN_5_EINT5__FUNC_CONN_MCU_TDI (MTK_PIN_NO(5) | 5) +#define MT8516_PIN_5_EINT5__FUNC_CONN_TEST_CK (MTK_PIN_NO(5) | 6) +#define MT8516_PIN_5_EINT5__FUNC_DBG_MON_A_11 (MTK_PIN_NO(5) | 7) + +#define MT8516_PIN_6_EINT6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT8516_PIN_6_EINT6__FUNC_URTS2 (MTK_PIN_NO(6) | 1) +#define MT8516_PIN_6_EINT6__FUNC_SPI_CLK (MTK_PIN_NO(6) | 3) +#define MT8516_PIN_6_EINT6__FUNC_EXT_RXC (MTK_PIN_NO(6) | 4) +#define MT8516_PIN_6_EINT6__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(6) | 5) +#define MT8516_PIN_6_EINT6__FUNC_DBG_MON_A_12 (MTK_PIN_NO(6) | 7) + +#define MT8516_PIN_7_EINT7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define MT8516_PIN_7_EINT7__FUNC_SQIRST (MTK_PIN_NO(7) | 1) +#define MT8516_PIN_7_EINT7__FUNC_SDA1_0 (MTK_PIN_NO(7) | 3) +#define MT8516_PIN_7_EINT7__FUNC_EXT_RXDV (MTK_PIN_NO(7) | 4) +#define MT8516_PIN_7_EINT7__FUNC_CONN_MCU_TMS (MTK_PIN_NO(7) | 5) +#define MT8516_PIN_7_EINT7__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(7) | 6) +#define MT8516_PIN_7_EINT7__FUNC_DBG_MON_A_13 (MTK_PIN_NO(7) | 7) + +#define MT8516_PIN_8_EINT8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define MT8516_PIN_8_EINT8__FUNC_SQICK (MTK_PIN_NO(8) | 1) +#define MT8516_PIN_8_EINT8__FUNC_CLKM3 (MTK_PIN_NO(8) | 2) +#define MT8516_PIN_8_EINT8__FUNC_SCL1_0 (MTK_PIN_NO(8) | 3) +#define MT8516_PIN_8_EINT8__FUNC_EXT_RXD0 (MTK_PIN_NO(8) | 4) +#define MT8516_PIN_8_EINT8__FUNC_ANT_SEL0 (MTK_PIN_NO(8) | 5) +#define MT8516_PIN_8_EINT8__FUNC_DBG_MON_A_14 (MTK_PIN_NO(8) | 7) + +#define MT8516_PIN_9_EINT9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define MT8516_PIN_9_EINT9__FUNC_CLKM4 (MTK_PIN_NO(9) | 1) +#define MT8516_PIN_9_EINT9__FUNC_SDA2_0 (MTK_PIN_NO(9) | 2) +#define MT8516_PIN_9_EINT9__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(9) | 3) +#define MT8516_PIN_9_EINT9__FUNC_EXT_RXD1 (MTK_PIN_NO(9) | 4) +#define MT8516_PIN_9_EINT9__FUNC_ANT_SEL1 (MTK_PIN_NO(9) | 5) +#define MT8516_PIN_9_EINT9__FUNC_DBG_MON_A_15 (MTK_PIN_NO(9) | 7) + +#define MT8516_PIN_10_EINT10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define MT8516_PIN_10_EINT10__FUNC_CLKM5 (MTK_PIN_NO(10) | 1) +#define MT8516_PIN_10_EINT10__FUNC_SCL2_0 (MTK_PIN_NO(10) | 2) +#define MT8516_PIN_10_EINT10__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(10) | 3) +#define MT8516_PIN_10_EINT10__FUNC_EXT_RXD2 (MTK_PIN_NO(10) | 4) +#define MT8516_PIN_10_EINT10__FUNC_ANT_SEL2 (MTK_PIN_NO(10) | 5) +#define MT8516_PIN_10_EINT10__FUNC_DBG_MON_A_16 (MTK_PIN_NO(10) | 7) + +#define MT8516_PIN_11_EINT11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define MT8516_PIN_11_EINT11__FUNC_CLKM4 (MTK_PIN_NO(11) | 1) +#define MT8516_PIN_11_EINT11__FUNC_PWM_C (MTK_PIN_NO(11) | 2) +#define MT8516_PIN_11_EINT11__FUNC_CONN_TEST_CK (MTK_PIN_NO(11) | 3) +#define MT8516_PIN_11_EINT11__FUNC_ANT_SEL3 (MTK_PIN_NO(11) | 4) +#define MT8516_PIN_11_EINT11__FUNC_EXT_RXD3 (MTK_PIN_NO(11) | 6) +#define MT8516_PIN_11_EINT11__FUNC_DBG_MON_A_17 (MTK_PIN_NO(11) | 7) + +#define MT8516_PIN_12_EINT12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define MT8516_PIN_12_EINT12__FUNC_CLKM5 (MTK_PIN_NO(12) | 1) +#define MT8516_PIN_12_EINT12__FUNC_PWM_A (MTK_PIN_NO(12) | 2) +#define MT8516_PIN_12_EINT12__FUNC_SPDIF_OUT (MTK_PIN_NO(12) | 3) +#define MT8516_PIN_12_EINT12__FUNC_ANT_SEL4 (MTK_PIN_NO(12) | 4) +#define MT8516_PIN_12_EINT12__FUNC_EXT_TXEN (MTK_PIN_NO(12) | 6) +#define MT8516_PIN_12_EINT12__FUNC_DBG_MON_A_18 (MTK_PIN_NO(12) | 7) + +#define MT8516_PIN_13_EINT13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define MT8516_PIN_13_EINT13__FUNC_TSF_IN (MTK_PIN_NO(13) | 3) +#define MT8516_PIN_13_EINT13__FUNC_ANT_SEL5 (MTK_PIN_NO(13) | 4) +#define MT8516_PIN_13_EINT13__FUNC_SPDIF_IN (MTK_PIN_NO(13) | 6) +#define MT8516_PIN_13_EINT13__FUNC_DBG_MON_A_19 (MTK_PIN_NO(13) | 7) + +#define MT8516_PIN_14_EINT14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define MT8516_PIN_14_EINT14__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(14) | 2) +#define MT8516_PIN_14_EINT14__FUNC_TDM_RX_MCK (MTK_PIN_NO(14) | 3) +#define MT8516_PIN_14_EINT14__FUNC_ANT_SEL1 (MTK_PIN_NO(14) | 4) +#define MT8516_PIN_14_EINT14__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(14) | 5) +#define MT8516_PIN_14_EINT14__FUNC_NCLE (MTK_PIN_NO(14) | 6) +#define MT8516_PIN_14_EINT14__FUNC_DBG_MON_B_8 (MTK_PIN_NO(14) | 7) + +#define MT8516_PIN_15_EINT15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define MT8516_PIN_15_EINT15__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(15) | 2) +#define MT8516_PIN_15_EINT15__FUNC_TDM_RX_BCK (MTK_PIN_NO(15) | 3) +#define MT8516_PIN_15_EINT15__FUNC_ANT_SEL2 (MTK_PIN_NO(15) | 4) +#define MT8516_PIN_15_EINT15__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(15) | 5) +#define MT8516_PIN_15_EINT15__FUNC_NCEB1 (MTK_PIN_NO(15) | 6) +#define MT8516_PIN_15_EINT15__FUNC_DBG_MON_B_9 (MTK_PIN_NO(15) | 7) + +#define MT8516_PIN_16_EINT16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define MT8516_PIN_16_EINT16__FUNC_I2S_8CH_BCK (MTK_PIN_NO(16) | 2) +#define MT8516_PIN_16_EINT16__FUNC_TDM_RX_LRCK (MTK_PIN_NO(16) | 3) +#define MT8516_PIN_16_EINT16__FUNC_ANT_SEL3 (MTK_PIN_NO(16) | 4) +#define MT8516_PIN_16_EINT16__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(16) | 5) +#define MT8516_PIN_16_EINT16__FUNC_NCEB0 (MTK_PIN_NO(16) | 6) +#define MT8516_PIN_16_EINT16__FUNC_DBG_MON_B_10 (MTK_PIN_NO(16) | 7) + +#define MT8516_PIN_17_EINT17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define MT8516_PIN_17_EINT17__FUNC_I2S_8CH_MCK (MTK_PIN_NO(17) | 2) +#define MT8516_PIN_17_EINT17__FUNC_TDM_RX_DI (MTK_PIN_NO(17) | 3) +#define MT8516_PIN_17_EINT17__FUNC_IDDIG (MTK_PIN_NO(17) | 4) +#define MT8516_PIN_17_EINT17__FUNC_ANT_SEL4 (MTK_PIN_NO(17) | 5) +#define MT8516_PIN_17_EINT17__FUNC_NREB (MTK_PIN_NO(17) | 6) +#define MT8516_PIN_17_EINT17__FUNC_DBG_MON_B_11 (MTK_PIN_NO(17) | 7) + +#define MT8516_PIN_18_EINT18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define MT8516_PIN_18_EINT18__FUNC_USB_DRVVBUS (MTK_PIN_NO(18) | 2) +#define MT8516_PIN_18_EINT18__FUNC_I2S3_LRCK (MTK_PIN_NO(18) | 3) +#define MT8516_PIN_18_EINT18__FUNC_CLKM1 (MTK_PIN_NO(18) | 4) +#define MT8516_PIN_18_EINT18__FUNC_ANT_SEL3 (MTK_PIN_NO(18) | 5) +#define MT8516_PIN_18_EINT18__FUNC_I2S2_BCK (MTK_PIN_NO(18) | 6) +#define MT8516_PIN_18_EINT18__FUNC_DBG_MON_A_20 (MTK_PIN_NO(18) | 7) + +#define MT8516_PIN_19_EINT19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define MT8516_PIN_19_EINT19__FUNC_UCTS1 (MTK_PIN_NO(19) | 1) +#define MT8516_PIN_19_EINT19__FUNC_IDDIG (MTK_PIN_NO(19) | 2) +#define MT8516_PIN_19_EINT19__FUNC_I2S3_BCK (MTK_PIN_NO(19) | 3) +#define MT8516_PIN_19_EINT19__FUNC_CLKM2 (MTK_PIN_NO(19) | 4) +#define MT8516_PIN_19_EINT19__FUNC_ANT_SEL4 (MTK_PIN_NO(19) | 5) +#define MT8516_PIN_19_EINT19__FUNC_I2S2_DI (MTK_PIN_NO(19) | 6) +#define MT8516_PIN_19_EINT19__FUNC_DBG_MON_A_21 (MTK_PIN_NO(19) | 7) + +#define MT8516_PIN_20_EINT20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define MT8516_PIN_20_EINT20__FUNC_URTS1 (MTK_PIN_NO(20) | 1) +#define MT8516_PIN_20_EINT20__FUNC_I2S3_DO (MTK_PIN_NO(20) | 3) +#define MT8516_PIN_20_EINT20__FUNC_CLKM3 (MTK_PIN_NO(20) | 4) +#define MT8516_PIN_20_EINT20__FUNC_ANT_SEL5 (MTK_PIN_NO(20) | 5) +#define MT8516_PIN_20_EINT20__FUNC_I2S2_LRCK (MTK_PIN_NO(20) | 6) +#define MT8516_PIN_20_EINT20__FUNC_DBG_MON_A_22 (MTK_PIN_NO(20) | 7) + +#define MT8516_PIN_21_EINT21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define MT8516_PIN_21_EINT21__FUNC_NRNB (MTK_PIN_NO(21) | 1) +#define MT8516_PIN_21_EINT21__FUNC_ANT_SEL0 (MTK_PIN_NO(21) | 2) +#define MT8516_PIN_21_EINT21__FUNC_I2S_8CH_DO4 (MTK_PIN_NO(21) | 3) +#define MT8516_PIN_21_EINT21__FUNC_DBG_MON_B_31 (MTK_PIN_NO(21) | 7) + +#define MT8516_PIN_22_EINT22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define MT8516_PIN_22_EINT22__FUNC_I2S_8CH_DO2 (MTK_PIN_NO(22) | 2) +#define MT8516_PIN_22_EINT22__FUNC_TSF_IN (MTK_PIN_NO(22) | 3) +#define MT8516_PIN_22_EINT22__FUNC_USB_DRVVBUS (MTK_PIN_NO(22) | 4) +#define MT8516_PIN_22_EINT22__FUNC_SPDIF_OUT (MTK_PIN_NO(22) | 5) +#define MT8516_PIN_22_EINT22__FUNC_NRE_C (MTK_PIN_NO(22) | 6) +#define MT8516_PIN_22_EINT22__FUNC_DBG_MON_B_12 (MTK_PIN_NO(22) | 7) + +#define MT8516_PIN_23_EINT23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define MT8516_PIN_23_EINT23__FUNC_I2S_8CH_DO3 (MTK_PIN_NO(23) | 2) +#define MT8516_PIN_23_EINT23__FUNC_CLKM0 (MTK_PIN_NO(23) | 3) +#define MT8516_PIN_23_EINT23__FUNC_IR (MTK_PIN_NO(23) | 4) +#define MT8516_PIN_23_EINT23__FUNC_SPDIF_IN (MTK_PIN_NO(23) | 5) +#define MT8516_PIN_23_EINT23__FUNC_NDQS_C (MTK_PIN_NO(23) | 6) +#define MT8516_PIN_23_EINT23__FUNC_DBG_MON_B_13 (MTK_PIN_NO(23) | 7) + +#define MT8516_PIN_24_EINT24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define MT8516_PIN_24_EINT24__FUNC_ANT_SEL1 (MTK_PIN_NO(24) | 3) +#define MT8516_PIN_24_EINT24__FUNC_UCTS2 (MTK_PIN_NO(24) | 4) +#define MT8516_PIN_24_EINT24__FUNC_PWM_A (MTK_PIN_NO(24) | 5) +#define MT8516_PIN_24_EINT24__FUNC_I2S0_MCK (MTK_PIN_NO(24) | 6) +#define MT8516_PIN_24_EINT24__FUNC_DBG_MON_A_0 (MTK_PIN_NO(24) | 7) + +#define MT8516_PIN_25_EINT25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define MT8516_PIN_25_EINT25__FUNC_ANT_SEL0 (MTK_PIN_NO(25) | 3) +#define MT8516_PIN_25_EINT25__FUNC_URTS2 (MTK_PIN_NO(25) | 4) +#define MT8516_PIN_25_EINT25__FUNC_PWM_B (MTK_PIN_NO(25) | 5) +#define MT8516_PIN_25_EINT25__FUNC_I2S_8CH_MCK (MTK_PIN_NO(25) | 6) +#define MT8516_PIN_25_EINT25__FUNC_DBG_MON_A_1 (MTK_PIN_NO(25) | 7) + +#define MT8516_PIN_26_PWRAP_SPI0_MI__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define MT8516_PIN_26_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(26) | 1) +#define MT8516_PIN_26_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(26) | 2) + +#define MT8516_PIN_27_PWRAP_SPI0_MO__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define MT8516_PIN_27_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(27) | 1) +#define MT8516_PIN_27_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(27) | 2) + +#define MT8516_PIN_28_PWRAP_INT__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define MT8516_PIN_28_PWRAP_INT__FUNC_I2S0_MCK (MTK_PIN_NO(28) | 1) +#define MT8516_PIN_28_PWRAP_INT__FUNC_I2S_8CH_MCK (MTK_PIN_NO(28) | 4) +#define MT8516_PIN_28_PWRAP_INT__FUNC_I2S2_MCK (MTK_PIN_NO(28) | 5) +#define MT8516_PIN_28_PWRAP_INT__FUNC_I2S3_MCK (MTK_PIN_NO(28) | 6) + +#define MT8516_PIN_29_PWRAP_SPI0_CK__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define MT8516_PIN_29_PWRAP_SPI0_CK__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(29) | 1) + +#define MT8516_PIN_30_PWRAP_SPI0_CSN__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define MT8516_PIN_30_PWRAP_SPI0_CSN__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(30) | 1) + +#define MT8516_PIN_31_RTC32K_CK__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define MT8516_PIN_31_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(31) | 1) + +#define MT8516_PIN_32_WATCHDOG__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define MT8516_PIN_32_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(32) | 1) + +#define MT8516_PIN_33_SRCLKENA__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define MT8516_PIN_33_SRCLKENA__FUNC_SRCLKENA0 (MTK_PIN_NO(33) | 1) + +#define MT8516_PIN_34_URXD2__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define MT8516_PIN_34_URXD2__FUNC_URXD2 (MTK_PIN_NO(34) | 1) +#define MT8516_PIN_34_URXD2__FUNC_UTXD2 (MTK_PIN_NO(34) | 3) +#define MT8516_PIN_34_URXD2__FUNC_DBG_SCL (MTK_PIN_NO(34) | 4) +#define MT8516_PIN_34_URXD2__FUNC_I2S2_MCK (MTK_PIN_NO(34) | 6) +#define MT8516_PIN_34_URXD2__FUNC_DBG_MON_B_0 (MTK_PIN_NO(34) | 7) + +#define MT8516_PIN_35_UTXD2__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define MT8516_PIN_35_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(35) | 1) +#define MT8516_PIN_35_UTXD2__FUNC_URXD2 (MTK_PIN_NO(35) | 3) +#define MT8516_PIN_35_UTXD2__FUNC_DBG_SDA (MTK_PIN_NO(35) | 4) +#define MT8516_PIN_35_UTXD2__FUNC_I2S3_MCK (MTK_PIN_NO(35) | 6) +#define MT8516_PIN_35_UTXD2__FUNC_DBG_MON_B_1 (MTK_PIN_NO(35) | 7) + +#define MT8516_PIN_36_MRG_CLK__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define MT8516_PIN_36_MRG_CLK__FUNC_MRG_CLK (MTK_PIN_NO(36) | 1) +#define MT8516_PIN_36_MRG_CLK__FUNC_I2S0_BCK (MTK_PIN_NO(36) | 3) +#define MT8516_PIN_36_MRG_CLK__FUNC_I2S3_BCK (MTK_PIN_NO(36) | 4) +#define MT8516_PIN_36_MRG_CLK__FUNC_PCM0_CLK (MTK_PIN_NO(36) | 5) +#define MT8516_PIN_36_MRG_CLK__FUNC_IR (MTK_PIN_NO(36) | 6) +#define MT8516_PIN_36_MRG_CLK__FUNC_DBG_MON_A_2 (MTK_PIN_NO(36) | 7) + +#define MT8516_PIN_37_MRG_SYNC__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define MT8516_PIN_37_MRG_SYNC__FUNC_MRG_SYNC (MTK_PIN_NO(37) | 1) +#define MT8516_PIN_37_MRG_SYNC__FUNC_I2S0_LRCK (MTK_PIN_NO(37) | 3) +#define MT8516_PIN_37_MRG_SYNC__FUNC_I2S3_LRCK (MTK_PIN_NO(37) | 4) +#define MT8516_PIN_37_MRG_SYNC__FUNC_PCM0_SYNC (MTK_PIN_NO(37) | 5) +#define MT8516_PIN_37_MRG_SYNC__FUNC_EXT_COL (MTK_PIN_NO(37) | 6) +#define MT8516_PIN_37_MRG_SYNC__FUNC_DBG_MON_A_3 (MTK_PIN_NO(37) | 7) + +#define MT8516_PIN_38_MRG_DI__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define MT8516_PIN_38_MRG_DI__FUNC_MRG_DI (MTK_PIN_NO(38) | 1) +#define MT8516_PIN_38_MRG_DI__FUNC_I2S0_DI (MTK_PIN_NO(38) | 3) +#define MT8516_PIN_38_MRG_DI__FUNC_I2S3_DO (MTK_PIN_NO(38) | 4) +#define MT8516_PIN_38_MRG_DI__FUNC_PCM0_DI (MTK_PIN_NO(38) | 5) +#define MT8516_PIN_38_MRG_DI__FUNC_EXT_MDIO (MTK_PIN_NO(38) | 6) +#define MT8516_PIN_38_MRG_DI__FUNC_DBG_MON_A_4 (MTK_PIN_NO(38) | 7) + +#define MT8516_PIN_39_MRG_DO__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define MT8516_PIN_39_MRG_DO__FUNC_MRG_DO (MTK_PIN_NO(39) | 1) +#define MT8516_PIN_39_MRG_DO__FUNC_I2S0_MCK (MTK_PIN_NO(39) | 3) +#define MT8516_PIN_39_MRG_DO__FUNC_I2S3_MCK (MTK_PIN_NO(39) | 4) +#define MT8516_PIN_39_MRG_DO__FUNC_PCM0_DO (MTK_PIN_NO(39) | 5) +#define MT8516_PIN_39_MRG_DO__FUNC_EXT_MDC (MTK_PIN_NO(39) | 6) +#define MT8516_PIN_39_MRG_DO__FUNC_DBG_MON_A_5 (MTK_PIN_NO(39) | 7) + +#define MT8516_PIN_40_KPROW0__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define MT8516_PIN_40_KPROW0__FUNC_KPROW0 (MTK_PIN_NO(40) | 1) +#define MT8516_PIN_40_KPROW0__FUNC_DBG_MON_B_4 (MTK_PIN_NO(40) | 7) + +#define MT8516_PIN_41_KPROW1__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define MT8516_PIN_41_KPROW1__FUNC_KPROW1 (MTK_PIN_NO(41) | 1) +#define MT8516_PIN_41_KPROW1__FUNC_IDDIG (MTK_PIN_NO(41) | 2) +#define MT8516_PIN_41_KPROW1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(41) | 3) +#define MT8516_PIN_41_KPROW1__FUNC_DBG_MON_B_5 (MTK_PIN_NO(41) | 7) + +#define MT8516_PIN_42_KPCOL0__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define MT8516_PIN_42_KPCOL0__FUNC_KPCOL0 (MTK_PIN_NO(42) | 1) +#define MT8516_PIN_42_KPCOL0__FUNC_DBG_MON_B_6 (MTK_PIN_NO(42) | 7) + +#define MT8516_PIN_43_KPCOL1__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define MT8516_PIN_43_KPCOL1__FUNC_KPCOL1 (MTK_PIN_NO(43) | 1) +#define MT8516_PIN_43_KPCOL1__FUNC_USB_DRVVBUS (MTK_PIN_NO(43) | 2) +#define MT8516_PIN_43_KPCOL1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(43) | 3) +#define MT8516_PIN_43_KPCOL1__FUNC_TSF_IN (MTK_PIN_NO(43) | 4) +#define MT8516_PIN_43_KPCOL1__FUNC_DBG_MON_B_7 (MTK_PIN_NO(43) | 7) + +#define MT8516_PIN_44_JTMS__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define MT8516_PIN_44_JTMS__FUNC_JTMS (MTK_PIN_NO(44) | 1) +#define MT8516_PIN_44_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(44) | 2) +#define MT8516_PIN_44_JTMS__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(44) | 3) +#define MT8516_PIN_44_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(44) | 5) +#define MT8516_PIN_44_JTMS__FUNC_UDI_TMS_XI (MTK_PIN_NO(44) | 6) + +#define MT8516_PIN_45_JTCK__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define MT8516_PIN_45_JTCK__FUNC_JTCK (MTK_PIN_NO(45) | 1) +#define MT8516_PIN_45_JTCK__FUNC_CONN_MCU_TCK (MTK_PIN_NO(45) | 2) +#define MT8516_PIN_45_JTCK__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(45) | 3) + +#define MT8516_PIN_46_JTDI__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define MT8516_PIN_46_JTDI__FUNC_JTDI (MTK_PIN_NO(46) | 1) +#define MT8516_PIN_46_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(46) | 2) + +#define MT8516_PIN_47_JTDO__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define MT8516_PIN_47_JTDO__FUNC_JTDO (MTK_PIN_NO(47) | 1) +#define MT8516_PIN_47_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(47) | 2) + +#define MT8516_PIN_48_SPI_CS__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define MT8516_PIN_48_SPI_CS__FUNC_SPI_CSB (MTK_PIN_NO(48) | 1) +#define MT8516_PIN_48_SPI_CS__FUNC_I2S0_DI (MTK_PIN_NO(48) | 3) +#define MT8516_PIN_48_SPI_CS__FUNC_I2S2_BCK (MTK_PIN_NO(48) | 4) +#define MT8516_PIN_48_SPI_CS__FUNC_DBG_MON_A_23 (MTK_PIN_NO(48) | 7) + +#define MT8516_PIN_49_SPI_CK__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define MT8516_PIN_49_SPI_CK__FUNC_SPI_CLK (MTK_PIN_NO(49) | 1) +#define MT8516_PIN_49_SPI_CK__FUNC_I2S0_LRCK (MTK_PIN_NO(49) | 3) +#define MT8516_PIN_49_SPI_CK__FUNC_I2S2_DI (MTK_PIN_NO(49) | 4) +#define MT8516_PIN_49_SPI_CK__FUNC_DBG_MON_A_24 (MTK_PIN_NO(49) | 7) + +#define MT8516_PIN_50_SPI_MI__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define MT8516_PIN_50_SPI_MI__FUNC_SPI_MI (MTK_PIN_NO(50) | 1) +#define MT8516_PIN_50_SPI_MI__FUNC_SPI_MO (MTK_PIN_NO(50) | 2) +#define MT8516_PIN_50_SPI_MI__FUNC_I2S0_BCK (MTK_PIN_NO(50) | 3) +#define MT8516_PIN_50_SPI_MI__FUNC_I2S2_LRCK (MTK_PIN_NO(50) | 4) +#define MT8516_PIN_50_SPI_MI__FUNC_DBG_MON_A_25 (MTK_PIN_NO(50) | 7) + +#define MT8516_PIN_51_SPI_MO__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define MT8516_PIN_51_SPI_MO__FUNC_SPI_MO (MTK_PIN_NO(51) | 1) +#define MT8516_PIN_51_SPI_MO__FUNC_SPI_MI (MTK_PIN_NO(51) | 2) +#define MT8516_PIN_51_SPI_MO__FUNC_I2S0_MCK (MTK_PIN_NO(51) | 3) +#define MT8516_PIN_51_SPI_MO__FUNC_I2S2_MCK (MTK_PIN_NO(51) | 4) +#define MT8516_PIN_51_SPI_MO__FUNC_DBG_MON_A_26 (MTK_PIN_NO(51) | 7) + +#define MT8516_PIN_52_SDA1__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define MT8516_PIN_52_SDA1__FUNC_SDA1_0 (MTK_PIN_NO(52) | 1) + +#define MT8516_PIN_53_SCL1__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define MT8516_PIN_53_SCL1__FUNC_SCL1_0 (MTK_PIN_NO(53) | 1) + +#define MT8516_PIN_54_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define MT8516_PIN_54_GPIO54__FUNC_PWM_B (MTK_PIN_NO(54) | 2) +#define MT8516_PIN_54_GPIO54__FUNC_DBG_MON_B_2 (MTK_PIN_NO(54) | 7) + +#define MT8516_PIN_55_I2S_DATA_IN__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define MT8516_PIN_55_I2S_DATA_IN__FUNC_I2S0_DI (MTK_PIN_NO(55) | 1) +#define MT8516_PIN_55_I2S_DATA_IN__FUNC_UCTS0 (MTK_PIN_NO(55) | 2) +#define MT8516_PIN_55_I2S_DATA_IN__FUNC_I2S3_DO (MTK_PIN_NO(55) | 3) +#define MT8516_PIN_55_I2S_DATA_IN__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(55) | 4) +#define MT8516_PIN_55_I2S_DATA_IN__FUNC_PWM_A (MTK_PIN_NO(55) | 5) +#define MT8516_PIN_55_I2S_DATA_IN__FUNC_I2S2_BCK (MTK_PIN_NO(55) | 6) +#define MT8516_PIN_55_I2S_DATA_IN__FUNC_DBG_MON_A_28 (MTK_PIN_NO(55) | 7) + +#define MT8516_PIN_56_I2S_LRCK__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define MT8516_PIN_56_I2S_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(56) | 1) +#define MT8516_PIN_56_I2S_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(56) | 3) +#define MT8516_PIN_56_I2S_LRCK__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(56) | 4) +#define MT8516_PIN_56_I2S_LRCK__FUNC_PWM_B (MTK_PIN_NO(56) | 5) +#define MT8516_PIN_56_I2S_LRCK__FUNC_I2S2_DI (MTK_PIN_NO(56) | 6) +#define MT8516_PIN_56_I2S_LRCK__FUNC_DBG_MON_A_29 (MTK_PIN_NO(56) | 7) + +#define MT8516_PIN_57_I2S_BCK__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define MT8516_PIN_57_I2S_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(57) | 1) +#define MT8516_PIN_57_I2S_BCK__FUNC_URTS0 (MTK_PIN_NO(57) | 2) +#define MT8516_PIN_57_I2S_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(57) | 3) +#define MT8516_PIN_57_I2S_BCK__FUNC_I2S_8CH_BCK (MTK_PIN_NO(57) | 4) +#define MT8516_PIN_57_I2S_BCK__FUNC_PWM_C (MTK_PIN_NO(57) | 5) +#define MT8516_PIN_57_I2S_BCK__FUNC_I2S2_LRCK (MTK_PIN_NO(57) | 6) +#define MT8516_PIN_57_I2S_BCK__FUNC_DBG_MON_A_30 (MTK_PIN_NO(57) | 7) + +#define MT8516_PIN_58_SDA0__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define MT8516_PIN_58_SDA0__FUNC_SDA0_0 (MTK_PIN_NO(58) | 1) + +#define MT8516_PIN_59_SCL0__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define MT8516_PIN_59_SCL0__FUNC_SCL0_0 (MTK_PIN_NO(59) | 1) + +#define MT8516_PIN_60_SDA2__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define MT8516_PIN_60_SDA2__FUNC_SDA2_0 (MTK_PIN_NO(60) | 1) +#define MT8516_PIN_60_SDA2__FUNC_PWM_B (MTK_PIN_NO(60) | 2) + +#define MT8516_PIN_61_SCL2__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define MT8516_PIN_61_SCL2__FUNC_SCL2_0 (MTK_PIN_NO(61) | 1) +#define MT8516_PIN_61_SCL2__FUNC_PWM_C (MTK_PIN_NO(61) | 2) + +#define MT8516_PIN_62_URXD0__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define MT8516_PIN_62_URXD0__FUNC_URXD0 (MTK_PIN_NO(62) | 1) +#define MT8516_PIN_62_URXD0__FUNC_UTXD0 (MTK_PIN_NO(62) | 2) + +#define MT8516_PIN_63_UTXD0__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define MT8516_PIN_63_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(63) | 1) +#define MT8516_PIN_63_UTXD0__FUNC_URXD0 (MTK_PIN_NO(63) | 2) + +#define MT8516_PIN_64_URXD1__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define MT8516_PIN_64_URXD1__FUNC_URXD1 (MTK_PIN_NO(64) | 1) +#define MT8516_PIN_64_URXD1__FUNC_UTXD1 (MTK_PIN_NO(64) | 2) +#define MT8516_PIN_64_URXD1__FUNC_DBG_MON_A_27 (MTK_PIN_NO(64) | 7) + +#define MT8516_PIN_65_UTXD1__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define MT8516_PIN_65_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(65) | 1) +#define MT8516_PIN_65_UTXD1__FUNC_URXD1 (MTK_PIN_NO(65) | 2) +#define MT8516_PIN_65_UTXD1__FUNC_DBG_MON_A_31 (MTK_PIN_NO(65) | 7) + +#define MT8516_PIN_68_MSDC2_CMD__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define MT8516_PIN_68_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(68) | 1) +#define MT8516_PIN_68_MSDC2_CMD__FUNC_I2S_8CH_DO4 (MTK_PIN_NO(68) | 2) +#define MT8516_PIN_68_MSDC2_CMD__FUNC_SDA1_0 (MTK_PIN_NO(68) | 3) +#define MT8516_PIN_68_MSDC2_CMD__FUNC_USB_SDA (MTK_PIN_NO(68) | 5) +#define MT8516_PIN_68_MSDC2_CMD__FUNC_I2S3_BCK (MTK_PIN_NO(68) | 6) +#define MT8516_PIN_68_MSDC2_CMD__FUNC_DBG_MON_B_15 (MTK_PIN_NO(68) | 7) + +#define MT8516_PIN_69_MSDC2_CLK__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define MT8516_PIN_69_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(69) | 1) +#define MT8516_PIN_69_MSDC2_CLK__FUNC_I2S_8CH_DO3 (MTK_PIN_NO(69) | 2) +#define MT8516_PIN_69_MSDC2_CLK__FUNC_SCL1_0 (MTK_PIN_NO(69) | 3) +#define MT8516_PIN_69_MSDC2_CLK__FUNC_USB_SCL (MTK_PIN_NO(69) | 5) +#define MT8516_PIN_69_MSDC2_CLK__FUNC_I2S3_LRCK (MTK_PIN_NO(69) | 6) +#define MT8516_PIN_69_MSDC2_CLK__FUNC_DBG_MON_B_16 (MTK_PIN_NO(69) | 7) + +#define MT8516_PIN_70_MSDC2_DAT0__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define MT8516_PIN_70_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(70) | 1) +#define MT8516_PIN_70_MSDC2_DAT0__FUNC_I2S_8CH_DO2 (MTK_PIN_NO(70) | 2) +#define MT8516_PIN_70_MSDC2_DAT0__FUNC_UTXD0 (MTK_PIN_NO(70) | 5) +#define MT8516_PIN_70_MSDC2_DAT0__FUNC_I2S3_DO (MTK_PIN_NO(70) | 6) +#define MT8516_PIN_70_MSDC2_DAT0__FUNC_DBG_MON_B_17 (MTK_PIN_NO(70) | 7) + +#define MT8516_PIN_71_MSDC2_DAT1__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define MT8516_PIN_71_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(71) | 1) +#define MT8516_PIN_71_MSDC2_DAT1__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(71) | 2) +#define MT8516_PIN_71_MSDC2_DAT1__FUNC_PWM_A (MTK_PIN_NO(71) | 3) +#define MT8516_PIN_71_MSDC2_DAT1__FUNC_I2S3_MCK (MTK_PIN_NO(71) | 4) +#define MT8516_PIN_71_MSDC2_DAT1__FUNC_URXD0 (MTK_PIN_NO(71) | 5) +#define MT8516_PIN_71_MSDC2_DAT1__FUNC_PWM_B (MTK_PIN_NO(71) | 6) +#define MT8516_PIN_71_MSDC2_DAT1__FUNC_DBG_MON_B_18 (MTK_PIN_NO(71) | 7) + +#define MT8516_PIN_72_MSDC2_DAT2__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define MT8516_PIN_72_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(72) | 1) +#define MT8516_PIN_72_MSDC2_DAT2__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(72) | 2) +#define MT8516_PIN_72_MSDC2_DAT2__FUNC_SDA2_0 (MTK_PIN_NO(72) | 3) +#define MT8516_PIN_72_MSDC2_DAT2__FUNC_UTXD1 (MTK_PIN_NO(72) | 5) +#define MT8516_PIN_72_MSDC2_DAT2__FUNC_PWM_C (MTK_PIN_NO(72) | 6) +#define MT8516_PIN_72_MSDC2_DAT2__FUNC_DBG_MON_B_19 (MTK_PIN_NO(72) | 7) + +#define MT8516_PIN_73_MSDC2_DAT3__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define MT8516_PIN_73_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(73) | 1) +#define MT8516_PIN_73_MSDC2_DAT3__FUNC_I2S_8CH_BCK (MTK_PIN_NO(73) | 2) +#define MT8516_PIN_73_MSDC2_DAT3__FUNC_SCL2_0 (MTK_PIN_NO(73) | 3) +#define MT8516_PIN_73_MSDC2_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(73) | 4) +#define MT8516_PIN_73_MSDC2_DAT3__FUNC_URXD1 (MTK_PIN_NO(73) | 5) +#define MT8516_PIN_73_MSDC2_DAT3__FUNC_PWM_A (MTK_PIN_NO(73) | 6) +#define MT8516_PIN_73_MSDC2_DAT3__FUNC_DBG_MON_B_20 (MTK_PIN_NO(73) | 7) + +#define MT8516_PIN_74_TDN3__FUNC_GPI74 (MTK_PIN_NO(74) | 0) +#define MT8516_PIN_74_TDN3__FUNC_TDN3 (MTK_PIN_NO(74) | 1) + +#define MT8516_PIN_75_TDP3__FUNC_GPI75 (MTK_PIN_NO(75) | 0) +#define MT8516_PIN_75_TDP3__FUNC_TDP3 (MTK_PIN_NO(75) | 1) + +#define MT8516_PIN_76_TDN2__FUNC_GPI76 (MTK_PIN_NO(76) | 0) +#define MT8516_PIN_76_TDN2__FUNC_TDN2 (MTK_PIN_NO(76) | 1) + +#define MT8516_PIN_77_TDP2__FUNC_GPI77 (MTK_PIN_NO(77) | 0) +#define MT8516_PIN_77_TDP2__FUNC_TDP2 (MTK_PIN_NO(77) | 1) + +#define MT8516_PIN_78_TCN__FUNC_GPI78 (MTK_PIN_NO(78) | 0) +#define MT8516_PIN_78_TCN__FUNC_TCN (MTK_PIN_NO(78) | 1) + +#define MT8516_PIN_79_TCP__FUNC_GPI79 (MTK_PIN_NO(79) | 0) +#define MT8516_PIN_79_TCP__FUNC_TCP (MTK_PIN_NO(79) | 1) + +#define MT8516_PIN_80_TDN1__FUNC_GPI80 (MTK_PIN_NO(80) | 0) +#define MT8516_PIN_80_TDN1__FUNC_TDN1 (MTK_PIN_NO(80) | 1) + +#define MT8516_PIN_81_TDP1__FUNC_GPI81 (MTK_PIN_NO(81) | 0) +#define MT8516_PIN_81_TDP1__FUNC_TDP1 (MTK_PIN_NO(81) | 1) + +#define MT8516_PIN_82_TDN0__FUNC_GPI82 (MTK_PIN_NO(82) | 0) +#define MT8516_PIN_82_TDN0__FUNC_TDN0 (MTK_PIN_NO(82) | 1) + +#define MT8516_PIN_83_TDP0__FUNC_GPI83 (MTK_PIN_NO(83) | 0) +#define MT8516_PIN_83_TDP0__FUNC_TDP0 (MTK_PIN_NO(83) | 1) + +#define MT8516_PIN_84_RDN0__FUNC_GPI84 (MTK_PIN_NO(84) | 0) +#define MT8516_PIN_84_RDN0__FUNC_RDN0 (MTK_PIN_NO(84) | 1) + +#define MT8516_PIN_85_RDP0__FUNC_GPI85 (MTK_PIN_NO(85) | 0) +#define MT8516_PIN_85_RDP0__FUNC_RDP0 (MTK_PIN_NO(85) | 1) + +#define MT8516_PIN_86_RDN1__FUNC_GPI86 (MTK_PIN_NO(86) | 0) +#define MT8516_PIN_86_RDN1__FUNC_RDN1 (MTK_PIN_NO(86) | 1) + +#define MT8516_PIN_87_RDP1__FUNC_GPI87 (MTK_PIN_NO(87) | 0) +#define MT8516_PIN_87_RDP1__FUNC_RDP1 (MTK_PIN_NO(87) | 1) + +#define MT8516_PIN_88_RCN__FUNC_GPI88 (MTK_PIN_NO(88) | 0) +#define MT8516_PIN_88_RCN__FUNC_RCN (MTK_PIN_NO(88) | 1) + +#define MT8516_PIN_89_RCP__FUNC_GPI89 (MTK_PIN_NO(89) | 0) +#define MT8516_PIN_89_RCP__FUNC_RCP (MTK_PIN_NO(89) | 1) + +#define MT8516_PIN_90_RDN2__FUNC_GPI90 (MTK_PIN_NO(90) | 0) +#define MT8516_PIN_90_RDN2__FUNC_RDN2 (MTK_PIN_NO(90) | 1) +#define MT8516_PIN_90_RDN2__FUNC_CMDAT8 (MTK_PIN_NO(90) | 2) + +#define MT8516_PIN_91_RDP2__FUNC_GPI91 (MTK_PIN_NO(91) | 0) +#define MT8516_PIN_91_RDP2__FUNC_RDP2 (MTK_PIN_NO(91) | 1) +#define MT8516_PIN_91_RDP2__FUNC_CMDAT9 (MTK_PIN_NO(91) | 2) + +#define MT8516_PIN_92_RDN3__FUNC_GPI92 (MTK_PIN_NO(92) | 0) +#define MT8516_PIN_92_RDN3__FUNC_RDN3 (MTK_PIN_NO(92) | 1) +#define MT8516_PIN_92_RDN3__FUNC_CMDAT4 (MTK_PIN_NO(92) | 2) + +#define MT8516_PIN_93_RDP3__FUNC_GPI93 (MTK_PIN_NO(93) | 0) +#define MT8516_PIN_93_RDP3__FUNC_RDP3 (MTK_PIN_NO(93) | 1) +#define MT8516_PIN_93_RDP3__FUNC_CMDAT5 (MTK_PIN_NO(93) | 2) + +#define MT8516_PIN_94_RCN_A__FUNC_GPI94 (MTK_PIN_NO(94) | 0) +#define MT8516_PIN_94_RCN_A__FUNC_RCN_A (MTK_PIN_NO(94) | 1) +#define MT8516_PIN_94_RCN_A__FUNC_CMDAT6 (MTK_PIN_NO(94) | 2) + +#define MT8516_PIN_95_RCP_A__FUNC_GPI95 (MTK_PIN_NO(95) | 0) +#define MT8516_PIN_95_RCP_A__FUNC_RCP_A (MTK_PIN_NO(95) | 1) +#define MT8516_PIN_95_RCP_A__FUNC_CMDAT7 (MTK_PIN_NO(95) | 2) + +#define MT8516_PIN_96_RDN1_A__FUNC_GPI96 (MTK_PIN_NO(96) | 0) +#define MT8516_PIN_96_RDN1_A__FUNC_RDN1_A (MTK_PIN_NO(96) | 1) +#define MT8516_PIN_96_RDN1_A__FUNC_CMDAT2 (MTK_PIN_NO(96) | 2) +#define MT8516_PIN_96_RDN1_A__FUNC_CMCSD2 (MTK_PIN_NO(96) | 3) + +#define MT8516_PIN_97_RDP1_A__FUNC_GPI97 (MTK_PIN_NO(97) | 0) +#define MT8516_PIN_97_RDP1_A__FUNC_RDP1_A (MTK_PIN_NO(97) | 1) +#define MT8516_PIN_97_RDP1_A__FUNC_CMDAT3 (MTK_PIN_NO(97) | 2) +#define MT8516_PIN_97_RDP1_A__FUNC_CMCSD3 (MTK_PIN_NO(97) | 3) + +#define MT8516_PIN_98_RDN0_A__FUNC_GPI98 (MTK_PIN_NO(98) | 0) +#define MT8516_PIN_98_RDN0_A__FUNC_RDN0_A (MTK_PIN_NO(98) | 1) +#define MT8516_PIN_98_RDN0_A__FUNC_CMHSYNC (MTK_PIN_NO(98) | 2) + +#define MT8516_PIN_99_RDP0_A__FUNC_GPI99 (MTK_PIN_NO(99) | 0) +#define MT8516_PIN_99_RDP0_A__FUNC_RDP0_A (MTK_PIN_NO(99) | 1) +#define MT8516_PIN_99_RDP0_A__FUNC_CMVSYNC (MTK_PIN_NO(99) | 2) + +#define MT8516_PIN_100_CMDAT0__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define MT8516_PIN_100_CMDAT0__FUNC_CMDAT0 (MTK_PIN_NO(100) | 1) +#define MT8516_PIN_100_CMDAT0__FUNC_CMCSD0 (MTK_PIN_NO(100) | 2) +#define MT8516_PIN_100_CMDAT0__FUNC_ANT_SEL2 (MTK_PIN_NO(100) | 3) +#define MT8516_PIN_100_CMDAT0__FUNC_TDM_RX_MCK (MTK_PIN_NO(100) | 5) +#define MT8516_PIN_100_CMDAT0__FUNC_DBG_MON_B_21 (MTK_PIN_NO(100) | 7) + +#define MT8516_PIN_101_CMDAT1__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define MT8516_PIN_101_CMDAT1__FUNC_CMDAT1 (MTK_PIN_NO(101) | 1) +#define MT8516_PIN_101_CMDAT1__FUNC_CMCSD1 (MTK_PIN_NO(101) | 2) +#define MT8516_PIN_101_CMDAT1__FUNC_ANT_SEL3 (MTK_PIN_NO(101) | 3) +#define MT8516_PIN_101_CMDAT1__FUNC_CMFLASH (MTK_PIN_NO(101) | 4) +#define MT8516_PIN_101_CMDAT1__FUNC_TDM_RX_BCK (MTK_PIN_NO(101) | 5) +#define MT8516_PIN_101_CMDAT1__FUNC_DBG_MON_B_22 (MTK_PIN_NO(101) | 7) + +#define MT8516_PIN_102_CMMCLK__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define MT8516_PIN_102_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(102) | 1) +#define MT8516_PIN_102_CMMCLK__FUNC_ANT_SEL4 (MTK_PIN_NO(102) | 3) +#define MT8516_PIN_102_CMMCLK__FUNC_TDM_RX_LRCK (MTK_PIN_NO(102) | 5) +#define MT8516_PIN_102_CMMCLK__FUNC_DBG_MON_B_23 (MTK_PIN_NO(102) | 7) + +#define MT8516_PIN_103_CMPCLK__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define MT8516_PIN_103_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(103) | 1) +#define MT8516_PIN_103_CMPCLK__FUNC_CMCSK (MTK_PIN_NO(103) | 2) +#define MT8516_PIN_103_CMPCLK__FUNC_ANT_SEL5 (MTK_PIN_NO(103) | 3) +#define MT8516_PIN_103_CMPCLK__FUNC_TDM_RX_DI (MTK_PIN_NO(103) | 5) +#define MT8516_PIN_103_CMPCLK__FUNC_DBG_MON_B_24 (MTK_PIN_NO(103) | 7) + +#define MT8516_PIN_104_MSDC1_CMD__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define MT8516_PIN_104_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(104) | 1) +#define MT8516_PIN_104_MSDC1_CMD__FUNC_SQICS (MTK_PIN_NO(104) | 4) +#define MT8516_PIN_104_MSDC1_CMD__FUNC_DBG_MON_B_25 (MTK_PIN_NO(104) | 7) + +#define MT8516_PIN_105_MSDC1_CLK__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define MT8516_PIN_105_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(105) | 1) +#define MT8516_PIN_105_MSDC1_CLK__FUNC_SQISO (MTK_PIN_NO(105) | 4) +#define MT8516_PIN_105_MSDC1_CLK__FUNC_DBG_MON_B_26 (MTK_PIN_NO(105) | 7) + +#define MT8516_PIN_106_MSDC1_DAT0__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define MT8516_PIN_106_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(106) | 1) +#define MT8516_PIN_106_MSDC1_DAT0__FUNC_SQISI (MTK_PIN_NO(106) | 4) +#define MT8516_PIN_106_MSDC1_DAT0__FUNC_DBG_MON_B_27 (MTK_PIN_NO(106) | 7) + +#define MT8516_PIN_107_MSDC1_DAT1__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define MT8516_PIN_107_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(107) | 1) +#define MT8516_PIN_107_MSDC1_DAT1__FUNC_SQIWP (MTK_PIN_NO(107) | 4) +#define MT8516_PIN_107_MSDC1_DAT1__FUNC_DBG_MON_B_28 (MTK_PIN_NO(107) | 7) + +#define MT8516_PIN_108_MSDC1_DAT2__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define MT8516_PIN_108_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(108) | 1) +#define MT8516_PIN_108_MSDC1_DAT2__FUNC_SQIRST (MTK_PIN_NO(108) | 4) +#define MT8516_PIN_108_MSDC1_DAT2__FUNC_DBG_MON_B_29 (MTK_PIN_NO(108) | 7) + +#define MT8516_PIN_109_MSDC1_DAT3__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define MT8516_PIN_109_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(109) | 1) +#define MT8516_PIN_109_MSDC1_DAT3__FUNC_SQICK (MTK_PIN_NO(109) | 4) +#define MT8516_PIN_109_MSDC1_DAT3__FUNC_DBG_MON_B_30 (MTK_PIN_NO(109) | 7) + +#define MT8516_PIN_110_MSDC0_DAT7__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define MT8516_PIN_110_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(110) | 1) +#define MT8516_PIN_110_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(110) | 4) + +#define MT8516_PIN_111_MSDC0_DAT6__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define MT8516_PIN_111_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(111) | 1) +#define MT8516_PIN_111_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(111) | 4) + +#define MT8516_PIN_112_MSDC0_DAT5__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define MT8516_PIN_112_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(112) | 1) +#define MT8516_PIN_112_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(112) | 4) + +#define MT8516_PIN_113_MSDC0_DAT4__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define MT8516_PIN_113_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(113) | 1) +#define MT8516_PIN_113_MSDC0_DAT4__FUNC_NLD3 (MTK_PIN_NO(113) | 4) + +#define MT8516_PIN_114_MSDC0_RSTB__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define MT8516_PIN_114_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(114) | 1) +#define MT8516_PIN_114_MSDC0_RSTB__FUNC_NLD0 (MTK_PIN_NO(114) | 4) + +#define MT8516_PIN_115_MSDC0_CMD__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define MT8516_PIN_115_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(115) | 1) +#define MT8516_PIN_115_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(115) | 4) + +#define MT8516_PIN_116_MSDC0_CLK__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define MT8516_PIN_116_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(116) | 1) +#define MT8516_PIN_116_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(116) | 4) + +#define MT8516_PIN_117_MSDC0_DAT3__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define MT8516_PIN_117_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(117) | 1) +#define MT8516_PIN_117_MSDC0_DAT3__FUNC_NLD1 (MTK_PIN_NO(117) | 4) + +#define MT8516_PIN_118_MSDC0_DAT2__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define MT8516_PIN_118_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(118) | 1) +#define MT8516_PIN_118_MSDC0_DAT2__FUNC_NLD5 (MTK_PIN_NO(118) | 4) + +#define MT8516_PIN_119_MSDC0_DAT1__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define MT8516_PIN_119_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(119) | 1) +#define MT8516_PIN_119_MSDC0_DAT1__FUNC_NLD8 (MTK_PIN_NO(119) | 4) + +#define MT8516_PIN_120_MSDC0_DAT0__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define MT8516_PIN_120_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(120) | 1) +#define MT8516_PIN_120_MSDC0_DAT0__FUNC_WATCHDOG (MTK_PIN_NO(120) | 4) +#define MT8516_PIN_120_MSDC0_DAT0__FUNC_NLD2 (MTK_PIN_NO(120) | 5) + +#endif /* __DTS_MT8516_PINFUNC_H */ diff --git a/arch/arm64/boot/dts/mediatek/mt8516-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8516-pumpkin.dts new file mode 100644 index 000000000..cce642c53 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8516-pumpkin.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 BayLibre, SAS. + * Author: Fabien Parent <fparent@baylibre.com> + */ + +/dts-v1/; + +#include "mt8516.dtsi" +#include "pumpkin-common.dtsi" + +/ { + model = "Pumpkin MT8516"; + compatible = "mediatek,mt8516"; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi b/arch/arm64/boot/dts/mediatek/mt8516.dtsi new file mode 100644 index 000000000..d1b67c82d --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi @@ -0,0 +1,528 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 MediaTek Inc. + * Copyright (c) 2019 BayLibre, SAS. + * Author: Fabien Parent <fparent@baylibre.com> + */ + +#include <dt-bindings/clock/mt8516-clk.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/phy/phy.h> + +#include "mt8516-pinfunc.h" + +/ { + compatible = "mediatek,mt8516"; + interrupt-parent = <&sysirq>; + #address-cells = <2>; + #size-cells = <2>; + + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + opp-598000000 { + opp-hz = /bits/ 64 <598000000>; + opp-microvolt = <1150000>; + }; + opp-747500000 { + opp-hz = /bits/ 64 <747500000>; + opp-microvolt = <1150000>; + }; + opp-1040000000 { + opp-hz = /bits/ 64 <1040000000>; + opp-microvolt = <1200000>; + }; + opp-1196000000 { + opp-hz = /bits/ 64 <1196000000>; + opp-microvolt = <1250000>; + }; + opp-1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <1300000>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0>; + enable-method = "psci"; + cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, + <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; + clocks = <&infracfg CLK_IFR_MUX1_SEL>, + <&topckgen CLK_TOP_MAINPLL_D2>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x1>; + enable-method = "psci"; + cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, + <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; + clocks = <&infracfg CLK_IFR_MUX1_SEL>, + <&topckgen CLK_TOP_MAINPLL_D2>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x2>; + enable-method = "psci"; + cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, + <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; + clocks = <&infracfg CLK_IFR_MUX1_SEL>, + <&topckgen CLK_TOP_MAINPLL_D2>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x3>; + enable-method = "psci"; + cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, + <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; + clocks = <&infracfg CLK_IFR_MUX1_SEL>, + <&topckgen CLK_TOP_MAINPLL_D2>; + clock-names = "cpu", "intermediate", "armpll"; + operating-points-v2 = <&cluster0_opp>; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + entry-latency-us = <600>; + exit-latency-us = <600>; + min-residency-us = <1200>; + arm,psci-suspend-param = <0x0010000>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + entry-latency-us = <800>; + exit-latency-us = <1000>; + min-residency-us = <2000>; + arm,psci-suspend-param = <0x2010000>; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + clk26m: clk26m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + clk32k: clk32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + clock-output-names = "clk32k"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 128 KiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: secmon@43000000 { + no-map; + reg = <0 0x43000000 0 0x20000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + topckgen: topckgen@10000000 { + compatible = "mediatek,mt8516-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: infracfg@10001000 { + compatible = "mediatek,mt8516-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + pericfg: pericfg@10003050 { + compatible = "mediatek,mt8516-pericfg", "syscon"; + reg = <0 0x10003050 0 0x1000>; + }; + + apmixedsys: apmixedsys@10018000 { + compatible = "mediatek,mt8516-apmixedsys", "syscon"; + reg = <0 0x10018000 0 0x710>; + #clock-cells = <1>; + }; + + toprgu: toprgu@10007000 { + compatible = "mediatek,mt8516-wdt", + "mediatek,mt6589-wdt"; + reg = <0 0x10007000 0 0x1000>; + interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_FALLING>; + #reset-cells = <1>; + }; + + timer: timer@10008000 { + compatible = "mediatek,mt8516-timer", + "mediatek,mt6577-timer"; + reg = <0 0x10008000 0 0x1000>; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_CLK26M_D2>, + <&topckgen CLK_TOP_APXGPT>; + clock-names = "clk13m", "bus"; + }; + + syscfg_pctl: syscfg-pctl@10005000 { + compatible = "syscon"; + reg = <0 0x10005000 0 0x1000>; + }; + + pio: pinctrl@1000b000 { + compatible = "mediatek,mt8516-pinctrl"; + reg = <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl>; + pins-are-numbered; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; + }; + + efuse: efuse@10009000 { + compatible = "mediatek,mt8516-efuse", "mediatek,efuse"; + reg = <0 0x10009000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + pwrap: pwrap@1000f000 { + compatible = "mediatek,mt8516-pwrap"; + reg = <0 0x1000f000 0 0x1000>; + reg-names = "pwrap"; + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_PMICWRAP_26M>, + <&topckgen CLK_TOP_PMICWRAP_AP>; + clock-names = "spi", "wrap"; + }; + + sysirq: interrupt-controller@10200620 { + compatible = "mediatek,mt8516-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10200620 0 0x20>; + }; + + gic: interrupt-controller@10310000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x10310000 0 0x1000>, + <0 0x10320000 0 0x1000>, + <0 0x10340000 0 0x2000>, + <0 0x10360000 0 0x2000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + apdma: dma-controller@11000480 { + compatible = "mediatek,mt8516-uart-dma", + "mediatek,mt6577-uart-dma"; + reg = <0 0x11000480 0 0x80>, + <0 0x11000500 0 0x80>, + <0 0x11000580 0 0x80>, + <0 0x11000600 0 0x80>, + <0 0x11000980 0 0x80>, + <0 0x11000a00 0 0x80>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_LOW>; + dma-requests = <6>; + clocks = <&topckgen CLK_TOP_APDMA>; + clock-names = "apdma"; + #dma-cells = <1>; + }; + + uart0: serial@11005000 { + compatible = "mediatek,mt8516-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11005000 0 0x1000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_UART0_SEL>, + <&topckgen CLK_TOP_UART0>; + clock-names = "baud", "bus"; + dmas = <&apdma 0 + &apdma 1>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart1: serial@11006000 { + compatible = "mediatek,mt8516-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11006000 0 0x1000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_UART1_SEL>, + <&topckgen CLK_TOP_UART1>; + clock-names = "baud", "bus"; + dmas = <&apdma 2 + &apdma 3>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart2: serial@11007000 { + compatible = "mediatek,mt8516-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11007000 0 0x1000>; + interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_UART2_SEL>, + <&topckgen CLK_TOP_UART2>; + clock-names = "baud", "bus"; + dmas = <&apdma 4 + &apdma 5>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c0: i2c@11009000 { + compatible = "mediatek,mt8516-i2c", + "mediatek,mt2712-i2c"; + reg = <0 0x11009000 0 0x90>, + <0 0x11000180 0 0x80>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_I2C0>, + <&topckgen CLK_TOP_APDMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@1100a000 { + compatible = "mediatek,mt8516-i2c", + "mediatek,mt2712-i2c"; + reg = <0 0x1100a000 0 0x90>, + <0 0x11000200 0 0x80>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_I2C1>, + <&topckgen CLK_TOP_APDMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@1100b000 { + compatible = "mediatek,mt8516-i2c", + "mediatek,mt2712-i2c"; + reg = <0 0x1100b000 0 0x90>, + <0 0x11000280 0 0x80>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_I2C2>, + <&topckgen CLK_TOP_APDMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi: spi@1100c000 { + compatible = "mediatek,mt8516-spi", + "mediatek,mt2712-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100c000 0 0x1000>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_UNIVPLL_D12>, + <&topckgen CLK_TOP_SPI_SEL>, + <&topckgen CLK_TOP_SPI>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + mmc0: mmc@11120000 { + compatible = "mediatek,mt8516-mmc"; + reg = <0 0x11120000 0 0x1000>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_MSDC0>, + <&topckgen CLK_TOP_AHB_INFRA_SEL>, + <&topckgen CLK_TOP_MSDC0_INFRA>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + mmc1: mmc@11130000 { + compatible = "mediatek,mt8516-mmc"; + reg = <0 0x11130000 0 0x1000>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_MSDC1>, + <&topckgen CLK_TOP_AHB_INFRA_SEL>, + <&topckgen CLK_TOP_MSDC1_INFRA>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + mmc2: mmc@11170000 { + compatible = "mediatek,mt8516-mmc"; + reg = <0 0x11170000 0 0x1000>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_MSDC2>, + <&topckgen CLK_TOP_RG_MSDC2>, + <&topckgen CLK_TOP_MSDC2_INFRA>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + ethernet: ethernet@11180000 { + compatible = "mediatek,mt8516-eth"; + reg = <0 0x11180000 0 0x1000>; + mediatek,pericfg = <&pericfg>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_RG_ETH>, + <&topckgen CLK_TOP_66M_ETH>, + <&topckgen CLK_TOP_133M_ETH>; + clock-names = "core", "reg", "trans"; + status = "disabled"; + }; + + rng: rng@1020c000 { + compatible = "mediatek,mt8516-rng", + "mediatek,mt7623-rng"; + reg = <0 0x1020c000 0 0x100>; + clocks = <&topckgen CLK_TOP_TRNG>; + clock-names = "rng"; + }; + + pwm: pwm@11008000 { + compatible = "mediatek,mt8516-pwm"; + reg = <0 0x11008000 0 0x1000>; + #pwm-cells = <2>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_PWM>, + <&topckgen CLK_TOP_PWM_B>, + <&topckgen CLK_TOP_PWM1_FB>, + <&topckgen CLK_TOP_PWM2_FB>, + <&topckgen CLK_TOP_PWM3_FB>, + <&topckgen CLK_TOP_PWM4_FB>, + <&topckgen CLK_TOP_PWM5_FB>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3", + "pwm4", "pwm5"; + }; + + usb0: usb@11100000 { + compatible = "mediatek,mt8516-musb", "mediatek,mtk-musb"; + reg = <0 0x11100000 0 0x1000>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "mc"; + phys = <&usb0_port PHY_TYPE_USB2>; + clocks = <&topckgen CLK_TOP_USB>, + <&topckgen CLK_TOP_USBIF>, + <&topckgen CLK_TOP_USB_1P>; + clock-names = "main","mcu","univpll"; + status = "disabled"; + }; + + usb1: usb@11190000 { + compatible = "mediatek,mt8516-musb", "mediatek,mtk-musb"; + reg = <0 0x11190000 0 0x1000>; + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "mc"; + phys = <&usb1_port PHY_TYPE_USB2>; + clocks = <&topckgen CLK_TOP_USB>, + <&topckgen CLK_TOP_USBIF>, + <&topckgen CLK_TOP_USB_1P>; + clock-names = "main","mcu","univpll"; + dr_mode = "host"; + status = "disabled"; + }; + + usb_phy: t-phy@11110000 { + compatible = "mediatek,mt8516-tphy", + "mediatek,generic-tphy-v1"; + reg = <0 0x11110000 0 0x800>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb0_port: usb-phy@11110800 { + reg = <0 0x11110800 0 0x100>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; + #phy-cells = <1>; + }; + + usb1_port: usb-phy@11110900 { + reg = <0 0x11110900 0 0x100>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + + auxadc: adc@11003000 { + compatible = "mediatek,mt8516-auxadc", + "mediatek,mt8173-auxadc"; + reg = <0 0x11003000 0 0x1000>; + clocks = <&topckgen CLK_TOP_AUX_ADC>; + clock-names = "main"; + #io-channel-cells = <1>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi new file mode 100644 index 000000000..ec8dfb3d1 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi @@ -0,0 +1,255 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 BayLibre, SAS. + * Author: Fabien Parent <fparent@baylibre.com> + */ + +#include <dt-bindings/gpio/gpio.h> + +/ { + aliases { + serial0 = &uart0; + ethernet0 = ðernet; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_default>; + + key-volume-up { + gpios = <&pio 42 GPIO_ACTIVE_LOW>; + label = "volume_up"; + linux,code = <115>; + wakeup-source; + debounce-interval = <15>; + }; + + key-volume-down { + gpios = <&pio 43 GPIO_ACTIVE_LOW>; + label = "volume_down"; + linux,code = <114>; + wakeup-source; + debounce-interval = <15>; + }; + }; +}; + +&i2c0 { + clock-div = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + tca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + reset-gpios = <&pio 65 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&tca6416_pins>; + + gpio-controller; + #gpio-cells = <2>; + + eint20-mux-sel0-hog { + gpio-hog; + gpios = <0 0>; + input; + line-name = "eint20_mux_sel0"; + }; + + expcon-mux-sel1-hog { + gpio-hog; + gpios = <1 0>; + input; + line-name = "expcon_mux_sel1"; + }; + + mrg-di-mux-sel2-hog { + gpio-hog; + gpios = <2 0>; + input; + line-name = "mrg_di_mux_sel2"; + }; + + sd-sdio-mux-sel3-hog { + gpio-hog; + gpios = <3 0>; + input; + line-name = "sd_sdio_mux_sel3"; + }; + + sd-sdio-mux-ctrl7-hog { + gpio-hog; + gpios = <7 0>; + output-low; + line-name = "sd_sdio_mux_ctrl7"; + }; + + hw-id0-hog { + gpio-hog; + gpios = <8 0>; + input; + line-name = "hw_id0"; + }; + + hw-id1-hog { + gpio-hog; + gpios = <9 0>; + input; + line-name = "hw_id1"; + }; + + hw-id2-hog { + gpio-hog; + gpios = <10 0>; + input; + line-name = "hw_id2"; + }; + + fg-int-n-hog { + gpio-hog; + gpios = <11 0>; + input; + line-name = "fg_int_n"; + }; + + usba-pwr-en-hog { + gpio-hog; + gpios = <12 0>; + output-high; + line-name = "usba_pwr_en"; + }; + + wifi-3v3-pg-hog { + gpio-hog; + gpios = <13 0>; + input; + line-name = "wifi_3v3_pg"; + }; + + cam-rst-hog { + gpio-hog; + gpios = <14 0>; + output-low; + line-name = "cam_rst"; + }; + + cam-pwdn-hog { + gpio-hog; + gpios = <15 0>; + output-low; + line-name = "cam_pwdn"; + }; + }; +}; + +&i2c2 { + clock-div = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +ðernet { + pinctrl-names = "default"; + pinctrl-0 = <ðernet_pins_default>; + phy-handle = <ð_phy>; + phy-mode = "rmii"; + mac-address = [00 00 00 00 00 00]; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + eth_phy: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&usb0 { + status = "okay"; + dr_mode = "peripheral"; + usb-role-switch; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + }; +}; + +&usb_phy { + status = "okay"; +}; + +&pio { + gpio_keys_default: gpiodefault { + pins_cmd_dat { + pinmux = <MT8516_PIN_42_KPCOL0__FUNC_GPIO42>, + <MT8516_PIN_43_KPCOL1__FUNC_GPIO43>; + bias-pull-up; + input-enable; + }; + }; + + i2c0_pins_a: i2c0 { + pins1 { + pinmux = <MT8516_PIN_58_SDA0__FUNC_SDA0_0>, + <MT8516_PIN_59_SCL0__FUNC_SCL0_0>; + bias-disable; + }; + }; + + i2c2_pins_a: i2c2 { + pins1 { + pinmux = <MT8516_PIN_60_SDA2__FUNC_SDA2_0>, + <MT8516_PIN_61_SCL2__FUNC_SCL2_0>; + bias-disable; + }; + }; + + tca6416_pins: pinmux_tca6416_pins { + gpio_mux_rst_n_pin { + pinmux = <MT8516_PIN_65_UTXD1__FUNC_GPIO65>; + output-high; + }; + + gpio_mux_int_n_pin { + pinmux = <MT8516_PIN_64_URXD1__FUNC_GPIO64>; + input-enable; + bias-pull-up; + }; + }; + + ethernet_pins_default: ethernet { + pins_ethernet { + pinmux = <MT8516_PIN_0_EINT0__FUNC_EXT_TXD0>, + <MT8516_PIN_1_EINT1__FUNC_EXT_TXD1>, + <MT8516_PIN_5_EINT5__FUNC_EXT_RXER>, + <MT8516_PIN_6_EINT6__FUNC_EXT_RXC>, + <MT8516_PIN_7_EINT7__FUNC_EXT_RXDV>, + <MT8516_PIN_8_EINT8__FUNC_EXT_RXD0>, + <MT8516_PIN_9_EINT9__FUNC_EXT_RXD1>, + <MT8516_PIN_12_EINT12__FUNC_EXT_TXEN>, + <MT8516_PIN_38_MRG_DI__FUNC_EXT_MDIO>, + <MT8516_PIN_39_MRG_DO__FUNC_EXT_MDC>; + }; + }; +}; |