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authorDaniel Baumann <daniel.baumann@progress-linux.org>2024-04-07 18:49:45 +0000
committerDaniel Baumann <daniel.baumann@progress-linux.org>2024-04-07 18:49:45 +0000
commit2c3c1048746a4622d8c89a29670120dc8fab93c4 (patch)
tree848558de17fb3008cdf4d861b01ac7781903ce39 /drivers/media/pci/ddbridge
parentInitial commit. (diff)
downloadlinux-2c3c1048746a4622d8c89a29670120dc8fab93c4.tar.xz
linux-2c3c1048746a4622d8c89a29670120dc8fab93c4.zip
Adding upstream version 6.1.76.upstream/6.1.76
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'drivers/media/pci/ddbridge')
-rw-r--r--drivers/media/pci/ddbridge/Kconfig46
-rw-r--r--drivers/media/pci/ddbridge/Makefile13
-rw-r--r--drivers/media/pci/ddbridge/ddbridge-ci.c377
-rw-r--r--drivers/media/pci/ddbridge/ddbridge-ci.h20
-rw-r--r--drivers/media/pci/ddbridge/ddbridge-core.c3439
-rw-r--r--drivers/media/pci/ddbridge/ddbridge-dummy-fe.c153
-rw-r--r--drivers/media/pci/ddbridge/ddbridge-dummy-fe.h16
-rw-r--r--drivers/media/pci/ddbridge/ddbridge-hw.c379
-rw-r--r--drivers/media/pci/ddbridge/ddbridge-hw.h34
-rw-r--r--drivers/media/pci/ddbridge/ddbridge-i2c.c225
-rw-r--r--drivers/media/pci/ddbridge/ddbridge-i2c.h103
-rw-r--r--drivers/media/pci/ddbridge/ddbridge-io.h62
-rw-r--r--drivers/media/pci/ddbridge/ddbridge-main.c313
-rw-r--r--drivers/media/pci/ddbridge/ddbridge-max.c495
-rw-r--r--drivers/media/pci/ddbridge/ddbridge-max.h21
-rw-r--r--drivers/media/pci/ddbridge/ddbridge-mci.c169
-rw-r--r--drivers/media/pci/ddbridge/ddbridge-mci.h253
-rw-r--r--drivers/media/pci/ddbridge/ddbridge-regs.h140
-rw-r--r--drivers/media/pci/ddbridge/ddbridge-sx8.c477
-rw-r--r--drivers/media/pci/ddbridge/ddbridge.h373
20 files changed, 7108 insertions, 0 deletions
diff --git a/drivers/media/pci/ddbridge/Kconfig b/drivers/media/pci/ddbridge/Kconfig
new file mode 100644
index 000000000..169efd558
--- /dev/null
+++ b/drivers/media/pci/ddbridge/Kconfig
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config DVB_DDBRIDGE
+ tristate "Digital Devices bridge support"
+ depends on DVB_CORE && PCI && I2C
+ select DVB_LNBP21 if MEDIA_SUBDRV_AUTOSELECT
+ select DVB_STV6110x if MEDIA_SUBDRV_AUTOSELECT
+ select DVB_STV090x if MEDIA_SUBDRV_AUTOSELECT
+ select DVB_DRXK if MEDIA_SUBDRV_AUTOSELECT
+ select DVB_TDA18271C2DD if MEDIA_SUBDRV_AUTOSELECT
+ select DVB_STV0367 if MEDIA_SUBDRV_AUTOSELECT
+ select DVB_CXD2841ER if MEDIA_SUBDRV_AUTOSELECT
+ select DVB_STV0910 if MEDIA_SUBDRV_AUTOSELECT
+ select DVB_STV6111 if MEDIA_SUBDRV_AUTOSELECT
+ select DVB_LNBH25 if MEDIA_SUBDRV_AUTOSELECT
+ select MEDIA_TUNER_TDA18212 if MEDIA_SUBDRV_AUTOSELECT
+ select DVB_MXL5XX if MEDIA_SUBDRV_AUTOSELECT
+ select DVB_CXD2099 if MEDIA_SUBDRV_AUTOSELECT
+ help
+ Support for cards with the Digital Devices PCI express bridge:
+ - Octopus PCIe Bridge
+ - Octopus mini PCIe Bridge
+ - Octopus LE
+ - DuoFlex S2 Octopus
+ - DuoFlex CT Octopus
+ - cineS2(v6)
+ - CineCTv6 and DuoFlex CT (STV0367-based)
+ - CineCTv7 and DuoFlex CT2/C2T2/C2T2I (Sony CXD28xx-based)
+ - MaxA8 series
+ - CineS2 V7/V7A and DuoFlex S2 V4 (ST STV0910-based)
+ - Max S4/8
+
+ Say Y if you own such a card and want to use it.
+
+config DVB_DDBRIDGE_MSIENABLE
+ bool "Enable Message Signaled Interrupts (MSI) per default (EXPERIMENTAL)"
+ depends on DVB_DDBRIDGE
+ depends on PCI_MSI
+ help
+ Use PCI MSI (Message Signaled Interrupts) per default. Enabling this
+ might lead to I2C errors originating from the bridge in conjunction
+ with certain SATA controllers, requiring a reload of the ddbridge
+ module. MSI can still be disabled by passing msi=0 as option, as
+ this will just change the msi option default value.
+
+ If you're unsure, concerned about stability and don't want to pass
+ module options in case of troubles, say N.
diff --git a/drivers/media/pci/ddbridge/Makefile b/drivers/media/pci/ddbridge/Makefile
new file mode 100644
index 000000000..5e7eab811
--- /dev/null
+++ b/drivers/media/pci/ddbridge/Makefile
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile for the ddbridge device driver
+#
+
+ddbridge-objs := ddbridge-main.o ddbridge-core.o ddbridge-ci.o \
+ ddbridge-hw.o ddbridge-i2c.o ddbridge-max.o ddbridge-mci.o \
+ ddbridge-sx8.o
+
+obj-$(CONFIG_DVB_DDBRIDGE) += ddbridge.o ddbridge-dummy-fe.o
+
+ccflags-y += -I $(srctree)/drivers/media/dvb-frontends/
+ccflags-y += -I $(srctree)/drivers/media/tuners/
diff --git a/drivers/media/pci/ddbridge/ddbridge-ci.c b/drivers/media/pci/ddbridge/ddbridge-ci.c
new file mode 100644
index 000000000..ee20813c3
--- /dev/null
+++ b/drivers/media/pci/ddbridge/ddbridge-ci.c
@@ -0,0 +1,377 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ddbridge-ci.c: Digital Devices bridge CI (DuoFlex, CI Bridge) support
+ *
+ * Copyright (C) 2010-2017 Digital Devices GmbH
+ * Marcus Metzler <mocm@metzlerbros.de>
+ * Ralph Metzler <rjkm@metzlerbros.de>
+ */
+
+#include "ddbridge.h"
+#include "ddbridge-regs.h"
+#include "ddbridge-ci.h"
+#include "ddbridge-io.h"
+#include "ddbridge-i2c.h"
+
+#include "cxd2099.h"
+
+/* Octopus CI internal CI interface */
+
+static int wait_ci_ready(struct ddb_ci *ci)
+{
+ u32 count = 10;
+
+ ndelay(500);
+ do {
+ if (ddbreadl(ci->port->dev,
+ CI_CONTROL(ci->nr)) & CI_READY)
+ break;
+ usleep_range(1, 2);
+ if ((--count) == 0)
+ return -1;
+ } while (1);
+ return 0;
+}
+
+static int read_attribute_mem(struct dvb_ca_en50221 *ca,
+ int slot, int address)
+{
+ struct ddb_ci *ci = ca->data;
+ u32 val, off = (address >> 1) & (CI_BUFFER_SIZE - 1);
+
+ if (address > CI_BUFFER_SIZE)
+ return -1;
+ ddbwritel(ci->port->dev, CI_READ_CMD | (1 << 16) | address,
+ CI_DO_READ_ATTRIBUTES(ci->nr));
+ wait_ci_ready(ci);
+ val = 0xff & ddbreadl(ci->port->dev, CI_BUFFER(ci->nr) + off);
+ return val;
+}
+
+static int write_attribute_mem(struct dvb_ca_en50221 *ca, int slot,
+ int address, u8 value)
+{
+ struct ddb_ci *ci = ca->data;
+
+ ddbwritel(ci->port->dev, CI_WRITE_CMD | (value << 16) | address,
+ CI_DO_ATTRIBUTE_RW(ci->nr));
+ wait_ci_ready(ci);
+ return 0;
+}
+
+static int read_cam_control(struct dvb_ca_en50221 *ca,
+ int slot, u8 address)
+{
+ u32 count = 100;
+ struct ddb_ci *ci = ca->data;
+ u32 res;
+
+ ddbwritel(ci->port->dev, CI_READ_CMD | address,
+ CI_DO_IO_RW(ci->nr));
+ ndelay(500);
+ do {
+ res = ddbreadl(ci->port->dev, CI_READDATA(ci->nr));
+ if (res & CI_READY)
+ break;
+ usleep_range(1, 2);
+ if ((--count) == 0)
+ return -1;
+ } while (1);
+ return 0xff & res;
+}
+
+static int write_cam_control(struct dvb_ca_en50221 *ca, int slot,
+ u8 address, u8 value)
+{
+ struct ddb_ci *ci = ca->data;
+
+ ddbwritel(ci->port->dev, CI_WRITE_CMD | (value << 16) | address,
+ CI_DO_IO_RW(ci->nr));
+ wait_ci_ready(ci);
+ return 0;
+}
+
+static int slot_reset(struct dvb_ca_en50221 *ca, int slot)
+{
+ struct ddb_ci *ci = ca->data;
+
+ ddbwritel(ci->port->dev, CI_POWER_ON,
+ CI_CONTROL(ci->nr));
+ msleep(100);
+ ddbwritel(ci->port->dev, CI_POWER_ON | CI_RESET_CAM,
+ CI_CONTROL(ci->nr));
+ ddbwritel(ci->port->dev, CI_ENABLE | CI_POWER_ON | CI_RESET_CAM,
+ CI_CONTROL(ci->nr));
+ usleep_range(20, 25);
+ ddbwritel(ci->port->dev, CI_ENABLE | CI_POWER_ON,
+ CI_CONTROL(ci->nr));
+ return 0;
+}
+
+static int slot_shutdown(struct dvb_ca_en50221 *ca, int slot)
+{
+ struct ddb_ci *ci = ca->data;
+
+ ddbwritel(ci->port->dev, 0, CI_CONTROL(ci->nr));
+ msleep(300);
+ return 0;
+}
+
+static int slot_ts_enable(struct dvb_ca_en50221 *ca, int slot)
+{
+ struct ddb_ci *ci = ca->data;
+ u32 val = ddbreadl(ci->port->dev, CI_CONTROL(ci->nr));
+
+ ddbwritel(ci->port->dev, val | CI_BYPASS_DISABLE,
+ CI_CONTROL(ci->nr));
+ return 0;
+}
+
+static int poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open)
+{
+ struct ddb_ci *ci = ca->data;
+ u32 val = ddbreadl(ci->port->dev, CI_CONTROL(ci->nr));
+ int stat = 0;
+
+ if (val & CI_CAM_DETECT)
+ stat |= DVB_CA_EN50221_POLL_CAM_PRESENT;
+ if (val & CI_CAM_READY)
+ stat |= DVB_CA_EN50221_POLL_CAM_READY;
+ return stat;
+}
+
+static struct dvb_ca_en50221 en_templ = {
+ .read_attribute_mem = read_attribute_mem,
+ .write_attribute_mem = write_attribute_mem,
+ .read_cam_control = read_cam_control,
+ .write_cam_control = write_cam_control,
+ .slot_reset = slot_reset,
+ .slot_shutdown = slot_shutdown,
+ .slot_ts_enable = slot_ts_enable,
+ .poll_slot_status = poll_slot_status,
+};
+
+static void ci_attach(struct ddb_port *port)
+{
+ struct ddb_ci *ci;
+
+ ci = kzalloc(sizeof(*ci), GFP_KERNEL);
+ if (!ci)
+ return;
+ memcpy(&ci->en, &en_templ, sizeof(en_templ));
+ ci->en.data = ci;
+ port->en = &ci->en;
+ port->en_freedata = 1;
+ ci->port = port;
+ ci->nr = port->nr - 2;
+}
+
+/* DuoFlex Dual CI support */
+
+static int write_creg(struct ddb_ci *ci, u8 data, u8 mask)
+{
+ struct i2c_adapter *i2c = &ci->port->i2c->adap;
+ u8 adr = (ci->port->type == DDB_CI_EXTERNAL_XO2) ? 0x12 : 0x13;
+
+ ci->port->creg = (ci->port->creg & ~mask) | data;
+ return i2c_write_reg(i2c, adr, 0x02, ci->port->creg);
+}
+
+static int read_attribute_mem_xo2(struct dvb_ca_en50221 *ca,
+ int slot, int address)
+{
+ struct ddb_ci *ci = ca->data;
+ struct i2c_adapter *i2c = &ci->port->i2c->adap;
+ u8 adr = (ci->port->type == DDB_CI_EXTERNAL_XO2) ? 0x12 : 0x13;
+ int res;
+ u8 val;
+
+ res = i2c_read_reg16(i2c, adr, 0x8000 | address, &val);
+ return res ? res : val;
+}
+
+static int write_attribute_mem_xo2(struct dvb_ca_en50221 *ca, int slot,
+ int address, u8 value)
+{
+ struct ddb_ci *ci = ca->data;
+ struct i2c_adapter *i2c = &ci->port->i2c->adap;
+ u8 adr = (ci->port->type == DDB_CI_EXTERNAL_XO2) ? 0x12 : 0x13;
+
+ return i2c_write_reg16(i2c, adr, 0x8000 | address, value);
+}
+
+static int read_cam_control_xo2(struct dvb_ca_en50221 *ca,
+ int slot, u8 address)
+{
+ struct ddb_ci *ci = ca->data;
+ struct i2c_adapter *i2c = &ci->port->i2c->adap;
+ u8 adr = (ci->port->type == DDB_CI_EXTERNAL_XO2) ? 0x12 : 0x13;
+ u8 val;
+ int res;
+
+ res = i2c_read_reg(i2c, adr, 0x20 | (address & 3), &val);
+ return res ? res : val;
+}
+
+static int write_cam_control_xo2(struct dvb_ca_en50221 *ca, int slot,
+ u8 address, u8 value)
+{
+ struct ddb_ci *ci = ca->data;
+ struct i2c_adapter *i2c = &ci->port->i2c->adap;
+ u8 adr = (ci->port->type == DDB_CI_EXTERNAL_XO2) ? 0x12 : 0x13;
+
+ return i2c_write_reg(i2c, adr, 0x20 | (address & 3), value);
+}
+
+static int slot_reset_xo2(struct dvb_ca_en50221 *ca, int slot)
+{
+ struct ddb_ci *ci = ca->data;
+
+ dev_dbg(ci->port->dev->dev, "%s\n", __func__);
+ write_creg(ci, 0x01, 0x01);
+ write_creg(ci, 0x04, 0x04);
+ msleep(20);
+ write_creg(ci, 0x02, 0x02);
+ write_creg(ci, 0x00, 0x04);
+ write_creg(ci, 0x18, 0x18);
+ return 0;
+}
+
+static int slot_shutdown_xo2(struct dvb_ca_en50221 *ca, int slot)
+{
+ struct ddb_ci *ci = ca->data;
+
+ dev_dbg(ci->port->dev->dev, "%s\n", __func__);
+ write_creg(ci, 0x10, 0xff);
+ write_creg(ci, 0x08, 0x08);
+ return 0;
+}
+
+static int slot_ts_enable_xo2(struct dvb_ca_en50221 *ca, int slot)
+{
+ struct ddb_ci *ci = ca->data;
+
+ dev_dbg(ci->port->dev->dev, "%s\n", __func__);
+ write_creg(ci, 0x00, 0x10);
+ return 0;
+}
+
+static int poll_slot_status_xo2(struct dvb_ca_en50221 *ca, int slot, int open)
+{
+ struct ddb_ci *ci = ca->data;
+ struct i2c_adapter *i2c = &ci->port->i2c->adap;
+ u8 adr = (ci->port->type == DDB_CI_EXTERNAL_XO2) ? 0x12 : 0x13;
+ u8 val = 0;
+ int stat = 0;
+
+ i2c_read_reg(i2c, adr, 0x01, &val);
+
+ if (val & 2)
+ stat |= DVB_CA_EN50221_POLL_CAM_PRESENT;
+ if (val & 1)
+ stat |= DVB_CA_EN50221_POLL_CAM_READY;
+ return stat;
+}
+
+static struct dvb_ca_en50221 en_xo2_templ = {
+ .read_attribute_mem = read_attribute_mem_xo2,
+ .write_attribute_mem = write_attribute_mem_xo2,
+ .read_cam_control = read_cam_control_xo2,
+ .write_cam_control = write_cam_control_xo2,
+ .slot_reset = slot_reset_xo2,
+ .slot_shutdown = slot_shutdown_xo2,
+ .slot_ts_enable = slot_ts_enable_xo2,
+ .poll_slot_status = poll_slot_status_xo2,
+};
+
+static void ci_xo2_attach(struct ddb_port *port)
+{
+ struct ddb_ci *ci;
+
+ ci = kzalloc(sizeof(*ci), GFP_KERNEL);
+ if (!ci)
+ return;
+ memcpy(&ci->en, &en_xo2_templ, sizeof(en_xo2_templ));
+ ci->en.data = ci;
+ port->en = &ci->en;
+ port->en_freedata = 1;
+ ci->port = port;
+ ci->nr = port->nr - 2;
+ ci->port->creg = 0;
+ write_creg(ci, 0x10, 0xff);
+ write_creg(ci, 0x08, 0x08);
+}
+
+static const struct cxd2099_cfg cxd_cfgtmpl = {
+ .bitrate = 72000,
+ .polarity = 1,
+ .clock_mode = 1,
+ .max_i2c = 512,
+};
+
+static int ci_cxd2099_attach(struct ddb_port *port, u32 bitrate)
+{
+ struct cxd2099_cfg cxd_cfg = cxd_cfgtmpl;
+ struct i2c_client *client;
+
+ cxd_cfg.bitrate = bitrate;
+ cxd_cfg.en = &port->en;
+
+ client = dvb_module_probe("cxd2099", NULL, &port->i2c->adap,
+ 0x40, &cxd_cfg);
+ if (!client)
+ goto err;
+
+ port->dvb[0].i2c_client[0] = client;
+ port->en_freedata = 0;
+ return 0;
+
+err:
+ dev_err(port->dev->dev, "CXD2099AR attach failed\n");
+ return -ENODEV;
+}
+
+int ddb_ci_attach(struct ddb_port *port, u32 bitrate)
+{
+ int ret;
+
+ switch (port->type) {
+ case DDB_CI_EXTERNAL_SONY:
+ ret = ci_cxd2099_attach(port, bitrate);
+ if (ret)
+ return -ENODEV;
+ break;
+ case DDB_CI_EXTERNAL_XO2:
+ case DDB_CI_EXTERNAL_XO2_B:
+ ci_xo2_attach(port);
+ break;
+ case DDB_CI_INTERNAL:
+ ci_attach(port);
+ break;
+ default:
+ return -ENODEV;
+ }
+
+ if (!port->en)
+ return -ENODEV;
+ dvb_ca_en50221_init(port->dvb[0].adap, port->en, 0, 1);
+ return 0;
+}
+
+void ddb_ci_detach(struct ddb_port *port)
+{
+ if (port->dvb[0].dev)
+ dvb_unregister_device(port->dvb[0].dev);
+ if (port->en) {
+ dvb_ca_en50221_release(port->en);
+
+ dvb_module_release(port->dvb[0].i2c_client[0]);
+ port->dvb[0].i2c_client[0] = NULL;
+
+ /* free alloc'ed memory if needed */
+ if (port->en_freedata)
+ kfree(port->en->data);
+
+ port->en = NULL;
+ }
+}
diff --git a/drivers/media/pci/ddbridge/ddbridge-ci.h b/drivers/media/pci/ddbridge/ddbridge-ci.h
new file mode 100644
index 000000000..41cd97e52
--- /dev/null
+++ b/drivers/media/pci/ddbridge/ddbridge-ci.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * ddbridge-ci.h: Digital Devices bridge CI (DuoFlex, CI Bridge) support
+ *
+ * Copyright (C) 2010-2017 Digital Devices GmbH
+ * Marcus Metzler <mocm@metzlerbros.de>
+ * Ralph Metzler <rjkm@metzlerbros.de>
+ */
+
+#ifndef __DDBRIDGE_CI_H__
+#define __DDBRIDGE_CI_H__
+
+#include "ddbridge.h"
+
+/******************************************************************************/
+
+int ddb_ci_attach(struct ddb_port *port, u32 bitrate);
+void ddb_ci_detach(struct ddb_port *port);
+
+#endif /* __DDBRIDGE_CI_H__ */
diff --git a/drivers/media/pci/ddbridge/ddbridge-core.c b/drivers/media/pci/ddbridge/ddbridge-core.c
new file mode 100644
index 000000000..fe833f396
--- /dev/null
+++ b/drivers/media/pci/ddbridge/ddbridge-core.c
@@ -0,0 +1,3439 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ddbridge-core.c: Digital Devices bridge core functions
+ *
+ * Copyright (C) 2010-2017 Digital Devices GmbH
+ * Marcus Metzler <mocm@metzlerbros.de>
+ * Ralph Metzler <rjkm@metzlerbros.de>
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/poll.h>
+#include <linux/io.h>
+#include <linux/pci.h>
+#include <linux/pci_ids.h>
+#include <linux/timer.h>
+#include <linux/i2c.h>
+#include <linux/swab.h>
+#include <linux/vmalloc.h>
+
+#include "ddbridge.h"
+#include "ddbridge-i2c.h"
+#include "ddbridge-regs.h"
+#include "ddbridge-max.h"
+#include "ddbridge-ci.h"
+#include "ddbridge-io.h"
+
+#include "tda18271c2dd.h"
+#include "stv6110x.h"
+#include "stv090x.h"
+#include "lnbh24.h"
+#include "drxk.h"
+#include "stv0367.h"
+#include "stv0367_priv.h"
+#include "cxd2841er.h"
+#include "tda18212.h"
+#include "stv0910.h"
+#include "stv6111.h"
+#include "lnbh25.h"
+#include "cxd2099.h"
+#include "ddbridge-dummy-fe.h"
+
+/****************************************************************************/
+
+#define DDB_MAX_ADAPTER 64
+
+/****************************************************************************/
+
+DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
+
+static int adapter_alloc;
+module_param(adapter_alloc, int, 0444);
+MODULE_PARM_DESC(adapter_alloc,
+ "0-one adapter per io, 1-one per tab with io, 2-one per tab, 3-one for all");
+
+static int ci_bitrate = 70000;
+module_param(ci_bitrate, int, 0444);
+MODULE_PARM_DESC(ci_bitrate, " Bitrate in KHz for output to CI.");
+
+static int ts_loop = -1;
+module_param(ts_loop, int, 0444);
+MODULE_PARM_DESC(ts_loop, "TS in/out test loop on port ts_loop");
+
+static int xo2_speed = 2;
+module_param(xo2_speed, int, 0444);
+MODULE_PARM_DESC(xo2_speed, "default transfer speed for xo2 based duoflex, 0=55,1=75,2=90,3=104 MBit/s, default=2, use attribute to change for individual cards");
+
+#ifdef __arm__
+static int alt_dma = 1;
+#else
+static int alt_dma;
+#endif
+module_param(alt_dma, int, 0444);
+MODULE_PARM_DESC(alt_dma, "use alternative DMA buffer handling");
+
+static int no_init;
+module_param(no_init, int, 0444);
+MODULE_PARM_DESC(no_init, "do not initialize most devices");
+
+static int stv0910_single;
+module_param(stv0910_single, int, 0444);
+MODULE_PARM_DESC(stv0910_single, "use stv0910 cards as single demods");
+
+static int dma_buf_num = 8;
+module_param(dma_buf_num, int, 0444);
+MODULE_PARM_DESC(dma_buf_num, "Number of DMA buffers, possible values: 8-32");
+
+static int dma_buf_size = 21;
+module_param(dma_buf_size, int, 0444);
+MODULE_PARM_DESC(dma_buf_size,
+ "DMA buffer size as multiple of 128*47, possible values: 1-43");
+
+static int dummy_tuner;
+module_param(dummy_tuner, int, 0444);
+MODULE_PARM_DESC(dummy_tuner,
+ "attach dummy tuner to port 0 on Octopus V3 or Octopus Mini cards");
+
+/****************************************************************************/
+
+static DEFINE_MUTEX(redirect_lock);
+
+static struct workqueue_struct *ddb_wq;
+
+static struct ddb *ddbs[DDB_MAX_ADAPTER];
+
+/****************************************************************************/
+/****************************************************************************/
+/****************************************************************************/
+
+struct ddb_irq *ddb_irq_set(struct ddb *dev, u32 link, u32 nr,
+ void (*handler)(void *), void *data)
+{
+ struct ddb_irq *irq = &dev->link[link].irq[nr];
+
+ irq->handler = handler;
+ irq->data = data;
+ return irq;
+}
+
+static void ddb_set_dma_table(struct ddb_io *io)
+{
+ struct ddb *dev = io->port->dev;
+ struct ddb_dma *dma = io->dma;
+ u32 i;
+ u64 mem;
+
+ if (!dma)
+ return;
+ for (i = 0; i < dma->num; i++) {
+ mem = dma->pbuf[i];
+ ddbwritel(dev, mem & 0xffffffff, dma->bufregs + i * 8);
+ ddbwritel(dev, mem >> 32, dma->bufregs + i * 8 + 4);
+ }
+ dma->bufval = ((dma->div & 0x0f) << 16) |
+ ((dma->num & 0x1f) << 11) |
+ ((dma->size >> 7) & 0x7ff);
+}
+
+static void ddb_set_dma_tables(struct ddb *dev)
+{
+ u32 i;
+
+ for (i = 0; i < DDB_MAX_PORT; i++) {
+ if (dev->port[i].input[0])
+ ddb_set_dma_table(dev->port[i].input[0]);
+ if (dev->port[i].input[1])
+ ddb_set_dma_table(dev->port[i].input[1]);
+ if (dev->port[i].output)
+ ddb_set_dma_table(dev->port[i].output);
+ }
+}
+
+/****************************************************************************/
+/****************************************************************************/
+/****************************************************************************/
+
+static void ddb_redirect_dma(struct ddb *dev,
+ struct ddb_dma *sdma,
+ struct ddb_dma *ddma)
+{
+ u32 i, base;
+ u64 mem;
+
+ sdma->bufval = ddma->bufval;
+ base = sdma->bufregs;
+ for (i = 0; i < ddma->num; i++) {
+ mem = ddma->pbuf[i];
+ ddbwritel(dev, mem & 0xffffffff, base + i * 8);
+ ddbwritel(dev, mem >> 32, base + i * 8 + 4);
+ }
+}
+
+static int ddb_unredirect(struct ddb_port *port)
+{
+ struct ddb_input *oredi, *iredi = NULL;
+ struct ddb_output *iredo = NULL;
+
+ /* dev_info(port->dev->dev,
+ * "unredirect %d.%d\n", port->dev->nr, port->nr);
+ */
+ mutex_lock(&redirect_lock);
+ if (port->output->dma->running) {
+ mutex_unlock(&redirect_lock);
+ return -EBUSY;
+ }
+ oredi = port->output->redi;
+ if (!oredi)
+ goto done;
+ if (port->input[0]) {
+ iredi = port->input[0]->redi;
+ iredo = port->input[0]->redo;
+
+ if (iredo) {
+ iredo->port->output->redi = oredi;
+ if (iredo->port->input[0]) {
+ iredo->port->input[0]->redi = iredi;
+ ddb_redirect_dma(oredi->port->dev,
+ oredi->dma, iredo->dma);
+ }
+ port->input[0]->redo = NULL;
+ ddb_set_dma_table(port->input[0]);
+ }
+ oredi->redi = iredi;
+ port->input[0]->redi = NULL;
+ }
+ oredi->redo = NULL;
+ port->output->redi = NULL;
+
+ ddb_set_dma_table(oredi);
+done:
+ mutex_unlock(&redirect_lock);
+ return 0;
+}
+
+static int ddb_redirect(u32 i, u32 p)
+{
+ struct ddb *idev = ddbs[(i >> 4) & 0x3f];
+ struct ddb_input *input, *input2;
+ struct ddb *pdev = ddbs[(p >> 4) & 0x3f];
+ struct ddb_port *port;
+
+ if (!idev || !pdev)
+ return -EINVAL;
+ if (!idev->has_dma || !pdev->has_dma)
+ return -EINVAL;
+
+ port = &pdev->port[p & 0x0f];
+ if (!port->output)
+ return -EINVAL;
+ if (ddb_unredirect(port))
+ return -EBUSY;
+
+ if (i == 8)
+ return 0;
+
+ input = &idev->input[i & 7];
+ if (!input)
+ return -EINVAL;
+
+ mutex_lock(&redirect_lock);
+ if (port->output->dma->running || input->dma->running) {
+ mutex_unlock(&redirect_lock);
+ return -EBUSY;
+ }
+ input2 = port->input[0];
+ if (input2) {
+ if (input->redi) {
+ input2->redi = input->redi;
+ input->redi = NULL;
+ } else {
+ input2->redi = input;
+ }
+ }
+ input->redo = port->output;
+ port->output->redi = input;
+
+ ddb_redirect_dma(input->port->dev, input->dma, port->output->dma);
+ mutex_unlock(&redirect_lock);
+ return 0;
+}
+
+/****************************************************************************/
+/****************************************************************************/
+/****************************************************************************/
+
+static void dma_free(struct pci_dev *pdev, struct ddb_dma *dma, int dir)
+{
+ int i;
+
+ if (!dma)
+ return;
+ for (i = 0; i < dma->num; i++) {
+ if (dma->vbuf[i]) {
+ if (alt_dma) {
+ dma_unmap_single(&pdev->dev, dma->pbuf[i],
+ dma->size,
+ dir ? DMA_TO_DEVICE :
+ DMA_FROM_DEVICE);
+ kfree(dma->vbuf[i]);
+ dma->vbuf[i] = NULL;
+ } else {
+ dma_free_coherent(&pdev->dev, dma->size,
+ dma->vbuf[i], dma->pbuf[i]);
+ }
+
+ dma->vbuf[i] = NULL;
+ }
+ }
+}
+
+static int dma_alloc(struct pci_dev *pdev, struct ddb_dma *dma, int dir)
+{
+ int i;
+
+ if (!dma)
+ return 0;
+ for (i = 0; i < dma->num; i++) {
+ if (alt_dma) {
+ dma->vbuf[i] = kmalloc(dma->size, __GFP_RETRY_MAYFAIL);
+ if (!dma->vbuf[i])
+ return -ENOMEM;
+ dma->pbuf[i] = dma_map_single(&pdev->dev,
+ dma->vbuf[i],
+ dma->size,
+ dir ? DMA_TO_DEVICE :
+ DMA_FROM_DEVICE);
+ if (dma_mapping_error(&pdev->dev, dma->pbuf[i])) {
+ kfree(dma->vbuf[i]);
+ dma->vbuf[i] = NULL;
+ return -ENOMEM;
+ }
+ } else {
+ dma->vbuf[i] = dma_alloc_coherent(&pdev->dev,
+ dma->size,
+ &dma->pbuf[i],
+ GFP_KERNEL);
+ if (!dma->vbuf[i])
+ return -ENOMEM;
+ }
+ }
+ return 0;
+}
+
+int ddb_buffers_alloc(struct ddb *dev)
+{
+ int i;
+ struct ddb_port *port;
+
+ for (i = 0; i < dev->port_num; i++) {
+ port = &dev->port[i];
+ switch (port->class) {
+ case DDB_PORT_TUNER:
+ if (port->input[0]->dma)
+ if (dma_alloc(dev->pdev, port->input[0]->dma, 0)
+ < 0)
+ return -1;
+ if (port->input[1]->dma)
+ if (dma_alloc(dev->pdev, port->input[1]->dma, 0)
+ < 0)
+ return -1;
+ break;
+ case DDB_PORT_CI:
+ case DDB_PORT_LOOP:
+ if (port->input[0]->dma)
+ if (dma_alloc(dev->pdev, port->input[0]->dma, 0)
+ < 0)
+ return -1;
+ if (port->output->dma)
+ if (dma_alloc(dev->pdev, port->output->dma, 1)
+ < 0)
+ return -1;
+ break;
+ default:
+ break;
+ }
+ }
+ ddb_set_dma_tables(dev);
+ return 0;
+}
+
+void ddb_buffers_free(struct ddb *dev)
+{
+ int i;
+ struct ddb_port *port;
+
+ for (i = 0; i < dev->port_num; i++) {
+ port = &dev->port[i];
+
+ if (port->input[0] && port->input[0]->dma)
+ dma_free(dev->pdev, port->input[0]->dma, 0);
+ if (port->input[1] && port->input[1]->dma)
+ dma_free(dev->pdev, port->input[1]->dma, 0);
+ if (port->output && port->output->dma)
+ dma_free(dev->pdev, port->output->dma, 1);
+ }
+}
+
+static void calc_con(struct ddb_output *output, u32 *con, u32 *con2, u32 flags)
+{
+ struct ddb *dev = output->port->dev;
+ u32 bitrate = output->port->obr, max_bitrate = 72000;
+ u32 gap = 4, nco = 0;
+
+ *con = 0x1c;
+ if (output->port->gap != 0xffffffff) {
+ flags |= 1;
+ gap = output->port->gap;
+ max_bitrate = 0;
+ }
+ if (dev->link[0].info->type == DDB_OCTOPUS_CI && output->port->nr > 1) {
+ *con = 0x10c;
+ if (dev->link[0].ids.regmapid >= 0x10003 && !(flags & 1)) {
+ if (!(flags & 2)) {
+ /* NCO */
+ max_bitrate = 0;
+ gap = 0;
+ if (bitrate != 72000) {
+ if (bitrate >= 96000) {
+ *con |= 0x800;
+ } else {
+ *con |= 0x1000;
+ nco = (bitrate * 8192 + 71999)
+ / 72000;
+ }
+ }
+ } else {
+ /* Divider and gap */
+ *con |= 0x1810;
+ if (bitrate <= 64000) {
+ max_bitrate = 64000;
+ nco = 8;
+ } else if (bitrate <= 72000) {
+ max_bitrate = 72000;
+ nco = 7;
+ } else {
+ max_bitrate = 96000;
+ nco = 5;
+ }
+ }
+ } else {
+ if (bitrate > 72000) {
+ *con |= 0x810; /* 96 MBit/s and gap */
+ max_bitrate = 96000;
+ }
+ *con |= 0x10; /* enable gap */
+ }
+ }
+ if (max_bitrate > 0) {
+ if (bitrate > max_bitrate)
+ bitrate = max_bitrate;
+ if (bitrate < 31000)
+ bitrate = 31000;
+ gap = ((max_bitrate - bitrate) * 94) / bitrate;
+ if (gap < 2)
+ *con &= ~0x10; /* Disable gap */
+ else
+ gap -= 2;
+ if (gap > 127)
+ gap = 127;
+ }
+
+ *con2 = (nco << 16) | gap;
+}
+
+static void ddb_output_start(struct ddb_output *output)
+{
+ struct ddb *dev = output->port->dev;
+ u32 con = 0x11c, con2 = 0;
+
+ spin_lock_irq(&output->dma->lock);
+ output->dma->cbuf = 0;
+ output->dma->coff = 0;
+ output->dma->stat = 0;
+ ddbwritel(dev, 0, DMA_BUFFER_CONTROL(output->dma));
+
+ if (output->port->input[0]->port->class == DDB_PORT_LOOP)
+ con = (1UL << 13) | 0x14;
+ else
+ calc_con(output, &con, &con2, 0);
+
+ ddbwritel(dev, 0, TS_CONTROL(output));
+ ddbwritel(dev, 2, TS_CONTROL(output));
+ ddbwritel(dev, 0, TS_CONTROL(output));
+ ddbwritel(dev, con, TS_CONTROL(output));
+ ddbwritel(dev, con2, TS_CONTROL2(output));
+
+ ddbwritel(dev, output->dma->bufval,
+ DMA_BUFFER_SIZE(output->dma));
+ ddbwritel(dev, 0, DMA_BUFFER_ACK(output->dma));
+ ddbwritel(dev, 1, DMA_BASE_READ);
+ ddbwritel(dev, 7, DMA_BUFFER_CONTROL(output->dma));
+
+ ddbwritel(dev, con | 1, TS_CONTROL(output));
+
+ output->dma->running = 1;
+ spin_unlock_irq(&output->dma->lock);
+}
+
+static void ddb_output_stop(struct ddb_output *output)
+{
+ struct ddb *dev = output->port->dev;
+
+ spin_lock_irq(&output->dma->lock);
+
+ ddbwritel(dev, 0, TS_CONTROL(output));
+
+ ddbwritel(dev, 0, DMA_BUFFER_CONTROL(output->dma));
+ output->dma->running = 0;
+ spin_unlock_irq(&output->dma->lock);
+}
+
+static void ddb_input_stop(struct ddb_input *input)
+{
+ struct ddb *dev = input->port->dev;
+ u32 tag = DDB_LINK_TAG(input->port->lnr);
+
+ spin_lock_irq(&input->dma->lock);
+
+ ddbwritel(dev, 0, tag | TS_CONTROL(input));
+
+ ddbwritel(dev, 0, DMA_BUFFER_CONTROL(input->dma));
+ input->dma->running = 0;
+ spin_unlock_irq(&input->dma->lock);
+}
+
+static void ddb_input_start(struct ddb_input *input)
+{
+ struct ddb *dev = input->port->dev;
+
+ spin_lock_irq(&input->dma->lock);
+ input->dma->cbuf = 0;
+ input->dma->coff = 0;
+ input->dma->stat = 0;
+ ddbwritel(dev, 0, DMA_BUFFER_CONTROL(input->dma));
+
+ ddbwritel(dev, 0, TS_CONTROL(input));
+ ddbwritel(dev, 2, TS_CONTROL(input));
+ ddbwritel(dev, 0, TS_CONTROL(input));
+
+ ddbwritel(dev, input->dma->bufval,
+ DMA_BUFFER_SIZE(input->dma));
+ ddbwritel(dev, 0, DMA_BUFFER_ACK(input->dma));
+ ddbwritel(dev, 1, DMA_BASE_WRITE);
+ ddbwritel(dev, 3, DMA_BUFFER_CONTROL(input->dma));
+
+ ddbwritel(dev, 0x09, TS_CONTROL(input));
+
+ if (input->port->type == DDB_TUNER_DUMMY)
+ ddbwritel(dev, 0x000fff01, TS_CONTROL2(input));
+
+ input->dma->running = 1;
+ spin_unlock_irq(&input->dma->lock);
+}
+
+static void ddb_input_start_all(struct ddb_input *input)
+{
+ struct ddb_input *i = input;
+ struct ddb_output *o;
+
+ mutex_lock(&redirect_lock);
+ while (i && (o = i->redo)) {
+ ddb_output_start(o);
+ i = o->port->input[0];
+ if (i)
+ ddb_input_start(i);
+ }
+ ddb_input_start(input);
+ mutex_unlock(&redirect_lock);
+}
+
+static void ddb_input_stop_all(struct ddb_input *input)
+{
+ struct ddb_input *i = input;
+ struct ddb_output *o;
+
+ mutex_lock(&redirect_lock);
+ ddb_input_stop(input);
+ while (i && (o = i->redo)) {
+ ddb_output_stop(o);
+ i = o->port->input[0];
+ if (i)
+ ddb_input_stop(i);
+ }
+ mutex_unlock(&redirect_lock);
+}
+
+static u32 ddb_output_free(struct ddb_output *output)
+{
+ u32 idx, off, stat = output->dma->stat;
+ s32 diff;
+
+ idx = (stat >> 11) & 0x1f;
+ off = (stat & 0x7ff) << 7;
+
+ if (output->dma->cbuf != idx) {
+ if ((((output->dma->cbuf + 1) % output->dma->num) == idx) &&
+ (output->dma->size - output->dma->coff <= (2 * 188)))
+ return 0;
+ return 188;
+ }
+ diff = off - output->dma->coff;
+ if (diff <= 0 || diff > (2 * 188))
+ return 188;
+ return 0;
+}
+
+static ssize_t ddb_output_write(struct ddb_output *output,
+ const __user u8 *buf, size_t count)
+{
+ struct ddb *dev = output->port->dev;
+ u32 idx, off, stat = output->dma->stat;
+ u32 left = count, len;
+
+ idx = (stat >> 11) & 0x1f;
+ off = (stat & 0x7ff) << 7;
+
+ while (left) {
+ len = output->dma->size - output->dma->coff;
+ if ((((output->dma->cbuf + 1) % output->dma->num) == idx) &&
+ off == 0) {
+ if (len <= 188)
+ break;
+ len -= 188;
+ }
+ if (output->dma->cbuf == idx) {
+ if (off > output->dma->coff) {
+ len = off - output->dma->coff;
+ len -= (len % 188);
+ if (len <= 188)
+ break;
+ len -= 188;
+ }
+ }
+ if (len > left)
+ len = left;
+ if (copy_from_user(output->dma->vbuf[output->dma->cbuf] +
+ output->dma->coff,
+ buf, len))
+ return -EIO;
+ if (alt_dma)
+ dma_sync_single_for_device(
+ dev->dev,
+ output->dma->pbuf[output->dma->cbuf],
+ output->dma->size, DMA_TO_DEVICE);
+ left -= len;
+ buf += len;
+ output->dma->coff += len;
+ if (output->dma->coff == output->dma->size) {
+ output->dma->coff = 0;
+ output->dma->cbuf = ((output->dma->cbuf + 1) %
+ output->dma->num);
+ }
+ ddbwritel(dev,
+ (output->dma->cbuf << 11) |
+ (output->dma->coff >> 7),
+ DMA_BUFFER_ACK(output->dma));
+ }
+ return count - left;
+}
+
+static u32 ddb_input_avail(struct ddb_input *input)
+{
+ struct ddb *dev = input->port->dev;
+ u32 idx, off, stat = input->dma->stat;
+ u32 ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(input->dma));
+
+ idx = (stat >> 11) & 0x1f;
+ off = (stat & 0x7ff) << 7;
+
+ if (ctrl & 4) {
+ dev_err(dev->dev, "IA %d %d %08x\n", idx, off, ctrl);
+ ddbwritel(dev, stat, DMA_BUFFER_ACK(input->dma));
+ return 0;
+ }
+ if (input->dma->cbuf != idx)
+ return 188;
+ return 0;
+}
+
+static ssize_t ddb_input_read(struct ddb_input *input,
+ __user u8 *buf, size_t count)
+{
+ struct ddb *dev = input->port->dev;
+ u32 left = count;
+ u32 idx, free, stat = input->dma->stat;
+ int ret;
+
+ idx = (stat >> 11) & 0x1f;
+
+ while (left) {
+ if (input->dma->cbuf == idx)
+ return count - left;
+ free = input->dma->size - input->dma->coff;
+ if (free > left)
+ free = left;
+ if (alt_dma)
+ dma_sync_single_for_cpu(
+ dev->dev,
+ input->dma->pbuf[input->dma->cbuf],
+ input->dma->size, DMA_FROM_DEVICE);
+ ret = copy_to_user(buf, input->dma->vbuf[input->dma->cbuf] +
+ input->dma->coff, free);
+ if (ret)
+ return -EFAULT;
+ input->dma->coff += free;
+ if (input->dma->coff == input->dma->size) {
+ input->dma->coff = 0;
+ input->dma->cbuf = (input->dma->cbuf + 1) %
+ input->dma->num;
+ }
+ left -= free;
+ buf += free;
+ ddbwritel(dev,
+ (input->dma->cbuf << 11) | (input->dma->coff >> 7),
+ DMA_BUFFER_ACK(input->dma));
+ }
+ return count;
+}
+
+/****************************************************************************/
+/****************************************************************************/
+
+static ssize_t ts_write(struct file *file, const __user char *buf,
+ size_t count, loff_t *ppos)
+{
+ struct dvb_device *dvbdev = file->private_data;
+ struct ddb_output *output = dvbdev->priv;
+ struct ddb *dev = output->port->dev;
+ size_t left = count;
+ int stat;
+
+ if (!dev->has_dma)
+ return -EINVAL;
+ while (left) {
+ if (ddb_output_free(output) < 188) {
+ if (file->f_flags & O_NONBLOCK)
+ break;
+ if (wait_event_interruptible(
+ output->dma->wq,
+ ddb_output_free(output) >= 188) < 0)
+ break;
+ }
+ stat = ddb_output_write(output, buf, left);
+ if (stat < 0)
+ return stat;
+ buf += stat;
+ left -= stat;
+ }
+ return (left == count) ? -EAGAIN : (count - left);
+}
+
+static ssize_t ts_read(struct file *file, __user char *buf,
+ size_t count, loff_t *ppos)
+{
+ struct dvb_device *dvbdev = file->private_data;
+ struct ddb_output *output = dvbdev->priv;
+ struct ddb_input *input = output->port->input[0];
+ struct ddb *dev = output->port->dev;
+ size_t left = count;
+ int stat;
+
+ if (!dev->has_dma)
+ return -EINVAL;
+ while (left) {
+ if (ddb_input_avail(input) < 188) {
+ if (file->f_flags & O_NONBLOCK)
+ break;
+ if (wait_event_interruptible(
+ input->dma->wq,
+ ddb_input_avail(input) >= 188) < 0)
+ break;
+ }
+ stat = ddb_input_read(input, buf, left);
+ if (stat < 0)
+ return stat;
+ left -= stat;
+ buf += stat;
+ }
+ return (count && (left == count)) ? -EAGAIN : (count - left);
+}
+
+static __poll_t ts_poll(struct file *file, poll_table *wait)
+{
+ struct dvb_device *dvbdev = file->private_data;
+ struct ddb_output *output = dvbdev->priv;
+ struct ddb_input *input = output->port->input[0];
+
+ __poll_t mask = 0;
+
+ poll_wait(file, &input->dma->wq, wait);
+ poll_wait(file, &output->dma->wq, wait);
+ if (ddb_input_avail(input) >= 188)
+ mask |= EPOLLIN | EPOLLRDNORM;
+ if (ddb_output_free(output) >= 188)
+ mask |= EPOLLOUT | EPOLLWRNORM;
+ return mask;
+}
+
+static int ts_release(struct inode *inode, struct file *file)
+{
+ struct dvb_device *dvbdev = file->private_data;
+ struct ddb_output *output = NULL;
+ struct ddb_input *input = NULL;
+
+ if (dvbdev) {
+ output = dvbdev->priv;
+ input = output->port->input[0];
+ }
+
+ if ((file->f_flags & O_ACCMODE) == O_RDONLY) {
+ if (!input)
+ return -EINVAL;
+ ddb_input_stop(input);
+ } else if ((file->f_flags & O_ACCMODE) == O_WRONLY) {
+ if (!output)
+ return -EINVAL;
+ ddb_output_stop(output);
+ }
+ return dvb_generic_release(inode, file);
+}
+
+static int ts_open(struct inode *inode, struct file *file)
+{
+ int err;
+ struct dvb_device *dvbdev = file->private_data;
+ struct ddb_output *output = NULL;
+ struct ddb_input *input = NULL;
+
+ if (dvbdev) {
+ output = dvbdev->priv;
+ input = output->port->input[0];
+ }
+
+ if ((file->f_flags & O_ACCMODE) == O_RDONLY) {
+ if (!input)
+ return -EINVAL;
+ if (input->redo || input->redi)
+ return -EBUSY;
+ } else if ((file->f_flags & O_ACCMODE) == O_WRONLY) {
+ if (!output)
+ return -EINVAL;
+ } else {
+ return -EINVAL;
+ }
+
+ err = dvb_generic_open(inode, file);
+ if (err < 0)
+ return err;
+ if ((file->f_flags & O_ACCMODE) == O_RDONLY)
+ ddb_input_start(input);
+ else if ((file->f_flags & O_ACCMODE) == O_WRONLY)
+ ddb_output_start(output);
+ return err;
+}
+
+static const struct file_operations ci_fops = {
+ .owner = THIS_MODULE,
+ .read = ts_read,
+ .write = ts_write,
+ .open = ts_open,
+ .release = ts_release,
+ .poll = ts_poll,
+ .mmap = NULL,
+};
+
+static struct dvb_device dvbdev_ci = {
+ .priv = NULL,
+ .readers = 1,
+ .writers = 1,
+ .users = 2,
+ .fops = &ci_fops,
+};
+
+/****************************************************************************/
+/****************************************************************************/
+
+static int locked_gate_ctrl(struct dvb_frontend *fe, int enable)
+{
+ struct ddb_input *input = fe->sec_priv;
+ struct ddb_port *port = input->port;
+ struct ddb_dvb *dvb = &port->dvb[input->nr & 1];
+ int status;
+
+ if (enable) {
+ mutex_lock(&port->i2c_gate_lock);
+ status = dvb->i2c_gate_ctrl(fe, 1);
+ } else {
+ status = dvb->i2c_gate_ctrl(fe, 0);
+ mutex_unlock(&port->i2c_gate_lock);
+ }
+ return status;
+}
+
+static int demod_attach_drxk(struct ddb_input *input)
+{
+ struct i2c_adapter *i2c = &input->port->i2c->adap;
+ struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];
+ struct device *dev = input->port->dev->dev;
+ struct drxk_config config;
+
+ memset(&config, 0, sizeof(config));
+ config.adr = 0x29 + (input->nr & 1);
+ config.microcode_name = "drxk_a3.mc";
+
+ dvb->fe = dvb_attach(drxk_attach, &config, i2c);
+ if (!dvb->fe) {
+ dev_err(dev, "No DRXK found!\n");
+ return -ENODEV;
+ }
+ dvb->fe->sec_priv = input;
+ dvb->i2c_gate_ctrl = dvb->fe->ops.i2c_gate_ctrl;
+ dvb->fe->ops.i2c_gate_ctrl = locked_gate_ctrl;
+ return 0;
+}
+
+static int tuner_attach_tda18271(struct ddb_input *input)
+{
+ struct i2c_adapter *i2c = &input->port->i2c->adap;
+ struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];
+ struct device *dev = input->port->dev->dev;
+ struct dvb_frontend *fe;
+
+ if (dvb->fe->ops.i2c_gate_ctrl)
+ dvb->fe->ops.i2c_gate_ctrl(dvb->fe, 1);
+ fe = dvb_attach(tda18271c2dd_attach, dvb->fe, i2c, 0x60);
+ if (dvb->fe->ops.i2c_gate_ctrl)
+ dvb->fe->ops.i2c_gate_ctrl(dvb->fe, 0);
+ if (!fe) {
+ dev_err(dev, "No TDA18271 found!\n");
+ return -ENODEV;
+ }
+ return 0;
+}
+
+/******************************************************************************/
+/******************************************************************************/
+/******************************************************************************/
+
+static struct stv0367_config ddb_stv0367_config[] = {
+ {
+ .demod_address = 0x1f,
+ .xtal = 27000000,
+ .if_khz = 0,
+ .if_iq_mode = FE_TER_NORMAL_IF_TUNER,
+ .ts_mode = STV0367_SERIAL_PUNCT_CLOCK,
+ .clk_pol = STV0367_CLOCKPOLARITY_DEFAULT,
+ }, {
+ .demod_address = 0x1e,
+ .xtal = 27000000,
+ .if_khz = 0,
+ .if_iq_mode = FE_TER_NORMAL_IF_TUNER,
+ .ts_mode = STV0367_SERIAL_PUNCT_CLOCK,
+ .clk_pol = STV0367_CLOCKPOLARITY_DEFAULT,
+ },
+};
+
+static int demod_attach_stv0367(struct ddb_input *input)
+{
+ struct i2c_adapter *i2c = &input->port->i2c->adap;
+ struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];
+ struct device *dev = input->port->dev->dev;
+
+ /* attach frontend */
+ dvb->fe = dvb_attach(stv0367ddb_attach,
+ &ddb_stv0367_config[(input->nr & 1)], i2c);
+
+ if (!dvb->fe) {
+ dev_err(dev, "No stv0367 found!\n");
+ return -ENODEV;
+ }
+ dvb->fe->sec_priv = input;
+ dvb->i2c_gate_ctrl = dvb->fe->ops.i2c_gate_ctrl;
+ dvb->fe->ops.i2c_gate_ctrl = locked_gate_ctrl;
+ return 0;
+}
+
+static int tuner_tda18212_ping(struct ddb_input *input, unsigned short adr)
+{
+ struct i2c_adapter *adapter = &input->port->i2c->adap;
+ struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];
+ struct device *dev = input->port->dev->dev;
+ u8 tda_id[2];
+ u8 subaddr = 0x00;
+
+ dev_dbg(dev, "stv0367-tda18212 tuner ping\n");
+ if (dvb->fe->ops.i2c_gate_ctrl)
+ dvb->fe->ops.i2c_gate_ctrl(dvb->fe, 1);
+
+ if (i2c_read_regs(adapter, adr, subaddr, tda_id, sizeof(tda_id)) < 0)
+ dev_dbg(dev, "tda18212 ping 1 fail\n");
+ if (i2c_read_regs(adapter, adr, subaddr, tda_id, sizeof(tda_id)) < 0)
+ dev_warn(dev, "tda18212 ping failed, expect problems\n");
+
+ if (dvb->fe->ops.i2c_gate_ctrl)
+ dvb->fe->ops.i2c_gate_ctrl(dvb->fe, 0);
+
+ return 0;
+}
+
+static int demod_attach_cxd28xx(struct ddb_input *input, int par, int osc24)
+{
+ struct i2c_adapter *i2c = &input->port->i2c->adap;
+ struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];
+ struct device *dev = input->port->dev->dev;
+ struct cxd2841er_config cfg;
+
+ /* the cxd2841er driver expects 8bit/shifted I2C addresses */
+ cfg.i2c_addr = ((input->nr & 1) ? 0x6d : 0x6c) << 1;
+
+ cfg.xtal = osc24 ? SONY_XTAL_24000 : SONY_XTAL_20500;
+ cfg.flags = CXD2841ER_AUTO_IFHZ | CXD2841ER_EARLY_TUNE |
+ CXD2841ER_NO_WAIT_LOCK | CXD2841ER_NO_AGCNEG |
+ CXD2841ER_TSBITS;
+
+ if (!par)
+ cfg.flags |= CXD2841ER_TS_SERIAL;
+
+ /* attach frontend */
+ dvb->fe = dvb_attach(cxd2841er_attach_t_c, &cfg, i2c);
+
+ if (!dvb->fe) {
+ dev_err(dev, "No cxd2837/38/43/54 found!\n");
+ return -ENODEV;
+ }
+ dvb->fe->sec_priv = input;
+ dvb->i2c_gate_ctrl = dvb->fe->ops.i2c_gate_ctrl;
+ dvb->fe->ops.i2c_gate_ctrl = locked_gate_ctrl;
+ return 0;
+}
+
+static int tuner_attach_tda18212(struct ddb_input *input, u32 porttype)
+{
+ struct i2c_adapter *adapter = &input->port->i2c->adap;
+ struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];
+ struct device *dev = input->port->dev->dev;
+ struct i2c_client *client;
+ struct tda18212_config config = {
+ .fe = dvb->fe,
+ .if_dvbt_6 = 3550,
+ .if_dvbt_7 = 3700,
+ .if_dvbt_8 = 4150,
+ .if_dvbt2_6 = 3250,
+ .if_dvbt2_7 = 4000,
+ .if_dvbt2_8 = 4000,
+ .if_dvbc = 5000,
+ };
+ u8 addr = (input->nr & 1) ? 0x63 : 0x60;
+
+ /* due to a hardware quirk with the I2C gate on the stv0367+tda18212
+ * combo, the tda18212 must be probed by reading it's id _twice_ when
+ * cold started, or it very likely will fail.
+ */
+ if (porttype == DDB_TUNER_DVBCT_ST)
+ tuner_tda18212_ping(input, addr);
+
+ /* perform tuner probe/init/attach */
+ client = dvb_module_probe("tda18212", NULL, adapter, addr, &config);
+ if (!client)
+ goto err;
+
+ dvb->i2c_client[0] = client;
+ return 0;
+err:
+ dev_err(dev, "TDA18212 tuner not found. Device is not fully operational.\n");
+ return -ENODEV;
+}
+
+/****************************************************************************/
+/****************************************************************************/
+/****************************************************************************/
+
+static struct stv090x_config stv0900 = {
+ .device = STV0900,
+ .demod_mode = STV090x_DUAL,
+ .clk_mode = STV090x_CLK_EXT,
+
+ .xtal = 27000000,
+ .address = 0x69,
+
+ .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
+ .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
+
+ .ts1_tei = 1,
+ .ts2_tei = 1,
+
+ .repeater_level = STV090x_RPTLEVEL_16,
+
+ .adc1_range = STV090x_ADC_1Vpp,
+ .adc2_range = STV090x_ADC_1Vpp,
+
+ .diseqc_envelope_mode = true,
+};
+
+static struct stv090x_config stv0900_aa = {
+ .device = STV0900,
+ .demod_mode = STV090x_DUAL,
+ .clk_mode = STV090x_CLK_EXT,
+
+ .xtal = 27000000,
+ .address = 0x68,
+
+ .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
+ .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
+
+ .ts1_tei = 1,
+ .ts2_tei = 1,
+
+ .repeater_level = STV090x_RPTLEVEL_16,
+
+ .adc1_range = STV090x_ADC_1Vpp,
+ .adc2_range = STV090x_ADC_1Vpp,
+
+ .diseqc_envelope_mode = true,
+};
+
+static struct stv6110x_config stv6110a = {
+ .addr = 0x60,
+ .refclk = 27000000,
+ .clk_div = 1,
+};
+
+static struct stv6110x_config stv6110b = {
+ .addr = 0x63,
+ .refclk = 27000000,
+ .clk_div = 1,
+};
+
+static int demod_attach_stv0900(struct ddb_input *input, int type)
+{
+ struct i2c_adapter *i2c = &input->port->i2c->adap;
+ struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900;
+ struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];
+ struct device *dev = input->port->dev->dev;
+
+ dvb->fe = dvb_attach(stv090x_attach, feconf, i2c,
+ (input->nr & 1) ? STV090x_DEMODULATOR_1
+ : STV090x_DEMODULATOR_0);
+ if (!dvb->fe) {
+ dev_err(dev, "No STV0900 found!\n");
+ return -ENODEV;
+ }
+ if (!dvb_attach(lnbh24_attach, dvb->fe, i2c, 0,
+ 0, (input->nr & 1) ?
+ (0x09 - type) : (0x0b - type))) {
+ dev_err(dev, "No LNBH24 found!\n");
+ dvb_frontend_detach(dvb->fe);
+ return -ENODEV;
+ }
+ return 0;
+}
+
+static int tuner_attach_stv6110(struct ddb_input *input, int type)
+{
+ struct i2c_adapter *i2c = &input->port->i2c->adap;
+ struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];
+ struct device *dev = input->port->dev->dev;
+ struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900;
+ struct stv6110x_config *tunerconf = (input->nr & 1) ?
+ &stv6110b : &stv6110a;
+ const struct stv6110x_devctl *ctl;
+
+ ctl = dvb_attach(stv6110x_attach, dvb->fe, tunerconf, i2c);
+ if (!ctl) {
+ dev_err(dev, "No STV6110X found!\n");
+ return -ENODEV;
+ }
+ dev_info(dev, "attach tuner input %d adr %02x\n",
+ input->nr, tunerconf->addr);
+
+ feconf->tuner_init = ctl->tuner_init;
+ feconf->tuner_sleep = ctl->tuner_sleep;
+ feconf->tuner_set_mode = ctl->tuner_set_mode;
+ feconf->tuner_set_frequency = ctl->tuner_set_frequency;
+ feconf->tuner_get_frequency = ctl->tuner_get_frequency;
+ feconf->tuner_set_bandwidth = ctl->tuner_set_bandwidth;
+ feconf->tuner_get_bandwidth = ctl->tuner_get_bandwidth;
+ feconf->tuner_set_bbgain = ctl->tuner_set_bbgain;
+ feconf->tuner_get_bbgain = ctl->tuner_get_bbgain;
+ feconf->tuner_set_refclk = ctl->tuner_set_refclk;
+ feconf->tuner_get_status = ctl->tuner_get_status;
+
+ return 0;
+}
+
+static const struct stv0910_cfg stv0910_p = {
+ .adr = 0x68,
+ .parallel = 1,
+ .rptlvl = 4,
+ .clk = 30000000,
+ .tsspeed = 0x28,
+};
+
+static const struct lnbh25_config lnbh25_cfg = {
+ .i2c_address = 0x0c << 1,
+ .data2_config = LNBH25_TEN
+};
+
+static int has_lnbh25(struct i2c_adapter *i2c, u8 adr)
+{
+ u8 val;
+
+ return i2c_read_reg(i2c, adr, 0, &val) ? 0 : 1;
+}
+
+static int demod_attach_stv0910(struct ddb_input *input, int type, int tsfast)
+{
+ struct i2c_adapter *i2c = &input->port->i2c->adap;
+ struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];
+ struct device *dev = input->port->dev->dev;
+ struct stv0910_cfg cfg = stv0910_p;
+ struct lnbh25_config lnbcfg = lnbh25_cfg;
+
+ if (stv0910_single)
+ cfg.single = 1;
+
+ if (type)
+ cfg.parallel = 2;
+
+ if (tsfast) {
+ dev_info(dev, "Enabling stv0910 higher speed TS\n");
+ cfg.tsspeed = 0x10;
+ }
+
+ dvb->fe = dvb_attach(stv0910_attach, i2c, &cfg, (input->nr & 1));
+ if (!dvb->fe) {
+ cfg.adr = 0x6c;
+ dvb->fe = dvb_attach(stv0910_attach, i2c,
+ &cfg, (input->nr & 1));
+ }
+ if (!dvb->fe) {
+ dev_err(dev, "No STV0910 found!\n");
+ return -ENODEV;
+ }
+
+ /* attach lnbh25 - leftshift by one as the lnbh25 driver expects 8bit
+ * i2c addresses
+ */
+ if (has_lnbh25(i2c, 0x0d))
+ lnbcfg.i2c_address = (((input->nr & 1) ? 0x0d : 0x0c) << 1);
+ else
+ lnbcfg.i2c_address = (((input->nr & 1) ? 0x09 : 0x08) << 1);
+
+ if (!dvb_attach(lnbh25_attach, dvb->fe, &lnbcfg, i2c)) {
+ dev_err(dev, "No LNBH25 found!\n");
+ dvb_frontend_detach(dvb->fe);
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static int tuner_attach_stv6111(struct ddb_input *input, int type)
+{
+ struct i2c_adapter *i2c = &input->port->i2c->adap;
+ struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];
+ struct device *dev = input->port->dev->dev;
+ struct dvb_frontend *fe;
+ u8 adr = (type ? 0 : 4) + ((input->nr & 1) ? 0x63 : 0x60);
+
+ fe = dvb_attach(stv6111_attach, dvb->fe, i2c, adr);
+ if (!fe) {
+ fe = dvb_attach(stv6111_attach, dvb->fe, i2c, adr & ~4);
+ if (!fe) {
+ dev_err(dev, "No STV6111 found at 0x%02x!\n", adr);
+ return -ENODEV;
+ }
+ }
+ return 0;
+}
+
+static int demod_attach_dummy(struct ddb_input *input)
+{
+ struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];
+ struct device *dev = input->port->dev->dev;
+
+ dvb->fe = dvb_attach(ddbridge_dummy_fe_qam_attach);
+ if (!dvb->fe) {
+ dev_err(dev, "QAM dummy attach failed!\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static int start_feed(struct dvb_demux_feed *dvbdmxfeed)
+{
+ struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
+ struct ddb_input *input = dvbdmx->priv;
+ struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];
+
+ if (!dvb->users)
+ ddb_input_start_all(input);
+
+ return ++dvb->users;
+}
+
+static int stop_feed(struct dvb_demux_feed *dvbdmxfeed)
+{
+ struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
+ struct ddb_input *input = dvbdmx->priv;
+ struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];
+
+ if (--dvb->users)
+ return dvb->users;
+
+ ddb_input_stop_all(input);
+ return 0;
+}
+
+static void dvb_input_detach(struct ddb_input *input)
+{
+ struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];
+ struct dvb_demux *dvbdemux = &dvb->demux;
+
+ switch (dvb->attached) {
+ case 0x31:
+ if (dvb->fe2)
+ dvb_unregister_frontend(dvb->fe2);
+ if (dvb->fe)
+ dvb_unregister_frontend(dvb->fe);
+ fallthrough;
+ case 0x30:
+ dvb_module_release(dvb->i2c_client[0]);
+ dvb->i2c_client[0] = NULL;
+
+ if (dvb->fe2)
+ dvb_frontend_detach(dvb->fe2);
+ if (dvb->fe)
+ dvb_frontend_detach(dvb->fe);
+ dvb->fe = NULL;
+ dvb->fe2 = NULL;
+ fallthrough;
+ case 0x20:
+ dvb_net_release(&dvb->dvbnet);
+ fallthrough;
+ case 0x12:
+ dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
+ &dvb->hw_frontend);
+ dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
+ &dvb->mem_frontend);
+ fallthrough;
+ case 0x11:
+ dvb_dmxdev_release(&dvb->dmxdev);
+ fallthrough;
+ case 0x10:
+ dvb_dmx_release(&dvb->demux);
+ fallthrough;
+ case 0x01:
+ break;
+ }
+ dvb->attached = 0x00;
+}
+
+static int dvb_register_adapters(struct ddb *dev)
+{
+ int i, ret = 0;
+ struct ddb_port *port;
+ struct dvb_adapter *adap;
+
+ if (adapter_alloc == 3) {
+ port = &dev->port[0];
+ adap = port->dvb[0].adap;
+ ret = dvb_register_adapter(adap, "DDBridge", THIS_MODULE,
+ port->dev->dev,
+ adapter_nr);
+ if (ret < 0)
+ return ret;
+ port->dvb[0].adap_registered = 1;
+ for (i = 0; i < dev->port_num; i++) {
+ port = &dev->port[i];
+ port->dvb[0].adap = adap;
+ port->dvb[1].adap = adap;
+ }
+ return 0;
+ }
+
+ for (i = 0; i < dev->port_num; i++) {
+ port = &dev->port[i];
+ switch (port->class) {
+ case DDB_PORT_TUNER:
+ adap = port->dvb[0].adap;
+ ret = dvb_register_adapter(adap, "DDBridge",
+ THIS_MODULE,
+ port->dev->dev,
+ adapter_nr);
+ if (ret < 0)
+ return ret;
+ port->dvb[0].adap_registered = 1;
+
+ if (adapter_alloc > 0) {
+ port->dvb[1].adap = port->dvb[0].adap;
+ break;
+ }
+ adap = port->dvb[1].adap;
+ ret = dvb_register_adapter(adap, "DDBridge",
+ THIS_MODULE,
+ port->dev->dev,
+ adapter_nr);
+ if (ret < 0)
+ return ret;
+ port->dvb[1].adap_registered = 1;
+ break;
+
+ case DDB_PORT_CI:
+ case DDB_PORT_LOOP:
+ adap = port->dvb[0].adap;
+ ret = dvb_register_adapter(adap, "DDBridge",
+ THIS_MODULE,
+ port->dev->dev,
+ adapter_nr);
+ if (ret < 0)
+ return ret;
+ port->dvb[0].adap_registered = 1;
+ break;
+ default:
+ if (adapter_alloc < 2)
+ break;
+ adap = port->dvb[0].adap;
+ ret = dvb_register_adapter(adap, "DDBridge",
+ THIS_MODULE,
+ port->dev->dev,
+ adapter_nr);
+ if (ret < 0)
+ return ret;
+ port->dvb[0].adap_registered = 1;
+ break;
+ }
+ }
+ return ret;
+}
+
+static void dvb_unregister_adapters(struct ddb *dev)
+{
+ int i;
+ struct ddb_port *port;
+ struct ddb_dvb *dvb;
+
+ for (i = 0; i < dev->link[0].info->port_num; i++) {
+ port = &dev->port[i];
+
+ dvb = &port->dvb[0];
+ if (dvb->adap_registered)
+ dvb_unregister_adapter(dvb->adap);
+ dvb->adap_registered = 0;
+
+ dvb = &port->dvb[1];
+ if (dvb->adap_registered)
+ dvb_unregister_adapter(dvb->adap);
+ dvb->adap_registered = 0;
+ }
+}
+
+static int dvb_input_attach(struct ddb_input *input)
+{
+ int ret = 0;
+ struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];
+ struct ddb_port *port = input->port;
+ struct dvb_adapter *adap = dvb->adap;
+ struct dvb_demux *dvbdemux = &dvb->demux;
+ struct ddb_ids *devids = &input->port->dev->link[input->port->lnr].ids;
+ int par = 0, osc24 = 0, tsfast = 0;
+
+ /*
+ * Determine if bridges with stv0910 demods can run with fast TS and
+ * thus support high bandwidth transponders.
+ * STV0910_PR and STV0910_P tuner types covers all relevant bridges,
+ * namely the CineS2 V7(A) and the Octopus CI S2 Pro/Advanced. All
+ * DuoFlex S2 V4(A) have type=DDB_TUNER_DVBS_STV0910 without any suffix
+ * and are limited by the serial link to the bridge, thus won't work
+ * in fast TS mode.
+ */
+ if (port->nr == 0 &&
+ (port->type == DDB_TUNER_DVBS_STV0910_PR ||
+ port->type == DDB_TUNER_DVBS_STV0910_P)) {
+ /* fast TS on port 0 requires FPGA version >= 1.7 */
+ if ((devids->hwid & 0x00ffffff) >= 0x00010007)
+ tsfast = 1;
+ }
+
+ dvb->attached = 0x01;
+
+ dvbdemux->priv = input;
+ dvbdemux->dmx.capabilities = DMX_TS_FILTERING |
+ DMX_SECTION_FILTERING | DMX_MEMORY_BASED_FILTERING;
+ dvbdemux->start_feed = start_feed;
+ dvbdemux->stop_feed = stop_feed;
+ dvbdemux->filternum = 256;
+ dvbdemux->feednum = 256;
+ ret = dvb_dmx_init(dvbdemux);
+ if (ret < 0)
+ return ret;
+ dvb->attached = 0x10;
+
+ dvb->dmxdev.filternum = 256;
+ dvb->dmxdev.demux = &dvbdemux->dmx;
+ ret = dvb_dmxdev_init(&dvb->dmxdev, adap);
+ if (ret < 0)
+ goto err_detach;
+ dvb->attached = 0x11;
+
+ dvb->mem_frontend.source = DMX_MEMORY_FE;
+ dvb->demux.dmx.add_frontend(&dvb->demux.dmx, &dvb->mem_frontend);
+ dvb->hw_frontend.source = DMX_FRONTEND_0;
+ dvb->demux.dmx.add_frontend(&dvb->demux.dmx, &dvb->hw_frontend);
+ ret = dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, &dvb->hw_frontend);
+ if (ret < 0)
+ goto err_detach;
+ dvb->attached = 0x12;
+
+ ret = dvb_net_init(adap, &dvb->dvbnet, dvb->dmxdev.demux);
+ if (ret < 0)
+ goto err_detach;
+ dvb->attached = 0x20;
+
+ dvb->fe = NULL;
+ dvb->fe2 = NULL;
+ switch (port->type) {
+ case DDB_TUNER_MXL5XX:
+ if (ddb_fe_attach_mxl5xx(input) < 0)
+ goto err_detach;
+ break;
+ case DDB_TUNER_DVBS_ST:
+ if (demod_attach_stv0900(input, 0) < 0)
+ goto err_detach;
+ if (tuner_attach_stv6110(input, 0) < 0)
+ goto err_tuner;
+ break;
+ case DDB_TUNER_DVBS_ST_AA:
+ if (demod_attach_stv0900(input, 1) < 0)
+ goto err_detach;
+ if (tuner_attach_stv6110(input, 1) < 0)
+ goto err_tuner;
+ break;
+ case DDB_TUNER_DVBS_STV0910:
+ if (demod_attach_stv0910(input, 0, tsfast) < 0)
+ goto err_detach;
+ if (tuner_attach_stv6111(input, 0) < 0)
+ goto err_tuner;
+ break;
+ case DDB_TUNER_DVBS_STV0910_PR:
+ if (demod_attach_stv0910(input, 1, tsfast) < 0)
+ goto err_detach;
+ if (tuner_attach_stv6111(input, 1) < 0)
+ goto err_tuner;
+ break;
+ case DDB_TUNER_DVBS_STV0910_P:
+ if (demod_attach_stv0910(input, 0, tsfast) < 0)
+ goto err_detach;
+ if (tuner_attach_stv6111(input, 1) < 0)
+ goto err_tuner;
+ break;
+ case DDB_TUNER_DVBCT_TR:
+ if (demod_attach_drxk(input) < 0)
+ goto err_detach;
+ if (tuner_attach_tda18271(input) < 0)
+ goto err_tuner;
+ break;
+ case DDB_TUNER_DVBCT_ST:
+ if (demod_attach_stv0367(input) < 0)
+ goto err_detach;
+ if (tuner_attach_tda18212(input, port->type) < 0)
+ goto err_tuner;
+ break;
+ case DDB_TUNER_DVBC2T2I_SONY_P:
+ if (input->port->dev->link[input->port->lnr].info->ts_quirks &
+ TS_QUIRK_ALT_OSC)
+ osc24 = 0;
+ else
+ osc24 = 1;
+ fallthrough;
+ case DDB_TUNER_DVBCT2_SONY_P:
+ case DDB_TUNER_DVBC2T2_SONY_P:
+ case DDB_TUNER_ISDBT_SONY_P:
+ if (input->port->dev->link[input->port->lnr].info->ts_quirks
+ & TS_QUIRK_SERIAL)
+ par = 0;
+ else
+ par = 1;
+ if (demod_attach_cxd28xx(input, par, osc24) < 0)
+ goto err_detach;
+ if (tuner_attach_tda18212(input, port->type) < 0)
+ goto err_tuner;
+ break;
+ case DDB_TUNER_DVBC2T2I_SONY:
+ osc24 = 1;
+ fallthrough;
+ case DDB_TUNER_DVBCT2_SONY:
+ case DDB_TUNER_DVBC2T2_SONY:
+ case DDB_TUNER_ISDBT_SONY:
+ if (demod_attach_cxd28xx(input, 0, osc24) < 0)
+ goto err_detach;
+ if (tuner_attach_tda18212(input, port->type) < 0)
+ goto err_tuner;
+ break;
+ case DDB_TUNER_DUMMY:
+ if (demod_attach_dummy(input) < 0)
+ goto err_detach;
+ break;
+ case DDB_TUNER_MCI_SX8:
+ if (ddb_fe_attach_mci(input, port->type) < 0)
+ goto err_detach;
+ break;
+ default:
+ return 0;
+ }
+ dvb->attached = 0x30;
+
+ if (dvb->fe) {
+ if (dvb_register_frontend(adap, dvb->fe) < 0)
+ goto err_detach;
+
+ if (dvb->fe2) {
+ if (dvb_register_frontend(adap, dvb->fe2) < 0) {
+ dvb_unregister_frontend(dvb->fe);
+ goto err_detach;
+ }
+ dvb->fe2->tuner_priv = dvb->fe->tuner_priv;
+ memcpy(&dvb->fe2->ops.tuner_ops,
+ &dvb->fe->ops.tuner_ops,
+ sizeof(struct dvb_tuner_ops));
+ }
+ }
+
+ dvb->attached = 0x31;
+ return 0;
+
+err_tuner:
+ dev_err(port->dev->dev, "tuner attach failed!\n");
+
+ if (dvb->fe2)
+ dvb_frontend_detach(dvb->fe2);
+ if (dvb->fe)
+ dvb_frontend_detach(dvb->fe);
+err_detach:
+ dvb_input_detach(input);
+
+ /* return error from ret if set */
+ if (ret < 0)
+ return ret;
+
+ return -ENODEV;
+}
+
+static int port_has_encti(struct ddb_port *port)
+{
+ struct device *dev = port->dev->dev;
+ u8 val;
+ int ret = i2c_read_reg(&port->i2c->adap, 0x20, 0, &val);
+
+ if (!ret)
+ dev_info(dev, "[0x20]=0x%02x\n", val);
+ return ret ? 0 : 1;
+}
+
+static int port_has_cxd(struct ddb_port *port, u8 *type)
+{
+ u8 val;
+ u8 probe[4] = { 0xe0, 0x00, 0x00, 0x00 }, data[4];
+ struct i2c_msg msgs[2] = {{ .addr = 0x40, .flags = 0,
+ .buf = probe, .len = 4 },
+ { .addr = 0x40, .flags = I2C_M_RD,
+ .buf = data, .len = 4 } };
+ val = i2c_transfer(&port->i2c->adap, msgs, 2);
+ if (val != 2)
+ return 0;
+
+ if (data[0] == 0x02 && data[1] == 0x2b && data[3] == 0x43)
+ *type = 2;
+ else
+ *type = 1;
+ return 1;
+}
+
+static int port_has_xo2(struct ddb_port *port, u8 *type, u8 *id)
+{
+ u8 probe[1] = { 0x00 }, data[4];
+
+ if (i2c_io(&port->i2c->adap, 0x10, probe, 1, data, 4))
+ return 0;
+ if (data[0] == 'D' && data[1] == 'F') {
+ *id = data[2];
+ *type = 1;
+ return 1;
+ }
+ if (data[0] == 'C' && data[1] == 'I') {
+ *id = data[2];
+ *type = 2;
+ return 1;
+ }
+ return 0;
+}
+
+static int port_has_stv0900(struct ddb_port *port)
+{
+ u8 val;
+
+ if (i2c_read_reg16(&port->i2c->adap, 0x69, 0xf100, &val) < 0)
+ return 0;
+ return 1;
+}
+
+static int port_has_stv0900_aa(struct ddb_port *port, u8 *id)
+{
+ if (i2c_read_reg16(&port->i2c->adap, 0x68, 0xf100, id) < 0)
+ return 0;
+ return 1;
+}
+
+static int port_has_drxks(struct ddb_port *port)
+{
+ u8 val;
+
+ if (i2c_read(&port->i2c->adap, 0x29, &val) < 0)
+ return 0;
+ if (i2c_read(&port->i2c->adap, 0x2a, &val) < 0)
+ return 0;
+ return 1;
+}
+
+static int port_has_stv0367(struct ddb_port *port)
+{
+ u8 val;
+
+ if (i2c_read_reg16(&port->i2c->adap, 0x1e, 0xf000, &val) < 0)
+ return 0;
+ if (val != 0x60)
+ return 0;
+ if (i2c_read_reg16(&port->i2c->adap, 0x1f, 0xf000, &val) < 0)
+ return 0;
+ if (val != 0x60)
+ return 0;
+ return 1;
+}
+
+static int init_xo2(struct ddb_port *port)
+{
+ struct i2c_adapter *i2c = &port->i2c->adap;
+ struct ddb *dev = port->dev;
+ u8 val, data[2];
+ int res;
+
+ res = i2c_read_regs(i2c, 0x10, 0x04, data, 2);
+ if (res < 0)
+ return res;
+
+ if (data[0] != 0x01) {
+ dev_info(dev->dev, "Port %d: invalid XO2\n", port->nr);
+ return -1;
+ }
+
+ i2c_read_reg(i2c, 0x10, 0x08, &val);
+ if (val != 0) {
+ i2c_write_reg(i2c, 0x10, 0x08, 0x00);
+ msleep(100);
+ }
+ /* Enable tuner power, disable pll, reset demods */
+ i2c_write_reg(i2c, 0x10, 0x08, 0x04);
+ usleep_range(2000, 3000);
+ /* Release demod resets */
+ i2c_write_reg(i2c, 0x10, 0x08, 0x07);
+
+ /* speed: 0=55,1=75,2=90,3=104 MBit/s */
+ i2c_write_reg(i2c, 0x10, 0x09, xo2_speed);
+
+ if (dev->link[port->lnr].info->con_clock) {
+ dev_info(dev->dev, "Setting continuous clock for XO2\n");
+ i2c_write_reg(i2c, 0x10, 0x0a, 0x03);
+ i2c_write_reg(i2c, 0x10, 0x0b, 0x03);
+ } else {
+ i2c_write_reg(i2c, 0x10, 0x0a, 0x01);
+ i2c_write_reg(i2c, 0x10, 0x0b, 0x01);
+ }
+
+ usleep_range(2000, 3000);
+ /* Start XO2 PLL */
+ i2c_write_reg(i2c, 0x10, 0x08, 0x87);
+
+ return 0;
+}
+
+static int init_xo2_ci(struct ddb_port *port)
+{
+ struct i2c_adapter *i2c = &port->i2c->adap;
+ struct ddb *dev = port->dev;
+ u8 val, data[2];
+ int res;
+
+ res = i2c_read_regs(i2c, 0x10, 0x04, data, 2);
+ if (res < 0)
+ return res;
+
+ if (data[0] > 1) {
+ dev_info(dev->dev, "Port %d: invalid XO2 CI %02x\n",
+ port->nr, data[0]);
+ return -1;
+ }
+ dev_info(dev->dev, "Port %d: DuoFlex CI %u.%u\n",
+ port->nr, data[0], data[1]);
+
+ i2c_read_reg(i2c, 0x10, 0x08, &val);
+ if (val != 0) {
+ i2c_write_reg(i2c, 0x10, 0x08, 0x00);
+ msleep(100);
+ }
+ /* Enable both CI */
+ i2c_write_reg(i2c, 0x10, 0x08, 3);
+ usleep_range(2000, 3000);
+
+ /* speed: 0=55,1=75,2=90,3=104 MBit/s */
+ i2c_write_reg(i2c, 0x10, 0x09, 1);
+
+ i2c_write_reg(i2c, 0x10, 0x08, 0x83);
+ usleep_range(2000, 3000);
+
+ if (dev->link[port->lnr].info->con_clock) {
+ dev_info(dev->dev, "Setting continuous clock for DuoFlex CI\n");
+ i2c_write_reg(i2c, 0x10, 0x0a, 0x03);
+ i2c_write_reg(i2c, 0x10, 0x0b, 0x03);
+ } else {
+ i2c_write_reg(i2c, 0x10, 0x0a, 0x01);
+ i2c_write_reg(i2c, 0x10, 0x0b, 0x01);
+ }
+ return 0;
+}
+
+static int port_has_cxd28xx(struct ddb_port *port, u8 *id)
+{
+ struct i2c_adapter *i2c = &port->i2c->adap;
+ int status;
+
+ status = i2c_write_reg(&port->i2c->adap, 0x6e, 0, 0);
+ if (status)
+ return 0;
+ status = i2c_read_reg(i2c, 0x6e, 0xfd, id);
+ if (status)
+ return 0;
+ return 1;
+}
+
+static char *xo2names[] = {
+ "DUAL DVB-S2", "DUAL DVB-C/T/T2",
+ "DUAL DVB-ISDBT", "DUAL DVB-C/C2/T/T2",
+ "DUAL ATSC", "DUAL DVB-C/C2/T/T2,ISDB-T",
+ "", ""
+};
+
+static char *xo2types[] = {
+ "DVBS_ST", "DVBCT2_SONY",
+ "ISDBT_SONY", "DVBC2T2_SONY",
+ "ATSC_ST", "DVBC2T2I_SONY"
+};
+
+static void ddb_port_probe(struct ddb_port *port)
+{
+ struct ddb *dev = port->dev;
+ u32 l = port->lnr;
+ struct ddb_link *link = &dev->link[l];
+ u8 id, type;
+
+ port->name = "NO MODULE";
+ port->type_name = "NONE";
+ port->class = DDB_PORT_NONE;
+
+ /* Handle missing ports and ports without I2C */
+
+ if (dummy_tuner && !port->nr &&
+ link->ids.device == 0x0005) {
+ port->name = "DUMMY";
+ port->class = DDB_PORT_TUNER;
+ port->type = DDB_TUNER_DUMMY;
+ port->type_name = "DUMMY";
+ return;
+ }
+
+ if (port->nr == ts_loop) {
+ port->name = "TS LOOP";
+ port->class = DDB_PORT_LOOP;
+ return;
+ }
+
+ if (port->nr == 1 && link->info->type == DDB_OCTOPUS_CI &&
+ link->info->i2c_mask == 1) {
+ port->name = "NO TAB";
+ port->class = DDB_PORT_NONE;
+ return;
+ }
+
+ if (link->info->type == DDB_OCTOPUS_MAX) {
+ port->name = "DUAL DVB-S2 MAX";
+ port->type_name = "MXL5XX";
+ port->class = DDB_PORT_TUNER;
+ port->type = DDB_TUNER_MXL5XX;
+ if (port->i2c)
+ ddbwritel(dev, I2C_SPEED_400,
+ port->i2c->regs + I2C_TIMING);
+ return;
+ }
+
+ if (link->info->type == DDB_OCTOPUS_MCI) {
+ if (port->nr >= link->info->mci_ports)
+ return;
+ port->name = "DUAL MCI";
+ port->type_name = "MCI";
+ port->class = DDB_PORT_TUNER;
+ port->type = DDB_TUNER_MCI + link->info->mci_type;
+ return;
+ }
+
+ if (port->nr > 1 && link->info->type == DDB_OCTOPUS_CI) {
+ port->name = "CI internal";
+ port->type_name = "INTERNAL";
+ port->class = DDB_PORT_CI;
+ port->type = DDB_CI_INTERNAL;
+ }
+
+ if (!port->i2c)
+ return;
+
+ /* Probe ports with I2C */
+
+ if (port_has_cxd(port, &id)) {
+ if (id == 1) {
+ port->name = "CI";
+ port->type_name = "CXD2099";
+ port->class = DDB_PORT_CI;
+ port->type = DDB_CI_EXTERNAL_SONY;
+ ddbwritel(dev, I2C_SPEED_400,
+ port->i2c->regs + I2C_TIMING);
+ } else {
+ dev_info(dev->dev, "Port %d: Uninitialized DuoFlex\n",
+ port->nr);
+ return;
+ }
+ } else if (port_has_xo2(port, &type, &id)) {
+ ddbwritel(dev, I2C_SPEED_400, port->i2c->regs + I2C_TIMING);
+ /*dev_info(dev->dev, "XO2 ID %02x\n", id);*/
+ if (type == 2) {
+ port->name = "DuoFlex CI";
+ port->class = DDB_PORT_CI;
+ port->type = DDB_CI_EXTERNAL_XO2;
+ port->type_name = "CI_XO2";
+ init_xo2_ci(port);
+ return;
+ }
+ id >>= 2;
+ if (id > 5) {
+ port->name = "unknown XO2 DuoFlex";
+ port->type_name = "UNKNOWN";
+ } else {
+ port->name = xo2names[id];
+ port->class = DDB_PORT_TUNER;
+ port->type = DDB_TUNER_XO2 + id;
+ port->type_name = xo2types[id];
+ init_xo2(port);
+ }
+ } else if (port_has_cxd28xx(port, &id)) {
+ switch (id) {
+ case 0xa4:
+ port->name = "DUAL DVB-C2T2 CXD2843";
+ port->type = DDB_TUNER_DVBC2T2_SONY_P;
+ port->type_name = "DVBC2T2_SONY";
+ break;
+ case 0xb1:
+ port->name = "DUAL DVB-CT2 CXD2837";
+ port->type = DDB_TUNER_DVBCT2_SONY_P;
+ port->type_name = "DVBCT2_SONY";
+ break;
+ case 0xb0:
+ port->name = "DUAL ISDB-T CXD2838";
+ port->type = DDB_TUNER_ISDBT_SONY_P;
+ port->type_name = "ISDBT_SONY";
+ break;
+ case 0xc1:
+ port->name = "DUAL DVB-C2T2 ISDB-T CXD2854";
+ port->type = DDB_TUNER_DVBC2T2I_SONY_P;
+ port->type_name = "DVBC2T2I_ISDBT_SONY";
+ break;
+ default:
+ return;
+ }
+ port->class = DDB_PORT_TUNER;
+ ddbwritel(dev, I2C_SPEED_400, port->i2c->regs + I2C_TIMING);
+ } else if (port_has_stv0900(port)) {
+ port->name = "DUAL DVB-S2";
+ port->class = DDB_PORT_TUNER;
+ port->type = DDB_TUNER_DVBS_ST;
+ port->type_name = "DVBS_ST";
+ ddbwritel(dev, I2C_SPEED_100, port->i2c->regs + I2C_TIMING);
+ } else if (port_has_stv0900_aa(port, &id)) {
+ port->name = "DUAL DVB-S2";
+ port->class = DDB_PORT_TUNER;
+ if (id == 0x51) {
+ if (port->nr == 0 &&
+ link->info->ts_quirks & TS_QUIRK_REVERSED)
+ port->type = DDB_TUNER_DVBS_STV0910_PR;
+ else
+ port->type = DDB_TUNER_DVBS_STV0910_P;
+ port->type_name = "DVBS_ST_0910";
+ } else {
+ port->type = DDB_TUNER_DVBS_ST_AA;
+ port->type_name = "DVBS_ST_AA";
+ }
+ ddbwritel(dev, I2C_SPEED_100, port->i2c->regs + I2C_TIMING);
+ } else if (port_has_drxks(port)) {
+ port->name = "DUAL DVB-C/T";
+ port->class = DDB_PORT_TUNER;
+ port->type = DDB_TUNER_DVBCT_TR;
+ port->type_name = "DVBCT_TR";
+ ddbwritel(dev, I2C_SPEED_400, port->i2c->regs + I2C_TIMING);
+ } else if (port_has_stv0367(port)) {
+ port->name = "DUAL DVB-C/T";
+ port->class = DDB_PORT_TUNER;
+ port->type = DDB_TUNER_DVBCT_ST;
+ port->type_name = "DVBCT_ST";
+ ddbwritel(dev, I2C_SPEED_100, port->i2c->regs + I2C_TIMING);
+ } else if (port_has_encti(port)) {
+ port->name = "ENCTI";
+ port->class = DDB_PORT_LOOP;
+ }
+}
+
+/****************************************************************************/
+/****************************************************************************/
+/****************************************************************************/
+
+static int ddb_port_attach(struct ddb_port *port)
+{
+ int ret = 0;
+
+ switch (port->class) {
+ case DDB_PORT_TUNER:
+ ret = dvb_input_attach(port->input[0]);
+ if (ret < 0)
+ break;
+ ret = dvb_input_attach(port->input[1]);
+ if (ret < 0) {
+ dvb_input_detach(port->input[0]);
+ break;
+ }
+ port->input[0]->redi = port->input[0];
+ port->input[1]->redi = port->input[1];
+ break;
+ case DDB_PORT_CI:
+ ret = ddb_ci_attach(port, ci_bitrate);
+ if (ret < 0)
+ break;
+ fallthrough;
+ case DDB_PORT_LOOP:
+ ret = dvb_register_device(port->dvb[0].adap,
+ &port->dvb[0].dev,
+ &dvbdev_ci, (void *)port->output,
+ DVB_DEVICE_SEC, 0);
+ break;
+ default:
+ break;
+ }
+ if (ret < 0)
+ dev_err(port->dev->dev, "port_attach on port %d failed\n",
+ port->nr);
+ return ret;
+}
+
+int ddb_ports_attach(struct ddb *dev)
+{
+ int i, numports, err_ports = 0, ret = 0;
+ struct ddb_port *port;
+
+ if (dev->port_num) {
+ ret = dvb_register_adapters(dev);
+ if (ret < 0) {
+ dev_err(dev->dev, "Registering adapters failed. Check DVB_MAX_ADAPTERS in config.\n");
+ return ret;
+ }
+ }
+
+ numports = dev->port_num;
+
+ for (i = 0; i < dev->port_num; i++) {
+ port = &dev->port[i];
+ if (port->class != DDB_PORT_NONE) {
+ ret = ddb_port_attach(port);
+ if (ret)
+ err_ports++;
+ } else {
+ numports--;
+ }
+ }
+
+ if (err_ports) {
+ if (err_ports == numports) {
+ dev_err(dev->dev, "All connected ports failed to initialise!\n");
+ return -ENODEV;
+ }
+
+ dev_warn(dev->dev, "%d of %d connected ports failed to initialise!\n",
+ err_ports, numports);
+ }
+
+ return 0;
+}
+
+void ddb_ports_detach(struct ddb *dev)
+{
+ int i;
+ struct ddb_port *port;
+
+ for (i = 0; i < dev->port_num; i++) {
+ port = &dev->port[i];
+
+ switch (port->class) {
+ case DDB_PORT_TUNER:
+ dvb_input_detach(port->input[1]);
+ dvb_input_detach(port->input[0]);
+ break;
+ case DDB_PORT_CI:
+ case DDB_PORT_LOOP:
+ ddb_ci_detach(port);
+ break;
+ }
+ }
+ dvb_unregister_adapters(dev);
+}
+
+/* Copy input DMA pointers to output DMA and ACK. */
+
+static void input_write_output(struct ddb_input *input,
+ struct ddb_output *output)
+{
+ ddbwritel(output->port->dev,
+ input->dma->stat, DMA_BUFFER_ACK(output->dma));
+ output->dma->cbuf = (input->dma->stat >> 11) & 0x1f;
+ output->dma->coff = (input->dma->stat & 0x7ff) << 7;
+}
+
+static void output_ack_input(struct ddb_output *output,
+ struct ddb_input *input)
+{
+ ddbwritel(input->port->dev,
+ output->dma->stat, DMA_BUFFER_ACK(input->dma));
+}
+
+static void input_write_dvb(struct ddb_input *input,
+ struct ddb_input *input2)
+{
+ struct ddb_dvb *dvb = &input2->port->dvb[input2->nr & 1];
+ struct ddb_dma *dma, *dma2;
+ struct ddb *dev = input->port->dev;
+ int ack = 1;
+
+ dma = input->dma;
+ dma2 = input->dma;
+ /*
+ * if there also is an output connected, do not ACK.
+ * input_write_output will ACK.
+ */
+ if (input->redo) {
+ dma2 = input->redo->dma;
+ ack = 0;
+ }
+ while (dma->cbuf != ((dma->stat >> 11) & 0x1f) ||
+ (4 & dma->ctrl)) {
+ if (4 & dma->ctrl) {
+ /* dev_err(dev->dev, "Overflow dma %d\n", dma->nr); */
+ ack = 1;
+ }
+ if (alt_dma)
+ dma_sync_single_for_cpu(dev->dev, dma2->pbuf[dma->cbuf],
+ dma2->size, DMA_FROM_DEVICE);
+ dvb_dmx_swfilter_packets(&dvb->demux,
+ dma2->vbuf[dma->cbuf],
+ dma2->size / 188);
+ dma->cbuf = (dma->cbuf + 1) % dma2->num;
+ if (ack)
+ ddbwritel(dev, (dma->cbuf << 11),
+ DMA_BUFFER_ACK(dma));
+ dma->stat = safe_ddbreadl(dev, DMA_BUFFER_CURRENT(dma));
+ dma->ctrl = safe_ddbreadl(dev, DMA_BUFFER_CONTROL(dma));
+ }
+}
+
+static void input_work(struct work_struct *work)
+{
+ struct ddb_dma *dma = container_of(work, struct ddb_dma, work);
+ struct ddb_input *input = (struct ddb_input *)dma->io;
+ struct ddb *dev = input->port->dev;
+ unsigned long flags;
+
+ spin_lock_irqsave(&dma->lock, flags);
+ if (!dma->running) {
+ spin_unlock_irqrestore(&dma->lock, flags);
+ return;
+ }
+ dma->stat = ddbreadl(dev, DMA_BUFFER_CURRENT(dma));
+ dma->ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(dma));
+
+ if (input->redi)
+ input_write_dvb(input, input->redi);
+ if (input->redo)
+ input_write_output(input, input->redo);
+ wake_up(&dma->wq);
+ spin_unlock_irqrestore(&dma->lock, flags);
+}
+
+static void input_handler(void *data)
+{
+ struct ddb_input *input = (struct ddb_input *)data;
+ struct ddb_dma *dma = input->dma;
+
+ queue_work(ddb_wq, &dma->work);
+}
+
+static void output_work(struct work_struct *work)
+{
+ struct ddb_dma *dma = container_of(work, struct ddb_dma, work);
+ struct ddb_output *output = (struct ddb_output *)dma->io;
+ struct ddb *dev = output->port->dev;
+ unsigned long flags;
+
+ spin_lock_irqsave(&dma->lock, flags);
+ if (!dma->running)
+ goto unlock_exit;
+ dma->stat = ddbreadl(dev, DMA_BUFFER_CURRENT(dma));
+ dma->ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(dma));
+ if (output->redi)
+ output_ack_input(output, output->redi);
+ wake_up(&dma->wq);
+unlock_exit:
+ spin_unlock_irqrestore(&dma->lock, flags);
+}
+
+static void output_handler(void *data)
+{
+ struct ddb_output *output = (struct ddb_output *)data;
+ struct ddb_dma *dma = output->dma;
+
+ queue_work(ddb_wq, &dma->work);
+}
+
+/****************************************************************************/
+/****************************************************************************/
+
+static const struct ddb_regmap *io_regmap(struct ddb_io *io, int link)
+{
+ const struct ddb_info *info;
+
+ if (link)
+ info = io->port->dev->link[io->port->lnr].info;
+ else
+ info = io->port->dev->link[0].info;
+
+ if (!info)
+ return NULL;
+
+ return info->regmap;
+}
+
+static void ddb_dma_init(struct ddb_io *io, int nr, int out)
+{
+ struct ddb_dma *dma;
+ const struct ddb_regmap *rm = io_regmap(io, 0);
+
+ dma = out ? &io->port->dev->odma[nr] : &io->port->dev->idma[nr];
+ io->dma = dma;
+ dma->io = io;
+
+ spin_lock_init(&dma->lock);
+ init_waitqueue_head(&dma->wq);
+ if (out) {
+ INIT_WORK(&dma->work, output_work);
+ dma->regs = rm->odma->base + rm->odma->size * nr;
+ dma->bufregs = rm->odma_buf->base + rm->odma_buf->size * nr;
+ dma->num = dma_buf_num;
+ dma->size = dma_buf_size * 128 * 47;
+ dma->div = 1;
+ } else {
+ INIT_WORK(&dma->work, input_work);
+ dma->regs = rm->idma->base + rm->idma->size * nr;
+ dma->bufregs = rm->idma_buf->base + rm->idma_buf->size * nr;
+ dma->num = dma_buf_num;
+ dma->size = dma_buf_size * 128 * 47;
+ dma->div = 1;
+ }
+ ddbwritel(io->port->dev, 0, DMA_BUFFER_ACK(dma));
+ dev_dbg(io->port->dev->dev, "init link %u, io %u, dma %u, dmaregs %08x bufregs %08x\n",
+ io->port->lnr, io->nr, nr, dma->regs, dma->bufregs);
+}
+
+static void ddb_input_init(struct ddb_port *port, int nr, int pnr, int anr)
+{
+ struct ddb *dev = port->dev;
+ struct ddb_input *input = &dev->input[anr];
+ const struct ddb_regmap *rm;
+
+ port->input[pnr] = input;
+ input->nr = nr;
+ input->port = port;
+ rm = io_regmap(input, 1);
+ input->regs = DDB_LINK_TAG(port->lnr) |
+ (rm->input->base + rm->input->size * nr);
+ dev_dbg(dev->dev, "init link %u, input %u, regs %08x\n",
+ port->lnr, nr, input->regs);
+
+ if (dev->has_dma) {
+ const struct ddb_regmap *rm0 = io_regmap(input, 0);
+ u32 base = rm0->irq_base_idma;
+ u32 dma_nr = nr;
+
+ if (port->lnr)
+ dma_nr += 32 + (port->lnr - 1) * 8;
+
+ dev_dbg(dev->dev, "init link %u, input %u, handler %u\n",
+ port->lnr, nr, dma_nr + base);
+
+ ddb_irq_set(dev, 0, dma_nr + base, &input_handler, input);
+ ddb_dma_init(input, dma_nr, 0);
+ }
+}
+
+static void ddb_output_init(struct ddb_port *port, int nr)
+{
+ struct ddb *dev = port->dev;
+ struct ddb_output *output = &dev->output[nr];
+ const struct ddb_regmap *rm;
+
+ port->output = output;
+ output->nr = nr;
+ output->port = port;
+ rm = io_regmap(output, 1);
+ output->regs = DDB_LINK_TAG(port->lnr) |
+ (rm->output->base + rm->output->size * nr);
+
+ dev_dbg(dev->dev, "init link %u, output %u, regs %08x\n",
+ port->lnr, nr, output->regs);
+
+ if (dev->has_dma) {
+ const struct ddb_regmap *rm0 = io_regmap(output, 0);
+ u32 base = rm0->irq_base_odma;
+
+ ddb_irq_set(dev, 0, nr + base, &output_handler, output);
+ ddb_dma_init(output, nr, 1);
+ }
+}
+
+static int ddb_port_match_i2c(struct ddb_port *port)
+{
+ struct ddb *dev = port->dev;
+ u32 i;
+
+ for (i = 0; i < dev->i2c_num; i++) {
+ if (dev->i2c[i].link == port->lnr &&
+ dev->i2c[i].nr == port->nr) {
+ port->i2c = &dev->i2c[i];
+ return 1;
+ }
+ }
+ return 0;
+}
+
+static int ddb_port_match_link_i2c(struct ddb_port *port)
+{
+ struct ddb *dev = port->dev;
+ u32 i;
+
+ for (i = 0; i < dev->i2c_num; i++) {
+ if (dev->i2c[i].link == port->lnr) {
+ port->i2c = &dev->i2c[i];
+ return 1;
+ }
+ }
+ return 0;
+}
+
+void ddb_ports_init(struct ddb *dev)
+{
+ u32 i, l, p;
+ struct ddb_port *port;
+ const struct ddb_info *info;
+ const struct ddb_regmap *rm;
+
+ for (p = l = 0; l < DDB_MAX_LINK; l++) {
+ info = dev->link[l].info;
+ if (!info)
+ continue;
+ rm = info->regmap;
+ if (!rm)
+ continue;
+ for (i = 0; i < info->port_num; i++, p++) {
+ port = &dev->port[p];
+ port->dev = dev;
+ port->nr = i;
+ port->lnr = l;
+ port->pnr = p;
+ port->gap = 0xffffffff;
+ port->obr = ci_bitrate;
+ mutex_init(&port->i2c_gate_lock);
+
+ if (!ddb_port_match_i2c(port)) {
+ if (info->type == DDB_OCTOPUS_MAX)
+ ddb_port_match_link_i2c(port);
+ }
+
+ ddb_port_probe(port);
+
+ port->dvb[0].adap = &dev->adap[2 * p];
+ port->dvb[1].adap = &dev->adap[2 * p + 1];
+
+ if (port->class == DDB_PORT_NONE && i && p &&
+ dev->port[p - 1].type == DDB_CI_EXTERNAL_XO2) {
+ port->class = DDB_PORT_CI;
+ port->type = DDB_CI_EXTERNAL_XO2_B;
+ port->name = "DuoFlex CI_B";
+ port->i2c = dev->port[p - 1].i2c;
+ }
+
+ dev_info(dev->dev, "Port %u: Link %u, Link Port %u (TAB %u): %s\n",
+ port->pnr, port->lnr, port->nr, port->nr + 1,
+ port->name);
+
+ if (port->class == DDB_PORT_CI &&
+ port->type == DDB_CI_EXTERNAL_XO2) {
+ ddb_input_init(port, 2 * i, 0, 2 * i);
+ ddb_output_init(port, i);
+ continue;
+ }
+
+ if (port->class == DDB_PORT_CI &&
+ port->type == DDB_CI_EXTERNAL_XO2_B) {
+ ddb_input_init(port, 2 * i - 1, 0, 2 * i - 1);
+ ddb_output_init(port, i);
+ continue;
+ }
+
+ if (port->class == DDB_PORT_NONE)
+ continue;
+
+ switch (dev->link[l].info->type) {
+ case DDB_OCTOPUS_CI:
+ if (i >= 2) {
+ ddb_input_init(port, 2 + i, 0, 2 + i);
+ ddb_input_init(port, 4 + i, 1, 4 + i);
+ ddb_output_init(port, i);
+ break;
+ }
+ fallthrough;
+ case DDB_OCTOPUS:
+ ddb_input_init(port, 2 * i, 0, 2 * i);
+ ddb_input_init(port, 2 * i + 1, 1, 2 * i + 1);
+ ddb_output_init(port, i);
+ break;
+ case DDB_OCTOPUS_MAX:
+ case DDB_OCTOPUS_MAX_CT:
+ case DDB_OCTOPUS_MCI:
+ ddb_input_init(port, 2 * i, 0, 2 * p);
+ ddb_input_init(port, 2 * i + 1, 1, 2 * p + 1);
+ break;
+ default:
+ break;
+ }
+ }
+ }
+ dev->port_num = p;
+}
+
+void ddb_ports_release(struct ddb *dev)
+{
+ int i;
+ struct ddb_port *port;
+
+ for (i = 0; i < dev->port_num; i++) {
+ port = &dev->port[i];
+ if (port->input[0] && port->input[0]->dma)
+ cancel_work_sync(&port->input[0]->dma->work);
+ if (port->input[1] && port->input[1]->dma)
+ cancel_work_sync(&port->input[1]->dma->work);
+ if (port->output && port->output->dma)
+ cancel_work_sync(&port->output->dma->work);
+ }
+}
+
+/****************************************************************************/
+/****************************************************************************/
+/****************************************************************************/
+
+#define IRQ_HANDLE(_nr) \
+ do { if ((s & (1UL << ((_nr) & 0x1f))) && \
+ dev->link[0].irq[_nr].handler) \
+ dev->link[0].irq[_nr].handler(dev->link[0].irq[_nr].data); } \
+ while (0)
+
+#define IRQ_HANDLE_NIBBLE(_shift) { \
+ if (s & (0x0000000f << ((_shift) & 0x1f))) { \
+ IRQ_HANDLE(0 + (_shift)); \
+ IRQ_HANDLE(1 + (_shift)); \
+ IRQ_HANDLE(2 + (_shift)); \
+ IRQ_HANDLE(3 + (_shift)); \
+ } \
+}
+
+#define IRQ_HANDLE_BYTE(_shift) { \
+ if (s & (0x000000ff << ((_shift) & 0x1f))) { \
+ IRQ_HANDLE(0 + (_shift)); \
+ IRQ_HANDLE(1 + (_shift)); \
+ IRQ_HANDLE(2 + (_shift)); \
+ IRQ_HANDLE(3 + (_shift)); \
+ IRQ_HANDLE(4 + (_shift)); \
+ IRQ_HANDLE(5 + (_shift)); \
+ IRQ_HANDLE(6 + (_shift)); \
+ IRQ_HANDLE(7 + (_shift)); \
+ } \
+}
+
+static void irq_handle_msg(struct ddb *dev, u32 s)
+{
+ dev->i2c_irq++;
+ IRQ_HANDLE_NIBBLE(0);
+}
+
+static void irq_handle_io(struct ddb *dev, u32 s)
+{
+ dev->ts_irq++;
+ IRQ_HANDLE_NIBBLE(4);
+ IRQ_HANDLE_BYTE(8);
+ IRQ_HANDLE_BYTE(16);
+ IRQ_HANDLE_BYTE(24);
+}
+
+irqreturn_t ddb_irq_handler0(int irq, void *dev_id)
+{
+ struct ddb *dev = (struct ddb *)dev_id;
+ u32 mask = 0x8fffff00;
+ u32 s = mask & ddbreadl(dev, INTERRUPT_STATUS);
+
+ if (!s)
+ return IRQ_NONE;
+ do {
+ if (s & 0x80000000)
+ return IRQ_NONE;
+ ddbwritel(dev, s, INTERRUPT_ACK);
+ irq_handle_io(dev, s);
+ } while ((s = mask & ddbreadl(dev, INTERRUPT_STATUS)));
+
+ return IRQ_HANDLED;
+}
+
+irqreturn_t ddb_irq_handler1(int irq, void *dev_id)
+{
+ struct ddb *dev = (struct ddb *)dev_id;
+ u32 mask = 0x8000000f;
+ u32 s = mask & ddbreadl(dev, INTERRUPT_STATUS);
+
+ if (!s)
+ return IRQ_NONE;
+ do {
+ if (s & 0x80000000)
+ return IRQ_NONE;
+ ddbwritel(dev, s, INTERRUPT_ACK);
+ irq_handle_msg(dev, s);
+ } while ((s = mask & ddbreadl(dev, INTERRUPT_STATUS)));
+
+ return IRQ_HANDLED;
+}
+
+irqreturn_t ddb_irq_handler(int irq, void *dev_id)
+{
+ struct ddb *dev = (struct ddb *)dev_id;
+ u32 s = ddbreadl(dev, INTERRUPT_STATUS);
+ int ret = IRQ_HANDLED;
+
+ if (!s)
+ return IRQ_NONE;
+ do {
+ if (s & 0x80000000)
+ return IRQ_NONE;
+ ddbwritel(dev, s, INTERRUPT_ACK);
+
+ if (s & 0x0000000f)
+ irq_handle_msg(dev, s);
+ if (s & 0x0fffff00)
+ irq_handle_io(dev, s);
+ } while ((s = ddbreadl(dev, INTERRUPT_STATUS)));
+
+ return ret;
+}
+
+/****************************************************************************/
+/****************************************************************************/
+/****************************************************************************/
+
+static int reg_wait(struct ddb *dev, u32 reg, u32 bit)
+{
+ u32 count = 0;
+
+ while (safe_ddbreadl(dev, reg) & bit) {
+ ndelay(10);
+ if (++count == 100)
+ return -1;
+ }
+ return 0;
+}
+
+static int flashio(struct ddb *dev, u32 lnr, u8 *wbuf, u32 wlen, u8 *rbuf,
+ u32 rlen)
+{
+ u32 data, shift;
+ u32 tag = DDB_LINK_TAG(lnr);
+ struct ddb_link *link = &dev->link[lnr];
+
+ mutex_lock(&link->flash_mutex);
+ if (wlen > 4)
+ ddbwritel(dev, 1, tag | SPI_CONTROL);
+ while (wlen > 4) {
+ /* FIXME: check for big-endian */
+ data = swab32(*(u32 *)wbuf);
+ wbuf += 4;
+ wlen -= 4;
+ ddbwritel(dev, data, tag | SPI_DATA);
+ if (reg_wait(dev, tag | SPI_CONTROL, 4))
+ goto fail;
+ }
+ if (rlen)
+ ddbwritel(dev, 0x0001 | ((wlen << (8 + 3)) & 0x1f00),
+ tag | SPI_CONTROL);
+ else
+ ddbwritel(dev, 0x0003 | ((wlen << (8 + 3)) & 0x1f00),
+ tag | SPI_CONTROL);
+
+ data = 0;
+ shift = ((4 - wlen) * 8);
+ while (wlen) {
+ data <<= 8;
+ data |= *wbuf;
+ wlen--;
+ wbuf++;
+ }
+ if (shift)
+ data <<= shift;
+ ddbwritel(dev, data, tag | SPI_DATA);
+ if (reg_wait(dev, tag | SPI_CONTROL, 4))
+ goto fail;
+
+ if (!rlen) {
+ ddbwritel(dev, 0, tag | SPI_CONTROL);
+ goto exit;
+ }
+ if (rlen > 4)
+ ddbwritel(dev, 1, tag | SPI_CONTROL);
+
+ while (rlen > 4) {
+ ddbwritel(dev, 0xffffffff, tag | SPI_DATA);
+ if (reg_wait(dev, tag | SPI_CONTROL, 4))
+ goto fail;
+ data = ddbreadl(dev, tag | SPI_DATA);
+ *(u32 *)rbuf = swab32(data);
+ rbuf += 4;
+ rlen -= 4;
+ }
+ ddbwritel(dev, 0x0003 | ((rlen << (8 + 3)) & 0x1F00),
+ tag | SPI_CONTROL);
+ ddbwritel(dev, 0xffffffff, tag | SPI_DATA);
+ if (reg_wait(dev, tag | SPI_CONTROL, 4))
+ goto fail;
+
+ data = ddbreadl(dev, tag | SPI_DATA);
+ ddbwritel(dev, 0, tag | SPI_CONTROL);
+
+ if (rlen < 4)
+ data <<= ((4 - rlen) * 8);
+
+ while (rlen > 0) {
+ *rbuf = ((data >> 24) & 0xff);
+ data <<= 8;
+ rbuf++;
+ rlen--;
+ }
+exit:
+ mutex_unlock(&link->flash_mutex);
+ return 0;
+fail:
+ mutex_unlock(&link->flash_mutex);
+ return -1;
+}
+
+int ddbridge_flashread(struct ddb *dev, u32 link, u8 *buf, u32 addr, u32 len)
+{
+ u8 cmd[4] = {0x03, (addr >> 16) & 0xff,
+ (addr >> 8) & 0xff, addr & 0xff};
+
+ return flashio(dev, link, cmd, 4, buf, len);
+}
+
+/*
+ * TODO/FIXME: add/implement IOCTLs from upstream driver
+ */
+
+#define DDB_NAME "ddbridge"
+
+static u32 ddb_num;
+static int ddb_major;
+static DEFINE_MUTEX(ddb_mutex);
+
+static int ddb_release(struct inode *inode, struct file *file)
+{
+ struct ddb *dev = file->private_data;
+
+ dev->ddb_dev_users--;
+ return 0;
+}
+
+static int ddb_open(struct inode *inode, struct file *file)
+{
+ struct ddb *dev = ddbs[iminor(inode)];
+
+ if (dev->ddb_dev_users)
+ return -EBUSY;
+ dev->ddb_dev_users++;
+ file->private_data = dev;
+ return 0;
+}
+
+static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
+{
+ struct ddb *dev = file->private_data;
+
+ dev_warn(dev->dev, "DDB IOCTLs unsupported (cmd: %d, arg: %lu)\n",
+ cmd, arg);
+
+ return -ENOTTY;
+}
+
+static const struct file_operations ddb_fops = {
+ .unlocked_ioctl = ddb_ioctl,
+ .open = ddb_open,
+ .release = ddb_release,
+};
+
+static char *ddb_devnode(struct device *device, umode_t *mode)
+{
+ struct ddb *dev = dev_get_drvdata(device);
+
+ return kasprintf(GFP_KERNEL, "ddbridge/card%d", dev->nr);
+}
+
+#define __ATTR_MRO(_name, _show) { \
+ .attr = { .name = __stringify(_name), .mode = 0444 }, \
+ .show = _show, \
+}
+
+#define __ATTR_MWO(_name, _store) { \
+ .attr = { .name = __stringify(_name), .mode = 0222 }, \
+ .store = _store, \
+}
+
+static ssize_t ports_show(struct device *device,
+ struct device_attribute *attr, char *buf)
+{
+ struct ddb *dev = dev_get_drvdata(device);
+
+ return sprintf(buf, "%d\n", dev->port_num);
+}
+
+static ssize_t ts_irq_show(struct device *device,
+ struct device_attribute *attr, char *buf)
+{
+ struct ddb *dev = dev_get_drvdata(device);
+
+ return sprintf(buf, "%d\n", dev->ts_irq);
+}
+
+static ssize_t i2c_irq_show(struct device *device,
+ struct device_attribute *attr, char *buf)
+{
+ struct ddb *dev = dev_get_drvdata(device);
+
+ return sprintf(buf, "%d\n", dev->i2c_irq);
+}
+
+static ssize_t fan_show(struct device *device,
+ struct device_attribute *attr, char *buf)
+{
+ struct ddb *dev = dev_get_drvdata(device);
+ u32 val;
+
+ val = ddbreadl(dev, GPIO_OUTPUT) & 1;
+ return sprintf(buf, "%d\n", val);
+}
+
+static ssize_t fan_store(struct device *device, struct device_attribute *d,
+ const char *buf, size_t count)
+{
+ struct ddb *dev = dev_get_drvdata(device);
+ u32 val;
+
+ if (sscanf(buf, "%u\n", &val) != 1)
+ return -EINVAL;
+ ddbwritel(dev, 1, GPIO_DIRECTION);
+ ddbwritel(dev, val & 1, GPIO_OUTPUT);
+ return count;
+}
+
+static ssize_t fanspeed_show(struct device *device,
+ struct device_attribute *attr, char *buf)
+{
+ struct ddb *dev = dev_get_drvdata(device);
+ int num = attr->attr.name[8] - 0x30;
+ struct ddb_link *link = &dev->link[num];
+ u32 spd;
+
+ spd = ddblreadl(link, TEMPMON_FANCONTROL) & 0xff;
+ return sprintf(buf, "%u\n", spd * 100);
+}
+
+static ssize_t temp_show(struct device *device,
+ struct device_attribute *attr, char *buf)
+{
+ struct ddb *dev = dev_get_drvdata(device);
+ struct ddb_link *link = &dev->link[0];
+ struct i2c_adapter *adap;
+ int temp, temp2;
+ u8 tmp[2];
+
+ if (!link->info->temp_num)
+ return sprintf(buf, "no sensor\n");
+ adap = &dev->i2c[link->info->temp_bus].adap;
+ if (i2c_read_regs(adap, 0x48, 0, tmp, 2) < 0)
+ return sprintf(buf, "read_error\n");
+ temp = (tmp[0] << 3) | (tmp[1] >> 5);
+ temp *= 125;
+ if (link->info->temp_num == 2) {
+ if (i2c_read_regs(adap, 0x49, 0, tmp, 2) < 0)
+ return sprintf(buf, "read_error\n");
+ temp2 = (tmp[0] << 3) | (tmp[1] >> 5);
+ temp2 *= 125;
+ return sprintf(buf, "%d %d\n", temp, temp2);
+ }
+ return sprintf(buf, "%d\n", temp);
+}
+
+static ssize_t ctemp_show(struct device *device,
+ struct device_attribute *attr, char *buf)
+{
+ struct ddb *dev = dev_get_drvdata(device);
+ struct i2c_adapter *adap;
+ int temp;
+ u8 tmp[2];
+ int num = attr->attr.name[4] - 0x30;
+
+ adap = &dev->i2c[num].adap;
+ if (!adap)
+ return 0;
+ if (i2c_read_regs(adap, 0x49, 0, tmp, 2) < 0)
+ if (i2c_read_regs(adap, 0x4d, 0, tmp, 2) < 0)
+ return sprintf(buf, "no sensor\n");
+ temp = tmp[0] * 1000;
+ return sprintf(buf, "%d\n", temp);
+}
+
+static ssize_t led_show(struct device *device,
+ struct device_attribute *attr, char *buf)
+{
+ struct ddb *dev = dev_get_drvdata(device);
+ int num = attr->attr.name[3] - 0x30;
+
+ return sprintf(buf, "%d\n", dev->leds & (1 << num) ? 1 : 0);
+}
+
+static void ddb_set_led(struct ddb *dev, int num, int val)
+{
+ if (!dev->link[0].info->led_num)
+ return;
+ switch (dev->port[num].class) {
+ case DDB_PORT_TUNER:
+ switch (dev->port[num].type) {
+ case DDB_TUNER_DVBS_ST:
+ i2c_write_reg16(&dev->i2c[num].adap,
+ 0x69, 0xf14c, val ? 2 : 0);
+ break;
+ case DDB_TUNER_DVBCT_ST:
+ i2c_write_reg16(&dev->i2c[num].adap,
+ 0x1f, 0xf00e, 0);
+ i2c_write_reg16(&dev->i2c[num].adap,
+ 0x1f, 0xf00f, val ? 1 : 0);
+ break;
+ case DDB_TUNER_XO2 ... DDB_TUNER_DVBC2T2I_SONY:
+ {
+ u8 v;
+
+ i2c_read_reg(&dev->i2c[num].adap, 0x10, 0x08, &v);
+ v = (v & ~0x10) | (val ? 0x10 : 0);
+ i2c_write_reg(&dev->i2c[num].adap, 0x10, 0x08, v);
+ break;
+ }
+ default:
+ break;
+ }
+ break;
+ }
+}
+
+static ssize_t led_store(struct device *device,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct ddb *dev = dev_get_drvdata(device);
+ int num = attr->attr.name[3] - 0x30;
+ u32 val;
+
+ if (sscanf(buf, "%u\n", &val) != 1)
+ return -EINVAL;
+ if (val)
+ dev->leds |= (1 << num);
+ else
+ dev->leds &= ~(1 << num);
+ ddb_set_led(dev, num, val);
+ return count;
+}
+
+static ssize_t snr_show(struct device *device,
+ struct device_attribute *attr, char *buf)
+{
+ struct ddb *dev = dev_get_drvdata(device);
+ char snr[32];
+ int num = attr->attr.name[3] - 0x30;
+
+ if (dev->port[num].type >= DDB_TUNER_XO2) {
+ if (i2c_read_regs(&dev->i2c[num].adap, 0x10, 0x10, snr, 16) < 0)
+ return sprintf(buf, "NO SNR\n");
+ snr[16] = 0;
+ } else {
+ /* serial number at 0x100-0x11f */
+ if (i2c_read_regs16(&dev->i2c[num].adap,
+ 0x57, 0x100, snr, 32) < 0)
+ if (i2c_read_regs16(&dev->i2c[num].adap,
+ 0x50, 0x100, snr, 32) < 0)
+ return sprintf(buf, "NO SNR\n");
+ snr[31] = 0; /* in case it is not terminated on EEPROM */
+ }
+ return sprintf(buf, "%s\n", snr);
+}
+
+static ssize_t bsnr_show(struct device *device,
+ struct device_attribute *attr, char *buf)
+{
+ struct ddb *dev = dev_get_drvdata(device);
+ char snr[16];
+
+ ddbridge_flashread(dev, 0, snr, 0x10, 15);
+ snr[15] = 0; /* in case it is not terminated on EEPROM */
+ return sprintf(buf, "%s\n", snr);
+}
+
+static ssize_t bpsnr_show(struct device *device,
+ struct device_attribute *attr, char *buf)
+{
+ struct ddb *dev = dev_get_drvdata(device);
+ unsigned char snr[32];
+
+ if (!dev->i2c_num)
+ return 0;
+
+ if (i2c_read_regs16(&dev->i2c[0].adap,
+ 0x50, 0x0000, snr, 32) < 0 ||
+ snr[0] == 0xff)
+ return sprintf(buf, "NO SNR\n");
+ snr[31] = 0; /* in case it is not terminated on EEPROM */
+ return sprintf(buf, "%s\n", snr);
+}
+
+static ssize_t redirect_show(struct device *device,
+ struct device_attribute *attr, char *buf)
+{
+ return 0;
+}
+
+static ssize_t redirect_store(struct device *device,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ unsigned int i, p;
+ int res;
+
+ if (sscanf(buf, "%x %x\n", &i, &p) != 2)
+ return -EINVAL;
+ res = ddb_redirect(i, p);
+ if (res < 0)
+ return res;
+ dev_info(device, "redirect: %02x, %02x\n", i, p);
+ return count;
+}
+
+static ssize_t gap_show(struct device *device,
+ struct device_attribute *attr, char *buf)
+{
+ struct ddb *dev = dev_get_drvdata(device);
+ int num = attr->attr.name[3] - 0x30;
+
+ return sprintf(buf, "%d\n", dev->port[num].gap);
+}
+
+static ssize_t gap_store(struct device *device, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct ddb *dev = dev_get_drvdata(device);
+ int num = attr->attr.name[3] - 0x30;
+ unsigned int val;
+
+ if (sscanf(buf, "%u\n", &val) != 1)
+ return -EINVAL;
+ if (val > 128)
+ return -EINVAL;
+ if (val == 128)
+ val = 0xffffffff;
+ dev->port[num].gap = val;
+ return count;
+}
+
+static ssize_t version_show(struct device *device,
+ struct device_attribute *attr, char *buf)
+{
+ struct ddb *dev = dev_get_drvdata(device);
+
+ return sprintf(buf, "%08x %08x\n",
+ dev->link[0].ids.hwid, dev->link[0].ids.regmapid);
+}
+
+static ssize_t hwid_show(struct device *device,
+ struct device_attribute *attr, char *buf)
+{
+ struct ddb *dev = dev_get_drvdata(device);
+
+ return sprintf(buf, "0x%08X\n", dev->link[0].ids.hwid);
+}
+
+static ssize_t regmap_show(struct device *device,
+ struct device_attribute *attr, char *buf)
+{
+ struct ddb *dev = dev_get_drvdata(device);
+
+ return sprintf(buf, "0x%08X\n", dev->link[0].ids.regmapid);
+}
+
+static ssize_t fmode_show(struct device *device,
+ struct device_attribute *attr, char *buf)
+{
+ int num = attr->attr.name[5] - 0x30;
+ struct ddb *dev = dev_get_drvdata(device);
+
+ return sprintf(buf, "%u\n", dev->link[num].lnb.fmode);
+}
+
+static ssize_t devid_show(struct device *device,
+ struct device_attribute *attr, char *buf)
+{
+ int num = attr->attr.name[5] - 0x30;
+ struct ddb *dev = dev_get_drvdata(device);
+
+ return sprintf(buf, "%08x\n", dev->link[num].ids.devid);
+}
+
+static ssize_t fmode_store(struct device *device, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct ddb *dev = dev_get_drvdata(device);
+ int num = attr->attr.name[5] - 0x30;
+ unsigned int val;
+
+ if (sscanf(buf, "%u\n", &val) != 1)
+ return -EINVAL;
+ if (val > 3)
+ return -EINVAL;
+ ddb_lnb_init_fmode(dev, &dev->link[num], val);
+ return count;
+}
+
+static struct device_attribute ddb_attrs[] = {
+ __ATTR_RO(version),
+ __ATTR_RO(ports),
+ __ATTR_RO(ts_irq),
+ __ATTR_RO(i2c_irq),
+ __ATTR(gap0, 0664, gap_show, gap_store),
+ __ATTR(gap1, 0664, gap_show, gap_store),
+ __ATTR(gap2, 0664, gap_show, gap_store),
+ __ATTR(gap3, 0664, gap_show, gap_store),
+ __ATTR(fmode0, 0664, fmode_show, fmode_store),
+ __ATTR(fmode1, 0664, fmode_show, fmode_store),
+ __ATTR(fmode2, 0664, fmode_show, fmode_store),
+ __ATTR(fmode3, 0664, fmode_show, fmode_store),
+ __ATTR_MRO(devid0, devid_show),
+ __ATTR_MRO(devid1, devid_show),
+ __ATTR_MRO(devid2, devid_show),
+ __ATTR_MRO(devid3, devid_show),
+ __ATTR_RO(hwid),
+ __ATTR_RO(regmap),
+ __ATTR(redirect, 0664, redirect_show, redirect_store),
+ __ATTR_MRO(snr, bsnr_show),
+ __ATTR_RO(bpsnr),
+ __ATTR_NULL,
+};
+
+static struct device_attribute ddb_attrs_temp[] = {
+ __ATTR_RO(temp),
+};
+
+static struct device_attribute ddb_attrs_fan[] = {
+ __ATTR(fan, 0664, fan_show, fan_store),
+};
+
+static struct device_attribute ddb_attrs_snr[] = {
+ __ATTR_MRO(snr0, snr_show),
+ __ATTR_MRO(snr1, snr_show),
+ __ATTR_MRO(snr2, snr_show),
+ __ATTR_MRO(snr3, snr_show),
+};
+
+static struct device_attribute ddb_attrs_ctemp[] = {
+ __ATTR_MRO(temp0, ctemp_show),
+ __ATTR_MRO(temp1, ctemp_show),
+ __ATTR_MRO(temp2, ctemp_show),
+ __ATTR_MRO(temp3, ctemp_show),
+};
+
+static struct device_attribute ddb_attrs_led[] = {
+ __ATTR(led0, 0664, led_show, led_store),
+ __ATTR(led1, 0664, led_show, led_store),
+ __ATTR(led2, 0664, led_show, led_store),
+ __ATTR(led3, 0664, led_show, led_store),
+};
+
+static struct device_attribute ddb_attrs_fanspeed[] = {
+ __ATTR_MRO(fanspeed0, fanspeed_show),
+ __ATTR_MRO(fanspeed1, fanspeed_show),
+ __ATTR_MRO(fanspeed2, fanspeed_show),
+ __ATTR_MRO(fanspeed3, fanspeed_show),
+};
+
+static struct class ddb_class = {
+ .name = "ddbridge",
+ .owner = THIS_MODULE,
+ .devnode = ddb_devnode,
+};
+
+static int ddb_class_create(void)
+{
+ ddb_major = register_chrdev(0, DDB_NAME, &ddb_fops);
+ if (ddb_major < 0)
+ return ddb_major;
+ if (class_register(&ddb_class) < 0)
+ return -1;
+ return 0;
+}
+
+static void ddb_class_destroy(void)
+{
+ class_unregister(&ddb_class);
+ unregister_chrdev(ddb_major, DDB_NAME);
+}
+
+static void ddb_device_attrs_del(struct ddb *dev)
+{
+ int i;
+
+ for (i = 0; i < 4; i++)
+ if (dev->link[i].info && dev->link[i].info->tempmon_irq)
+ device_remove_file(dev->ddb_dev,
+ &ddb_attrs_fanspeed[i]);
+ for (i = 0; i < dev->link[0].info->temp_num; i++)
+ device_remove_file(dev->ddb_dev, &ddb_attrs_temp[i]);
+ for (i = 0; i < dev->link[0].info->fan_num; i++)
+ device_remove_file(dev->ddb_dev, &ddb_attrs_fan[i]);
+ for (i = 0; i < dev->i2c_num && i < 4; i++) {
+ if (dev->link[0].info->led_num)
+ device_remove_file(dev->ddb_dev, &ddb_attrs_led[i]);
+ device_remove_file(dev->ddb_dev, &ddb_attrs_snr[i]);
+ device_remove_file(dev->ddb_dev, &ddb_attrs_ctemp[i]);
+ }
+ for (i = 0; ddb_attrs[i].attr.name; i++)
+ device_remove_file(dev->ddb_dev, &ddb_attrs[i]);
+}
+
+static int ddb_device_attrs_add(struct ddb *dev)
+{
+ int i;
+
+ for (i = 0; ddb_attrs[i].attr.name; i++)
+ if (device_create_file(dev->ddb_dev, &ddb_attrs[i]))
+ goto fail;
+ for (i = 0; i < dev->link[0].info->temp_num; i++)
+ if (device_create_file(dev->ddb_dev, &ddb_attrs_temp[i]))
+ goto fail;
+ for (i = 0; i < dev->link[0].info->fan_num; i++)
+ if (device_create_file(dev->ddb_dev, &ddb_attrs_fan[i]))
+ goto fail;
+ for (i = 0; (i < dev->i2c_num) && (i < 4); i++) {
+ if (device_create_file(dev->ddb_dev, &ddb_attrs_snr[i]))
+ goto fail;
+ if (device_create_file(dev->ddb_dev, &ddb_attrs_ctemp[i]))
+ goto fail;
+ if (dev->link[0].info->led_num)
+ if (device_create_file(dev->ddb_dev,
+ &ddb_attrs_led[i]))
+ goto fail;
+ }
+ for (i = 0; i < 4; i++)
+ if (dev->link[i].info && dev->link[i].info->tempmon_irq)
+ if (device_create_file(dev->ddb_dev,
+ &ddb_attrs_fanspeed[i]))
+ goto fail;
+ return 0;
+fail:
+ return -1;
+}
+
+int ddb_device_create(struct ddb *dev)
+{
+ int res = 0;
+
+ if (ddb_num == DDB_MAX_ADAPTER)
+ return -ENOMEM;
+ mutex_lock(&ddb_mutex);
+ dev->nr = ddb_num;
+ ddbs[dev->nr] = dev;
+ dev->ddb_dev = device_create(&ddb_class, dev->dev,
+ MKDEV(ddb_major, dev->nr),
+ dev, "ddbridge%d", dev->nr);
+ if (IS_ERR(dev->ddb_dev)) {
+ res = PTR_ERR(dev->ddb_dev);
+ dev_info(dev->dev, "Could not create ddbridge%d\n", dev->nr);
+ goto fail;
+ }
+ res = ddb_device_attrs_add(dev);
+ if (res) {
+ ddb_device_attrs_del(dev);
+ device_destroy(&ddb_class, MKDEV(ddb_major, dev->nr));
+ ddbs[dev->nr] = NULL;
+ dev->ddb_dev = ERR_PTR(-ENODEV);
+ } else {
+ ddb_num++;
+ }
+fail:
+ mutex_unlock(&ddb_mutex);
+ return res;
+}
+
+void ddb_device_destroy(struct ddb *dev)
+{
+ if (IS_ERR(dev->ddb_dev))
+ return;
+ ddb_device_attrs_del(dev);
+ device_destroy(&ddb_class, MKDEV(ddb_major, dev->nr));
+}
+
+/****************************************************************************/
+/****************************************************************************/
+/****************************************************************************/
+
+static void tempmon_setfan(struct ddb_link *link)
+{
+ u32 temp, temp2, pwm;
+
+ if ((ddblreadl(link, TEMPMON_CONTROL) &
+ TEMPMON_CONTROL_OVERTEMP) != 0) {
+ dev_info(link->dev->dev, "Over temperature condition\n");
+ link->overtemperature_error = 1;
+ }
+ temp = (ddblreadl(link, TEMPMON_SENSOR0) >> 8) & 0xFF;
+ if (temp & 0x80)
+ temp = 0;
+ temp2 = (ddblreadl(link, TEMPMON_SENSOR1) >> 8) & 0xFF;
+ if (temp2 & 0x80)
+ temp2 = 0;
+ if (temp2 > temp)
+ temp = temp2;
+
+ pwm = (ddblreadl(link, TEMPMON_FANCONTROL) >> 8) & 0x0F;
+ if (pwm > 10)
+ pwm = 10;
+
+ if (temp >= link->temp_tab[pwm]) {
+ while (pwm < 10 && temp >= link->temp_tab[pwm + 1])
+ pwm += 1;
+ } else {
+ while (pwm > 1 && temp < link->temp_tab[pwm - 2])
+ pwm -= 1;
+ }
+ ddblwritel(link, (pwm << 8), TEMPMON_FANCONTROL);
+}
+
+static void temp_handler(void *data)
+{
+ struct ddb_link *link = (struct ddb_link *)data;
+
+ spin_lock(&link->temp_lock);
+ tempmon_setfan(link);
+ spin_unlock(&link->temp_lock);
+}
+
+static int tempmon_init(struct ddb_link *link, int first_time)
+{
+ struct ddb *dev = link->dev;
+ int status = 0;
+ u32 l = link->nr;
+
+ spin_lock_irq(&link->temp_lock);
+ if (first_time) {
+ static u8 temperature_table[11] = {
+ 30, 35, 40, 45, 50, 55, 60, 65, 70, 75, 80 };
+
+ memcpy(link->temp_tab, temperature_table,
+ sizeof(temperature_table));
+ }
+ ddb_irq_set(dev, l, link->info->tempmon_irq, temp_handler, link);
+ ddblwritel(link, (TEMPMON_CONTROL_OVERTEMP | TEMPMON_CONTROL_AUTOSCAN |
+ TEMPMON_CONTROL_INTENABLE),
+ TEMPMON_CONTROL);
+ ddblwritel(link, (3 << 8), TEMPMON_FANCONTROL);
+
+ link->overtemperature_error =
+ ((ddblreadl(link, TEMPMON_CONTROL) &
+ TEMPMON_CONTROL_OVERTEMP) != 0);
+ if (link->overtemperature_error) {
+ dev_info(link->dev->dev, "Over temperature condition\n");
+ status = -1;
+ }
+ tempmon_setfan(link);
+ spin_unlock_irq(&link->temp_lock);
+ return status;
+}
+
+static int ddb_init_tempmon(struct ddb_link *link)
+{
+ const struct ddb_info *info = link->info;
+
+ if (!info->tempmon_irq)
+ return 0;
+ if (info->type == DDB_OCTOPUS_MAX_CT)
+ if (link->ids.regmapid < 0x00010002)
+ return 0;
+ spin_lock_init(&link->temp_lock);
+ dev_dbg(link->dev->dev, "init_tempmon\n");
+ return tempmon_init(link, 1);
+}
+
+/****************************************************************************/
+/****************************************************************************/
+/****************************************************************************/
+
+static int ddb_init_boards(struct ddb *dev)
+{
+ const struct ddb_info *info;
+ struct ddb_link *link;
+ u32 l;
+
+ for (l = 0; l < DDB_MAX_LINK; l++) {
+ link = &dev->link[l];
+ info = link->info;
+
+ if (!info)
+ continue;
+ if (info->board_control) {
+ ddbwritel(dev, 0, DDB_LINK_TAG(l) | BOARD_CONTROL);
+ msleep(100);
+ ddbwritel(dev, info->board_control_2,
+ DDB_LINK_TAG(l) | BOARD_CONTROL);
+ usleep_range(2000, 3000);
+ ddbwritel(dev,
+ info->board_control_2 | info->board_control,
+ DDB_LINK_TAG(l) | BOARD_CONTROL);
+ usleep_range(2000, 3000);
+ }
+ ddb_init_tempmon(link);
+ }
+ return 0;
+}
+
+int ddb_init(struct ddb *dev)
+{
+ mutex_init(&dev->link[0].lnb.lock);
+ mutex_init(&dev->link[0].flash_mutex);
+ if (no_init) {
+ ddb_device_create(dev);
+ return 0;
+ }
+
+ ddb_init_boards(dev);
+
+ if (ddb_i2c_init(dev) < 0)
+ goto fail1;
+ ddb_ports_init(dev);
+ if (ddb_buffers_alloc(dev) < 0) {
+ dev_info(dev->dev, "Could not allocate buffer memory\n");
+ goto fail2;
+ }
+ if (ddb_ports_attach(dev) < 0)
+ goto fail3;
+
+ ddb_device_create(dev);
+
+ if (dev->link[0].info->fan_num) {
+ ddbwritel(dev, 1, GPIO_DIRECTION);
+ ddbwritel(dev, 1, GPIO_OUTPUT);
+ }
+ return 0;
+
+fail3:
+ dev_err(dev->dev, "fail3\n");
+ ddb_ports_detach(dev);
+ ddb_buffers_free(dev);
+fail2:
+ dev_err(dev->dev, "fail2\n");
+ ddb_ports_release(dev);
+ ddb_i2c_release(dev);
+fail1:
+ dev_err(dev->dev, "fail1\n");
+ return -1;
+}
+
+void ddb_unmap(struct ddb *dev)
+{
+ if (dev->regs)
+ iounmap(dev->regs);
+ vfree(dev);
+}
+
+int ddb_exit_ddbridge(int stage, int error)
+{
+ switch (stage) {
+ default:
+ case 2:
+ destroy_workqueue(ddb_wq);
+ fallthrough;
+ case 1:
+ ddb_class_destroy();
+ break;
+ }
+
+ return error;
+}
+
+int ddb_init_ddbridge(void)
+{
+ if (dma_buf_num < 8)
+ dma_buf_num = 8;
+ if (dma_buf_num > 32)
+ dma_buf_num = 32;
+ if (dma_buf_size < 1)
+ dma_buf_size = 1;
+ if (dma_buf_size > 43)
+ dma_buf_size = 43;
+
+ if (ddb_class_create() < 0)
+ return -1;
+ ddb_wq = alloc_workqueue("ddbridge", 0, 0);
+ if (!ddb_wq)
+ return ddb_exit_ddbridge(1, -1);
+
+ return 0;
+}
diff --git a/drivers/media/pci/ddbridge/ddbridge-dummy-fe.c b/drivers/media/pci/ddbridge/ddbridge-dummy-fe.c
new file mode 100644
index 000000000..520ebd16b
--- /dev/null
+++ b/drivers/media/pci/ddbridge/ddbridge-dummy-fe.c
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Driver for Dummy Frontend
+ *
+ * Written by Emard <emard@softhome.net>
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/string.h>
+#include <linux/slab.h>
+
+#include <media/dvb_frontend.h>
+#include "ddbridge-dummy-fe.h"
+
+struct ddbridge_dummy_fe_state {
+ struct dvb_frontend frontend;
+};
+
+static int ddbridge_dummy_fe_read_status(struct dvb_frontend *fe,
+ enum fe_status *status)
+{
+ *status = FE_HAS_SIGNAL
+ | FE_HAS_CARRIER
+ | FE_HAS_VITERBI
+ | FE_HAS_SYNC
+ | FE_HAS_LOCK;
+
+ return 0;
+}
+
+static int ddbridge_dummy_fe_read_ber(struct dvb_frontend *fe, u32 *ber)
+{
+ *ber = 0;
+ return 0;
+}
+
+static int ddbridge_dummy_fe_read_signal_strength(struct dvb_frontend *fe,
+ u16 *strength)
+{
+ *strength = 0;
+ return 0;
+}
+
+static int ddbridge_dummy_fe_read_snr(struct dvb_frontend *fe, u16 *snr)
+{
+ *snr = 0;
+ return 0;
+}
+
+static int ddbridge_dummy_fe_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
+{
+ *ucblocks = 0;
+ return 0;
+}
+
+/*
+ * Should only be implemented if it actually reads something from the hardware.
+ * Also, it should check for the locks, in order to avoid report wrong data
+ * to userspace.
+ */
+static int ddbridge_dummy_fe_get_frontend(struct dvb_frontend *fe,
+ struct dtv_frontend_properties *p)
+{
+ return 0;
+}
+
+static int ddbridge_dummy_fe_set_frontend(struct dvb_frontend *fe)
+{
+ if (fe->ops.tuner_ops.set_params) {
+ fe->ops.tuner_ops.set_params(fe);
+ if (fe->ops.i2c_gate_ctrl)
+ fe->ops.i2c_gate_ctrl(fe, 0);
+ }
+
+ return 0;
+}
+
+static int ddbridge_dummy_fe_sleep(struct dvb_frontend *fe)
+{
+ return 0;
+}
+
+static int ddbridge_dummy_fe_init(struct dvb_frontend *fe)
+{
+ return 0;
+}
+
+static void ddbridge_dummy_fe_release(struct dvb_frontend *fe)
+{
+ struct ddbridge_dummy_fe_state *state = fe->demodulator_priv;
+
+ kfree(state);
+}
+
+static const struct dvb_frontend_ops ddbridge_dummy_fe_qam_ops;
+
+struct dvb_frontend *ddbridge_dummy_fe_qam_attach(void)
+{
+ struct ddbridge_dummy_fe_state *state = NULL;
+
+ /* allocate memory for the internal state */
+ state = kzalloc(sizeof(struct ddbridge_dummy_fe_state), GFP_KERNEL);
+ if (!state)
+ return NULL;
+
+ /* create dvb_frontend */
+ memcpy(&state->frontend.ops,
+ &ddbridge_dummy_fe_qam_ops,
+ sizeof(struct dvb_frontend_ops));
+
+ state->frontend.demodulator_priv = state;
+ return &state->frontend;
+}
+EXPORT_SYMBOL_GPL(ddbridge_dummy_fe_qam_attach);
+
+static const struct dvb_frontend_ops ddbridge_dummy_fe_qam_ops = {
+ .delsys = { SYS_DVBC_ANNEX_A },
+ .info = {
+ .name = "ddbridge dummy DVB-C",
+ .frequency_min_hz = 51 * MHz,
+ .frequency_max_hz = 858 * MHz,
+ .frequency_stepsize_hz = 62500,
+ /* symbol_rate_min: SACLK/64 == (XIN/2)/64 */
+ .symbol_rate_min = (57840000 / 2) / 64,
+ .symbol_rate_max = (57840000 / 2) / 4, /* SACLK/4 */
+ .caps = FE_CAN_QAM_16 |
+ FE_CAN_QAM_32 |
+ FE_CAN_QAM_64 |
+ FE_CAN_QAM_128 |
+ FE_CAN_QAM_256 |
+ FE_CAN_FEC_AUTO |
+ FE_CAN_INVERSION_AUTO
+ },
+
+ .release = ddbridge_dummy_fe_release,
+
+ .init = ddbridge_dummy_fe_init,
+ .sleep = ddbridge_dummy_fe_sleep,
+
+ .set_frontend = ddbridge_dummy_fe_set_frontend,
+ .get_frontend = ddbridge_dummy_fe_get_frontend,
+
+ .read_status = ddbridge_dummy_fe_read_status,
+ .read_ber = ddbridge_dummy_fe_read_ber,
+ .read_signal_strength = ddbridge_dummy_fe_read_signal_strength,
+ .read_snr = ddbridge_dummy_fe_read_snr,
+ .read_ucblocks = ddbridge_dummy_fe_read_ucblocks,
+};
+
+MODULE_DESCRIPTION("ddbridge dummy Frontend");
+MODULE_AUTHOR("Emard");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/pci/ddbridge/ddbridge-dummy-fe.h b/drivers/media/pci/ddbridge/ddbridge-dummy-fe.h
new file mode 100644
index 000000000..ddf189c09
--- /dev/null
+++ b/drivers/media/pci/ddbridge/ddbridge-dummy-fe.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Driver for Dummy Frontend
+ *
+ * Written by Emard <emard@softhome.net>
+ */
+
+#ifndef DDBRIDGE_DUMMY_FE_H
+#define DDBRIDGE_DUMMY_FE_H
+
+#include <linux/dvb/frontend.h>
+#include <media/dvb_frontend.h>
+
+struct dvb_frontend *ddbridge_dummy_fe_qam_attach(void);
+
+#endif // DDBRIDGE_DUMMY_FE_H
diff --git a/drivers/media/pci/ddbridge/ddbridge-hw.c b/drivers/media/pci/ddbridge/ddbridge-hw.c
new file mode 100644
index 000000000..d7d9cd0da
--- /dev/null
+++ b/drivers/media/pci/ddbridge/ddbridge-hw.c
@@ -0,0 +1,379 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ddbridge-hw.c: Digital Devices bridge hardware maps
+ *
+ * Copyright (C) 2010-2017 Digital Devices GmbH
+ * Ralph Metzler <rjkm@metzlerbros.de>
+ * Marcus Metzler <mocm@metzlerbros.de>
+ */
+
+#include "ddbridge.h"
+#include "ddbridge-hw.h"
+
+/******************************************************************************/
+
+static const struct ddb_regset octopus_input = {
+ .base = 0x200,
+ .num = 0x08,
+ .size = 0x10,
+};
+
+static const struct ddb_regset octopus_output = {
+ .base = 0x280,
+ .num = 0x08,
+ .size = 0x10,
+};
+
+static const struct ddb_regset octopus_idma = {
+ .base = 0x300,
+ .num = 0x08,
+ .size = 0x10,
+};
+
+static const struct ddb_regset octopus_idma_buf = {
+ .base = 0x2000,
+ .num = 0x08,
+ .size = 0x100,
+};
+
+static const struct ddb_regset octopus_odma = {
+ .base = 0x380,
+ .num = 0x04,
+ .size = 0x10,
+};
+
+static const struct ddb_regset octopus_odma_buf = {
+ .base = 0x2800,
+ .num = 0x04,
+ .size = 0x100,
+};
+
+static const struct ddb_regset octopus_i2c = {
+ .base = 0x80,
+ .num = 0x04,
+ .size = 0x20,
+};
+
+static const struct ddb_regset octopus_i2c_buf = {
+ .base = 0x1000,
+ .num = 0x04,
+ .size = 0x200,
+};
+
+/****************************************************************************/
+
+static const struct ddb_regmap octopus_map = {
+ .irq_base_i2c = 0,
+ .irq_base_idma = 8,
+ .irq_base_odma = 16,
+ .i2c = &octopus_i2c,
+ .i2c_buf = &octopus_i2c_buf,
+ .idma = &octopus_idma,
+ .idma_buf = &octopus_idma_buf,
+ .odma = &octopus_odma,
+ .odma_buf = &octopus_odma_buf,
+ .input = &octopus_input,
+ .output = &octopus_output,
+};
+
+/****************************************************************************/
+
+static const struct ddb_info ddb_none = {
+ .type = DDB_NONE,
+ .name = "unknown Digital Devices PCIe card, install newer driver",
+ .regmap = &octopus_map,
+};
+
+static const struct ddb_info ddb_octopus = {
+ .type = DDB_OCTOPUS,
+ .name = "Digital Devices Octopus DVB adapter",
+ .regmap = &octopus_map,
+ .port_num = 4,
+ .i2c_mask = 0x0f,
+};
+
+static const struct ddb_info ddb_octopusv3 = {
+ .type = DDB_OCTOPUS,
+ .name = "Digital Devices Octopus V3 DVB adapter",
+ .regmap = &octopus_map,
+ .port_num = 4,
+ .i2c_mask = 0x0f,
+};
+
+static const struct ddb_info ddb_octopus_le = {
+ .type = DDB_OCTOPUS,
+ .name = "Digital Devices Octopus LE DVB adapter",
+ .regmap = &octopus_map,
+ .port_num = 2,
+ .i2c_mask = 0x03,
+};
+
+static const struct ddb_info ddb_octopus_oem = {
+ .type = DDB_OCTOPUS,
+ .name = "Digital Devices Octopus OEM",
+ .regmap = &octopus_map,
+ .port_num = 4,
+ .i2c_mask = 0x0f,
+ .led_num = 1,
+ .fan_num = 1,
+ .temp_num = 1,
+ .temp_bus = 0,
+};
+
+static const struct ddb_info ddb_octopus_mini = {
+ .type = DDB_OCTOPUS,
+ .name = "Digital Devices Octopus Mini",
+ .regmap = &octopus_map,
+ .port_num = 4,
+ .i2c_mask = 0x0f,
+};
+
+static const struct ddb_info ddb_v6 = {
+ .type = DDB_OCTOPUS,
+ .name = "Digital Devices Cine S2 V6 DVB adapter",
+ .regmap = &octopus_map,
+ .port_num = 3,
+ .i2c_mask = 0x07,
+};
+
+static const struct ddb_info ddb_v6_5 = {
+ .type = DDB_OCTOPUS,
+ .name = "Digital Devices Cine S2 V6.5 DVB adapter",
+ .regmap = &octopus_map,
+ .port_num = 4,
+ .i2c_mask = 0x0f,
+};
+
+static const struct ddb_info ddb_v7 = {
+ .type = DDB_OCTOPUS,
+ .name = "Digital Devices Cine S2 V7 DVB adapter",
+ .regmap = &octopus_map,
+ .port_num = 4,
+ .i2c_mask = 0x0f,
+ .board_control = 2,
+ .board_control_2 = 4,
+ .ts_quirks = TS_QUIRK_REVERSED,
+};
+
+static const struct ddb_info ddb_v7a = {
+ .type = DDB_OCTOPUS,
+ .name = "Digital Devices Cine S2 V7 Advanced DVB adapter",
+ .regmap = &octopus_map,
+ .port_num = 4,
+ .i2c_mask = 0x0f,
+ .board_control = 2,
+ .board_control_2 = 4,
+ .ts_quirks = TS_QUIRK_REVERSED,
+};
+
+static const struct ddb_info ddb_ctv7 = {
+ .type = DDB_OCTOPUS,
+ .name = "Digital Devices Cine CT V7 DVB adapter",
+ .regmap = &octopus_map,
+ .port_num = 4,
+ .i2c_mask = 0x0f,
+ .board_control = 3,
+ .board_control_2 = 4,
+};
+
+static const struct ddb_info ddb_satixs2v3 = {
+ .type = DDB_OCTOPUS,
+ .name = "Mystique SaTiX-S2 V3 DVB adapter",
+ .regmap = &octopus_map,
+ .port_num = 3,
+ .i2c_mask = 0x07,
+};
+
+static const struct ddb_info ddb_ci = {
+ .type = DDB_OCTOPUS_CI,
+ .name = "Digital Devices Octopus CI",
+ .regmap = &octopus_map,
+ .port_num = 4,
+ .i2c_mask = 0x03,
+};
+
+static const struct ddb_info ddb_cis = {
+ .type = DDB_OCTOPUS_CI,
+ .name = "Digital Devices Octopus CI single",
+ .regmap = &octopus_map,
+ .port_num = 3,
+ .i2c_mask = 0x03,
+};
+
+static const struct ddb_info ddb_ci_s2_pro = {
+ .type = DDB_OCTOPUS_CI,
+ .name = "Digital Devices Octopus CI S2 Pro",
+ .regmap = &octopus_map,
+ .port_num = 4,
+ .i2c_mask = 0x01,
+ .board_control = 2,
+ .board_control_2 = 4,
+};
+
+static const struct ddb_info ddb_ci_s2_pro_a = {
+ .type = DDB_OCTOPUS_CI,
+ .name = "Digital Devices Octopus CI S2 Pro Advanced",
+ .regmap = &octopus_map,
+ .port_num = 4,
+ .i2c_mask = 0x01,
+ .board_control = 2,
+ .board_control_2 = 4,
+};
+
+static const struct ddb_info ddb_dvbct = {
+ .type = DDB_OCTOPUS,
+ .name = "Digital Devices DVBCT V6.1 DVB adapter",
+ .regmap = &octopus_map,
+ .port_num = 3,
+ .i2c_mask = 0x07,
+};
+
+/****************************************************************************/
+
+static const struct ddb_info ddb_ct2_8 = {
+ .type = DDB_OCTOPUS_MAX_CT,
+ .name = "Digital Devices MAX A8 CT2",
+ .regmap = &octopus_map,
+ .port_num = 4,
+ .i2c_mask = 0x0f,
+ .board_control = 0x0ff,
+ .board_control_2 = 0xf00,
+ .ts_quirks = TS_QUIRK_SERIAL,
+ .tempmon_irq = 24,
+};
+
+static const struct ddb_info ddb_c2t2_8 = {
+ .type = DDB_OCTOPUS_MAX_CT,
+ .name = "Digital Devices MAX A8 C2T2",
+ .regmap = &octopus_map,
+ .port_num = 4,
+ .i2c_mask = 0x0f,
+ .board_control = 0x0ff,
+ .board_control_2 = 0xf00,
+ .ts_quirks = TS_QUIRK_SERIAL,
+ .tempmon_irq = 24,
+};
+
+static const struct ddb_info ddb_isdbt_8 = {
+ .type = DDB_OCTOPUS_MAX_CT,
+ .name = "Digital Devices MAX A8 ISDBT",
+ .regmap = &octopus_map,
+ .port_num = 4,
+ .i2c_mask = 0x0f,
+ .board_control = 0x0ff,
+ .board_control_2 = 0xf00,
+ .ts_quirks = TS_QUIRK_SERIAL,
+ .tempmon_irq = 24,
+};
+
+static const struct ddb_info ddb_c2t2i_v0_8 = {
+ .type = DDB_OCTOPUS_MAX_CT,
+ .name = "Digital Devices MAX A8 C2T2I V0",
+ .regmap = &octopus_map,
+ .port_num = 4,
+ .i2c_mask = 0x0f,
+ .board_control = 0x0ff,
+ .board_control_2 = 0xf00,
+ .ts_quirks = TS_QUIRK_SERIAL | TS_QUIRK_ALT_OSC,
+ .tempmon_irq = 24,
+};
+
+static const struct ddb_info ddb_c2t2i_8 = {
+ .type = DDB_OCTOPUS_MAX_CT,
+ .name = "Digital Devices MAX A8 C2T2I",
+ .regmap = &octopus_map,
+ .port_num = 4,
+ .i2c_mask = 0x0f,
+ .board_control = 0x0ff,
+ .board_control_2 = 0xf00,
+ .ts_quirks = TS_QUIRK_SERIAL,
+ .tempmon_irq = 24,
+};
+
+/****************************************************************************/
+
+static const struct ddb_info ddb_s2_48 = {
+ .type = DDB_OCTOPUS_MAX,
+ .name = "Digital Devices MAX S8 4/8",
+ .regmap = &octopus_map,
+ .port_num = 4,
+ .i2c_mask = 0x01,
+ .board_control = 1,
+ .tempmon_irq = 24,
+};
+
+static const struct ddb_info ddb_s2x_48 = {
+ .type = DDB_OCTOPUS_MCI,
+ .name = "Digital Devices MAX SX8",
+ .regmap = &octopus_map,
+ .port_num = 4,
+ .i2c_mask = 0x00,
+ .tempmon_irq = 24,
+ .mci_ports = 4,
+ .mci_type = 0,
+};
+
+/****************************************************************************/
+/****************************************************************************/
+/****************************************************************************/
+
+#define DDB_DEVID(_device, _subdevice, _info) { \
+ .vendor = DDVID, \
+ .device = _device, \
+ .subvendor = DDVID, \
+ .subdevice = _subdevice, \
+ .info = &_info }
+
+static const struct ddb_device_id ddb_device_ids[] = {
+ /* PCIe devices */
+ DDB_DEVID(0x0002, 0x0001, ddb_octopus),
+ DDB_DEVID(0x0003, 0x0001, ddb_octopus),
+ DDB_DEVID(0x0005, 0x0004, ddb_octopusv3),
+ DDB_DEVID(0x0003, 0x0002, ddb_octopus_le),
+ DDB_DEVID(0x0003, 0x0003, ddb_octopus_oem),
+ DDB_DEVID(0x0003, 0x0010, ddb_octopus_mini),
+ DDB_DEVID(0x0005, 0x0011, ddb_octopus_mini),
+ DDB_DEVID(0x0003, 0x0020, ddb_v6),
+ DDB_DEVID(0x0003, 0x0021, ddb_v6_5),
+ DDB_DEVID(0x0006, 0x0022, ddb_v7),
+ DDB_DEVID(0x0006, 0x0024, ddb_v7a),
+ DDB_DEVID(0x0003, 0x0030, ddb_dvbct),
+ DDB_DEVID(0x0003, 0xdb03, ddb_satixs2v3),
+ DDB_DEVID(0x0006, 0x0031, ddb_ctv7),
+ DDB_DEVID(0x0006, 0x0032, ddb_ctv7),
+ DDB_DEVID(0x0006, 0x0033, ddb_ctv7),
+ DDB_DEVID(0x0007, 0x0023, ddb_s2_48),
+ DDB_DEVID(0x0008, 0x0034, ddb_ct2_8),
+ DDB_DEVID(0x0008, 0x0035, ddb_c2t2_8),
+ DDB_DEVID(0x0008, 0x0036, ddb_isdbt_8),
+ DDB_DEVID(0x0008, 0x0037, ddb_c2t2i_v0_8),
+ DDB_DEVID(0x0008, 0x0038, ddb_c2t2i_8),
+ DDB_DEVID(0x0009, 0x0025, ddb_s2x_48),
+ DDB_DEVID(0x0006, 0x0039, ddb_ctv7),
+ DDB_DEVID(0x0011, 0x0040, ddb_ci),
+ DDB_DEVID(0x0011, 0x0041, ddb_cis),
+ DDB_DEVID(0x0012, 0x0042, ddb_ci),
+ DDB_DEVID(0x0013, 0x0043, ddb_ci_s2_pro),
+ DDB_DEVID(0x0013, 0x0044, ddb_ci_s2_pro_a),
+};
+
+/****************************************************************************/
+
+const struct ddb_info *get_ddb_info(u16 vendor, u16 device,
+ u16 subvendor, u16 subdevice)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(ddb_device_ids); i++) {
+ const struct ddb_device_id *id = &ddb_device_ids[i];
+
+ if (vendor == id->vendor &&
+ device == id->device &&
+ subvendor == id->subvendor &&
+ (subdevice == id->subdevice ||
+ id->subdevice == 0xffff))
+ return id->info;
+ }
+
+ return &ddb_none;
+}
diff --git a/drivers/media/pci/ddbridge/ddbridge-hw.h b/drivers/media/pci/ddbridge/ddbridge-hw.h
new file mode 100644
index 000000000..934f296f4
--- /dev/null
+++ b/drivers/media/pci/ddbridge/ddbridge-hw.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * ddbridge-hw.h: Digital Devices bridge hardware maps
+ *
+ * Copyright (C) 2010-2017 Digital Devices GmbH
+ * Ralph Metzler <rjkm@metzlerbros.de>
+ * Marcus Metzler <mocm@metzlerbros.de>
+ */
+
+#ifndef _DDBRIDGE_HW_H_
+#define _DDBRIDGE_HW_H_
+
+#include "ddbridge.h"
+
+/******************************************************************************/
+
+#define DDVID 0xdd01 /* Digital Devices Vendor ID */
+
+/******************************************************************************/
+
+struct ddb_device_id {
+ u16 vendor;
+ u16 device;
+ u16 subvendor;
+ u16 subdevice;
+ const struct ddb_info *info;
+};
+
+/******************************************************************************/
+
+const struct ddb_info *get_ddb_info(u16 vendor, u16 device,
+ u16 subvendor, u16 subdevice);
+
+#endif /* _DDBRIDGE_HW_H_ */
diff --git a/drivers/media/pci/ddbridge/ddbridge-i2c.c b/drivers/media/pci/ddbridge/ddbridge-i2c.c
new file mode 100644
index 000000000..c894be180
--- /dev/null
+++ b/drivers/media/pci/ddbridge/ddbridge-i2c.c
@@ -0,0 +1,225 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ddbridge-i2c.c: Digital Devices bridge i2c driver
+ *
+ * Copyright (C) 2010-2017 Digital Devices GmbH
+ * Ralph Metzler <rjkm@metzlerbros.de>
+ * Marcus Metzler <mocm@metzlerbros.de>
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/poll.h>
+#include <linux/io.h>
+#include <linux/pci.h>
+#include <linux/pci_ids.h>
+#include <linux/timer.h>
+#include <linux/i2c.h>
+#include <linux/swab.h>
+#include <linux/vmalloc.h>
+
+#include "ddbridge.h"
+#include "ddbridge-i2c.h"
+#include "ddbridge-regs.h"
+#include "ddbridge-io.h"
+
+/******************************************************************************/
+
+static int ddb_i2c_cmd(struct ddb_i2c *i2c, u32 adr, u32 cmd)
+{
+ struct ddb *dev = i2c->dev;
+ unsigned long stat;
+ u32 val;
+
+ ddbwritel(dev, (adr << 9) | cmd, i2c->regs + I2C_COMMAND);
+ stat = wait_for_completion_timeout(&i2c->completion, HZ);
+ val = ddbreadl(dev, i2c->regs + I2C_COMMAND);
+ if (stat == 0) {
+ dev_err(dev->dev, "I2C timeout, card %d, port %d, link %u\n",
+ dev->nr, i2c->nr, i2c->link);
+ {
+ u32 istat = ddbreadl(dev, INTERRUPT_STATUS);
+
+ dev_err(dev->dev, "DDBridge IRS %08x\n", istat);
+ if (i2c->link) {
+ u32 listat = ddbreadl(dev,
+ DDB_LINK_TAG(i2c->link) |
+ INTERRUPT_STATUS);
+
+ dev_err(dev->dev, "DDBridge link %u IRS %08x\n",
+ i2c->link, listat);
+ }
+ if (istat & 1) {
+ ddbwritel(dev, istat & 1, INTERRUPT_ACK);
+ } else {
+ u32 mon = ddbreadl(dev,
+ i2c->regs + I2C_MONITOR);
+
+ dev_err(dev->dev, "I2C cmd=%08x mon=%08x\n",
+ val, mon);
+ }
+ }
+ return -EIO;
+ }
+ val &= 0x70000;
+ if (val == 0x20000)
+ dev_err(dev->dev, "I2C bus error\n");
+ if (val)
+ return -EIO;
+ return 0;
+}
+
+static int ddb_i2c_master_xfer(struct i2c_adapter *adapter,
+ struct i2c_msg msg[], int num)
+{
+ struct ddb_i2c *i2c = (struct ddb_i2c *)i2c_get_adapdata(adapter);
+ struct ddb *dev = i2c->dev;
+ u8 addr = 0;
+
+ addr = msg[0].addr;
+ if (msg[0].len > i2c->bsize)
+ return -EIO;
+ switch (num) {
+ case 1:
+ if (msg[0].flags & I2C_M_RD) {
+ ddbwritel(dev, msg[0].len << 16,
+ i2c->regs + I2C_TASKLENGTH);
+ if (ddb_i2c_cmd(i2c, addr, 3))
+ break;
+ ddbcpyfrom(dev, msg[0].buf,
+ i2c->rbuf, msg[0].len);
+ return num;
+ }
+ ddbcpyto(dev, i2c->wbuf, msg[0].buf, msg[0].len);
+ ddbwritel(dev, msg[0].len, i2c->regs + I2C_TASKLENGTH);
+ if (ddb_i2c_cmd(i2c, addr, 2))
+ break;
+ return num;
+ case 2:
+ if ((msg[0].flags & I2C_M_RD) == I2C_M_RD)
+ break;
+ if ((msg[1].flags & I2C_M_RD) != I2C_M_RD)
+ break;
+ if (msg[1].len > i2c->bsize)
+ break;
+ ddbcpyto(dev, i2c->wbuf, msg[0].buf, msg[0].len);
+ ddbwritel(dev, msg[0].len | (msg[1].len << 16),
+ i2c->regs + I2C_TASKLENGTH);
+ if (ddb_i2c_cmd(i2c, addr, 1))
+ break;
+ ddbcpyfrom(dev, msg[1].buf,
+ i2c->rbuf,
+ msg[1].len);
+ return num;
+ default:
+ break;
+ }
+ return -EIO;
+}
+
+static u32 ddb_i2c_functionality(struct i2c_adapter *adap)
+{
+ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
+}
+
+static const struct i2c_algorithm ddb_i2c_algo = {
+ .master_xfer = ddb_i2c_master_xfer,
+ .functionality = ddb_i2c_functionality,
+};
+
+void ddb_i2c_release(struct ddb *dev)
+{
+ int i;
+ struct ddb_i2c *i2c;
+
+ for (i = 0; i < dev->i2c_num; i++) {
+ i2c = &dev->i2c[i];
+ i2c_del_adapter(&i2c->adap);
+ }
+}
+
+static void i2c_handler(void *priv)
+{
+ struct ddb_i2c *i2c = (struct ddb_i2c *)priv;
+
+ complete(&i2c->completion);
+}
+
+static int ddb_i2c_add(struct ddb *dev, struct ddb_i2c *i2c,
+ const struct ddb_regmap *regmap, int link,
+ int i, int num)
+{
+ struct i2c_adapter *adap;
+
+ i2c->nr = i;
+ i2c->dev = dev;
+ i2c->link = link;
+ i2c->bsize = regmap->i2c_buf->size;
+ i2c->wbuf = DDB_LINK_TAG(link) |
+ (regmap->i2c_buf->base + i2c->bsize * i);
+ i2c->rbuf = i2c->wbuf; /* + i2c->bsize / 2 */
+ i2c->regs = DDB_LINK_TAG(link) |
+ (regmap->i2c->base + regmap->i2c->size * i);
+ ddbwritel(dev, I2C_SPEED_100, i2c->regs + I2C_TIMING);
+ ddbwritel(dev, ((i2c->rbuf & 0xffff) << 16) | (i2c->wbuf & 0xffff),
+ i2c->regs + I2C_TASKADDRESS);
+ init_completion(&i2c->completion);
+
+ adap = &i2c->adap;
+ i2c_set_adapdata(adap, i2c);
+#ifdef I2C_ADAP_CLASS_TV_DIGITAL
+ adap->class = I2C_ADAP_CLASS_TV_DIGITAL | I2C_CLASS_TV_ANALOG;
+#else
+#ifdef I2C_CLASS_TV_ANALOG
+ adap->class = I2C_CLASS_TV_ANALOG;
+#endif
+#endif
+ snprintf(adap->name, I2C_NAME_SIZE, "ddbridge_%02x.%x.%x",
+ dev->nr, i2c->link, i);
+ adap->algo = &ddb_i2c_algo;
+ adap->algo_data = (void *)i2c;
+ adap->dev.parent = dev->dev;
+ return i2c_add_adapter(adap);
+}
+
+int ddb_i2c_init(struct ddb *dev)
+{
+ int stat = 0;
+ u32 i, j, num = 0, l, base;
+ struct ddb_i2c *i2c;
+ struct i2c_adapter *adap;
+ const struct ddb_regmap *regmap;
+
+ for (l = 0; l < DDB_MAX_LINK; l++) {
+ if (!dev->link[l].info)
+ continue;
+ regmap = dev->link[l].info->regmap;
+ if (!regmap || !regmap->i2c)
+ continue;
+ base = regmap->irq_base_i2c;
+ for (i = 0; i < regmap->i2c->num; i++) {
+ if (!(dev->link[l].info->i2c_mask & (1 << i)))
+ continue;
+ i2c = &dev->i2c[num];
+ ddb_irq_set(dev, l, i + base, i2c_handler, i2c);
+ stat = ddb_i2c_add(dev, i2c, regmap, l, i, num);
+ if (stat)
+ break;
+ num++;
+ }
+ }
+ if (stat) {
+ for (j = 0; j < num; j++) {
+ i2c = &dev->i2c[j];
+ adap = &i2c->adap;
+ i2c_del_adapter(adap);
+ }
+ } else {
+ dev->i2c_num = num;
+ }
+
+ return stat;
+}
diff --git a/drivers/media/pci/ddbridge/ddbridge-i2c.h b/drivers/media/pci/ddbridge/ddbridge-i2c.h
new file mode 100644
index 000000000..48555d41a
--- /dev/null
+++ b/drivers/media/pci/ddbridge/ddbridge-i2c.h
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * ddbridge-i2c.h: Digital Devices bridge i2c driver
+ *
+ * Copyright (C) 2010-2017 Digital Devices GmbH
+ * Ralph Metzler <rjkm@metzlerbros.de>
+ * Marcus Metzler <mocm@metzlerbros.de>
+ */
+
+#ifndef __DDBRIDGE_I2C_H__
+#define __DDBRIDGE_I2C_H__
+
+#include <linux/i2c.h>
+
+#include "ddbridge.h"
+
+/******************************************************************************/
+
+void ddb_i2c_release(struct ddb *dev);
+int ddb_i2c_init(struct ddb *dev);
+
+/******************************************************************************/
+
+static int __maybe_unused i2c_io(struct i2c_adapter *adapter, u8 adr,
+ u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen)
+{
+ struct i2c_msg msgs[2] = { { .addr = adr, .flags = 0,
+ .buf = wbuf, .len = wlen },
+ { .addr = adr, .flags = I2C_M_RD,
+ .buf = rbuf, .len = rlen } };
+
+ return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1;
+}
+
+static int __maybe_unused i2c_write(struct i2c_adapter *adap, u8 adr,
+ u8 *data, int len)
+{
+ struct i2c_msg msg = { .addr = adr, .flags = 0,
+ .buf = data, .len = len };
+
+ return (i2c_transfer(adap, &msg, 1) == 1) ? 0 : -1;
+}
+
+static int __maybe_unused i2c_read(struct i2c_adapter *adapter, u8 adr, u8 *val)
+{
+ struct i2c_msg msgs[1] = { { .addr = adr, .flags = I2C_M_RD,
+ .buf = val, .len = 1 } };
+
+ return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1;
+}
+
+static int __maybe_unused i2c_read_regs(struct i2c_adapter *adapter,
+ u8 adr, u8 reg, u8 *val, u8 len)
+{
+ struct i2c_msg msgs[2] = { { .addr = adr, .flags = 0,
+ .buf = &reg, .len = 1 },
+ { .addr = adr, .flags = I2C_M_RD,
+ .buf = val, .len = len } };
+
+ return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1;
+}
+
+static int __maybe_unused i2c_read_regs16(struct i2c_adapter *adapter,
+ u8 adr, u16 reg, u8 *val, u8 len)
+{
+ u8 msg[2] = { reg >> 8, reg & 0xff };
+ struct i2c_msg msgs[2] = { { .addr = adr, .flags = 0,
+ .buf = msg, .len = 2 },
+ { .addr = adr, .flags = I2C_M_RD,
+ .buf = val, .len = len } };
+
+ return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1;
+}
+
+static int __maybe_unused i2c_write_reg16(struct i2c_adapter *adap,
+ u8 adr, u16 reg, u8 val)
+{
+ u8 msg[3] = { reg >> 8, reg & 0xff, val };
+
+ return i2c_write(adap, adr, msg, 3);
+}
+
+static int __maybe_unused i2c_write_reg(struct i2c_adapter *adap,
+ u8 adr, u8 reg, u8 val)
+{
+ u8 msg[2] = { reg, val };
+
+ return i2c_write(adap, adr, msg, 2);
+}
+
+static int __maybe_unused i2c_read_reg16(struct i2c_adapter *adapter,
+ u8 adr, u16 reg, u8 *val)
+{
+ return i2c_read_regs16(adapter, adr, reg, val, 1);
+}
+
+static int __maybe_unused i2c_read_reg(struct i2c_adapter *adapter,
+ u8 adr, u8 reg, u8 *val)
+{
+ return i2c_read_regs(adapter, adr, reg, val, 1);
+}
+
+#endif /* __DDBRIDGE_I2C_H__ */
diff --git a/drivers/media/pci/ddbridge/ddbridge-io.h b/drivers/media/pci/ddbridge/ddbridge-io.h
new file mode 100644
index 000000000..991246cec
--- /dev/null
+++ b/drivers/media/pci/ddbridge/ddbridge-io.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * ddbridge-io.h: Digital Devices bridge I/O inline functions
+ *
+ * Copyright (C) 2010-2017 Digital Devices GmbH
+ * Ralph Metzler <rjkm@metzlerbros.de>
+ * Marcus Metzler <mocm@metzlerbros.de>
+ */
+
+#ifndef __DDBRIDGE_IO_H__
+#define __DDBRIDGE_IO_H__
+
+#include <linux/io.h>
+
+#include "ddbridge.h"
+
+/******************************************************************************/
+
+static inline u32 ddblreadl(struct ddb_link *link, u32 adr)
+{
+ return readl(link->dev->regs + adr);
+}
+
+static inline void ddblwritel(struct ddb_link *link, u32 val, u32 adr)
+{
+ writel(val, link->dev->regs + adr);
+}
+
+static inline u32 ddbreadl(struct ddb *dev, u32 adr)
+{
+ return readl(dev->regs + adr);
+}
+
+static inline void ddbwritel(struct ddb *dev, u32 val, u32 adr)
+{
+ writel(val, dev->regs + adr);
+}
+
+static inline void ddbcpyto(struct ddb *dev, u32 adr, void *src, long count)
+{
+ memcpy_toio(dev->regs + adr, src, count);
+}
+
+static inline void ddbcpyfrom(struct ddb *dev, void *dst, u32 adr, long count)
+{
+ memcpy_fromio(dst, dev->regs + adr, count);
+}
+
+static inline u32 safe_ddbreadl(struct ddb *dev, u32 adr)
+{
+ u32 val = ddbreadl(dev, adr);
+
+ /* (ddb)readl returns (uint)-1 (all bits set) on failure, catch that */
+ if (val == ~0) {
+ dev_err(&dev->pdev->dev, "ddbreadl failure, adr=%08x\n", adr);
+ return 0;
+ }
+
+ return val;
+}
+
+#endif /* __DDBRIDGE_IO_H__ */
diff --git a/drivers/media/pci/ddbridge/ddbridge-main.c b/drivers/media/pci/ddbridge/ddbridge-main.c
new file mode 100644
index 000000000..91733ab9f
--- /dev/null
+++ b/drivers/media/pci/ddbridge/ddbridge-main.c
@@ -0,0 +1,313 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ddbridge.c: Digital Devices PCIe bridge driver
+ *
+ * Copyright (C) 2010-2017 Digital Devices GmbH
+ * Ralph Metzler <rjkm@metzlerbros.de>
+ * Marcus Metzler <mocm@metzlerbros.de>
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/poll.h>
+#include <linux/io.h>
+#include <linux/pci.h>
+#include <linux/pci_ids.h>
+#include <linux/timer.h>
+#include <linux/i2c.h>
+#include <linux/swab.h>
+#include <linux/vmalloc.h>
+
+#include "ddbridge.h"
+#include "ddbridge-i2c.h"
+#include "ddbridge-regs.h"
+#include "ddbridge-hw.h"
+#include "ddbridge-io.h"
+
+/****************************************************************************/
+/* module parameters */
+
+#ifdef CONFIG_PCI_MSI
+#ifdef CONFIG_DVB_DDBRIDGE_MSIENABLE
+static int msi = 1;
+#else
+static int msi;
+#endif
+module_param(msi, int, 0444);
+#ifdef CONFIG_DVB_DDBRIDGE_MSIENABLE
+MODULE_PARM_DESC(msi, "Control MSI interrupts: 0-disable, 1-enable (default)");
+#else
+MODULE_PARM_DESC(msi, "Control MSI interrupts: 0-disable (default), 1-enable");
+#endif
+#endif
+
+/****************************************************************************/
+/****************************************************************************/
+/****************************************************************************/
+
+static void ddb_irq_disable(struct ddb *dev)
+{
+ ddbwritel(dev, 0, INTERRUPT_ENABLE);
+ ddbwritel(dev, 0, MSI1_ENABLE);
+}
+
+static void ddb_msi_exit(struct ddb *dev)
+{
+#ifdef CONFIG_PCI_MSI
+ if (dev->msi)
+ pci_free_irq_vectors(dev->pdev);
+#endif
+}
+
+static void ddb_irq_exit(struct ddb *dev)
+{
+ ddb_irq_disable(dev);
+ if (dev->msi == 2)
+ free_irq(pci_irq_vector(dev->pdev, 1), dev);
+ free_irq(pci_irq_vector(dev->pdev, 0), dev);
+}
+
+static void ddb_remove(struct pci_dev *pdev)
+{
+ struct ddb *dev = (struct ddb *)pci_get_drvdata(pdev);
+
+ ddb_device_destroy(dev);
+ ddb_ports_detach(dev);
+ ddb_i2c_release(dev);
+
+ ddb_irq_exit(dev);
+ ddb_msi_exit(dev);
+ ddb_ports_release(dev);
+ ddb_buffers_free(dev);
+
+ ddb_unmap(dev);
+ pci_set_drvdata(pdev, NULL);
+ pci_disable_device(pdev);
+}
+
+#ifdef CONFIG_PCI_MSI
+static void ddb_irq_msi(struct ddb *dev, int nr)
+{
+ int stat;
+
+ if (msi && pci_msi_enabled()) {
+ stat = pci_alloc_irq_vectors(dev->pdev, 1, nr,
+ PCI_IRQ_MSI | PCI_IRQ_MSIX);
+ if (stat >= 1) {
+ dev->msi = stat;
+ dev_info(dev->dev, "using %d MSI interrupt(s)\n",
+ dev->msi);
+ } else {
+ dev_info(dev->dev, "MSI not available.\n");
+ }
+ }
+}
+#endif
+
+static int ddb_irq_init(struct ddb *dev)
+{
+ int stat;
+ int irq_flag = IRQF_SHARED;
+
+ ddbwritel(dev, 0x00000000, INTERRUPT_ENABLE);
+ ddbwritel(dev, 0x00000000, MSI1_ENABLE);
+ ddbwritel(dev, 0x00000000, MSI2_ENABLE);
+ ddbwritel(dev, 0x00000000, MSI3_ENABLE);
+ ddbwritel(dev, 0x00000000, MSI4_ENABLE);
+ ddbwritel(dev, 0x00000000, MSI5_ENABLE);
+ ddbwritel(dev, 0x00000000, MSI6_ENABLE);
+ ddbwritel(dev, 0x00000000, MSI7_ENABLE);
+
+#ifdef CONFIG_PCI_MSI
+ ddb_irq_msi(dev, 2);
+
+ if (dev->msi)
+ irq_flag = 0;
+ if (dev->msi == 2) {
+ stat = request_irq(pci_irq_vector(dev->pdev, 0),
+ ddb_irq_handler0, irq_flag, "ddbridge",
+ (void *)dev);
+ if (stat < 0)
+ return stat;
+ stat = request_irq(pci_irq_vector(dev->pdev, 1),
+ ddb_irq_handler1, irq_flag, "ddbridge",
+ (void *)dev);
+ if (stat < 0) {
+ free_irq(pci_irq_vector(dev->pdev, 0), dev);
+ return stat;
+ }
+ } else
+#endif
+ {
+ stat = request_irq(pci_irq_vector(dev->pdev, 0),
+ ddb_irq_handler, irq_flag, "ddbridge",
+ (void *)dev);
+ if (stat < 0)
+ return stat;
+ }
+ if (dev->msi == 2) {
+ ddbwritel(dev, 0x0fffff00, INTERRUPT_ENABLE);
+ ddbwritel(dev, 0x0000000f, MSI1_ENABLE);
+ } else {
+ ddbwritel(dev, 0x0fffff0f, INTERRUPT_ENABLE);
+ ddbwritel(dev, 0x00000000, MSI1_ENABLE);
+ }
+ return stat;
+}
+
+static int ddb_probe(struct pci_dev *pdev,
+ const struct pci_device_id *id)
+{
+ struct ddb *dev;
+ int stat = 0;
+
+ if (pci_enable_device(pdev) < 0)
+ return -ENODEV;
+
+ pci_set_master(pdev);
+
+ if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)))
+ if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)))
+ return -ENODEV;
+
+ dev = vzalloc(sizeof(*dev));
+ if (!dev)
+ return -ENOMEM;
+
+ mutex_init(&dev->mutex);
+ dev->has_dma = 1;
+ dev->pdev = pdev;
+ dev->dev = &pdev->dev;
+ pci_set_drvdata(pdev, dev);
+
+ dev->link[0].ids.vendor = id->vendor;
+ dev->link[0].ids.device = id->device;
+ dev->link[0].ids.subvendor = id->subvendor;
+ dev->link[0].ids.subdevice = pdev->subsystem_device;
+ dev->link[0].ids.devid = (id->device << 16) | id->vendor;
+
+ dev->link[0].dev = dev;
+ dev->link[0].info = get_ddb_info(id->vendor, id->device,
+ id->subvendor, pdev->subsystem_device);
+
+ dev_info(&pdev->dev, "detected %s\n", dev->link[0].info->name);
+
+ dev->regs_len = pci_resource_len(dev->pdev, 0);
+ dev->regs = ioremap(pci_resource_start(dev->pdev, 0),
+ pci_resource_len(dev->pdev, 0));
+
+ if (!dev->regs) {
+ dev_err(&pdev->dev, "not enough memory for register map\n");
+ stat = -ENOMEM;
+ goto fail;
+ }
+ if (ddbreadl(dev, 0) == 0xffffffff) {
+ dev_err(&pdev->dev, "cannot read registers\n");
+ stat = -ENODEV;
+ goto fail;
+ }
+
+ dev->link[0].ids.hwid = ddbreadl(dev, 0);
+ dev->link[0].ids.regmapid = ddbreadl(dev, 4);
+
+ dev_info(&pdev->dev, "HW %08x REGMAP %08x\n",
+ dev->link[0].ids.hwid, dev->link[0].ids.regmapid);
+
+ ddbwritel(dev, 0, DMA_BASE_READ);
+ ddbwritel(dev, 0, DMA_BASE_WRITE);
+
+ stat = ddb_irq_init(dev);
+ if (stat < 0)
+ goto fail0;
+
+ if (ddb_init(dev) == 0)
+ return 0;
+
+ ddb_irq_exit(dev);
+fail0:
+ dev_err(&pdev->dev, "fail0\n");
+ ddb_msi_exit(dev);
+fail:
+ dev_err(&pdev->dev, "fail\n");
+
+ ddb_unmap(dev);
+ pci_set_drvdata(pdev, NULL);
+ pci_disable_device(pdev);
+ return -1;
+}
+
+/****************************************************************************/
+/****************************************************************************/
+/****************************************************************************/
+
+#define DDB_DEVICE_ANY(_device) \
+ { PCI_DEVICE_SUB(DDVID, _device, DDVID, PCI_ANY_ID) }
+
+static const struct pci_device_id ddb_id_table[] = {
+ DDB_DEVICE_ANY(0x0002),
+ DDB_DEVICE_ANY(0x0003),
+ DDB_DEVICE_ANY(0x0005),
+ DDB_DEVICE_ANY(0x0006),
+ DDB_DEVICE_ANY(0x0007),
+ DDB_DEVICE_ANY(0x0008),
+ DDB_DEVICE_ANY(0x0009),
+ DDB_DEVICE_ANY(0x0011),
+ DDB_DEVICE_ANY(0x0012),
+ DDB_DEVICE_ANY(0x0013),
+ DDB_DEVICE_ANY(0x0201),
+ DDB_DEVICE_ANY(0x0203),
+ DDB_DEVICE_ANY(0x0210),
+ DDB_DEVICE_ANY(0x0220),
+ DDB_DEVICE_ANY(0x0320),
+ DDB_DEVICE_ANY(0x0321),
+ DDB_DEVICE_ANY(0x0322),
+ DDB_DEVICE_ANY(0x0323),
+ DDB_DEVICE_ANY(0x0328),
+ DDB_DEVICE_ANY(0x0329),
+ {0}
+};
+
+MODULE_DEVICE_TABLE(pci, ddb_id_table);
+
+static struct pci_driver ddb_pci_driver = {
+ .name = "ddbridge",
+ .id_table = ddb_id_table,
+ .probe = ddb_probe,
+ .remove = ddb_remove,
+};
+
+static __init int module_init_ddbridge(void)
+{
+ int stat;
+
+ pr_info("Digital Devices PCIE bridge driver "
+ DDBRIDGE_VERSION
+ ", Copyright (C) 2010-17 Digital Devices GmbH\n");
+ stat = ddb_init_ddbridge();
+ if (stat < 0)
+ return stat;
+ stat = pci_register_driver(&ddb_pci_driver);
+ if (stat < 0)
+ ddb_exit_ddbridge(0, stat);
+
+ return stat;
+}
+
+static __exit void module_exit_ddbridge(void)
+{
+ pci_unregister_driver(&ddb_pci_driver);
+ ddb_exit_ddbridge(0, 0);
+}
+
+module_init(module_init_ddbridge);
+module_exit(module_exit_ddbridge);
+
+MODULE_DESCRIPTION("Digital Devices PCIe Bridge");
+MODULE_AUTHOR("Ralph and Marcus Metzler, Metzler Brothers Systementwicklung GbR");
+MODULE_LICENSE("GPL v2");
+MODULE_VERSION(DDBRIDGE_VERSION);
diff --git a/drivers/media/pci/ddbridge/ddbridge-max.c b/drivers/media/pci/ddbridge/ddbridge-max.c
new file mode 100644
index 000000000..0582b86bb
--- /dev/null
+++ b/drivers/media/pci/ddbridge/ddbridge-max.c
@@ -0,0 +1,495 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ddbridge-max.c: Digital Devices bridge MAX card support
+ *
+ * Copyright (C) 2010-2017 Digital Devices GmbH
+ * Ralph Metzler <rjkm@metzlerbros.de>
+ * Marcus Metzler <mocm@metzlerbros.de>
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/poll.h>
+#include <linux/io.h>
+#include <linux/pci.h>
+#include <linux/pci_ids.h>
+#include <linux/timer.h>
+#include <linux/i2c.h>
+#include <linux/swab.h>
+#include <linux/vmalloc.h>
+
+#include "ddbridge.h"
+#include "ddbridge-regs.h"
+#include "ddbridge-io.h"
+#include "ddbridge-mci.h"
+
+#include "ddbridge-max.h"
+#include "mxl5xx.h"
+
+/******************************************************************************/
+
+/* MaxS4/8 related modparams */
+static int fmode;
+module_param(fmode, int, 0444);
+MODULE_PARM_DESC(fmode, "frontend emulation mode");
+
+static int fmode_sat = -1;
+module_param(fmode_sat, int, 0444);
+MODULE_PARM_DESC(fmode_sat, "set frontend emulation mode sat");
+
+static int old_quattro;
+module_param(old_quattro, int, 0444);
+MODULE_PARM_DESC(old_quattro, "old quattro LNB input order ");
+
+/******************************************************************************/
+
+static int lnb_command(struct ddb *dev, u32 link, u32 lnb, u32 cmd)
+{
+ u32 c, v = 0, tag = DDB_LINK_TAG(link);
+
+ v = LNB_TONE & (dev->link[link].lnb.tone << (15 - lnb));
+ ddbwritel(dev, cmd | v, tag | LNB_CONTROL(lnb));
+ for (c = 0; c < 10; c++) {
+ v = ddbreadl(dev, tag | LNB_CONTROL(lnb));
+ if ((v & LNB_BUSY) == 0)
+ break;
+ msleep(20);
+ }
+ if (c == 10)
+ dev_info(dev->dev, "%s lnb = %08x cmd = %08x\n",
+ __func__, lnb, cmd);
+ return 0;
+}
+
+static int max_send_master_cmd(struct dvb_frontend *fe,
+ struct dvb_diseqc_master_cmd *cmd)
+{
+ struct ddb_input *input = fe->sec_priv;
+ struct ddb_port *port = input->port;
+ struct ddb *dev = port->dev;
+ struct ddb_dvb *dvb = &port->dvb[input->nr & 1];
+ u32 tag = DDB_LINK_TAG(port->lnr);
+ int i;
+ u32 fmode = dev->link[port->lnr].lnb.fmode;
+
+ if (fmode == 2 || fmode == 1)
+ return 0;
+ if (dvb->diseqc_send_master_cmd)
+ dvb->diseqc_send_master_cmd(fe, cmd);
+
+ mutex_lock(&dev->link[port->lnr].lnb.lock);
+ ddbwritel(dev, 0, tag | LNB_BUF_LEVEL(dvb->input));
+ for (i = 0; i < cmd->msg_len; i++)
+ ddbwritel(dev, cmd->msg[i], tag | LNB_BUF_WRITE(dvb->input));
+ lnb_command(dev, port->lnr, dvb->input, LNB_CMD_DISEQC);
+ mutex_unlock(&dev->link[port->lnr].lnb.lock);
+ return 0;
+}
+
+static int lnb_send_diseqc(struct ddb *dev, u32 link, u32 input,
+ struct dvb_diseqc_master_cmd *cmd)
+{
+ u32 tag = DDB_LINK_TAG(link);
+ int i;
+
+ ddbwritel(dev, 0, tag | LNB_BUF_LEVEL(input));
+ for (i = 0; i < cmd->msg_len; i++)
+ ddbwritel(dev, cmd->msg[i], tag | LNB_BUF_WRITE(input));
+ lnb_command(dev, link, input, LNB_CMD_DISEQC);
+ return 0;
+}
+
+static int lnb_set_sat(struct ddb *dev, u32 link, u32 input, u32 sat, u32 band,
+ u32 hor)
+{
+ struct dvb_diseqc_master_cmd cmd = {
+ .msg = {0xe0, 0x10, 0x38, 0xf0, 0x00, 0x00},
+ .msg_len = 4
+ };
+ cmd.msg[3] = 0xf0 | (((sat << 2) & 0x0c) | (band ? 1 : 0) |
+ (hor ? 2 : 0));
+ return lnb_send_diseqc(dev, link, input, &cmd);
+}
+
+static int lnb_set_tone(struct ddb *dev, u32 link, u32 input,
+ enum fe_sec_tone_mode tone)
+{
+ int s = 0;
+ u32 mask = (1ULL << input);
+
+ switch (tone) {
+ case SEC_TONE_OFF:
+ if (!(dev->link[link].lnb.tone & mask))
+ return 0;
+ dev->link[link].lnb.tone &= ~(1ULL << input);
+ break;
+ case SEC_TONE_ON:
+ if (dev->link[link].lnb.tone & mask)
+ return 0;
+ dev->link[link].lnb.tone |= (1ULL << input);
+ break;
+ default:
+ s = -EINVAL;
+ break;
+ }
+ if (!s)
+ s = lnb_command(dev, link, input, LNB_CMD_NOP);
+ return s;
+}
+
+static int lnb_set_voltage(struct ddb *dev, u32 link, u32 input,
+ enum fe_sec_voltage voltage)
+{
+ int s = 0;
+
+ if (dev->link[link].lnb.oldvoltage[input] == voltage)
+ return 0;
+ switch (voltage) {
+ case SEC_VOLTAGE_OFF:
+ if (dev->link[link].lnb.voltage[input])
+ return 0;
+ lnb_command(dev, link, input, LNB_CMD_OFF);
+ break;
+ case SEC_VOLTAGE_13:
+ lnb_command(dev, link, input, LNB_CMD_LOW);
+ break;
+ case SEC_VOLTAGE_18:
+ lnb_command(dev, link, input, LNB_CMD_HIGH);
+ break;
+ default:
+ s = -EINVAL;
+ break;
+ }
+ dev->link[link].lnb.oldvoltage[input] = voltage;
+ return s;
+}
+
+static int max_set_input_unlocked(struct dvb_frontend *fe, int in)
+{
+ struct ddb_input *input = fe->sec_priv;
+ struct ddb_port *port = input->port;
+ struct ddb *dev = port->dev;
+ struct ddb_dvb *dvb = &port->dvb[input->nr & 1];
+ int res = 0;
+
+ if (in > 3)
+ return -EINVAL;
+ if (dvb->input != in) {
+ u32 bit = (1ULL << input->nr);
+ u32 obit =
+ dev->link[port->lnr].lnb.voltage[dvb->input & 3] & bit;
+
+ dev->link[port->lnr].lnb.voltage[dvb->input & 3] &= ~bit;
+ dvb->input = in;
+ dev->link[port->lnr].lnb.voltage[dvb->input & 3] |= obit;
+ }
+ res = dvb->set_input(fe, in);
+ return res;
+}
+
+static int max_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
+{
+ struct ddb_input *input = fe->sec_priv;
+ struct ddb_port *port = input->port;
+ struct ddb *dev = port->dev;
+ struct ddb_dvb *dvb = &port->dvb[input->nr & 1];
+ int tuner = 0;
+ int res = 0;
+ u32 fmode = dev->link[port->lnr].lnb.fmode;
+
+ mutex_lock(&dev->link[port->lnr].lnb.lock);
+ dvb->tone = tone;
+ switch (fmode) {
+ default:
+ case 0:
+ case 3:
+ res = lnb_set_tone(dev, port->lnr, dvb->input, tone);
+ break;
+ case 1:
+ case 2:
+ if (old_quattro) {
+ if (dvb->tone == SEC_TONE_ON)
+ tuner |= 2;
+ if (dvb->voltage == SEC_VOLTAGE_18)
+ tuner |= 1;
+ } else {
+ if (dvb->tone == SEC_TONE_ON)
+ tuner |= 1;
+ if (dvb->voltage == SEC_VOLTAGE_18)
+ tuner |= 2;
+ }
+ res = max_set_input_unlocked(fe, tuner);
+ break;
+ }
+ mutex_unlock(&dev->link[port->lnr].lnb.lock);
+ return res;
+}
+
+static int max_set_voltage(struct dvb_frontend *fe, enum fe_sec_voltage voltage)
+{
+ struct ddb_input *input = fe->sec_priv;
+ struct ddb_port *port = input->port;
+ struct ddb *dev = port->dev;
+ struct ddb_dvb *dvb = &port->dvb[input->nr & 1];
+ int tuner = 0;
+ u32 nv, ov = dev->link[port->lnr].lnb.voltages;
+ int res = 0;
+ u32 fmode = dev->link[port->lnr].lnb.fmode;
+
+ mutex_lock(&dev->link[port->lnr].lnb.lock);
+ dvb->voltage = voltage;
+
+ switch (fmode) {
+ case 3:
+ default:
+ case 0:
+ if (fmode == 3)
+ max_set_input_unlocked(fe, 0);
+ if (voltage == SEC_VOLTAGE_OFF)
+ dev->link[port->lnr].lnb.voltage[dvb->input] &=
+ ~(1ULL << input->nr);
+ else
+ dev->link[port->lnr].lnb.voltage[dvb->input] |=
+ (1ULL << input->nr);
+
+ res = lnb_set_voltage(dev, port->lnr, dvb->input, voltage);
+ break;
+ case 1:
+ case 2:
+ if (voltage == SEC_VOLTAGE_OFF)
+ dev->link[port->lnr].lnb.voltages &=
+ ~(1ULL << input->nr);
+ else
+ dev->link[port->lnr].lnb.voltages |=
+ (1ULL << input->nr);
+
+ nv = dev->link[port->lnr].lnb.voltages;
+
+ if (old_quattro) {
+ if (dvb->tone == SEC_TONE_ON)
+ tuner |= 2;
+ if (dvb->voltage == SEC_VOLTAGE_18)
+ tuner |= 1;
+ } else {
+ if (dvb->tone == SEC_TONE_ON)
+ tuner |= 1;
+ if (dvb->voltage == SEC_VOLTAGE_18)
+ tuner |= 2;
+ }
+ res = max_set_input_unlocked(fe, tuner);
+
+ if (nv != ov) {
+ if (nv) {
+ lnb_set_voltage(
+ dev, port->lnr,
+ 0, SEC_VOLTAGE_13);
+ if (fmode == 1) {
+ lnb_set_voltage(
+ dev, port->lnr,
+ 0, SEC_VOLTAGE_13);
+ if (old_quattro) {
+ lnb_set_voltage(
+ dev, port->lnr,
+ 1, SEC_VOLTAGE_18);
+ lnb_set_voltage(
+ dev, port->lnr,
+ 2, SEC_VOLTAGE_13);
+ } else {
+ lnb_set_voltage(
+ dev, port->lnr,
+ 1, SEC_VOLTAGE_13);
+ lnb_set_voltage(
+ dev, port->lnr,
+ 2, SEC_VOLTAGE_18);
+ }
+ lnb_set_voltage(
+ dev, port->lnr,
+ 3, SEC_VOLTAGE_18);
+ }
+ } else {
+ lnb_set_voltage(
+ dev, port->lnr,
+ 0, SEC_VOLTAGE_OFF);
+ if (fmode == 1) {
+ lnb_set_voltage(
+ dev, port->lnr,
+ 1, SEC_VOLTAGE_OFF);
+ lnb_set_voltage(
+ dev, port->lnr,
+ 2, SEC_VOLTAGE_OFF);
+ lnb_set_voltage(
+ dev, port->lnr,
+ 3, SEC_VOLTAGE_OFF);
+ }
+ }
+ }
+ break;
+ }
+ mutex_unlock(&dev->link[port->lnr].lnb.lock);
+ return res;
+}
+
+static int max_enable_high_lnb_voltage(struct dvb_frontend *fe, long arg)
+{
+ return 0;
+}
+
+static int max_send_burst(struct dvb_frontend *fe, enum fe_sec_mini_cmd burst)
+{
+ return 0;
+}
+
+static int mxl_fw_read(void *priv, u8 *buf, u32 len)
+{
+ struct ddb_link *link = priv;
+ struct ddb *dev = link->dev;
+
+ dev_info(dev->dev, "Read mxl_fw from link %u\n", link->nr);
+
+ return ddbridge_flashread(dev, link->nr, buf, 0xc0000, len);
+}
+
+int ddb_lnb_init_fmode(struct ddb *dev, struct ddb_link *link, u32 fm)
+{
+ u32 l = link->nr;
+
+ if (link->lnb.fmode == fm)
+ return 0;
+ dev_info(dev->dev, "Set fmode link %u = %u\n", l, fm);
+ mutex_lock(&link->lnb.lock);
+ if (fm == 2 || fm == 1) {
+ if (fmode_sat >= 0) {
+ lnb_set_sat(dev, l, 0, fmode_sat, 0, 0);
+ if (old_quattro) {
+ lnb_set_sat(dev, l, 1, fmode_sat, 0, 1);
+ lnb_set_sat(dev, l, 2, fmode_sat, 1, 0);
+ } else {
+ lnb_set_sat(dev, l, 1, fmode_sat, 1, 0);
+ lnb_set_sat(dev, l, 2, fmode_sat, 0, 1);
+ }
+ lnb_set_sat(dev, l, 3, fmode_sat, 1, 1);
+ }
+ lnb_set_tone(dev, l, 0, SEC_TONE_OFF);
+ if (old_quattro) {
+ lnb_set_tone(dev, l, 1, SEC_TONE_OFF);
+ lnb_set_tone(dev, l, 2, SEC_TONE_ON);
+ } else {
+ lnb_set_tone(dev, l, 1, SEC_TONE_ON);
+ lnb_set_tone(dev, l, 2, SEC_TONE_OFF);
+ }
+ lnb_set_tone(dev, l, 3, SEC_TONE_ON);
+ }
+ link->lnb.fmode = fm;
+ mutex_unlock(&link->lnb.lock);
+ return 0;
+}
+
+static struct mxl5xx_cfg mxl5xx = {
+ .adr = 0x60,
+ .type = 0x01,
+ .clk = 27000000,
+ .ts_clk = 139,
+ .cap = 12,
+ .fw_read = mxl_fw_read,
+};
+
+int ddb_fe_attach_mxl5xx(struct ddb_input *input)
+{
+ struct ddb *dev = input->port->dev;
+ struct i2c_adapter *i2c = &input->port->i2c->adap;
+ struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];
+ struct ddb_port *port = input->port;
+ struct ddb_link *link = &dev->link[port->lnr];
+ struct mxl5xx_cfg cfg;
+ int demod, tuner;
+
+ cfg = mxl5xx;
+ cfg.fw_priv = link;
+ dvb->set_input = NULL;
+
+ demod = input->nr;
+ tuner = demod & 3;
+ if (fmode == 3)
+ tuner = 0;
+
+ dvb->fe = dvb_attach(mxl5xx_attach, i2c, &cfg,
+ demod, tuner, &dvb->set_input);
+
+ if (!dvb->fe) {
+ dev_err(dev->dev, "No MXL5XX found!\n");
+ return -ENODEV;
+ }
+
+ if (!dvb->set_input) {
+ dev_err(dev->dev, "No mxl5xx_set_input function pointer!\n");
+ return -ENODEV;
+ }
+
+ if (input->nr < 4) {
+ lnb_command(dev, port->lnr, input->nr, LNB_CMD_INIT);
+ lnb_set_voltage(dev, port->lnr, input->nr, SEC_VOLTAGE_OFF);
+ }
+ ddb_lnb_init_fmode(dev, link, fmode);
+
+ dvb->fe->ops.set_voltage = max_set_voltage;
+ dvb->fe->ops.enable_high_lnb_voltage = max_enable_high_lnb_voltage;
+ dvb->fe->ops.set_tone = max_set_tone;
+ dvb->diseqc_send_master_cmd = dvb->fe->ops.diseqc_send_master_cmd;
+ dvb->fe->ops.diseqc_send_master_cmd = max_send_master_cmd;
+ dvb->fe->ops.diseqc_send_burst = max_send_burst;
+ dvb->fe->sec_priv = input;
+ dvb->input = tuner;
+ return 0;
+}
+
+/******************************************************************************/
+/* MAX MCI related functions */
+
+int ddb_fe_attach_mci(struct ddb_input *input, u32 type)
+{
+ struct ddb *dev = input->port->dev;
+ struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1];
+ struct ddb_port *port = input->port;
+ struct ddb_link *link = &dev->link[port->lnr];
+ int demod, tuner;
+ struct mci_cfg cfg;
+
+ demod = input->nr;
+ tuner = demod & 3;
+ switch (type) {
+ case DDB_TUNER_MCI_SX8:
+ cfg = ddb_max_sx8_cfg;
+ if (fmode == 3)
+ tuner = 0;
+ break;
+ default:
+ return -EINVAL;
+ }
+ dvb->fe = ddb_mci_attach(input, &cfg, demod, &dvb->set_input);
+ if (!dvb->fe) {
+ dev_err(dev->dev, "No MCI card found!\n");
+ return -ENODEV;
+ }
+ if (!dvb->set_input) {
+ dev_err(dev->dev, "No MCI set_input function pointer!\n");
+ return -ENODEV;
+ }
+ if (input->nr < 4) {
+ lnb_command(dev, port->lnr, input->nr, LNB_CMD_INIT);
+ lnb_set_voltage(dev, port->lnr, input->nr, SEC_VOLTAGE_OFF);
+ }
+ ddb_lnb_init_fmode(dev, link, fmode);
+
+ dvb->fe->ops.set_voltage = max_set_voltage;
+ dvb->fe->ops.enable_high_lnb_voltage = max_enable_high_lnb_voltage;
+ dvb->fe->ops.set_tone = max_set_tone;
+ dvb->diseqc_send_master_cmd = dvb->fe->ops.diseqc_send_master_cmd;
+ dvb->fe->ops.diseqc_send_master_cmd = max_send_master_cmd;
+ dvb->fe->ops.diseqc_send_burst = max_send_burst;
+ dvb->fe->sec_priv = input;
+ dvb->input = tuner;
+ return 0;
+}
diff --git a/drivers/media/pci/ddbridge/ddbridge-max.h b/drivers/media/pci/ddbridge/ddbridge-max.h
new file mode 100644
index 000000000..da1553fe8
--- /dev/null
+++ b/drivers/media/pci/ddbridge/ddbridge-max.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * ddbridge-max.h: Digital Devices bridge MAX card support
+ *
+ * Copyright (C) 2010-2017 Digital Devices GmbH
+ * Ralph Metzler <rjkm@metzlerbros.de>
+ * Marcus Metzler <mocm@metzlerbros.de>
+ */
+
+#ifndef _DDBRIDGE_MAX_H_
+#define _DDBRIDGE_MAX_H_
+
+#include "ddbridge.h"
+
+/******************************************************************************/
+
+int ddb_lnb_init_fmode(struct ddb *dev, struct ddb_link *link, u32 fm);
+int ddb_fe_attach_mxl5xx(struct ddb_input *input);
+int ddb_fe_attach_mci(struct ddb_input *input, u32 type);
+
+#endif /* _DDBRIDGE_MAX_H_ */
diff --git a/drivers/media/pci/ddbridge/ddbridge-mci.c b/drivers/media/pci/ddbridge/ddbridge-mci.c
new file mode 100644
index 000000000..a006cb0fa
--- /dev/null
+++ b/drivers/media/pci/ddbridge/ddbridge-mci.c
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ddbridge-mci.c: Digital Devices microcode interface
+ *
+ * Copyright (C) 2017-2018 Digital Devices GmbH
+ * Ralph Metzler <rjkm@metzlerbros.de>
+ * Marcus Metzler <mocm@metzlerbros.de>
+ */
+
+#include "ddbridge.h"
+#include "ddbridge-io.h"
+#include "ddbridge-mci.h"
+
+static LIST_HEAD(mci_list);
+
+static int mci_reset(struct mci *state)
+{
+ struct ddb_link *link = state->base->link;
+ u32 status = 0;
+ u32 timeout = 40;
+
+ ddblwritel(link, MCI_CONTROL_RESET, MCI_CONTROL);
+ ddblwritel(link, 0, MCI_CONTROL + 4); /* 1= no internal init */
+ msleep(300);
+ ddblwritel(link, 0, MCI_CONTROL);
+
+ while (1) {
+ status = ddblreadl(link, MCI_CONTROL);
+ if ((status & MCI_CONTROL_READY) == MCI_CONTROL_READY)
+ break;
+ if (--timeout == 0)
+ break;
+ msleep(50);
+ }
+ if ((status & MCI_CONTROL_READY) == 0)
+ return -1;
+ if (link->ids.device == 0x0009)
+ ddblwritel(link, SX8_TSCONFIG_MODE_NORMAL, SX8_TSCONFIG);
+ return 0;
+}
+
+int ddb_mci_config(struct mci *state, u32 config)
+{
+ struct ddb_link *link = state->base->link;
+
+ if (link->ids.device != 0x0009)
+ return -EINVAL;
+ ddblwritel(link, config, SX8_TSCONFIG);
+ return 0;
+}
+
+static int _mci_cmd_unlocked(struct mci *state,
+ u32 *cmd, u32 cmd_len,
+ u32 *res, u32 res_len)
+{
+ struct ddb_link *link = state->base->link;
+ u32 i, val;
+ unsigned long stat;
+
+ val = ddblreadl(link, MCI_CONTROL);
+ if (val & (MCI_CONTROL_RESET | MCI_CONTROL_START_COMMAND))
+ return -EIO;
+ if (cmd && cmd_len)
+ for (i = 0; i < cmd_len; i++)
+ ddblwritel(link, cmd[i], MCI_COMMAND + i * 4);
+ val |= (MCI_CONTROL_START_COMMAND | MCI_CONTROL_ENABLE_DONE_INTERRUPT);
+ ddblwritel(link, val, MCI_CONTROL);
+
+ stat = wait_for_completion_timeout(&state->base->completion, HZ);
+ if (stat == 0) {
+ dev_warn(state->base->dev, "MCI-%d: MCI timeout\n", state->nr);
+ return -EIO;
+ }
+ if (res && res_len)
+ for (i = 0; i < res_len; i++)
+ res[i] = ddblreadl(link, MCI_RESULT + i * 4);
+ return 0;
+}
+
+int ddb_mci_cmd(struct mci *state,
+ struct mci_command *command,
+ struct mci_result *result)
+{
+ int stat;
+
+ mutex_lock(&state->base->mci_lock);
+ stat = _mci_cmd_unlocked(state,
+ (u32 *)command, sizeof(*command) / sizeof(u32),
+ (u32 *)result, sizeof(*result) / sizeof(u32));
+ mutex_unlock(&state->base->mci_lock);
+ return stat;
+}
+
+static void mci_handler(void *priv)
+{
+ struct mci_base *base = (struct mci_base *)priv;
+
+ complete(&base->completion);
+}
+
+static struct mci_base *match_base(void *key)
+{
+ struct mci_base *p;
+
+ list_for_each_entry(p, &mci_list, mci_list)
+ if (p->key == key)
+ return p;
+ return NULL;
+}
+
+static int probe(struct mci *state)
+{
+ mci_reset(state);
+ return 0;
+}
+
+struct dvb_frontend
+*ddb_mci_attach(struct ddb_input *input, struct mci_cfg *cfg, int nr,
+ int (**fn_set_input)(struct dvb_frontend *fe, int input))
+{
+ struct ddb_port *port = input->port;
+ struct ddb *dev = port->dev;
+ struct ddb_link *link = &dev->link[port->lnr];
+ struct mci_base *base;
+ struct mci *state;
+ void *key = cfg->type ? (void *)port : (void *)link;
+
+ state = kzalloc(cfg->state_size, GFP_KERNEL);
+ if (!state)
+ return NULL;
+
+ base = match_base(key);
+ if (base) {
+ base->count++;
+ state->base = base;
+ } else {
+ base = kzalloc(cfg->base_size, GFP_KERNEL);
+ if (!base)
+ goto fail;
+ base->key = key;
+ base->count = 1;
+ base->link = link;
+ base->dev = dev->dev;
+ mutex_init(&base->mci_lock);
+ mutex_init(&base->tuner_lock);
+ ddb_irq_set(dev, link->nr, 0, mci_handler, base);
+ init_completion(&base->completion);
+ state->base = base;
+ if (probe(state) < 0) {
+ kfree(base);
+ goto fail;
+ }
+ list_add(&base->mci_list, &mci_list);
+ if (cfg->base_init)
+ cfg->base_init(base);
+ }
+ memcpy(&state->fe.ops, cfg->fe_ops, sizeof(struct dvb_frontend_ops));
+ state->fe.demodulator_priv = state;
+ state->nr = nr;
+ *fn_set_input = cfg->set_input;
+ state->tuner = nr;
+ state->demod = nr;
+ if (cfg->init)
+ cfg->init(state);
+ return &state->fe;
+fail:
+ kfree(state);
+ return NULL;
+}
diff --git a/drivers/media/pci/ddbridge/ddbridge-mci.h b/drivers/media/pci/ddbridge/ddbridge-mci.h
new file mode 100644
index 000000000..d9799fbf5
--- /dev/null
+++ b/drivers/media/pci/ddbridge/ddbridge-mci.h
@@ -0,0 +1,253 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * ddbridge-mci.h: Digital Devices micro code interface
+ *
+ * Copyright (C) 2017-2018 Digital Devices GmbH
+ * Marcus Metzler <mocm@metzlerbros.de>
+ * Ralph Metzler <rjkm@metzlerbros.de>
+ */
+
+#ifndef _DDBRIDGE_MCI_H_
+#define _DDBRIDGE_MCI_H_
+
+#define MCI_DEMOD_MAX 8
+#define MCI_TUNER_MAX 4
+#define DEMOD_UNUSED (0xFF)
+
+#define MCI_CONTROL (0x500)
+#define MCI_COMMAND (0x600)
+#define MCI_RESULT (0x680)
+
+#define MCI_COMMAND_SIZE (0x80)
+#define MCI_RESULT_SIZE (0x80)
+
+#define MCI_CONTROL_START_COMMAND (0x00000001)
+#define MCI_CONTROL_ENABLE_DONE_INTERRUPT (0x00000002)
+#define MCI_CONTROL_RESET (0x00008000)
+#define MCI_CONTROL_READY (0x00010000)
+
+#define SX8_TSCONFIG (0x280)
+
+#define SX8_TSCONFIG_MODE_MASK (0x00000003)
+#define SX8_TSCONFIG_MODE_OFF (0x00000000)
+#define SX8_TSCONFIG_MODE_NORMAL (0x00000001)
+#define SX8_TSCONFIG_MODE_IQ (0x00000003)
+
+/*
+ * IQMode is only available on MaxSX8 on a single tuner
+ *
+ * IQ_MODE_SAMPLES
+ * sampling rate is 1550/24 MHz (64.583 MHz)
+ * channel agc is frozen, to allow stitching the FFT results together
+ *
+ * IQ_MODE_VTM
+ * sampling rate is the supplied symbolrate
+ * channel agc is active
+ *
+ * in both cases down sampling is done with a RRC Filter (currently fixed to
+ * alpha = 0.05) which causes some (ca 5%) aliasing at the edges from
+ * outside the spectrum
+ */
+
+#define SX8_TSCONFIG_TSHEADER (0x00000004)
+#define SX8_TSCONFIG_BURST (0x00000008)
+
+#define SX8_TSCONFIG_BURSTSIZE_MASK (0x00000030)
+#define SX8_TSCONFIG_BURSTSIZE_2K (0x00000000)
+#define SX8_TSCONFIG_BURSTSIZE_4K (0x00000010)
+#define SX8_TSCONFIG_BURSTSIZE_8K (0x00000020)
+#define SX8_TSCONFIG_BURSTSIZE_16K (0x00000030)
+
+#define SX8_DEMOD_STOPPED (0)
+#define SX8_DEMOD_IQ_MODE (1)
+#define SX8_DEMOD_WAIT_SIGNAL (2)
+#define SX8_DEMOD_WAIT_MATYPE (3)
+#define SX8_DEMOD_TIMEOUT (14)
+#define SX8_DEMOD_LOCKED (15)
+
+#define MCI_CMD_STOP (0x01)
+#define MCI_CMD_GETSTATUS (0x02)
+#define MCI_CMD_GETSIGNALINFO (0x03)
+#define MCI_CMD_RFPOWER (0x04)
+
+#define MCI_CMD_SEARCH_DVBS (0x10)
+
+#define MCI_CMD_GET_IQSYMBOL (0x30)
+
+#define SX8_CMD_INPUT_ENABLE (0x40)
+#define SX8_CMD_INPUT_DISABLE (0x41)
+#define SX8_CMD_START_IQ (0x42)
+#define SX8_CMD_STOP_IQ (0x43)
+#define SX8_CMD_ENABLE_IQOUTPUT (0x44)
+#define SX8_CMD_DISABLE_IQOUTPUT (0x45)
+
+#define MCI_STATUS_OK (0x00)
+#define MCI_STATUS_UNSUPPORTED (0x80)
+#define MCI_STATUS_RETRY (0xFD)
+#define MCI_STATUS_NOT_READY (0xFE)
+#define MCI_STATUS_ERROR (0xFF)
+
+#define MCI_SUCCESS(status) ((status & MCI_STATUS_UNSUPPORTED) == 0)
+
+struct mci_command {
+ union {
+ u32 command_word;
+ struct {
+ u8 command;
+ u8 tuner;
+ u8 demod;
+ u8 output;
+ };
+ };
+ union {
+ u32 params[31];
+ struct {
+ /*
+ * Bit 0: DVB-S Enabled
+ * Bit 1: DVB-S2 Enabled
+ * Bit 7: InputStreamID
+ */
+ u8 flags;
+ /*
+ * Bit 0: QPSK,
+ * Bit 1: 8PSK/8APSK
+ * Bit 2: 16APSK
+ * Bit 3: 32APSK
+ * Bit 4: 64APSK
+ * Bit 5: 128APSK
+ * Bit 6: 256APSK
+ */
+ u8 s2_modulation_mask;
+ u8 rsvd1;
+ u8 retry;
+ u32 frequency;
+ u32 symbol_rate;
+ u8 input_stream_id;
+ u8 rsvd2[3];
+ u32 scrambling_sequence_index;
+ u32 frequency_range;
+ } dvbs2_search;
+
+ struct {
+ u8 tap;
+ u8 rsvd;
+ u16 point;
+ } get_iq_symbol;
+
+ struct {
+ /*
+ * Bit 0: 0=VTM/1=SCAN
+ * Bit 1: Set Gain
+ */
+ u8 flags;
+ u8 roll_off;
+ u8 rsvd1;
+ u8 rsvd2;
+ u32 frequency;
+ u32 symbol_rate; /* Only in VTM mode */
+ u16 gain;
+ } sx8_start_iq;
+
+ struct {
+ /*
+ * Bit 1:0 = STVVGLNA Gain.
+ * 0 = AGC, 1 = 0dB, 2 = Minimum, 3 = Maximum
+ */
+ u8 flags;
+ } sx8_input_enable;
+ };
+};
+
+struct mci_result {
+ union {
+ u32 status_word;
+ struct {
+ u8 status;
+ u8 mode;
+ u16 time;
+ };
+ };
+ union {
+ u32 result[27];
+ struct {
+ /* 1 = DVB-S, 2 = DVB-S2X */
+ u8 standard;
+ /* puncture rate for DVB-S */
+ u8 pls_code;
+ /* 2-0: rolloff */
+ u8 roll_off;
+ u8 rsvd;
+ /* actual frequency in Hz */
+ u32 frequency;
+ /* actual symbolrate in Hz */
+ u32 symbol_rate;
+ /* channel power in dBm x 100 */
+ s16 channel_power;
+ /* band power in dBm x 100 */
+ s16 band_power;
+ /*
+ * SNR in dB x 100
+ * Note: negative values are valid in DVB-S2
+ */
+ s16 signal_to_noise;
+ s16 rsvd2;
+ /*
+ * Counter for packet errors
+ * (set to 0 on start command)
+ */
+ u32 packet_errors;
+ /* Bit error rate: PreRS in DVB-S, PreBCH in DVB-S2X */
+ u32 ber_numerator;
+ u32 ber_denominator;
+ } dvbs2_signal_info;
+
+ struct {
+ s16 i;
+ s16 q;
+ } iq_symbol;
+ };
+ u32 version[4];
+};
+
+struct mci_base {
+ struct list_head mci_list;
+ void *key;
+ struct ddb_link *link;
+ struct completion completion;
+ struct device *dev;
+ struct mutex tuner_lock; /* concurrent tuner access lock */
+ struct mutex mci_lock; /* concurrent MCI access lock */
+ int count;
+ int type;
+};
+
+struct mci {
+ struct mci_base *base;
+ struct dvb_frontend fe;
+ int nr;
+ int demod;
+ int tuner;
+};
+
+struct mci_cfg {
+ int type;
+ struct dvb_frontend_ops *fe_ops;
+ u32 base_size;
+ u32 state_size;
+ int (*init)(struct mci *mci);
+ int (*base_init)(struct mci_base *mci_base);
+ int (*set_input)(struct dvb_frontend *fe, int input);
+};
+
+/* defined in ddbridge-sx8.c */
+extern const struct mci_cfg ddb_max_sx8_cfg;
+
+int ddb_mci_cmd(struct mci *state, struct mci_command *command,
+ struct mci_result *result);
+int ddb_mci_config(struct mci *state, u32 config);
+
+struct dvb_frontend
+*ddb_mci_attach(struct ddb_input *input, struct mci_cfg *cfg, int nr,
+ int (**fn_set_input)(struct dvb_frontend *fe, int input));
+
+#endif /* _DDBRIDGE_MCI_H_ */
diff --git a/drivers/media/pci/ddbridge/ddbridge-regs.h b/drivers/media/pci/ddbridge/ddbridge-regs.h
new file mode 100644
index 000000000..42256fc96
--- /dev/null
+++ b/drivers/media/pci/ddbridge/ddbridge-regs.h
@@ -0,0 +1,140 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * ddbridge-regs.h: Digital Devices PCIe bridge driver
+ *
+ * Copyright (C) 2010-2017 Digital Devices GmbH
+ */
+
+#ifndef __DDBRIDGE_REGS_H__
+#define __DDBRIDGE_REGS_H__
+
+/* ------------------------------------------------------------------------- */
+/* SPI Controller */
+
+#define SPI_CONTROL 0x10
+#define SPI_DATA 0x14
+
+/* ------------------------------------------------------------------------- */
+/* GPIO */
+
+#define GPIO_OUTPUT 0x20
+#define GPIO_INPUT 0x24
+#define GPIO_DIRECTION 0x28
+
+/* ------------------------------------------------------------------------- */
+
+#define BOARD_CONTROL 0x30
+
+/* ------------------------------------------------------------------------- */
+
+/* Interrupt controller
+ * How many MSI's are available depends on HW (Min 2 max 8)
+ * How many are usable also depends on Host platform
+ */
+
+#define INTERRUPT_BASE (0x40)
+
+#define INTERRUPT_ENABLE (INTERRUPT_BASE + 0x00)
+#define MSI1_ENABLE (INTERRUPT_BASE + 0x04)
+#define MSI2_ENABLE (INTERRUPT_BASE + 0x08)
+#define MSI3_ENABLE (INTERRUPT_BASE + 0x0C)
+#define MSI4_ENABLE (INTERRUPT_BASE + 0x10)
+#define MSI5_ENABLE (INTERRUPT_BASE + 0x14)
+#define MSI6_ENABLE (INTERRUPT_BASE + 0x18)
+#define MSI7_ENABLE (INTERRUPT_BASE + 0x1C)
+
+#define INTERRUPT_STATUS (INTERRUPT_BASE + 0x20)
+#define INTERRUPT_ACK (INTERRUPT_BASE + 0x20)
+
+/* Temperature Monitor ( 2x LM75A @ 0x90,0x92 I2c ) */
+#define TEMPMON_BASE (0x1c0)
+#define TEMPMON_CONTROL (TEMPMON_BASE + 0x00)
+
+#define TEMPMON_CONTROL_AUTOSCAN (0x00000002)
+#define TEMPMON_CONTROL_INTENABLE (0x00000004)
+#define TEMPMON_CONTROL_OVERTEMP (0x00008000)
+
+/* SHORT Temperature in Celsius x 256 */
+#define TEMPMON_SENSOR0 (TEMPMON_BASE + 0x04)
+#define TEMPMON_SENSOR1 (TEMPMON_BASE + 0x08)
+
+#define TEMPMON_FANCONTROL (TEMPMON_BASE + 0x10)
+
+/* ------------------------------------------------------------------------- */
+/* I2C Master Controller */
+
+#define I2C_COMMAND (0x00)
+#define I2C_TIMING (0x04)
+#define I2C_TASKLENGTH (0x08) /* High read, low write */
+#define I2C_TASKADDRESS (0x0C) /* High read, low write */
+#define I2C_MONITOR (0x1C)
+
+#define I2C_SPEED_400 (0x04030404)
+#define I2C_SPEED_100 (0x13121313)
+
+/* ------------------------------------------------------------------------- */
+/* DMA Controller */
+
+#define DMA_BASE_WRITE (0x100)
+#define DMA_BASE_READ (0x140)
+
+#define TS_CONTROL(_io) ((_io)->regs + 0x00)
+#define TS_CONTROL2(_io) ((_io)->regs + 0x04)
+
+/* ------------------------------------------------------------------------- */
+/* DMA Buffer */
+
+#define DMA_BUFFER_CONTROL(_dma) ((_dma)->regs + 0x00)
+#define DMA_BUFFER_ACK(_dma) ((_dma)->regs + 0x04)
+#define DMA_BUFFER_CURRENT(_dma) ((_dma)->regs + 0x08)
+#define DMA_BUFFER_SIZE(_dma) ((_dma)->regs + 0x0c)
+
+/* ------------------------------------------------------------------------- */
+/* CI Interface (only CI-Bridge) */
+
+#define CI_BASE (0x400)
+#define CI_CONTROL(i) (CI_BASE + (i) * 32 + 0x00)
+
+#define CI_DO_ATTRIBUTE_RW(i) (CI_BASE + (i) * 32 + 0x04)
+#define CI_DO_IO_RW(i) (CI_BASE + (i) * 32 + 0x08)
+#define CI_READDATA(i) (CI_BASE + (i) * 32 + 0x0c)
+#define CI_DO_READ_ATTRIBUTES(i) (CI_BASE + (i) * 32 + 0x10)
+
+#define CI_RESET_CAM (0x00000001)
+#define CI_POWER_ON (0x00000002)
+#define CI_ENABLE (0x00000004)
+#define CI_BYPASS_DISABLE (0x00000010)
+
+#define CI_CAM_READY (0x00010000)
+#define CI_CAM_DETECT (0x00020000)
+#define CI_READY (0x80000000)
+
+#define CI_READ_CMD (0x40000000)
+#define CI_WRITE_CMD (0x80000000)
+
+#define CI_BUFFER_BASE (0x3000)
+#define CI_BUFFER_SIZE (0x0800)
+
+#define CI_BUFFER(i) (CI_BUFFER_BASE + (i) * CI_BUFFER_SIZE)
+
+/* ------------------------------------------------------------------------- */
+/* LNB commands (mxl5xx / Max S8) */
+
+#define LNB_BASE (0x400)
+#define LNB_CONTROL(i) (LNB_BASE + (i) * 0x20 + 0x00)
+
+#define LNB_CMD (7ULL << 0)
+#define LNB_CMD_NOP 0
+#define LNB_CMD_INIT 1
+#define LNB_CMD_LOW 3
+#define LNB_CMD_HIGH 4
+#define LNB_CMD_OFF 5
+#define LNB_CMD_DISEQC 6
+
+#define LNB_BUSY BIT_ULL(4)
+#define LNB_TONE BIT_ULL(15)
+
+#define LNB_BUF_LEVEL(i) (LNB_BASE + (i) * 0x20 + 0x10)
+#define LNB_BUF_WRITE(i) (LNB_BASE + (i) * 0x20 + 0x14)
+
+#endif /* __DDBRIDGE_REGS_H__ */
diff --git a/drivers/media/pci/ddbridge/ddbridge-sx8.c b/drivers/media/pci/ddbridge/ddbridge-sx8.c
new file mode 100644
index 000000000..c8de8d283
--- /dev/null
+++ b/drivers/media/pci/ddbridge/ddbridge-sx8.c
@@ -0,0 +1,477 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ddbridge-sx8.c: Digital Devices MAX SX8 driver
+ *
+ * Copyright (C) 2018 Digital Devices GmbH
+ * Marcus Metzler <mocm@metzlerbros.de>
+ * Ralph Metzler <rjkm@metzlerbros.de>
+ */
+
+#include "ddbridge.h"
+#include "ddbridge-io.h"
+#include "ddbridge-mci.h"
+
+static const u32 MCLK = (1550000000 / 12);
+static const u32 MAX_LDPC_BITRATE = (720000000);
+static const u32 MAX_DEMOD_LDPC_BITRATE = (1550000000 / 6);
+
+#define SX8_TUNER_NUM 4
+#define SX8_DEMOD_NUM 8
+#define SX8_DEMOD_NONE 0xff
+
+struct sx8_base {
+ struct mci_base mci_base;
+
+ u8 tuner_use_count[SX8_TUNER_NUM];
+ u32 gain_mode[SX8_TUNER_NUM];
+
+ u32 used_ldpc_bitrate[SX8_DEMOD_NUM];
+ u8 demod_in_use[SX8_DEMOD_NUM];
+ u32 iq_mode;
+ u32 burst_size;
+ u32 direct_mode;
+};
+
+struct sx8 {
+ struct mci mci;
+
+ int first_time_lock;
+ int started;
+ struct mci_result signal_info;
+
+ u32 bb_mode;
+ u32 local_frequency;
+};
+
+static void release(struct dvb_frontend *fe)
+{
+ struct sx8 *state = fe->demodulator_priv;
+ struct mci_base *mci_base = state->mci.base;
+
+ mci_base->count--;
+ if (mci_base->count == 0) {
+ list_del(&mci_base->mci_list);
+ kfree(mci_base);
+ }
+ kfree(state);
+}
+
+static int get_info(struct dvb_frontend *fe)
+{
+ int stat;
+ struct sx8 *state = fe->demodulator_priv;
+ struct mci_command cmd;
+
+ memset(&cmd, 0, sizeof(cmd));
+ cmd.command = MCI_CMD_GETSIGNALINFO;
+ cmd.demod = state->mci.demod;
+ stat = ddb_mci_cmd(&state->mci, &cmd, &state->signal_info);
+ return stat;
+}
+
+static int get_snr(struct dvb_frontend *fe)
+{
+ struct sx8 *state = fe->demodulator_priv;
+ struct dtv_frontend_properties *p = &fe->dtv_property_cache;
+
+ p->cnr.len = 1;
+ p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
+ p->cnr.stat[0].svalue =
+ (s64)state->signal_info.dvbs2_signal_info.signal_to_noise
+ * 10;
+ return 0;
+}
+
+static int get_strength(struct dvb_frontend *fe)
+{
+ struct sx8 *state = fe->demodulator_priv;
+ struct dtv_frontend_properties *p = &fe->dtv_property_cache;
+ s32 str;
+
+ str = 100000 -
+ (state->signal_info.dvbs2_signal_info.channel_power
+ * 10 + 108750);
+ p->strength.len = 1;
+ p->strength.stat[0].scale = FE_SCALE_DECIBEL;
+ p->strength.stat[0].svalue = str;
+ return 0;
+}
+
+static int read_status(struct dvb_frontend *fe, enum fe_status *status)
+{
+ int stat;
+ struct sx8 *state = fe->demodulator_priv;
+ struct mci_command cmd;
+ struct mci_result res;
+
+ cmd.command = MCI_CMD_GETSTATUS;
+ cmd.demod = state->mci.demod;
+ stat = ddb_mci_cmd(&state->mci, &cmd, &res);
+ if (stat)
+ return stat;
+ *status = 0x00;
+ get_info(fe);
+ get_strength(fe);
+ if (res.status == SX8_DEMOD_WAIT_MATYPE)
+ *status = 0x0f;
+ if (res.status == SX8_DEMOD_LOCKED) {
+ *status = 0x1f;
+ get_snr(fe);
+ }
+ return stat;
+}
+
+static int mci_set_tuner(struct dvb_frontend *fe, u32 tuner, u32 on)
+{
+ struct sx8 *state = fe->demodulator_priv;
+ struct mci_base *mci_base = state->mci.base;
+ struct sx8_base *sx8_base = (struct sx8_base *)mci_base;
+ struct mci_command cmd;
+
+ memset(&cmd, 0, sizeof(cmd));
+ cmd.tuner = state->mci.tuner;
+ cmd.command = on ? SX8_CMD_INPUT_ENABLE : SX8_CMD_INPUT_DISABLE;
+ cmd.sx8_input_enable.flags = sx8_base->gain_mode[state->mci.tuner];
+ return ddb_mci_cmd(&state->mci, &cmd, NULL);
+}
+
+static int stop(struct dvb_frontend *fe)
+{
+ struct sx8 *state = fe->demodulator_priv;
+ struct mci_base *mci_base = state->mci.base;
+ struct sx8_base *sx8_base = (struct sx8_base *)mci_base;
+ struct mci_command cmd;
+ u32 input = state->mci.tuner;
+
+ memset(&cmd, 0, sizeof(cmd));
+ if (state->mci.demod != SX8_DEMOD_NONE) {
+ cmd.command = MCI_CMD_STOP;
+ cmd.demod = state->mci.demod;
+ ddb_mci_cmd(&state->mci, &cmd, NULL);
+ if (sx8_base->iq_mode) {
+ cmd.command = SX8_CMD_DISABLE_IQOUTPUT;
+ cmd.demod = state->mci.demod;
+ cmd.output = 0;
+ ddb_mci_cmd(&state->mci, &cmd, NULL);
+ ddb_mci_config(&state->mci, SX8_TSCONFIG_MODE_NORMAL);
+ }
+ }
+ mutex_lock(&mci_base->tuner_lock);
+ sx8_base->tuner_use_count[input]--;
+ if (!sx8_base->tuner_use_count[input])
+ mci_set_tuner(fe, input, 0);
+ if (state->mci.demod < SX8_DEMOD_NUM) {
+ sx8_base->demod_in_use[state->mci.demod] = 0;
+ state->mci.demod = SX8_DEMOD_NONE;
+ }
+ sx8_base->used_ldpc_bitrate[state->mci.nr] = 0;
+ sx8_base->iq_mode = 0;
+ mutex_unlock(&mci_base->tuner_lock);
+ state->started = 0;
+ return 0;
+}
+
+static int start(struct dvb_frontend *fe, u32 flags, u32 modmask, u32 ts_config)
+{
+ struct sx8 *state = fe->demodulator_priv;
+ struct mci_base *mci_base = state->mci.base;
+ struct sx8_base *sx8_base = (struct sx8_base *)mci_base;
+ struct dtv_frontend_properties *p = &fe->dtv_property_cache;
+ u32 used_ldpc_bitrate = 0, free_ldpc_bitrate;
+ u32 used_demods = 0;
+ struct mci_command cmd;
+ u32 input = state->mci.tuner;
+ u32 bits_per_symbol = 0;
+ int i = -1, stat = 0;
+
+ if (p->symbol_rate >= (MCLK / 2))
+ flags &= ~1;
+ if ((flags & 3) == 0)
+ return -EINVAL;
+
+ if (flags & 2) {
+ u32 tmp = modmask;
+
+ bits_per_symbol = 1;
+ while (tmp & 1) {
+ tmp >>= 1;
+ bits_per_symbol++;
+ }
+ }
+
+ mutex_lock(&mci_base->tuner_lock);
+ if (sx8_base->iq_mode) {
+ stat = -EBUSY;
+ goto unlock;
+ }
+
+ if (sx8_base->direct_mode) {
+ if (p->symbol_rate >= MCLK / 2) {
+ if (state->mci.nr < 4)
+ i = state->mci.nr;
+ } else {
+ i = state->mci.nr;
+ }
+ } else {
+ for (i = 0; i < SX8_DEMOD_NUM; i++) {
+ used_ldpc_bitrate += sx8_base->used_ldpc_bitrate[i];
+ if (sx8_base->demod_in_use[i])
+ used_demods++;
+ }
+ if (used_ldpc_bitrate >= MAX_LDPC_BITRATE ||
+ ((ts_config & SX8_TSCONFIG_MODE_MASK) >
+ SX8_TSCONFIG_MODE_NORMAL && used_demods > 0)) {
+ stat = -EBUSY;
+ goto unlock;
+ }
+ free_ldpc_bitrate = MAX_LDPC_BITRATE - used_ldpc_bitrate;
+ if (free_ldpc_bitrate > MAX_DEMOD_LDPC_BITRATE)
+ free_ldpc_bitrate = MAX_DEMOD_LDPC_BITRATE;
+
+ while (p->symbol_rate * bits_per_symbol > free_ldpc_bitrate)
+ bits_per_symbol--;
+ if (bits_per_symbol < 2) {
+ stat = -EBUSY;
+ goto unlock;
+ }
+
+ modmask &= ((1 << (bits_per_symbol - 1)) - 1);
+ if (((flags & 0x02) != 0) && modmask == 0) {
+ stat = -EBUSY;
+ goto unlock;
+ }
+
+ i = (p->symbol_rate > (MCLK / 2)) ? 3 : 7;
+ while (i >= 0 && sx8_base->demod_in_use[i])
+ i--;
+ }
+
+ if (i < 0) {
+ stat = -EBUSY;
+ goto unlock;
+ }
+ sx8_base->demod_in_use[i] = 1;
+ sx8_base->used_ldpc_bitrate[state->mci.nr] = p->symbol_rate
+ * bits_per_symbol;
+ state->mci.demod = i;
+
+ if (!sx8_base->tuner_use_count[input])
+ mci_set_tuner(fe, input, 1);
+ sx8_base->tuner_use_count[input]++;
+ sx8_base->iq_mode = (ts_config > 1);
+unlock:
+ mutex_unlock(&mci_base->tuner_lock);
+ if (stat)
+ return stat;
+ memset(&cmd, 0, sizeof(cmd));
+
+ if (sx8_base->iq_mode) {
+ cmd.command = SX8_CMD_ENABLE_IQOUTPUT;
+ cmd.demod = state->mci.demod;
+ cmd.output = 0;
+ ddb_mci_cmd(&state->mci, &cmd, NULL);
+ ddb_mci_config(&state->mci, ts_config);
+ }
+ if (p->stream_id != NO_STREAM_ID_FILTER && p->stream_id != 0x80000000)
+ flags |= 0x80;
+ dev_dbg(mci_base->dev, "MCI-%d: tuner=%d demod=%d\n",
+ state->mci.nr, state->mci.tuner, state->mci.demod);
+ cmd.command = MCI_CMD_SEARCH_DVBS;
+ cmd.dvbs2_search.flags = flags;
+ cmd.dvbs2_search.s2_modulation_mask = modmask;
+ cmd.dvbs2_search.retry = 2;
+ cmd.dvbs2_search.frequency = p->frequency * 1000;
+ cmd.dvbs2_search.symbol_rate = p->symbol_rate;
+ cmd.dvbs2_search.scrambling_sequence_index =
+ p->scrambling_sequence_index | 0x80000000;
+ cmd.dvbs2_search.input_stream_id =
+ (p->stream_id != NO_STREAM_ID_FILTER) ? p->stream_id : 0;
+ cmd.tuner = state->mci.tuner;
+ cmd.demod = state->mci.demod;
+ cmd.output = state->mci.nr;
+ if (p->stream_id == 0x80000000)
+ cmd.output |= 0x80;
+ stat = ddb_mci_cmd(&state->mci, &cmd, NULL);
+ if (stat)
+ stop(fe);
+ return stat;
+}
+
+static int start_iq(struct dvb_frontend *fe, u32 flags, u32 roll_off,
+ u32 ts_config)
+{
+ struct sx8 *state = fe->demodulator_priv;
+ struct mci_base *mci_base = state->mci.base;
+ struct sx8_base *sx8_base = (struct sx8_base *)mci_base;
+ struct dtv_frontend_properties *p = &fe->dtv_property_cache;
+ u32 used_demods = 0;
+ struct mci_command cmd;
+ u32 input = state->mci.tuner;
+ int i, stat = 0;
+
+ mutex_lock(&mci_base->tuner_lock);
+ if (sx8_base->iq_mode) {
+ stat = -EBUSY;
+ goto unlock;
+ }
+ for (i = 0; i < SX8_DEMOD_NUM; i++)
+ if (sx8_base->demod_in_use[i])
+ used_demods++;
+ if (used_demods > 0) {
+ stat = -EBUSY;
+ goto unlock;
+ }
+ state->mci.demod = 0;
+ if (!sx8_base->tuner_use_count[input])
+ mci_set_tuner(fe, input, 1);
+ sx8_base->tuner_use_count[input]++;
+ sx8_base->iq_mode = (ts_config > 1);
+unlock:
+ mutex_unlock(&mci_base->tuner_lock);
+ if (stat)
+ return stat;
+
+ memset(&cmd, 0, sizeof(cmd));
+ cmd.command = SX8_CMD_START_IQ;
+ cmd.sx8_start_iq.flags = flags;
+ cmd.sx8_start_iq.roll_off = roll_off;
+ cmd.sx8_start_iq.frequency = p->frequency * 1000;
+ cmd.sx8_start_iq.symbol_rate = p->symbol_rate;
+ cmd.tuner = state->mci.tuner;
+ cmd.demod = state->mci.demod;
+ stat = ddb_mci_cmd(&state->mci, &cmd, NULL);
+ if (stat)
+ stop(fe);
+ ddb_mci_config(&state->mci, ts_config);
+ return stat;
+}
+
+static int set_parameters(struct dvb_frontend *fe)
+{
+ int stat = 0;
+ struct sx8 *state = fe->demodulator_priv;
+ struct dtv_frontend_properties *p = &fe->dtv_property_cache;
+ u32 ts_config = SX8_TSCONFIG_MODE_NORMAL, iq_mode = 0, isi;
+
+ if (state->started)
+ stop(fe);
+
+ isi = p->stream_id;
+ if (isi != NO_STREAM_ID_FILTER)
+ iq_mode = (isi & 0x30000000) >> 28;
+
+ if (iq_mode)
+ ts_config = (SX8_TSCONFIG_TSHEADER | SX8_TSCONFIG_MODE_IQ);
+ if (iq_mode < 3) {
+ u32 mask;
+
+ switch (p->modulation) {
+ /* uncomment whenever these modulations hit the DVB API
+ * case APSK_256:
+ * mask = 0x7f;
+ * break;
+ * case APSK_128:
+ * mask = 0x3f;
+ * break;
+ * case APSK_64:
+ * mask = 0x1f;
+ * break;
+ */
+ case APSK_32:
+ mask = 0x0f;
+ break;
+ case APSK_16:
+ mask = 0x07;
+ break;
+ default:
+ mask = 0x03;
+ break;
+ }
+ stat = start(fe, 3, mask, ts_config);
+ } else {
+ stat = start_iq(fe, 0, 4, ts_config);
+ }
+ if (!stat) {
+ state->started = 1;
+ state->first_time_lock = 1;
+ state->signal_info.status = SX8_DEMOD_WAIT_SIGNAL;
+ }
+
+ return stat;
+}
+
+static int tune(struct dvb_frontend *fe, bool re_tune,
+ unsigned int mode_flags,
+ unsigned int *delay, enum fe_status *status)
+{
+ int r;
+
+ if (re_tune) {
+ r = set_parameters(fe);
+ if (r)
+ return r;
+ }
+ r = read_status(fe, status);
+ if (r)
+ return r;
+
+ if (*status & FE_HAS_LOCK)
+ return 0;
+ *delay = HZ / 10;
+ return 0;
+}
+
+static enum dvbfe_algo get_algo(struct dvb_frontend *fe)
+{
+ return DVBFE_ALGO_HW;
+}
+
+static int set_input(struct dvb_frontend *fe, int input)
+{
+ struct sx8 *state = fe->demodulator_priv;
+ struct mci_base *mci_base = state->mci.base;
+
+ if (input >= SX8_TUNER_NUM)
+ return -EINVAL;
+
+ state->mci.tuner = input;
+ dev_dbg(mci_base->dev, "MCI-%d: input=%d\n", state->mci.nr, input);
+ return 0;
+}
+
+static struct dvb_frontend_ops sx8_ops = {
+ .delsys = { SYS_DVBS, SYS_DVBS2 },
+ .info = {
+ .name = "Digital Devices MaxSX8 MCI DVB-S/S2/S2X",
+ .frequency_min_hz = 950 * MHz,
+ .frequency_max_hz = 2150 * MHz,
+ .symbol_rate_min = 100000,
+ .symbol_rate_max = 100000000,
+ .caps = FE_CAN_INVERSION_AUTO |
+ FE_CAN_FEC_AUTO |
+ FE_CAN_QPSK |
+ FE_CAN_2G_MODULATION |
+ FE_CAN_MULTISTREAM,
+ },
+ .get_frontend_algo = get_algo,
+ .tune = tune,
+ .release = release,
+ .read_status = read_status,
+};
+
+static int init(struct mci *mci)
+{
+ struct sx8 *state = (struct sx8 *)mci;
+
+ state->mci.demod = SX8_DEMOD_NONE;
+ return 0;
+}
+
+const struct mci_cfg ddb_max_sx8_cfg = {
+ .type = 0,
+ .fe_ops = &sx8_ops,
+ .base_size = sizeof(struct sx8_base),
+ .state_size = sizeof(struct sx8),
+ .init = init,
+ .set_input = set_input,
+};
diff --git a/drivers/media/pci/ddbridge/ddbridge.h b/drivers/media/pci/ddbridge/ddbridge.h
new file mode 100644
index 000000000..f3699dbd1
--- /dev/null
+++ b/drivers/media/pci/ddbridge/ddbridge.h
@@ -0,0 +1,373 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * ddbridge.h: Digital Devices PCIe bridge driver
+ *
+ * Copyright (C) 2010-2017 Digital Devices GmbH
+ * Ralph Metzler <rmetzler@digitaldevices.de>
+ */
+
+#ifndef _DDBRIDGE_H_
+#define _DDBRIDGE_H_
+
+#include <linux/clk.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/dvb/ca.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kthread.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/poll.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/socket.h>
+#include <linux/spi/spi.h>
+#include <linux/swab.h>
+#include <linux/timer.h>
+#include <linux/types.h>
+#include <linux/uaccess.h>
+#include <linux/vmalloc.h>
+#include <linux/workqueue.h>
+
+#include <asm/dma.h>
+#include <asm/irq.h>
+
+#include <media/dmxdev.h>
+#include <media/dvb_ca_en50221.h>
+#include <media/dvb_demux.h>
+#include <media/dvbdev.h>
+#include <media/dvb_frontend.h>
+#include <media/dvb_net.h>
+#include <media/dvb_ringbuffer.h>
+
+#define DDBRIDGE_VERSION "0.9.33-integrated"
+
+#define DDB_MAX_I2C 32
+#define DDB_MAX_PORT 32
+#define DDB_MAX_INPUT 64
+#define DDB_MAX_OUTPUT 32
+#define DDB_MAX_LINK 4
+#define DDB_LINK_SHIFT 28
+
+#define DDB_LINK_TAG(_x) (_x << DDB_LINK_SHIFT)
+
+struct ddb_regset {
+ u32 base;
+ u32 num;
+ u32 size;
+};
+
+struct ddb_regmap {
+ u32 irq_base_i2c;
+ u32 irq_base_idma;
+ u32 irq_base_odma;
+
+ const struct ddb_regset *i2c;
+ const struct ddb_regset *i2c_buf;
+ const struct ddb_regset *idma;
+ const struct ddb_regset *idma_buf;
+ const struct ddb_regset *odma;
+ const struct ddb_regset *odma_buf;
+
+ const struct ddb_regset *input;
+ const struct ddb_regset *output;
+
+ const struct ddb_regset *channel;
+};
+
+struct ddb_ids {
+ u16 vendor;
+ u16 device;
+ u16 subvendor;
+ u16 subdevice;
+
+ u32 hwid;
+ u32 regmapid;
+ u32 devid;
+ u32 mac;
+};
+
+struct ddb_info {
+ int type;
+#define DDB_NONE 0
+#define DDB_OCTOPUS 1
+#define DDB_OCTOPUS_CI 2
+#define DDB_OCTOPUS_MAX 5
+#define DDB_OCTOPUS_MAX_CT 6
+#define DDB_OCTOPUS_MCI 9
+ char *name;
+ u32 i2c_mask;
+ u32 board_control;
+ u32 board_control_2;
+
+ u8 port_num;
+ u8 led_num;
+ u8 fan_num;
+ u8 temp_num;
+ u8 temp_bus;
+ u8 con_clock; /* use a continuous clock */
+ u8 ts_quirks;
+#define TS_QUIRK_SERIAL 1
+#define TS_QUIRK_REVERSED 2
+#define TS_QUIRK_ALT_OSC 8
+ u8 mci_ports;
+ u8 mci_type;
+
+ u32 tempmon_irq;
+ const struct ddb_regmap *regmap;
+};
+
+#define DMA_MAX_BUFS 32 /* hardware table limit */
+
+struct ddb;
+struct ddb_port;
+
+struct ddb_dma {
+ void *io;
+ u32 regs;
+ u32 bufregs;
+
+ dma_addr_t pbuf[DMA_MAX_BUFS];
+ u8 *vbuf[DMA_MAX_BUFS];
+ u32 num;
+ u32 size;
+ u32 div;
+ u32 bufval;
+
+ struct work_struct work;
+ spinlock_t lock; /* DMA lock */
+ wait_queue_head_t wq;
+ int running;
+ u32 stat;
+ u32 ctrl;
+ u32 cbuf;
+ u32 coff;
+};
+
+struct ddb_dvb {
+ struct dvb_adapter *adap;
+ int adap_registered;
+ struct dvb_device *dev;
+ struct i2c_client *i2c_client[1];
+ struct dvb_frontend *fe;
+ struct dvb_frontend *fe2;
+ struct dmxdev dmxdev;
+ struct dvb_demux demux;
+ struct dvb_net dvbnet;
+ struct dmx_frontend hw_frontend;
+ struct dmx_frontend mem_frontend;
+ int users;
+ u32 attached;
+ u8 input;
+
+ enum fe_sec_tone_mode tone;
+ enum fe_sec_voltage voltage;
+
+ int (*i2c_gate_ctrl)(struct dvb_frontend *, int);
+ int (*set_voltage)(struct dvb_frontend *fe,
+ enum fe_sec_voltage voltage);
+ int (*set_input)(struct dvb_frontend *fe, int input);
+ int (*diseqc_send_master_cmd)(struct dvb_frontend *fe,
+ struct dvb_diseqc_master_cmd *cmd);
+};
+
+struct ddb_ci {
+ struct dvb_ca_en50221 en;
+ struct ddb_port *port;
+ u32 nr;
+};
+
+struct ddb_io {
+ struct ddb_port *port;
+ u32 nr;
+ u32 regs;
+ struct ddb_dma *dma;
+ struct ddb_io *redo;
+ struct ddb_io *redi;
+};
+
+#define ddb_output ddb_io
+#define ddb_input ddb_io
+
+struct ddb_i2c {
+ struct ddb *dev;
+ u32 nr;
+ u32 regs;
+ u32 link;
+ struct i2c_adapter adap;
+ u32 rbuf;
+ u32 wbuf;
+ u32 bsize;
+ struct completion completion;
+};
+
+struct ddb_port {
+ struct ddb *dev;
+ u32 nr;
+ u32 pnr;
+ u32 regs;
+ u32 lnr;
+ struct ddb_i2c *i2c;
+ struct mutex i2c_gate_lock; /* I2C access lock */
+ u32 class;
+#define DDB_PORT_NONE 0
+#define DDB_PORT_CI 1
+#define DDB_PORT_TUNER 2
+#define DDB_PORT_LOOP 3
+ char *name;
+ char *type_name;
+ u32 type;
+#define DDB_TUNER_DUMMY 0xffffffff
+#define DDB_TUNER_NONE 0
+#define DDB_TUNER_DVBS_ST 1
+#define DDB_TUNER_DVBS_ST_AA 2
+#define DDB_TUNER_DVBCT_TR 3
+#define DDB_TUNER_DVBCT_ST 4
+#define DDB_CI_INTERNAL 5
+#define DDB_CI_EXTERNAL_SONY 6
+#define DDB_TUNER_DVBCT2_SONY_P 7
+#define DDB_TUNER_DVBC2T2_SONY_P 8
+#define DDB_TUNER_ISDBT_SONY_P 9
+#define DDB_TUNER_DVBS_STV0910_P 10
+#define DDB_TUNER_MXL5XX 11
+#define DDB_CI_EXTERNAL_XO2 12
+#define DDB_CI_EXTERNAL_XO2_B 13
+#define DDB_TUNER_DVBS_STV0910_PR 14
+#define DDB_TUNER_DVBC2T2I_SONY_P 15
+
+#define DDB_TUNER_XO2 32
+#define DDB_TUNER_DVBS_STV0910 (DDB_TUNER_XO2 + 0)
+#define DDB_TUNER_DVBCT2_SONY (DDB_TUNER_XO2 + 1)
+#define DDB_TUNER_ISDBT_SONY (DDB_TUNER_XO2 + 2)
+#define DDB_TUNER_DVBC2T2_SONY (DDB_TUNER_XO2 + 3)
+#define DDB_TUNER_ATSC_ST (DDB_TUNER_XO2 + 4)
+#define DDB_TUNER_DVBC2T2I_SONY (DDB_TUNER_XO2 + 5)
+
+#define DDB_TUNER_MCI 48
+#define DDB_TUNER_MCI_SX8 (DDB_TUNER_MCI + 0)
+
+ struct ddb_input *input[2];
+ struct ddb_output *output;
+ struct dvb_ca_en50221 *en;
+ u8 en_freedata;
+ struct ddb_dvb dvb[2];
+ u32 gap;
+ u32 obr;
+ u8 creg;
+};
+
+#define CM_STARTUP_DELAY 2
+#define CM_AVERAGE 20
+#define CM_GAIN 10
+
+#define HW_LSB_SHIFT 12
+#define HW_LSB_MASK 0x1000
+
+#define CM_IDLE 0
+#define CM_STARTUP 1
+#define CM_ADJUST 2
+
+#define TS_CAPTURE_LEN (4096)
+
+struct ddb_lnb {
+ struct mutex lock; /* lock lnb access */
+ u32 tone;
+ enum fe_sec_voltage oldvoltage[4];
+ u32 voltage[4];
+ u32 voltages;
+ u32 fmode;
+};
+
+struct ddb_irq {
+ void (*handler)(void *);
+ void *data;
+};
+
+struct ddb_link {
+ struct ddb *dev;
+ const struct ddb_info *info;
+ u32 nr;
+ u32 regs;
+ spinlock_t lock; /* lock link access */
+ struct mutex flash_mutex; /* lock flash access */
+ struct ddb_lnb lnb;
+ struct tasklet_struct tasklet;
+ struct ddb_ids ids;
+
+ spinlock_t temp_lock; /* lock temp chip access */
+ int overtemperature_error;
+ u8 temp_tab[11];
+ struct ddb_irq irq[256];
+};
+
+struct ddb {
+ struct pci_dev *pdev;
+ struct platform_device *pfdev;
+ struct device *dev;
+
+ int msi;
+ struct workqueue_struct *wq;
+ u32 has_dma;
+
+ struct ddb_link link[DDB_MAX_LINK];
+ unsigned char __iomem *regs;
+ u32 regs_len;
+ u32 port_num;
+ struct ddb_port port[DDB_MAX_PORT];
+ u32 i2c_num;
+ struct ddb_i2c i2c[DDB_MAX_I2C];
+ struct ddb_input input[DDB_MAX_INPUT];
+ struct ddb_output output[DDB_MAX_OUTPUT];
+ struct dvb_adapter adap[DDB_MAX_INPUT];
+ struct ddb_dma idma[DDB_MAX_INPUT];
+ struct ddb_dma odma[DDB_MAX_OUTPUT];
+
+ struct device *ddb_dev;
+ u32 ddb_dev_users;
+ u32 nr;
+ u8 iobuf[1028];
+
+ u8 leds;
+ u32 ts_irq;
+ u32 i2c_irq;
+
+ struct mutex mutex; /* lock access to global ddb array */
+
+ u8 tsbuf[TS_CAPTURE_LEN];
+};
+
+/****************************************************************************/
+/****************************************************************************/
+/****************************************************************************/
+
+int ddbridge_flashread(struct ddb *dev, u32 link, u8 *buf, u32 addr, u32 len);
+
+/****************************************************************************/
+
+/* ddbridge-core.c */
+struct ddb_irq *ddb_irq_set(struct ddb *dev, u32 link, u32 nr,
+ void (*handler)(void *), void *data);
+void ddb_ports_detach(struct ddb *dev);
+void ddb_ports_release(struct ddb *dev);
+void ddb_buffers_free(struct ddb *dev);
+void ddb_device_destroy(struct ddb *dev);
+irqreturn_t ddb_irq_handler0(int irq, void *dev_id);
+irqreturn_t ddb_irq_handler1(int irq, void *dev_id);
+irqreturn_t ddb_irq_handler(int irq, void *dev_id);
+void ddb_ports_init(struct ddb *dev);
+int ddb_buffers_alloc(struct ddb *dev);
+int ddb_ports_attach(struct ddb *dev);
+int ddb_device_create(struct ddb *dev);
+int ddb_init(struct ddb *dev);
+void ddb_unmap(struct ddb *dev);
+int ddb_exit_ddbridge(int stage, int error);
+int ddb_init_ddbridge(void);
+
+#endif /* _DDBRIDGE_H_ */
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-27 17:33:24 +0000