diff options
Diffstat (limited to 'drivers/gpu/drm/bridge/imx')
| -rw-r--r-- | drivers/gpu/drm/bridge/imx/Kconfig | 47 | ||||
| -rw-r--r-- | drivers/gpu/drm/bridge/imx/Makefile | 9 | ||||
| -rw-r--r-- | drivers/gpu/drm/bridge/imx/imx-ldb-helper.c | 221 | ||||
| -rw-r--r-- | drivers/gpu/drm/bridge/imx/imx-ldb-helper.h | 96 | ||||
| -rw-r--r-- | drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c | 588 | ||||
| -rw-r--r-- | drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c | 723 | ||||
| -rw-r--r-- | drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c | 450 | ||||
| -rw-r--r-- | drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c | 430 | ||||
| -rw-r--r-- | drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c | 488 |
9 files changed, 3052 insertions, 0 deletions
diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig new file mode 100644 index 000000000..608f47f41 --- /dev/null +++ b/drivers/gpu/drm/bridge/imx/Kconfig @@ -0,0 +1,47 @@ +if ARCH_MXC || COMPILE_TEST + +config DRM_IMX8QM_LDB + tristate "Freescale i.MX8QM LVDS display bridge" + depends on OF + depends on COMMON_CLK + select DRM_KMS_HELPER + help + Choose this to enable the internal LVDS Display Bridge(LDB) found in + Freescale i.MX8qm processor. Official name of LDB is pixel mapper. + +config DRM_IMX8QXP_LDB + tristate "Freescale i.MX8QXP LVDS display bridge" + depends on OF + depends on COMMON_CLK + select DRM_KMS_HELPER + help + Choose this to enable the internal LVDS Display Bridge(LDB) found in + Freescale i.MX8qxp processor. Official name of LDB is pixel mapper. + +config DRM_IMX8QXP_PIXEL_COMBINER + tristate "Freescale i.MX8QM/QXP pixel combiner" + depends on OF + depends on COMMON_CLK + select DRM_KMS_HELPER + help + Choose this to enable pixel combiner found in + Freescale i.MX8qm/qxp processors. + +config DRM_IMX8QXP_PIXEL_LINK + tristate "Freescale i.MX8QM/QXP display pixel link" + depends on OF + depends on IMX_SCU + select DRM_KMS_HELPER + help + Choose this to enable display pixel link found in + Freescale i.MX8qm/qxp processors. + +config DRM_IMX8QXP_PIXEL_LINK_TO_DPI + tristate "Freescale i.MX8QXP pixel link to display pixel interface" + depends on OF + select DRM_KMS_HELPER + help + Choose this to enable pixel link to display pixel interface(PXL2DPI) + found in Freescale i.MX8qxp processor. + +endif # ARCH_MXC || COMPILE_TEST diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile new file mode 100644 index 000000000..aa90ec8d5 --- /dev/null +++ b/drivers/gpu/drm/bridge/imx/Makefile @@ -0,0 +1,9 @@ +imx8qm-ldb-objs := imx-ldb-helper.o imx8qm-ldb-drv.o +obj-$(CONFIG_DRM_IMX8QM_LDB) += imx8qm-ldb.o + +imx8qxp-ldb-objs := imx-ldb-helper.o imx8qxp-ldb-drv.o +obj-$(CONFIG_DRM_IMX8QXP_LDB) += imx8qxp-ldb.o + +obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o +obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o +obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI) += imx8qxp-pxl2dpi.o diff --git a/drivers/gpu/drm/bridge/imx/imx-ldb-helper.c b/drivers/gpu/drm/bridge/imx/imx-ldb-helper.c new file mode 100644 index 000000000..7338b84bc --- /dev/null +++ b/drivers/gpu/drm/bridge/imx/imx-ldb-helper.c @@ -0,0 +1,221 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2012 Sascha Hauer, Pengutronix + * Copyright 2019,2020,2022 NXP + */ + +#include <linux/media-bus-format.h> +#include <linux/mfd/syscon.h> +#include <linux/of.h> +#include <linux/regmap.h> + +#include <drm/drm_bridge.h> +#include <drm/drm_of.h> +#include <drm/drm_print.h> + +#include "imx-ldb-helper.h" + +bool ldb_channel_is_single_link(struct ldb_channel *ldb_ch) +{ + return ldb_ch->link_type == LDB_CH_SINGLE_LINK; +} + +bool ldb_channel_is_split_link(struct ldb_channel *ldb_ch) +{ + return ldb_ch->link_type == LDB_CH_DUAL_LINK_EVEN_ODD_PIXELS || + ldb_ch->link_type == LDB_CH_DUAL_LINK_ODD_EVEN_PIXELS; +} + +int ldb_bridge_atomic_check_helper(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + + ldb_ch->in_bus_format = bridge_state->input_bus_cfg.format; + ldb_ch->out_bus_format = bridge_state->output_bus_cfg.format; + + return 0; +} + +void ldb_bridge_mode_set_helper(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + const struct drm_display_mode *adjusted_mode) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + struct ldb *ldb = ldb_ch->ldb; + bool is_split = ldb_channel_is_split_link(ldb_ch); + + if (is_split) + ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN; + + switch (ldb_ch->out_bus_format) { + case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: + break; + case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: + if (ldb_ch->chno == 0 || is_split) + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24; + if (ldb_ch->chno == 1 || is_split) + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24; + break; + case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: + if (ldb_ch->chno == 0 || is_split) + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 | + LDB_BIT_MAP_CH0_JEIDA; + if (ldb_ch->chno == 1 || is_split) + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 | + LDB_BIT_MAP_CH1_JEIDA; + break; + } +} + +void ldb_bridge_enable_helper(struct drm_bridge *bridge) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + struct ldb *ldb = ldb_ch->ldb; + + /* + * Platform specific bridge drivers should set ldb_ctrl properly + * for the enablement, so just write the ctrl_reg here. + */ + regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl); +} + +void ldb_bridge_disable_helper(struct drm_bridge *bridge) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + struct ldb *ldb = ldb_ch->ldb; + bool is_split = ldb_channel_is_split_link(ldb_ch); + + if (ldb_ch->chno == 0 || is_split) + ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK; + if (ldb_ch->chno == 1 || is_split) + ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK; + + regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl); +} + +int ldb_bridge_attach_helper(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + struct ldb *ldb = ldb_ch->ldb; + + if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) { + DRM_DEV_ERROR(ldb->dev, + "do not support creating a drm_connector\n"); + return -EINVAL; + } + + if (!bridge->encoder) { + DRM_DEV_ERROR(ldb->dev, "missing encoder\n"); + return -ENODEV; + } + + return drm_bridge_attach(bridge->encoder, + ldb_ch->next_bridge, bridge, + DRM_BRIDGE_ATTACH_NO_CONNECTOR); +} + +int ldb_init_helper(struct ldb *ldb) +{ + struct device *dev = ldb->dev; + struct device_node *np = dev->of_node; + struct device_node *child; + int ret; + u32 i; + + ldb->regmap = syscon_node_to_regmap(np->parent); + if (IS_ERR(ldb->regmap)) { + ret = PTR_ERR(ldb->regmap); + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(dev, "failed to get regmap: %d\n", ret); + return ret; + } + + for_each_available_child_of_node(np, child) { + struct ldb_channel *ldb_ch; + + ret = of_property_read_u32(child, "reg", &i); + if (ret || i > MAX_LDB_CHAN_NUM - 1) { + ret = -EINVAL; + DRM_DEV_ERROR(dev, + "invalid channel node address: %u\n", i); + of_node_put(child); + return ret; + } + + ldb_ch = ldb->channel[i]; + ldb_ch->ldb = ldb; + ldb_ch->chno = i; + ldb_ch->is_available = true; + ldb_ch->np = child; + + ldb->available_ch_cnt++; + } + + return 0; +} + +int ldb_find_next_bridge_helper(struct ldb *ldb) +{ + struct device *dev = ldb->dev; + struct ldb_channel *ldb_ch; + int ret, i; + + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) { + ldb_ch = ldb->channel[i]; + + if (!ldb_ch->is_available) + continue; + + ldb_ch->next_bridge = devm_drm_of_get_bridge(dev, ldb_ch->np, + 1, 0); + if (IS_ERR(ldb_ch->next_bridge)) { + ret = PTR_ERR(ldb_ch->next_bridge); + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(dev, + "failed to get next bridge: %d\n", + ret); + return ret; + } + } + + return 0; +} + +void ldb_add_bridge_helper(struct ldb *ldb, + const struct drm_bridge_funcs *bridge_funcs) +{ + struct ldb_channel *ldb_ch; + int i; + + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) { + ldb_ch = ldb->channel[i]; + + if (!ldb_ch->is_available) + continue; + + ldb_ch->bridge.driver_private = ldb_ch; + ldb_ch->bridge.funcs = bridge_funcs; + ldb_ch->bridge.of_node = ldb_ch->np; + + drm_bridge_add(&ldb_ch->bridge); + } +} + +void ldb_remove_bridge_helper(struct ldb *ldb) +{ + struct ldb_channel *ldb_ch; + int i; + + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) { + ldb_ch = ldb->channel[i]; + + if (!ldb_ch->is_available) + continue; + + drm_bridge_remove(&ldb_ch->bridge); + } +} diff --git a/drivers/gpu/drm/bridge/imx/imx-ldb-helper.h b/drivers/gpu/drm/bridge/imx/imx-ldb-helper.h new file mode 100644 index 000000000..a0a5cde27 --- /dev/null +++ b/drivers/gpu/drm/bridge/imx/imx-ldb-helper.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +/* + * Copyright 2019,2020,2022 NXP + */ + +#ifndef __IMX_LDB_HELPER__ +#define __IMX_LDB_HELPER__ + +#include <linux/device.h> +#include <linux/kernel.h> +#include <linux/of.h> +#include <linux/regmap.h> + +#include <drm/drm_atomic.h> +#include <drm/drm_bridge.h> +#include <drm/drm_device.h> +#include <drm/drm_encoder.h> +#include <drm/drm_modeset_helper_vtables.h> + +#define LDB_CH0_MODE_EN_TO_DI0 BIT(0) +#define LDB_CH0_MODE_EN_TO_DI1 (3 << 0) +#define LDB_CH0_MODE_EN_MASK (3 << 0) +#define LDB_CH1_MODE_EN_TO_DI0 BIT(2) +#define LDB_CH1_MODE_EN_TO_DI1 (3 << 2) +#define LDB_CH1_MODE_EN_MASK (3 << 2) +#define LDB_SPLIT_MODE_EN BIT(4) +#define LDB_DATA_WIDTH_CH0_24 BIT(5) +#define LDB_BIT_MAP_CH0_JEIDA BIT(6) +#define LDB_DATA_WIDTH_CH1_24 BIT(7) +#define LDB_BIT_MAP_CH1_JEIDA BIT(8) +#define LDB_DI0_VS_POL_ACT_LOW BIT(9) +#define LDB_DI1_VS_POL_ACT_LOW BIT(10) + +#define MAX_LDB_CHAN_NUM 2 + +enum ldb_channel_link_type { + LDB_CH_SINGLE_LINK, + LDB_CH_DUAL_LINK_EVEN_ODD_PIXELS, + LDB_CH_DUAL_LINK_ODD_EVEN_PIXELS, +}; + +struct ldb; + +struct ldb_channel { + struct ldb *ldb; + struct drm_bridge bridge; + struct drm_bridge *next_bridge; + struct device_node *np; + u32 chno; + bool is_available; + u32 in_bus_format; + u32 out_bus_format; + enum ldb_channel_link_type link_type; +}; + +struct ldb { + struct regmap *regmap; + struct device *dev; + struct ldb_channel *channel[MAX_LDB_CHAN_NUM]; + unsigned int ctrl_reg; + u32 ldb_ctrl; + unsigned int available_ch_cnt; +}; + +#define bridge_to_ldb_ch(b) container_of(b, struct ldb_channel, bridge) + +bool ldb_channel_is_single_link(struct ldb_channel *ldb_ch); +bool ldb_channel_is_split_link(struct ldb_channel *ldb_ch); + +int ldb_bridge_atomic_check_helper(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state); + +void ldb_bridge_mode_set_helper(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + const struct drm_display_mode *adjusted_mode); + +void ldb_bridge_enable_helper(struct drm_bridge *bridge); + +void ldb_bridge_disable_helper(struct drm_bridge *bridge); + +int ldb_bridge_attach_helper(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags); + +int ldb_init_helper(struct ldb *ldb); + +int ldb_find_next_bridge_helper(struct ldb *ldb); + +void ldb_add_bridge_helper(struct ldb *ldb, + const struct drm_bridge_funcs *bridge_funcs); + +void ldb_remove_bridge_helper(struct ldb *ldb); + +#endif /* __IMX_LDB_HELPER__ */ diff --git a/drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c b/drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c new file mode 100644 index 000000000..178af8d2d --- /dev/null +++ b/drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c @@ -0,0 +1,588 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include <linux/clk.h> +#include <linux/media-bus-format.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/of_graph.h> +#include <linux/phy/phy.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h> + +#include <drm/drm_atomic_state_helper.h> +#include <drm/drm_bridge.h> +#include <drm/drm_connector.h> +#include <drm/drm_fourcc.h> +#include <drm/drm_of.h> +#include <drm/drm_print.h> + +#include "imx-ldb-helper.h" + +#define LDB_CH0_10BIT_EN BIT(22) +#define LDB_CH1_10BIT_EN BIT(23) +#define LDB_CH0_DATA_WIDTH_24BIT BIT(24) +#define LDB_CH1_DATA_WIDTH_24BIT BIT(26) +#define LDB_CH0_DATA_WIDTH_30BIT (2 << 24) +#define LDB_CH1_DATA_WIDTH_30BIT (2 << 26) + +#define SS_CTRL 0x20 +#define CH_HSYNC_M(id) BIT(0 + ((id) * 2)) +#define CH_VSYNC_M(id) BIT(1 + ((id) * 2)) +#define CH_PHSYNC(id) BIT(0 + ((id) * 2)) +#define CH_PVSYNC(id) BIT(1 + ((id) * 2)) + +#define DRIVER_NAME "imx8qm-ldb" + +struct imx8qm_ldb_channel { + struct ldb_channel base; + struct phy *phy; +}; + +struct imx8qm_ldb { + struct ldb base; + struct device *dev; + struct imx8qm_ldb_channel channel[MAX_LDB_CHAN_NUM]; + struct clk *clk_pixel; + struct clk *clk_bypass; + int active_chno; +}; + +static inline struct imx8qm_ldb_channel * +base_to_imx8qm_ldb_channel(struct ldb_channel *base) +{ + return container_of(base, struct imx8qm_ldb_channel, base); +} + +static inline struct imx8qm_ldb *base_to_imx8qm_ldb(struct ldb *base) +{ + return container_of(base, struct imx8qm_ldb, base); +} + +static void imx8qm_ldb_set_phy_cfg(struct imx8qm_ldb *imx8qm_ldb, + unsigned long di_clk, + bool is_split, bool is_slave, + struct phy_configure_opts_lvds *phy_cfg) +{ + phy_cfg->bits_per_lane_and_dclk_cycle = 7; + phy_cfg->lanes = 4; + phy_cfg->differential_clk_rate = is_split ? di_clk / 2 : di_clk; + phy_cfg->is_slave = is_slave; +} + +static int imx8qm_ldb_bridge_atomic_check(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + struct ldb *ldb = ldb_ch->ldb; + struct imx8qm_ldb_channel *imx8qm_ldb_ch = + base_to_imx8qm_ldb_channel(ldb_ch); + struct imx8qm_ldb *imx8qm_ldb = base_to_imx8qm_ldb(ldb); + struct drm_display_mode *adj = &crtc_state->adjusted_mode; + unsigned long di_clk = adj->clock * 1000; + bool is_split = ldb_channel_is_split_link(ldb_ch); + union phy_configure_opts opts = { }; + struct phy_configure_opts_lvds *phy_cfg = &opts.lvds; + int ret; + + ret = ldb_bridge_atomic_check_helper(bridge, bridge_state, + crtc_state, conn_state); + if (ret) + return ret; + + imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, false, phy_cfg); + ret = phy_validate(imx8qm_ldb_ch->phy, PHY_MODE_LVDS, 0, &opts); + if (ret < 0) { + DRM_DEV_DEBUG_DRIVER(imx8qm_ldb->dev, + "failed to validate PHY: %d\n", ret); + return ret; + } + + if (is_split) { + imx8qm_ldb_ch = + &imx8qm_ldb->channel[imx8qm_ldb->active_chno ^ 1]; + imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, true, + phy_cfg); + ret = phy_validate(imx8qm_ldb_ch->phy, PHY_MODE_LVDS, 0, &opts); + if (ret < 0) { + DRM_DEV_DEBUG_DRIVER(imx8qm_ldb->dev, + "failed to validate slave PHY: %d\n", + ret); + return ret; + } + } + + return ret; +} + +static void +imx8qm_ldb_bridge_mode_set(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + const struct drm_display_mode *adjusted_mode) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + struct ldb *ldb = ldb_ch->ldb; + struct imx8qm_ldb_channel *imx8qm_ldb_ch = + base_to_imx8qm_ldb_channel(ldb_ch); + struct imx8qm_ldb *imx8qm_ldb = base_to_imx8qm_ldb(ldb); + struct device *dev = imx8qm_ldb->dev; + unsigned long di_clk = adjusted_mode->clock * 1000; + bool is_split = ldb_channel_is_split_link(ldb_ch); + union phy_configure_opts opts = { }; + struct phy_configure_opts_lvds *phy_cfg = &opts.lvds; + u32 chno = ldb_ch->chno; + int ret; + + ret = pm_runtime_get_sync(dev); + if (ret < 0) + DRM_DEV_ERROR(dev, "failed to get runtime PM sync: %d\n", ret); + + ret = phy_init(imx8qm_ldb_ch->phy); + if (ret < 0) + DRM_DEV_ERROR(dev, "failed to initialize PHY: %d\n", ret); + + clk_set_rate(imx8qm_ldb->clk_bypass, di_clk); + clk_set_rate(imx8qm_ldb->clk_pixel, di_clk); + + imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, false, phy_cfg); + ret = phy_configure(imx8qm_ldb_ch->phy, &opts); + if (ret < 0) + DRM_DEV_ERROR(dev, "failed to configure PHY: %d\n", ret); + + if (is_split) { + imx8qm_ldb_ch = + &imx8qm_ldb->channel[imx8qm_ldb->active_chno ^ 1]; + imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, true, + phy_cfg); + ret = phy_configure(imx8qm_ldb_ch->phy, &opts); + if (ret < 0) + DRM_DEV_ERROR(dev, "failed to configure slave PHY: %d\n", + ret); + } + + /* input VSYNC signal from pixel link is active low */ + if (ldb_ch->chno == 0 || is_split) + ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW; + if (ldb_ch->chno == 1 || is_split) + ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW; + + switch (ldb_ch->out_bus_format) { + case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: + break; + case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: + case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: + if (ldb_ch->chno == 0 || is_split) + ldb->ldb_ctrl |= LDB_CH0_DATA_WIDTH_24BIT; + if (ldb_ch->chno == 1 || is_split) + ldb->ldb_ctrl |= LDB_CH1_DATA_WIDTH_24BIT; + break; + } + + ldb_bridge_mode_set_helper(bridge, mode, adjusted_mode); + + if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) + regmap_update_bits(ldb->regmap, SS_CTRL, CH_VSYNC_M(chno), 0); + else if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) + regmap_update_bits(ldb->regmap, SS_CTRL, + CH_VSYNC_M(chno), CH_PVSYNC(chno)); + + if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) + regmap_update_bits(ldb->regmap, SS_CTRL, CH_HSYNC_M(chno), 0); + else if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) + regmap_update_bits(ldb->regmap, SS_CTRL, + CH_HSYNC_M(chno), CH_PHSYNC(chno)); +} + +static void +imx8qm_ldb_bridge_atomic_enable(struct drm_bridge *bridge, + struct drm_bridge_state *old_bridge_state) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + struct ldb *ldb = ldb_ch->ldb; + struct imx8qm_ldb_channel *imx8qm_ldb_ch = + base_to_imx8qm_ldb_channel(ldb_ch); + struct imx8qm_ldb *imx8qm_ldb = base_to_imx8qm_ldb(ldb); + struct device *dev = imx8qm_ldb->dev; + bool is_split = ldb_channel_is_split_link(ldb_ch); + int ret; + + clk_prepare_enable(imx8qm_ldb->clk_pixel); + clk_prepare_enable(imx8qm_ldb->clk_bypass); + + /* both DI0 and DI1 connect with pixel link, so ok to use DI0 only */ + if (ldb_ch->chno == 0 || is_split) { + ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK; + ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0; + } + if (ldb_ch->chno == 1 || is_split) { + ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK; + ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0; + } + + if (is_split) { + ret = phy_power_on(imx8qm_ldb->channel[0].phy); + if (ret) + DRM_DEV_ERROR(dev, + "failed to power on channel0 PHY: %d\n", + ret); + + ret = phy_power_on(imx8qm_ldb->channel[1].phy); + if (ret) + DRM_DEV_ERROR(dev, + "failed to power on channel1 PHY: %d\n", + ret); + } else { + ret = phy_power_on(imx8qm_ldb_ch->phy); + if (ret) + DRM_DEV_ERROR(dev, "failed to power on PHY: %d\n", ret); + } + + ldb_bridge_enable_helper(bridge); +} + +static void +imx8qm_ldb_bridge_atomic_disable(struct drm_bridge *bridge, + struct drm_bridge_state *old_bridge_state) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + struct ldb *ldb = ldb_ch->ldb; + struct imx8qm_ldb_channel *imx8qm_ldb_ch = + base_to_imx8qm_ldb_channel(ldb_ch); + struct imx8qm_ldb *imx8qm_ldb = base_to_imx8qm_ldb(ldb); + struct device *dev = imx8qm_ldb->dev; + bool is_split = ldb_channel_is_split_link(ldb_ch); + int ret; + + ldb_bridge_disable_helper(bridge); + + if (is_split) { + ret = phy_power_off(imx8qm_ldb->channel[0].phy); + if (ret) + DRM_DEV_ERROR(dev, + "failed to power off channel0 PHY: %d\n", + ret); + ret = phy_power_off(imx8qm_ldb->channel[1].phy); + if (ret) + DRM_DEV_ERROR(dev, + "failed to power off channel1 PHY: %d\n", + ret); + } else { + ret = phy_power_off(imx8qm_ldb_ch->phy); + if (ret) + DRM_DEV_ERROR(dev, "failed to power off PHY: %d\n", ret); + } + + clk_disable_unprepare(imx8qm_ldb->clk_bypass); + clk_disable_unprepare(imx8qm_ldb->clk_pixel); + + ret = pm_runtime_put(dev); + if (ret < 0) + DRM_DEV_ERROR(dev, "failed to put runtime PM: %d\n", ret); +} + +static const u32 imx8qm_ldb_bus_output_fmts[] = { + MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, + MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, + MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, + MEDIA_BUS_FMT_FIXED, +}; + +static bool imx8qm_ldb_bus_output_fmt_supported(u32 fmt) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(imx8qm_ldb_bus_output_fmts); i++) { + if (imx8qm_ldb_bus_output_fmts[i] == fmt) + return true; + } + + return false; +} + +static u32 * +imx8qm_ldb_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + u32 output_fmt, + unsigned int *num_input_fmts) +{ + struct drm_display_info *di; + const struct drm_format_info *finfo; + u32 *input_fmts; + + if (!imx8qm_ldb_bus_output_fmt_supported(output_fmt)) + return NULL; + + *num_input_fmts = 1; + + input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL); + if (!input_fmts) + return NULL; + + switch (output_fmt) { + case MEDIA_BUS_FMT_FIXED: + di = &conn_state->connector->display_info; + + /* + * Look at the first bus format to determine input format. + * Default to MEDIA_BUS_FMT_RGB888_1X36_CPADLO, if no match. + */ + if (di->num_bus_formats) { + finfo = drm_format_info(di->bus_formats[0]); + + input_fmts[0] = finfo->depth == 18 ? + MEDIA_BUS_FMT_RGB666_1X36_CPADLO : + MEDIA_BUS_FMT_RGB888_1X36_CPADLO; + } else { + input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X36_CPADLO; + } + break; + case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: + input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X36_CPADLO; + break; + case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: + case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: + input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X36_CPADLO; + break; + default: + kfree(input_fmts); + input_fmts = NULL; + break; + } + + return input_fmts; +} + +static u32 * +imx8qm_ldb_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + unsigned int *num_output_fmts) +{ + *num_output_fmts = ARRAY_SIZE(imx8qm_ldb_bus_output_fmts); + return kmemdup(imx8qm_ldb_bus_output_fmts, + sizeof(imx8qm_ldb_bus_output_fmts), GFP_KERNEL); +} + +static enum drm_mode_status +imx8qm_ldb_bridge_mode_valid(struct drm_bridge *bridge, + const struct drm_display_info *info, + const struct drm_display_mode *mode) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + bool is_single = ldb_channel_is_single_link(ldb_ch); + + if (mode->clock > 300000) + return MODE_CLOCK_HIGH; + + if (mode->clock > 150000 && is_single) + return MODE_CLOCK_HIGH; + + return MODE_OK; +} + +static const struct drm_bridge_funcs imx8qm_ldb_bridge_funcs = { + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, + .atomic_reset = drm_atomic_helper_bridge_reset, + .mode_valid = imx8qm_ldb_bridge_mode_valid, + .attach = ldb_bridge_attach_helper, + .atomic_check = imx8qm_ldb_bridge_atomic_check, + .mode_set = imx8qm_ldb_bridge_mode_set, + .atomic_enable = imx8qm_ldb_bridge_atomic_enable, + .atomic_disable = imx8qm_ldb_bridge_atomic_disable, + .atomic_get_input_bus_fmts = + imx8qm_ldb_bridge_atomic_get_input_bus_fmts, + .atomic_get_output_bus_fmts = + imx8qm_ldb_bridge_atomic_get_output_bus_fmts, +}; + +static int imx8qm_ldb_get_phy(struct imx8qm_ldb *imx8qm_ldb) +{ + struct imx8qm_ldb_channel *imx8qm_ldb_ch; + struct ldb_channel *ldb_ch; + struct device *dev = imx8qm_ldb->dev; + int i, ret; + + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) { + imx8qm_ldb_ch = &imx8qm_ldb->channel[i]; + ldb_ch = &imx8qm_ldb_ch->base; + + if (!ldb_ch->is_available) + continue; + + imx8qm_ldb_ch->phy = devm_of_phy_get(dev, ldb_ch->np, + "lvds_phy"); + if (IS_ERR(imx8qm_ldb_ch->phy)) { + ret = PTR_ERR(imx8qm_ldb_ch->phy); + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(dev, + "failed to get channel%d PHY: %d\n", + i, ret); + return ret; + } + } + + return 0; +} + +static int imx8qm_ldb_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct imx8qm_ldb *imx8qm_ldb; + struct imx8qm_ldb_channel *imx8qm_ldb_ch; + struct ldb *ldb; + struct ldb_channel *ldb_ch; + struct device_node *port1, *port2; + int pixel_order; + int ret, i; + + imx8qm_ldb = devm_kzalloc(dev, sizeof(*imx8qm_ldb), GFP_KERNEL); + if (!imx8qm_ldb) + return -ENOMEM; + + imx8qm_ldb->clk_pixel = devm_clk_get(dev, "pixel"); + if (IS_ERR(imx8qm_ldb->clk_pixel)) { + ret = PTR_ERR(imx8qm_ldb->clk_pixel); + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(dev, + "failed to get pixel clock: %d\n", ret); + return ret; + } + + imx8qm_ldb->clk_bypass = devm_clk_get(dev, "bypass"); + if (IS_ERR(imx8qm_ldb->clk_bypass)) { + ret = PTR_ERR(imx8qm_ldb->clk_bypass); + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(dev, + "failed to get bypass clock: %d\n", ret); + return ret; + } + + imx8qm_ldb->dev = dev; + + ldb = &imx8qm_ldb->base; + ldb->dev = dev; + ldb->ctrl_reg = 0xe0; + + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) + ldb->channel[i] = &imx8qm_ldb->channel[i].base; + + ret = ldb_init_helper(ldb); + if (ret) + return ret; + + if (ldb->available_ch_cnt == 0) { + DRM_DEV_DEBUG_DRIVER(dev, "no available channel\n"); + return 0; + } + + if (ldb->available_ch_cnt == 2) { + port1 = of_graph_get_port_by_id(ldb->channel[0]->np, 1); + port2 = of_graph_get_port_by_id(ldb->channel[1]->np, 1); + pixel_order = + drm_of_lvds_get_dual_link_pixel_order(port1, port2); + of_node_put(port1); + of_node_put(port2); + + if (pixel_order != DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS) { + DRM_DEV_ERROR(dev, "invalid dual link pixel order: %d\n", + pixel_order); + return -EINVAL; + } + + imx8qm_ldb->active_chno = 0; + imx8qm_ldb_ch = &imx8qm_ldb->channel[0]; + ldb_ch = &imx8qm_ldb_ch->base; + ldb_ch->link_type = pixel_order; + } else { + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) { + imx8qm_ldb_ch = &imx8qm_ldb->channel[i]; + ldb_ch = &imx8qm_ldb_ch->base; + + if (ldb_ch->is_available) { + imx8qm_ldb->active_chno = ldb_ch->chno; + break; + } + } + } + + ret = imx8qm_ldb_get_phy(imx8qm_ldb); + if (ret) + return ret; + + ret = ldb_find_next_bridge_helper(ldb); + if (ret) + return ret; + + platform_set_drvdata(pdev, imx8qm_ldb); + pm_runtime_enable(dev); + + ldb_add_bridge_helper(ldb, &imx8qm_ldb_bridge_funcs); + + return ret; +} + +static int imx8qm_ldb_remove(struct platform_device *pdev) +{ + struct imx8qm_ldb *imx8qm_ldb = platform_get_drvdata(pdev); + struct ldb *ldb = &imx8qm_ldb->base; + + ldb_remove_bridge_helper(ldb); + + pm_runtime_disable(&pdev->dev); + + return 0; +} + +static int __maybe_unused imx8qm_ldb_runtime_suspend(struct device *dev) +{ + return 0; +} + +static int __maybe_unused imx8qm_ldb_runtime_resume(struct device *dev) +{ + struct imx8qm_ldb *imx8qm_ldb = dev_get_drvdata(dev); + struct ldb *ldb = &imx8qm_ldb->base; + + /* disable LDB by resetting the control register to POR default */ + regmap_write(ldb->regmap, ldb->ctrl_reg, 0); + + return 0; +} + +static const struct dev_pm_ops imx8qm_ldb_pm_ops = { + SET_RUNTIME_PM_OPS(imx8qm_ldb_runtime_suspend, + imx8qm_ldb_runtime_resume, NULL) +}; + +static const struct of_device_id imx8qm_ldb_dt_ids[] = { + { .compatible = "fsl,imx8qm-ldb" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx8qm_ldb_dt_ids); + +static struct platform_driver imx8qm_ldb_driver = { + .probe = imx8qm_ldb_probe, + .remove = imx8qm_ldb_remove, + .driver = { + .pm = &imx8qm_ldb_pm_ops, + .name = DRIVER_NAME, + .of_match_table = imx8qm_ldb_dt_ids, + }, +}; +module_platform_driver(imx8qm_ldb_driver); + +MODULE_DESCRIPTION("i.MX8QM LVDS Display Bridge(LDB)/Pixel Mapper bridge driver"); +MODULE_AUTHOR("Liu Ying <victor.liu@nxp.com>"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRIVER_NAME); diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c b/drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c new file mode 100644 index 000000000..63948d5d2 --- /dev/null +++ b/drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c @@ -0,0 +1,723 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include <linux/clk.h> +#include <linux/media-bus-format.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/of_graph.h> +#include <linux/phy/phy.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h> + +#include <drm/drm_atomic_state_helper.h> +#include <drm/drm_bridge.h> +#include <drm/drm_connector.h> +#include <drm/drm_fourcc.h> +#include <drm/drm_of.h> +#include <drm/drm_print.h> + +#include "imx-ldb-helper.h" + +#define LDB_CH_SEL BIT(28) + +#define SS_CTRL 0x20 +#define CH_HSYNC_M(id) BIT(0 + ((id) * 2)) +#define CH_VSYNC_M(id) BIT(1 + ((id) * 2)) +#define CH_PHSYNC(id) BIT(0 + ((id) * 2)) +#define CH_PVSYNC(id) BIT(1 + ((id) * 2)) + +#define DRIVER_NAME "imx8qxp-ldb" + +struct imx8qxp_ldb_channel { + struct ldb_channel base; + struct phy *phy; + unsigned int di_id; +}; + +struct imx8qxp_ldb { + struct ldb base; + struct device *dev; + struct imx8qxp_ldb_channel channel[MAX_LDB_CHAN_NUM]; + struct clk *clk_pixel; + struct clk *clk_bypass; + struct drm_bridge *companion; + int active_chno; +}; + +static inline struct imx8qxp_ldb_channel * +base_to_imx8qxp_ldb_channel(struct ldb_channel *base) +{ + return container_of(base, struct imx8qxp_ldb_channel, base); +} + +static inline struct imx8qxp_ldb *base_to_imx8qxp_ldb(struct ldb *base) +{ + return container_of(base, struct imx8qxp_ldb, base); +} + +static void imx8qxp_ldb_set_phy_cfg(struct imx8qxp_ldb *imx8qxp_ldb, + unsigned long di_clk, bool is_split, + struct phy_configure_opts_lvds *phy_cfg) +{ + phy_cfg->bits_per_lane_and_dclk_cycle = 7; + phy_cfg->lanes = 4; + + if (is_split) { + phy_cfg->differential_clk_rate = di_clk / 2; + phy_cfg->is_slave = !imx8qxp_ldb->companion; + } else { + phy_cfg->differential_clk_rate = di_clk; + phy_cfg->is_slave = false; + } +} + +static int +imx8qxp_ldb_bridge_atomic_check(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + struct ldb *ldb = ldb_ch->ldb; + struct imx8qxp_ldb_channel *imx8qxp_ldb_ch = + base_to_imx8qxp_ldb_channel(ldb_ch); + struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb); + struct drm_bridge *companion = imx8qxp_ldb->companion; + struct drm_display_mode *adj = &crtc_state->adjusted_mode; + unsigned long di_clk = adj->clock * 1000; + bool is_split = ldb_channel_is_split_link(ldb_ch); + union phy_configure_opts opts = { }; + struct phy_configure_opts_lvds *phy_cfg = &opts.lvds; + int ret; + + ret = ldb_bridge_atomic_check_helper(bridge, bridge_state, + crtc_state, conn_state); + if (ret) + return ret; + + imx8qxp_ldb_set_phy_cfg(imx8qxp_ldb, di_clk, is_split, phy_cfg); + ret = phy_validate(imx8qxp_ldb_ch->phy, PHY_MODE_LVDS, 0, &opts); + if (ret < 0) { + DRM_DEV_DEBUG_DRIVER(imx8qxp_ldb->dev, + "failed to validate PHY: %d\n", ret); + return ret; + } + + if (is_split && companion) { + ret = companion->funcs->atomic_check(companion, + bridge_state, crtc_state, conn_state); + if (ret) + return ret; + } + + return ret; +} + +static void +imx8qxp_ldb_bridge_mode_set(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + const struct drm_display_mode *adjusted_mode) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + struct ldb_channel *companion_ldb_ch; + struct ldb *ldb = ldb_ch->ldb; + struct imx8qxp_ldb_channel *imx8qxp_ldb_ch = + base_to_imx8qxp_ldb_channel(ldb_ch); + struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb); + struct drm_bridge *companion = imx8qxp_ldb->companion; + struct device *dev = imx8qxp_ldb->dev; + unsigned long di_clk = adjusted_mode->clock * 1000; + bool is_split = ldb_channel_is_split_link(ldb_ch); + union phy_configure_opts opts = { }; + struct phy_configure_opts_lvds *phy_cfg = &opts.lvds; + u32 chno = ldb_ch->chno; + int ret; + + ret = pm_runtime_get_sync(dev); + if (ret < 0) + DRM_DEV_ERROR(dev, "failed to get runtime PM sync: %d\n", ret); + + ret = phy_init(imx8qxp_ldb_ch->phy); + if (ret < 0) + DRM_DEV_ERROR(dev, "failed to initialize PHY: %d\n", ret); + + ret = phy_set_mode(imx8qxp_ldb_ch->phy, PHY_MODE_LVDS); + if (ret < 0) + DRM_DEV_ERROR(dev, "failed to set PHY mode: %d\n", ret); + + if (is_split && companion) { + companion_ldb_ch = bridge_to_ldb_ch(companion); + + companion_ldb_ch->in_bus_format = ldb_ch->in_bus_format; + companion_ldb_ch->out_bus_format = ldb_ch->out_bus_format; + } + + clk_set_rate(imx8qxp_ldb->clk_bypass, di_clk); + clk_set_rate(imx8qxp_ldb->clk_pixel, di_clk); + + imx8qxp_ldb_set_phy_cfg(imx8qxp_ldb, di_clk, is_split, phy_cfg); + ret = phy_configure(imx8qxp_ldb_ch->phy, &opts); + if (ret < 0) + DRM_DEV_ERROR(dev, "failed to configure PHY: %d\n", ret); + + if (chno == 0) + ldb->ldb_ctrl &= ~LDB_CH_SEL; + else + ldb->ldb_ctrl |= LDB_CH_SEL; + + /* input VSYNC signal from pixel link is active low */ + if (imx8qxp_ldb_ch->di_id == 0) + ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW; + else + ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW; + + /* + * For split mode, settle input VSYNC signal polarity and + * channel selection down early. + */ + if (is_split) + regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl); + + ldb_bridge_mode_set_helper(bridge, mode, adjusted_mode); + + if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) + regmap_update_bits(ldb->regmap, SS_CTRL, CH_VSYNC_M(chno), 0); + else if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) + regmap_update_bits(ldb->regmap, SS_CTRL, + CH_VSYNC_M(chno), CH_PVSYNC(chno)); + + if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) + regmap_update_bits(ldb->regmap, SS_CTRL, CH_HSYNC_M(chno), 0); + else if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) + regmap_update_bits(ldb->regmap, SS_CTRL, + CH_HSYNC_M(chno), CH_PHSYNC(chno)); + + if (is_split && companion) + companion->funcs->mode_set(companion, mode, adjusted_mode); +} + +static void +imx8qxp_ldb_bridge_atomic_pre_enable(struct drm_bridge *bridge, + struct drm_bridge_state *old_bridge_state) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + struct ldb *ldb = ldb_ch->ldb; + struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb); + struct drm_bridge *companion = imx8qxp_ldb->companion; + bool is_split = ldb_channel_is_split_link(ldb_ch); + + clk_prepare_enable(imx8qxp_ldb->clk_pixel); + clk_prepare_enable(imx8qxp_ldb->clk_bypass); + + if (is_split && companion) + companion->funcs->atomic_pre_enable(companion, old_bridge_state); +} + +static void +imx8qxp_ldb_bridge_atomic_enable(struct drm_bridge *bridge, + struct drm_bridge_state *old_bridge_state) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + struct ldb *ldb = ldb_ch->ldb; + struct imx8qxp_ldb_channel *imx8qxp_ldb_ch = + base_to_imx8qxp_ldb_channel(ldb_ch); + struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb); + struct drm_bridge *companion = imx8qxp_ldb->companion; + struct device *dev = imx8qxp_ldb->dev; + bool is_split = ldb_channel_is_split_link(ldb_ch); + int ret; + + if (ldb_ch->chno == 0 || is_split) { + ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK; + ldb->ldb_ctrl |= imx8qxp_ldb_ch->di_id == 0 ? + LDB_CH0_MODE_EN_TO_DI0 : LDB_CH0_MODE_EN_TO_DI1; + } + if (ldb_ch->chno == 1 || is_split) { + ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK; + ldb->ldb_ctrl |= imx8qxp_ldb_ch->di_id == 0 ? + LDB_CH1_MODE_EN_TO_DI0 : LDB_CH1_MODE_EN_TO_DI1; + } + + ldb_bridge_enable_helper(bridge); + + ret = phy_power_on(imx8qxp_ldb_ch->phy); + if (ret) + DRM_DEV_ERROR(dev, "failed to power on PHY: %d\n", ret); + + if (is_split && companion) + companion->funcs->atomic_enable(companion, old_bridge_state); +} + +static void +imx8qxp_ldb_bridge_atomic_disable(struct drm_bridge *bridge, + struct drm_bridge_state *old_bridge_state) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + struct ldb *ldb = ldb_ch->ldb; + struct imx8qxp_ldb_channel *imx8qxp_ldb_ch = + base_to_imx8qxp_ldb_channel(ldb_ch); + struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb); + struct drm_bridge *companion = imx8qxp_ldb->companion; + struct device *dev = imx8qxp_ldb->dev; + bool is_split = ldb_channel_is_split_link(ldb_ch); + int ret; + + ret = phy_power_off(imx8qxp_ldb_ch->phy); + if (ret) + DRM_DEV_ERROR(dev, "failed to power off PHY: %d\n", ret); + + ret = phy_exit(imx8qxp_ldb_ch->phy); + if (ret < 0) + DRM_DEV_ERROR(dev, "failed to teardown PHY: %d\n", ret); + + ldb_bridge_disable_helper(bridge); + + clk_disable_unprepare(imx8qxp_ldb->clk_bypass); + clk_disable_unprepare(imx8qxp_ldb->clk_pixel); + + if (is_split && companion) + companion->funcs->atomic_disable(companion, old_bridge_state); + + ret = pm_runtime_put(dev); + if (ret < 0) + DRM_DEV_ERROR(dev, "failed to put runtime PM: %d\n", ret); +} + +static const u32 imx8qxp_ldb_bus_output_fmts[] = { + MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, + MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, + MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, + MEDIA_BUS_FMT_FIXED, +}; + +static bool imx8qxp_ldb_bus_output_fmt_supported(u32 fmt) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(imx8qxp_ldb_bus_output_fmts); i++) { + if (imx8qxp_ldb_bus_output_fmts[i] == fmt) + return true; + } + + return false; +} + +static u32 * +imx8qxp_ldb_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + u32 output_fmt, + unsigned int *num_input_fmts) +{ + struct drm_display_info *di; + const struct drm_format_info *finfo; + u32 *input_fmts; + + if (!imx8qxp_ldb_bus_output_fmt_supported(output_fmt)) + return NULL; + + *num_input_fmts = 1; + + input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL); + if (!input_fmts) + return NULL; + + switch (output_fmt) { + case MEDIA_BUS_FMT_FIXED: + di = &conn_state->connector->display_info; + + /* + * Look at the first bus format to determine input format. + * Default to MEDIA_BUS_FMT_RGB888_1X24, if no match. + */ + if (di->num_bus_formats) { + finfo = drm_format_info(di->bus_formats[0]); + + input_fmts[0] = finfo->depth == 18 ? + MEDIA_BUS_FMT_RGB666_1X24_CPADHI : + MEDIA_BUS_FMT_RGB888_1X24; + } else { + input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; + } + break; + case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: + input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X24_CPADHI; + break; + case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: + case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: + input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; + break; + default: + kfree(input_fmts); + input_fmts = NULL; + break; + } + + return input_fmts; +} + +static u32 * +imx8qxp_ldb_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + unsigned int *num_output_fmts) +{ + *num_output_fmts = ARRAY_SIZE(imx8qxp_ldb_bus_output_fmts); + return kmemdup(imx8qxp_ldb_bus_output_fmts, + sizeof(imx8qxp_ldb_bus_output_fmts), GFP_KERNEL); +} + +static enum drm_mode_status +imx8qxp_ldb_bridge_mode_valid(struct drm_bridge *bridge, + const struct drm_display_info *info, + const struct drm_display_mode *mode) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + bool is_single = ldb_channel_is_single_link(ldb_ch); + + if (mode->clock > 170000) + return MODE_CLOCK_HIGH; + + if (mode->clock > 150000 && is_single) + return MODE_CLOCK_HIGH; + + return MODE_OK; +} + +static const struct drm_bridge_funcs imx8qxp_ldb_bridge_funcs = { + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, + .atomic_reset = drm_atomic_helper_bridge_reset, + .mode_valid = imx8qxp_ldb_bridge_mode_valid, + .attach = ldb_bridge_attach_helper, + .atomic_check = imx8qxp_ldb_bridge_atomic_check, + .mode_set = imx8qxp_ldb_bridge_mode_set, + .atomic_pre_enable = imx8qxp_ldb_bridge_atomic_pre_enable, + .atomic_enable = imx8qxp_ldb_bridge_atomic_enable, + .atomic_disable = imx8qxp_ldb_bridge_atomic_disable, + .atomic_get_input_bus_fmts = + imx8qxp_ldb_bridge_atomic_get_input_bus_fmts, + .atomic_get_output_bus_fmts = + imx8qxp_ldb_bridge_atomic_get_output_bus_fmts, +}; + +static int imx8qxp_ldb_set_di_id(struct imx8qxp_ldb *imx8qxp_ldb) +{ + struct imx8qxp_ldb_channel *imx8qxp_ldb_ch = + &imx8qxp_ldb->channel[imx8qxp_ldb->active_chno]; + struct ldb_channel *ldb_ch = &imx8qxp_ldb_ch->base; + struct device_node *ep, *remote; + struct device *dev = imx8qxp_ldb->dev; + struct of_endpoint endpoint; + int ret; + + ep = of_graph_get_endpoint_by_regs(ldb_ch->np, 0, -1); + if (!ep) { + DRM_DEV_ERROR(dev, "failed to get port0 endpoint\n"); + return -EINVAL; + } + + remote = of_graph_get_remote_endpoint(ep); + of_node_put(ep); + if (!remote) { + DRM_DEV_ERROR(dev, "failed to get port0 remote endpoint\n"); + return -EINVAL; + } + + ret = of_graph_parse_endpoint(remote, &endpoint); + of_node_put(remote); + if (ret) { + DRM_DEV_ERROR(dev, "failed to parse port0 remote endpoint: %d\n", + ret); + return ret; + } + + imx8qxp_ldb_ch->di_id = endpoint.id; + + return 0; +} + +static int +imx8qxp_ldb_check_chno_and_dual_link(struct ldb_channel *ldb_ch, int link) +{ + if ((link == DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS && ldb_ch->chno != 0) || + (link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS && ldb_ch->chno != 1)) + return -EINVAL; + + return 0; +} + +static int imx8qxp_ldb_parse_dt_companion(struct imx8qxp_ldb *imx8qxp_ldb) +{ + struct imx8qxp_ldb_channel *imx8qxp_ldb_ch = + &imx8qxp_ldb->channel[imx8qxp_ldb->active_chno]; + struct ldb_channel *ldb_ch = &imx8qxp_ldb_ch->base; + struct ldb_channel *companion_ldb_ch; + struct device_node *companion; + struct device_node *child; + struct device_node *companion_port = NULL; + struct device_node *port1, *port2; + struct device *dev = imx8qxp_ldb->dev; + const struct of_device_id *match; + u32 i; + int dual_link; + int ret; + + /* Locate the companion LDB for dual-link operation, if any. */ + companion = of_parse_phandle(dev->of_node, "fsl,companion-ldb", 0); + if (!companion) + return 0; + + if (!of_device_is_available(companion)) { + DRM_DEV_ERROR(dev, "companion LDB is not available\n"); + ret = -ENODEV; + goto out; + } + + /* + * Sanity check: the companion bridge must have the same compatible + * string. + */ + match = of_match_device(dev->driver->of_match_table, dev); + if (!of_device_is_compatible(companion, match->compatible)) { + DRM_DEV_ERROR(dev, "companion LDB is incompatible\n"); + ret = -ENXIO; + goto out; + } + + for_each_available_child_of_node(companion, child) { + ret = of_property_read_u32(child, "reg", &i); + if (ret || i > MAX_LDB_CHAN_NUM - 1) { + DRM_DEV_ERROR(dev, + "invalid channel node address: %u\n", i); + ret = -EINVAL; + of_node_put(child); + goto out; + } + + /* + * Channel numbers have to be different, because channel0 + * transmits odd pixels and channel1 transmits even pixels. + */ + if (i == (ldb_ch->chno ^ 0x1)) { + companion_port = child; + break; + } + } + + if (!companion_port) { + DRM_DEV_ERROR(dev, + "failed to find companion LDB channel port\n"); + ret = -EINVAL; + goto out; + } + + /* + * We need to work out if the sink is expecting us to function in + * dual-link mode. We do this by looking at the DT port nodes we are + * connected to. If they are marked as expecting odd pixels and + * even pixels than we need to enable LDB split mode. + */ + port1 = of_graph_get_port_by_id(ldb_ch->np, 1); + port2 = of_graph_get_port_by_id(companion_port, 1); + dual_link = drm_of_lvds_get_dual_link_pixel_order(port1, port2); + of_node_put(port1); + of_node_put(port2); + + switch (dual_link) { + case DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS: + ldb_ch->link_type = LDB_CH_DUAL_LINK_ODD_EVEN_PIXELS; + break; + case DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS: + ldb_ch->link_type = LDB_CH_DUAL_LINK_EVEN_ODD_PIXELS; + break; + default: + ret = dual_link; + DRM_DEV_ERROR(dev, + "failed to get dual link pixel order: %d\n", ret); + goto out; + } + + ret = imx8qxp_ldb_check_chno_and_dual_link(ldb_ch, dual_link); + if (ret < 0) { + DRM_DEV_ERROR(dev, + "unmatched channel number(%u) vs dual link(%d)\n", + ldb_ch->chno, dual_link); + goto out; + } + + imx8qxp_ldb->companion = of_drm_find_bridge(companion_port); + if (!imx8qxp_ldb->companion) { + ret = -EPROBE_DEFER; + DRM_DEV_DEBUG_DRIVER(dev, + "failed to find bridge for companion bridge: %d\n", + ret); + goto out; + } + + DRM_DEV_DEBUG_DRIVER(dev, + "dual-link configuration detected (companion bridge %pOF)\n", + companion); + + companion_ldb_ch = bridge_to_ldb_ch(imx8qxp_ldb->companion); + companion_ldb_ch->link_type = ldb_ch->link_type; +out: + of_node_put(companion_port); + of_node_put(companion); + return ret; +} + +static int imx8qxp_ldb_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct imx8qxp_ldb *imx8qxp_ldb; + struct imx8qxp_ldb_channel *imx8qxp_ldb_ch; + struct ldb *ldb; + struct ldb_channel *ldb_ch; + int ret, i; + + imx8qxp_ldb = devm_kzalloc(dev, sizeof(*imx8qxp_ldb), GFP_KERNEL); + if (!imx8qxp_ldb) + return -ENOMEM; + + imx8qxp_ldb->clk_pixel = devm_clk_get(dev, "pixel"); + if (IS_ERR(imx8qxp_ldb->clk_pixel)) { + ret = PTR_ERR(imx8qxp_ldb->clk_pixel); + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(dev, + "failed to get pixel clock: %d\n", ret); + return ret; + } + + imx8qxp_ldb->clk_bypass = devm_clk_get(dev, "bypass"); + if (IS_ERR(imx8qxp_ldb->clk_bypass)) { + ret = PTR_ERR(imx8qxp_ldb->clk_bypass); + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(dev, + "failed to get bypass clock: %d\n", ret); + return ret; + } + + imx8qxp_ldb->dev = dev; + + ldb = &imx8qxp_ldb->base; + ldb->dev = dev; + ldb->ctrl_reg = 0xe0; + + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) + ldb->channel[i] = &imx8qxp_ldb->channel[i].base; + + ret = ldb_init_helper(ldb); + if (ret) + return ret; + + if (ldb->available_ch_cnt == 0) { + DRM_DEV_DEBUG_DRIVER(dev, "no available channel\n"); + return 0; + } else if (ldb->available_ch_cnt > 1) { + DRM_DEV_ERROR(dev, "invalid available channel number(%u)\n", + ldb->available_ch_cnt); + return -EINVAL; + } + + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) { + imx8qxp_ldb_ch = &imx8qxp_ldb->channel[i]; + ldb_ch = &imx8qxp_ldb_ch->base; + + if (ldb_ch->is_available) { + imx8qxp_ldb->active_chno = ldb_ch->chno; + break; + } + } + + imx8qxp_ldb_ch->phy = devm_of_phy_get(dev, ldb_ch->np, "lvds_phy"); + if (IS_ERR(imx8qxp_ldb_ch->phy)) { + ret = PTR_ERR(imx8qxp_ldb_ch->phy); + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(dev, "failed to get channel%d PHY: %d\n", + imx8qxp_ldb->active_chno, ret); + return ret; + } + + ret = ldb_find_next_bridge_helper(ldb); + if (ret) + return ret; + + ret = imx8qxp_ldb_set_di_id(imx8qxp_ldb); + if (ret) + return ret; + + ret = imx8qxp_ldb_parse_dt_companion(imx8qxp_ldb); + if (ret) + return ret; + + platform_set_drvdata(pdev, imx8qxp_ldb); + pm_runtime_enable(dev); + + ldb_add_bridge_helper(ldb, &imx8qxp_ldb_bridge_funcs); + + return ret; +} + +static int imx8qxp_ldb_remove(struct platform_device *pdev) +{ + struct imx8qxp_ldb *imx8qxp_ldb = platform_get_drvdata(pdev); + struct ldb *ldb = &imx8qxp_ldb->base; + + ldb_remove_bridge_helper(ldb); + + pm_runtime_disable(&pdev->dev); + + return 0; +} + +static int __maybe_unused imx8qxp_ldb_runtime_suspend(struct device *dev) +{ + return 0; +} + +static int __maybe_unused imx8qxp_ldb_runtime_resume(struct device *dev) +{ + struct imx8qxp_ldb *imx8qxp_ldb = dev_get_drvdata(dev); + struct ldb *ldb = &imx8qxp_ldb->base; + + /* disable LDB by resetting the control register to POR default */ + regmap_write(ldb->regmap, ldb->ctrl_reg, 0); + + return 0; +} + +static const struct dev_pm_ops imx8qxp_ldb_pm_ops = { + SET_RUNTIME_PM_OPS(imx8qxp_ldb_runtime_suspend, + imx8qxp_ldb_runtime_resume, NULL) +}; + +static const struct of_device_id imx8qxp_ldb_dt_ids[] = { + { .compatible = "fsl,imx8qxp-ldb" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx8qxp_ldb_dt_ids); + +static struct platform_driver imx8qxp_ldb_driver = { + .probe = imx8qxp_ldb_probe, + .remove = imx8qxp_ldb_remove, + .driver = { + .pm = &imx8qxp_ldb_pm_ops, + .name = DRIVER_NAME, + .of_match_table = imx8qxp_ldb_dt_ids, + }, +}; +module_platform_driver(imx8qxp_ldb_driver); + +MODULE_DESCRIPTION("i.MX8QXP LVDS Display Bridge(LDB)/Pixel Mapper bridge driver"); +MODULE_AUTHOR("Liu Ying <victor.liu@nxp.com>"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRIVER_NAME); diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c new file mode 100644 index 000000000..503bd8db8 --- /dev/null +++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c @@ -0,0 +1,450 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include <linux/bitfield.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/media-bus-format.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_graph.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> + +#include <drm/drm_atomic_state_helper.h> +#include <drm/drm_bridge.h> +#include <drm/drm_print.h> + +#define PC_CTRL_REG 0x0 +#define PC_COMBINE_ENABLE BIT(0) +#define PC_DISP_BYPASS(n) BIT(1 + 21 * (n)) +#define PC_DISP_HSYNC_POLARITY(n) BIT(2 + 11 * (n)) +#define PC_DISP_HSYNC_POLARITY_POS(n) DISP_HSYNC_POLARITY(n) +#define PC_DISP_VSYNC_POLARITY(n) BIT(3 + 11 * (n)) +#define PC_DISP_VSYNC_POLARITY_POS(n) DISP_VSYNC_POLARITY(n) +#define PC_DISP_DVALID_POLARITY(n) BIT(4 + 11 * (n)) +#define PC_DISP_DVALID_POLARITY_POS(n) DISP_DVALID_POLARITY(n) +#define PC_VSYNC_MASK_ENABLE BIT(5) +#define PC_SKIP_MODE BIT(6) +#define PC_SKIP_NUMBER_MASK GENMASK(12, 7) +#define PC_SKIP_NUMBER(n) FIELD_PREP(PC_SKIP_NUMBER_MASK, (n)) +#define PC_DISP0_PIX_DATA_FORMAT_MASK GENMASK(18, 16) +#define PC_DISP0_PIX_DATA_FORMAT(fmt) \ + FIELD_PREP(PC_DISP0_PIX_DATA_FORMAT_MASK, (fmt)) +#define PC_DISP1_PIX_DATA_FORMAT_MASK GENMASK(21, 19) +#define PC_DISP1_PIX_DATA_FORMAT(fmt) \ + FIELD_PREP(PC_DISP1_PIX_DATA_FORMAT_MASK, (fmt)) + +#define PC_SW_RESET_REG 0x20 +#define PC_SW_RESET_N BIT(0) +#define PC_DISP_SW_RESET_N(n) BIT(1 + (n)) +#define PC_FULL_RESET_N (PC_SW_RESET_N | \ + PC_DISP_SW_RESET_N(0) | \ + PC_DISP_SW_RESET_N(1)) + +#define PC_REG_SET 0x4 +#define PC_REG_CLR 0x8 + +#define DRIVER_NAME "imx8qxp-pixel-combiner" + +enum imx8qxp_pc_pix_data_format { + RGB, + YUV444, + YUV422, + SPLIT_RGB, +}; + +struct imx8qxp_pc_channel { + struct drm_bridge bridge; + struct drm_bridge *next_bridge; + struct imx8qxp_pc *pc; + unsigned int stream_id; + bool is_available; +}; + +struct imx8qxp_pc { + struct device *dev; + struct imx8qxp_pc_channel ch[2]; + struct clk *clk_apb; + void __iomem *base; +}; + +static inline u32 imx8qxp_pc_read(struct imx8qxp_pc *pc, unsigned int offset) +{ + return readl(pc->base + offset); +} + +static inline void +imx8qxp_pc_write(struct imx8qxp_pc *pc, unsigned int offset, u32 value) +{ + writel(value, pc->base + offset); +} + +static inline void +imx8qxp_pc_write_set(struct imx8qxp_pc *pc, unsigned int offset, u32 value) +{ + imx8qxp_pc_write(pc, offset + PC_REG_SET, value); +} + +static inline void +imx8qxp_pc_write_clr(struct imx8qxp_pc *pc, unsigned int offset, u32 value) +{ + imx8qxp_pc_write(pc, offset + PC_REG_CLR, value); +} + +static enum drm_mode_status +imx8qxp_pc_bridge_mode_valid(struct drm_bridge *bridge, + const struct drm_display_info *info, + const struct drm_display_mode *mode) +{ + if (mode->hdisplay > 2560) + return MODE_BAD_HVALUE; + + return MODE_OK; +} + +static int imx8qxp_pc_bridge_attach(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags) +{ + struct imx8qxp_pc_channel *ch = bridge->driver_private; + struct imx8qxp_pc *pc = ch->pc; + + if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) { + DRM_DEV_ERROR(pc->dev, + "do not support creating a drm_connector\n"); + return -EINVAL; + } + + if (!bridge->encoder) { + DRM_DEV_ERROR(pc->dev, "missing encoder\n"); + return -ENODEV; + } + + return drm_bridge_attach(bridge->encoder, + ch->next_bridge, bridge, + DRM_BRIDGE_ATTACH_NO_CONNECTOR); +} + +static void +imx8qxp_pc_bridge_mode_set(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + const struct drm_display_mode *adjusted_mode) +{ + struct imx8qxp_pc_channel *ch = bridge->driver_private; + struct imx8qxp_pc *pc = ch->pc; + u32 val; + int ret; + + ret = pm_runtime_get_sync(pc->dev); + if (ret < 0) + DRM_DEV_ERROR(pc->dev, + "failed to get runtime PM sync: %d\n", ret); + + ret = clk_prepare_enable(pc->clk_apb); + if (ret) + DRM_DEV_ERROR(pc->dev, "%s: failed to enable apb clock: %d\n", + __func__, ret); + + /* HSYNC to pixel link is active low. */ + imx8qxp_pc_write_clr(pc, PC_CTRL_REG, + PC_DISP_HSYNC_POLARITY(ch->stream_id)); + + /* VSYNC to pixel link is active low. */ + imx8qxp_pc_write_clr(pc, PC_CTRL_REG, + PC_DISP_VSYNC_POLARITY(ch->stream_id)); + + /* Data enable to pixel link is active high. */ + imx8qxp_pc_write_set(pc, PC_CTRL_REG, + PC_DISP_DVALID_POLARITY(ch->stream_id)); + + /* Mask the first frame output which may be incomplete. */ + imx8qxp_pc_write_set(pc, PC_CTRL_REG, PC_VSYNC_MASK_ENABLE); + + /* Only support RGB currently. */ + val = imx8qxp_pc_read(pc, PC_CTRL_REG); + if (ch->stream_id == 0) { + val &= ~PC_DISP0_PIX_DATA_FORMAT_MASK; + val |= PC_DISP0_PIX_DATA_FORMAT(RGB); + } else { + val &= ~PC_DISP1_PIX_DATA_FORMAT_MASK; + val |= PC_DISP1_PIX_DATA_FORMAT(RGB); + } + imx8qxp_pc_write(pc, PC_CTRL_REG, val); + + /* Only support bypass mode currently. */ + imx8qxp_pc_write_set(pc, PC_CTRL_REG, PC_DISP_BYPASS(ch->stream_id)); + + clk_disable_unprepare(pc->clk_apb); +} + +static void +imx8qxp_pc_bridge_atomic_disable(struct drm_bridge *bridge, + struct drm_bridge_state *old_bridge_state) +{ + struct imx8qxp_pc_channel *ch = bridge->driver_private; + struct imx8qxp_pc *pc = ch->pc; + int ret; + + ret = pm_runtime_put(pc->dev); + if (ret < 0) + DRM_DEV_ERROR(pc->dev, "failed to put runtime PM: %d\n", ret); +} + +static const u32 imx8qxp_pc_bus_output_fmts[] = { + MEDIA_BUS_FMT_RGB888_1X36_CPADLO, + MEDIA_BUS_FMT_RGB666_1X36_CPADLO, +}; + +static bool imx8qxp_pc_bus_output_fmt_supported(u32 fmt) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(imx8qxp_pc_bus_output_fmts); i++) { + if (imx8qxp_pc_bus_output_fmts[i] == fmt) + return true; + } + + return false; +} + +static u32 * +imx8qxp_pc_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + u32 output_fmt, + unsigned int *num_input_fmts) +{ + u32 *input_fmts; + + if (!imx8qxp_pc_bus_output_fmt_supported(output_fmt)) + return NULL; + + *num_input_fmts = 1; + + input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL); + if (!input_fmts) + return NULL; + + switch (output_fmt) { + case MEDIA_BUS_FMT_RGB888_1X36_CPADLO: + input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X30_CPADLO; + break; + case MEDIA_BUS_FMT_RGB666_1X36_CPADLO: + input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X30_CPADLO; + break; + default: + kfree(input_fmts); + input_fmts = NULL; + break; + } + + return input_fmts; +} + +static u32 * +imx8qxp_pc_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + unsigned int *num_output_fmts) +{ + *num_output_fmts = ARRAY_SIZE(imx8qxp_pc_bus_output_fmts); + return kmemdup(imx8qxp_pc_bus_output_fmts, + sizeof(imx8qxp_pc_bus_output_fmts), GFP_KERNEL); +} + +static const struct drm_bridge_funcs imx8qxp_pc_bridge_funcs = { + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, + .atomic_reset = drm_atomic_helper_bridge_reset, + .mode_valid = imx8qxp_pc_bridge_mode_valid, + .attach = imx8qxp_pc_bridge_attach, + .mode_set = imx8qxp_pc_bridge_mode_set, + .atomic_disable = imx8qxp_pc_bridge_atomic_disable, + .atomic_get_input_bus_fmts = + imx8qxp_pc_bridge_atomic_get_input_bus_fmts, + .atomic_get_output_bus_fmts = + imx8qxp_pc_bridge_atomic_get_output_bus_fmts, +}; + +static int imx8qxp_pc_bridge_probe(struct platform_device *pdev) +{ + struct imx8qxp_pc *pc; + struct imx8qxp_pc_channel *ch; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct device_node *child, *remote; + u32 i; + int ret; + + pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL); + if (!pc) + return -ENOMEM; + + pc->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pc->base)) + return PTR_ERR(pc->base); + + pc->dev = dev; + + pc->clk_apb = devm_clk_get(dev, "apb"); + if (IS_ERR(pc->clk_apb)) { + ret = PTR_ERR(pc->clk_apb); + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(dev, "failed to get apb clock: %d\n", ret); + return ret; + } + + platform_set_drvdata(pdev, pc); + pm_runtime_enable(dev); + + for_each_available_child_of_node(np, child) { + ret = of_property_read_u32(child, "reg", &i); + if (ret || i > 1) { + ret = -EINVAL; + DRM_DEV_ERROR(dev, + "invalid channel(%u) node address\n", i); + goto free_child; + } + + ch = &pc->ch[i]; + ch->pc = pc; + ch->stream_id = i; + + remote = of_graph_get_remote_node(child, 1, 0); + if (!remote) { + ret = -ENODEV; + DRM_DEV_ERROR(dev, + "channel%u failed to get port1's remote node: %d\n", + i, ret); + goto free_child; + } + + ch->next_bridge = of_drm_find_bridge(remote); + if (!ch->next_bridge) { + of_node_put(remote); + ret = -EPROBE_DEFER; + DRM_DEV_DEBUG_DRIVER(dev, + "channel%u failed to find next bridge: %d\n", + i, ret); + goto free_child; + } + + of_node_put(remote); + + ch->bridge.driver_private = ch; + ch->bridge.funcs = &imx8qxp_pc_bridge_funcs; + ch->bridge.of_node = child; + ch->is_available = true; + + drm_bridge_add(&ch->bridge); + } + + return 0; + +free_child: + of_node_put(child); + + if (i == 1 && pc->ch[0].next_bridge) + drm_bridge_remove(&pc->ch[0].bridge); + + pm_runtime_disable(dev); + return ret; +} + +static int imx8qxp_pc_bridge_remove(struct platform_device *pdev) +{ + struct imx8qxp_pc *pc = platform_get_drvdata(pdev); + struct imx8qxp_pc_channel *ch; + int i; + + for (i = 0; i < 2; i++) { + ch = &pc->ch[i]; + + if (!ch->is_available) + continue; + + drm_bridge_remove(&ch->bridge); + ch->is_available = false; + } + + pm_runtime_disable(&pdev->dev); + + return 0; +} + +static int __maybe_unused imx8qxp_pc_runtime_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct imx8qxp_pc *pc = platform_get_drvdata(pdev); + int ret; + + ret = clk_prepare_enable(pc->clk_apb); + if (ret) + DRM_DEV_ERROR(pc->dev, "%s: failed to enable apb clock: %d\n", + __func__, ret); + + /* Disable pixel combiner by full reset. */ + imx8qxp_pc_write_clr(pc, PC_SW_RESET_REG, PC_FULL_RESET_N); + + clk_disable_unprepare(pc->clk_apb); + + /* Ensure the reset takes effect. */ + usleep_range(10, 20); + + return ret; +} + +static int __maybe_unused imx8qxp_pc_runtime_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct imx8qxp_pc *pc = platform_get_drvdata(pdev); + int ret; + + ret = clk_prepare_enable(pc->clk_apb); + if (ret) { + DRM_DEV_ERROR(pc->dev, "%s: failed to enable apb clock: %d\n", + __func__, ret); + return ret; + } + + /* out of reset */ + imx8qxp_pc_write_set(pc, PC_SW_RESET_REG, PC_FULL_RESET_N); + + clk_disable_unprepare(pc->clk_apb); + + return ret; +} + +static const struct dev_pm_ops imx8qxp_pc_pm_ops = { + SET_RUNTIME_PM_OPS(imx8qxp_pc_runtime_suspend, + imx8qxp_pc_runtime_resume, NULL) +}; + +static const struct of_device_id imx8qxp_pc_dt_ids[] = { + { .compatible = "fsl,imx8qm-pixel-combiner", }, + { .compatible = "fsl,imx8qxp-pixel-combiner", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx8qxp_pc_dt_ids); + +static struct platform_driver imx8qxp_pc_bridge_driver = { + .probe = imx8qxp_pc_bridge_probe, + .remove = imx8qxp_pc_bridge_remove, + .driver = { + .pm = &imx8qxp_pc_pm_ops, + .name = DRIVER_NAME, + .of_match_table = imx8qxp_pc_dt_ids, + }, +}; +module_platform_driver(imx8qxp_pc_bridge_driver); + +MODULE_DESCRIPTION("i.MX8QM/QXP pixel combiner bridge driver"); +MODULE_AUTHOR("Liu Ying <victor.liu@nxp.com>"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRIVER_NAME); diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c new file mode 100644 index 000000000..9e5f2b4dc --- /dev/null +++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c @@ -0,0 +1,430 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020,2022 NXP + */ + +#include <linux/firmware/imx/svc/misc.h> +#include <linux/media-bus-format.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_graph.h> +#include <linux/platform_device.h> + +#include <drm/drm_atomic_state_helper.h> +#include <drm/drm_bridge.h> +#include <drm/drm_print.h> + +#include <dt-bindings/firmware/imx/rsrc.h> + +#define DRIVER_NAME "imx8qxp-display-pixel-link" +#define PL_MAX_MST_ADDR 3 +#define PL_MAX_NEXT_BRIDGES 2 + +struct imx8qxp_pixel_link { + struct drm_bridge bridge; + struct drm_bridge *next_bridge; + struct device *dev; + struct imx_sc_ipc *ipc_handle; + u8 stream_id; + u8 dc_id; + u32 sink_rsc; + u32 mst_addr; + u8 mst_addr_ctrl; + u8 mst_en_ctrl; + u8 mst_vld_ctrl; + u8 sync_ctrl; +}; + +static void imx8qxp_pixel_link_enable_mst_en(struct imx8qxp_pixel_link *pl) +{ + int ret; + + ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc, + pl->mst_en_ctrl, true); + if (ret) + DRM_DEV_ERROR(pl->dev, + "failed to enable DC%u stream%u pixel link mst_en: %d\n", + pl->dc_id, pl->stream_id, ret); +} + +static void imx8qxp_pixel_link_enable_mst_vld(struct imx8qxp_pixel_link *pl) +{ + int ret; + + ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc, + pl->mst_vld_ctrl, true); + if (ret) + DRM_DEV_ERROR(pl->dev, + "failed to enable DC%u stream%u pixel link mst_vld: %d\n", + pl->dc_id, pl->stream_id, ret); +} + +static void imx8qxp_pixel_link_enable_sync(struct imx8qxp_pixel_link *pl) +{ + int ret; + + ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc, + pl->sync_ctrl, true); + if (ret) + DRM_DEV_ERROR(pl->dev, + "failed to enable DC%u stream%u pixel link sync: %d\n", + pl->dc_id, pl->stream_id, ret); +} + +static int imx8qxp_pixel_link_disable_mst_en(struct imx8qxp_pixel_link *pl) +{ + int ret; + + ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc, + pl->mst_en_ctrl, false); + if (ret) + DRM_DEV_ERROR(pl->dev, + "failed to disable DC%u stream%u pixel link mst_en: %d\n", + pl->dc_id, pl->stream_id, ret); + + return ret; +} + +static int imx8qxp_pixel_link_disable_mst_vld(struct imx8qxp_pixel_link *pl) +{ + int ret; + + ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc, + pl->mst_vld_ctrl, false); + if (ret) + DRM_DEV_ERROR(pl->dev, + "failed to disable DC%u stream%u pixel link mst_vld: %d\n", + pl->dc_id, pl->stream_id, ret); + + return ret; +} + +static int imx8qxp_pixel_link_disable_sync(struct imx8qxp_pixel_link *pl) +{ + int ret; + + ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc, + pl->sync_ctrl, false); + if (ret) + DRM_DEV_ERROR(pl->dev, + "failed to disable DC%u stream%u pixel link sync: %d\n", + pl->dc_id, pl->stream_id, ret); + + return ret; +} + +static void imx8qxp_pixel_link_set_mst_addr(struct imx8qxp_pixel_link *pl) +{ + int ret; + + ret = imx_sc_misc_set_control(pl->ipc_handle, + pl->sink_rsc, pl->mst_addr_ctrl, + pl->mst_addr); + if (ret) + DRM_DEV_ERROR(pl->dev, + "failed to set DC%u stream%u pixel link mst addr(%u): %d\n", + pl->dc_id, pl->stream_id, pl->mst_addr, ret); +} + +static int imx8qxp_pixel_link_bridge_attach(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags) +{ + struct imx8qxp_pixel_link *pl = bridge->driver_private; + + if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) { + DRM_DEV_ERROR(pl->dev, + "do not support creating a drm_connector\n"); + return -EINVAL; + } + + if (!bridge->encoder) { + DRM_DEV_ERROR(pl->dev, "missing encoder\n"); + return -ENODEV; + } + + return drm_bridge_attach(bridge->encoder, + pl->next_bridge, bridge, + DRM_BRIDGE_ATTACH_NO_CONNECTOR); +} + +static void +imx8qxp_pixel_link_bridge_mode_set(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + const struct drm_display_mode *adjusted_mode) +{ + struct imx8qxp_pixel_link *pl = bridge->driver_private; + + imx8qxp_pixel_link_set_mst_addr(pl); +} + +static void +imx8qxp_pixel_link_bridge_atomic_enable(struct drm_bridge *bridge, + struct drm_bridge_state *old_bridge_state) +{ + struct imx8qxp_pixel_link *pl = bridge->driver_private; + + imx8qxp_pixel_link_enable_mst_en(pl); + imx8qxp_pixel_link_enable_mst_vld(pl); + imx8qxp_pixel_link_enable_sync(pl); +} + +static void +imx8qxp_pixel_link_bridge_atomic_disable(struct drm_bridge *bridge, + struct drm_bridge_state *old_bridge_state) +{ + struct imx8qxp_pixel_link *pl = bridge->driver_private; + + imx8qxp_pixel_link_disable_mst_en(pl); + imx8qxp_pixel_link_disable_mst_vld(pl); + imx8qxp_pixel_link_disable_sync(pl); +} + +static const u32 imx8qxp_pixel_link_bus_output_fmts[] = { + MEDIA_BUS_FMT_RGB888_1X36_CPADLO, + MEDIA_BUS_FMT_RGB666_1X36_CPADLO, +}; + +static bool imx8qxp_pixel_link_bus_output_fmt_supported(u32 fmt) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(imx8qxp_pixel_link_bus_output_fmts); i++) { + if (imx8qxp_pixel_link_bus_output_fmts[i] == fmt) + return true; + } + + return false; +} + +static u32 * +imx8qxp_pixel_link_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + u32 output_fmt, + unsigned int *num_input_fmts) +{ + u32 *input_fmts; + + if (!imx8qxp_pixel_link_bus_output_fmt_supported(output_fmt)) + return NULL; + + *num_input_fmts = 1; + + input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL); + if (!input_fmts) + return NULL; + + input_fmts[0] = output_fmt; + + return input_fmts; +} + +static u32 * +imx8qxp_pixel_link_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + unsigned int *num_output_fmts) +{ + *num_output_fmts = ARRAY_SIZE(imx8qxp_pixel_link_bus_output_fmts); + return kmemdup(imx8qxp_pixel_link_bus_output_fmts, + sizeof(imx8qxp_pixel_link_bus_output_fmts), GFP_KERNEL); +} + +static const struct drm_bridge_funcs imx8qxp_pixel_link_bridge_funcs = { + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, + .atomic_reset = drm_atomic_helper_bridge_reset, + .attach = imx8qxp_pixel_link_bridge_attach, + .mode_set = imx8qxp_pixel_link_bridge_mode_set, + .atomic_enable = imx8qxp_pixel_link_bridge_atomic_enable, + .atomic_disable = imx8qxp_pixel_link_bridge_atomic_disable, + .atomic_get_input_bus_fmts = + imx8qxp_pixel_link_bridge_atomic_get_input_bus_fmts, + .atomic_get_output_bus_fmts = + imx8qxp_pixel_link_bridge_atomic_get_output_bus_fmts, +}; + +static int imx8qxp_pixel_link_disable_all_controls(struct imx8qxp_pixel_link *pl) +{ + int ret; + + ret = imx8qxp_pixel_link_disable_mst_en(pl); + if (ret) + return ret; + + ret = imx8qxp_pixel_link_disable_mst_vld(pl); + if (ret) + return ret; + + return imx8qxp_pixel_link_disable_sync(pl); +} + +static struct drm_bridge * +imx8qxp_pixel_link_find_next_bridge(struct imx8qxp_pixel_link *pl) +{ + struct device_node *np = pl->dev->of_node; + struct device_node *port, *remote; + struct drm_bridge *next_bridge[PL_MAX_NEXT_BRIDGES]; + u32 port_id; + bool found_port = false; + int reg, ep_cnt = 0; + /* select the first next bridge by default */ + int bridge_sel = 0; + + for (port_id = 1; port_id <= PL_MAX_MST_ADDR + 1; port_id++) { + port = of_graph_get_port_by_id(np, port_id); + if (!port) + continue; + + if (of_device_is_available(port)) { + found_port = true; + of_node_put(port); + break; + } + + of_node_put(port); + } + + if (!found_port) { + DRM_DEV_ERROR(pl->dev, "no available output port\n"); + return ERR_PTR(-ENODEV); + } + + for (reg = 0; reg < PL_MAX_NEXT_BRIDGES; reg++) { + remote = of_graph_get_remote_node(np, port_id, reg); + if (!remote) + continue; + + if (!of_device_is_available(remote->parent)) { + DRM_DEV_DEBUG(pl->dev, + "port%u endpoint%u remote parent is not available\n", + port_id, reg); + of_node_put(remote); + continue; + } + + next_bridge[ep_cnt] = of_drm_find_bridge(remote); + if (!next_bridge[ep_cnt]) { + of_node_put(remote); + return ERR_PTR(-EPROBE_DEFER); + } + + /* specially select the next bridge with companion PXL2DPI */ + if (of_find_property(remote, "fsl,companion-pxl2dpi", NULL)) + bridge_sel = ep_cnt; + + ep_cnt++; + + of_node_put(remote); + } + + pl->mst_addr = port_id - 1; + + return next_bridge[bridge_sel]; +} + +static int imx8qxp_pixel_link_bridge_probe(struct platform_device *pdev) +{ + struct imx8qxp_pixel_link *pl; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + int ret; + + pl = devm_kzalloc(dev, sizeof(*pl), GFP_KERNEL); + if (!pl) + return -ENOMEM; + + ret = imx_scu_get_handle(&pl->ipc_handle); + if (ret) { + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(dev, "failed to get SCU ipc handle: %d\n", + ret); + return ret; + } + + ret = of_property_read_u8(np, "fsl,dc-id", &pl->dc_id); + if (ret) { + DRM_DEV_ERROR(dev, "failed to get DC index: %d\n", ret); + return ret; + } + + ret = of_property_read_u8(np, "fsl,dc-stream-id", &pl->stream_id); + if (ret) { + DRM_DEV_ERROR(dev, "failed to get DC stream index: %d\n", ret); + return ret; + } + + pl->dev = dev; + + pl->sink_rsc = pl->dc_id ? IMX_SC_R_DC_1 : IMX_SC_R_DC_0; + + if (pl->stream_id == 0) { + pl->mst_addr_ctrl = IMX_SC_C_PXL_LINK_MST1_ADDR; + pl->mst_en_ctrl = IMX_SC_C_PXL_LINK_MST1_ENB; + pl->mst_vld_ctrl = IMX_SC_C_PXL_LINK_MST1_VLD; + pl->sync_ctrl = IMX_SC_C_SYNC_CTRL0; + } else { + pl->mst_addr_ctrl = IMX_SC_C_PXL_LINK_MST2_ADDR; + pl->mst_en_ctrl = IMX_SC_C_PXL_LINK_MST2_ENB; + pl->mst_vld_ctrl = IMX_SC_C_PXL_LINK_MST2_VLD; + pl->sync_ctrl = IMX_SC_C_SYNC_CTRL1; + } + + /* disable all controls to POR default */ + ret = imx8qxp_pixel_link_disable_all_controls(pl); + if (ret) + return ret; + + pl->next_bridge = imx8qxp_pixel_link_find_next_bridge(pl); + if (IS_ERR(pl->next_bridge)) { + ret = PTR_ERR(pl->next_bridge); + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(dev, "failed to find next bridge: %d\n", + ret); + return ret; + } + + platform_set_drvdata(pdev, pl); + + pl->bridge.driver_private = pl; + pl->bridge.funcs = &imx8qxp_pixel_link_bridge_funcs; + pl->bridge.of_node = np; + + drm_bridge_add(&pl->bridge); + + return ret; +} + +static int imx8qxp_pixel_link_bridge_remove(struct platform_device *pdev) +{ + struct imx8qxp_pixel_link *pl = platform_get_drvdata(pdev); + + drm_bridge_remove(&pl->bridge); + + return 0; +} + +static const struct of_device_id imx8qxp_pixel_link_dt_ids[] = { + { .compatible = "fsl,imx8qm-dc-pixel-link", }, + { .compatible = "fsl,imx8qxp-dc-pixel-link", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx8qxp_pixel_link_dt_ids); + +static struct platform_driver imx8qxp_pixel_link_bridge_driver = { + .probe = imx8qxp_pixel_link_bridge_probe, + .remove = imx8qxp_pixel_link_bridge_remove, + .driver = { + .of_match_table = imx8qxp_pixel_link_dt_ids, + .name = DRIVER_NAME, + }, +}; +module_platform_driver(imx8qxp_pixel_link_bridge_driver); + +MODULE_DESCRIPTION("i.MX8QXP/QM display pixel link bridge driver"); +MODULE_AUTHOR("Liu Ying <victor.liu@nxp.com>"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRIVER_NAME); diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c b/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c new file mode 100644 index 000000000..d0fec82f0 --- /dev/null +++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c @@ -0,0 +1,488 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2020 NXP + */ + +#include <linux/firmware/imx/svc/misc.h> +#include <linux/media-bus-format.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/of_graph.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h> + +#include <drm/drm_atomic_state_helper.h> +#include <drm/drm_bridge.h> +#include <drm/drm_of.h> +#include <drm/drm_print.h> + +#include <dt-bindings/firmware/imx/rsrc.h> + +#define PXL2DPI_CTRL 0x40 +#define CFG1_16BIT 0x0 +#define CFG2_16BIT 0x1 +#define CFG3_16BIT 0x2 +#define CFG1_18BIT 0x3 +#define CFG2_18BIT 0x4 +#define CFG_24BIT 0x5 + +#define DRIVER_NAME "imx8qxp-pxl2dpi" + +struct imx8qxp_pxl2dpi { + struct regmap *regmap; + struct drm_bridge bridge; + struct drm_bridge *next_bridge; + struct drm_bridge *companion; + struct device *dev; + struct imx_sc_ipc *ipc_handle; + u32 sc_resource; + u32 in_bus_format; + u32 out_bus_format; + u32 pl_sel; +}; + +#define bridge_to_p2d(b) container_of(b, struct imx8qxp_pxl2dpi, bridge) + +static int imx8qxp_pxl2dpi_bridge_attach(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags) +{ + struct imx8qxp_pxl2dpi *p2d = bridge->driver_private; + + if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) { + DRM_DEV_ERROR(p2d->dev, + "do not support creating a drm_connector\n"); + return -EINVAL; + } + + if (!bridge->encoder) { + DRM_DEV_ERROR(p2d->dev, "missing encoder\n"); + return -ENODEV; + } + + return drm_bridge_attach(bridge->encoder, + p2d->next_bridge, bridge, + DRM_BRIDGE_ATTACH_NO_CONNECTOR); +} + +static int +imx8qxp_pxl2dpi_bridge_atomic_check(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct imx8qxp_pxl2dpi *p2d = bridge->driver_private; + + p2d->in_bus_format = bridge_state->input_bus_cfg.format; + p2d->out_bus_format = bridge_state->output_bus_cfg.format; + + return 0; +} + +static void +imx8qxp_pxl2dpi_bridge_mode_set(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + const struct drm_display_mode *adjusted_mode) +{ + struct imx8qxp_pxl2dpi *p2d = bridge->driver_private; + struct imx8qxp_pxl2dpi *companion_p2d; + int ret; + + ret = pm_runtime_get_sync(p2d->dev); + if (ret < 0) + DRM_DEV_ERROR(p2d->dev, + "failed to get runtime PM sync: %d\n", ret); + + ret = imx_sc_misc_set_control(p2d->ipc_handle, p2d->sc_resource, + IMX_SC_C_PXL_LINK_SEL, p2d->pl_sel); + if (ret) + DRM_DEV_ERROR(p2d->dev, + "failed to set pixel link selection(%u): %d\n", + p2d->pl_sel, ret); + + switch (p2d->out_bus_format) { + case MEDIA_BUS_FMT_RGB888_1X24: + regmap_write(p2d->regmap, PXL2DPI_CTRL, CFG_24BIT); + break; + case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: + regmap_write(p2d->regmap, PXL2DPI_CTRL, CFG2_18BIT); + break; + default: + DRM_DEV_ERROR(p2d->dev, + "unsupported output bus format 0x%08x\n", + p2d->out_bus_format); + } + + if (p2d->companion) { + companion_p2d = bridge_to_p2d(p2d->companion); + + companion_p2d->in_bus_format = p2d->in_bus_format; + companion_p2d->out_bus_format = p2d->out_bus_format; + + p2d->companion->funcs->mode_set(p2d->companion, mode, + adjusted_mode); + } +} + +static void +imx8qxp_pxl2dpi_bridge_atomic_disable(struct drm_bridge *bridge, + struct drm_bridge_state *old_bridge_state) +{ + struct imx8qxp_pxl2dpi *p2d = bridge->driver_private; + int ret; + + ret = pm_runtime_put(p2d->dev); + if (ret < 0) + DRM_DEV_ERROR(p2d->dev, "failed to put runtime PM: %d\n", ret); + + if (p2d->companion) + p2d->companion->funcs->atomic_disable(p2d->companion, + old_bridge_state); +} + +static const u32 imx8qxp_pxl2dpi_bus_output_fmts[] = { + MEDIA_BUS_FMT_RGB888_1X24, + MEDIA_BUS_FMT_RGB666_1X24_CPADHI, +}; + +static bool imx8qxp_pxl2dpi_bus_output_fmt_supported(u32 fmt) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(imx8qxp_pxl2dpi_bus_output_fmts); i++) { + if (imx8qxp_pxl2dpi_bus_output_fmts[i] == fmt) + return true; + } + + return false; +} + +static u32 * +imx8qxp_pxl2dpi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + u32 output_fmt, + unsigned int *num_input_fmts) +{ + u32 *input_fmts; + + if (!imx8qxp_pxl2dpi_bus_output_fmt_supported(output_fmt)) + return NULL; + + *num_input_fmts = 1; + + input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL); + if (!input_fmts) + return NULL; + + switch (output_fmt) { + case MEDIA_BUS_FMT_RGB888_1X24: + input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X36_CPADLO; + break; + case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: + input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X36_CPADLO; + break; + default: + kfree(input_fmts); + input_fmts = NULL; + break; + } + + return input_fmts; +} + +static u32 * +imx8qxp_pxl2dpi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + unsigned int *num_output_fmts) +{ + *num_output_fmts = ARRAY_SIZE(imx8qxp_pxl2dpi_bus_output_fmts); + return kmemdup(imx8qxp_pxl2dpi_bus_output_fmts, + sizeof(imx8qxp_pxl2dpi_bus_output_fmts), GFP_KERNEL); +} + +static const struct drm_bridge_funcs imx8qxp_pxl2dpi_bridge_funcs = { + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, + .atomic_reset = drm_atomic_helper_bridge_reset, + .attach = imx8qxp_pxl2dpi_bridge_attach, + .atomic_check = imx8qxp_pxl2dpi_bridge_atomic_check, + .mode_set = imx8qxp_pxl2dpi_bridge_mode_set, + .atomic_disable = imx8qxp_pxl2dpi_bridge_atomic_disable, + .atomic_get_input_bus_fmts = + imx8qxp_pxl2dpi_bridge_atomic_get_input_bus_fmts, + .atomic_get_output_bus_fmts = + imx8qxp_pxl2dpi_bridge_atomic_get_output_bus_fmts, +}; + +static struct device_node * +imx8qxp_pxl2dpi_get_available_ep_from_port(struct imx8qxp_pxl2dpi *p2d, + u32 port_id) +{ + struct device_node *port, *ep; + int ep_cnt; + + port = of_graph_get_port_by_id(p2d->dev->of_node, port_id); + if (!port) { + DRM_DEV_ERROR(p2d->dev, "failed to get port@%u\n", port_id); + return ERR_PTR(-ENODEV); + } + + ep_cnt = of_get_available_child_count(port); + if (ep_cnt == 0) { + DRM_DEV_ERROR(p2d->dev, "no available endpoints of port@%u\n", + port_id); + ep = ERR_PTR(-ENODEV); + goto out; + } else if (ep_cnt > 1) { + DRM_DEV_ERROR(p2d->dev, + "invalid available endpoints of port@%u\n", + port_id); + ep = ERR_PTR(-EINVAL); + goto out; + } + + ep = of_get_next_available_child(port, NULL); + if (!ep) { + DRM_DEV_ERROR(p2d->dev, + "failed to get available endpoint of port@%u\n", + port_id); + ep = ERR_PTR(-ENODEV); + goto out; + } +out: + of_node_put(port); + return ep; +} + +static struct drm_bridge * +imx8qxp_pxl2dpi_find_next_bridge(struct imx8qxp_pxl2dpi *p2d) +{ + struct device_node *ep, *remote; + struct drm_bridge *next_bridge; + int ret; + + ep = imx8qxp_pxl2dpi_get_available_ep_from_port(p2d, 1); + if (IS_ERR(ep)) { + ret = PTR_ERR(ep); + return ERR_PTR(ret); + } + + remote = of_graph_get_remote_port_parent(ep); + if (!remote || !of_device_is_available(remote)) { + DRM_DEV_ERROR(p2d->dev, "no available remote\n"); + next_bridge = ERR_PTR(-ENODEV); + goto out; + } else if (!of_device_is_available(remote->parent)) { + DRM_DEV_ERROR(p2d->dev, "remote parent is not available\n"); + next_bridge = ERR_PTR(-ENODEV); + goto out; + } + + next_bridge = of_drm_find_bridge(remote); + if (!next_bridge) { + next_bridge = ERR_PTR(-EPROBE_DEFER); + goto out; + } +out: + of_node_put(remote); + of_node_put(ep); + + return next_bridge; +} + +static int imx8qxp_pxl2dpi_set_pixel_link_sel(struct imx8qxp_pxl2dpi *p2d) +{ + struct device_node *ep; + struct of_endpoint endpoint; + int ret; + + ep = imx8qxp_pxl2dpi_get_available_ep_from_port(p2d, 0); + if (IS_ERR(ep)) + return PTR_ERR(ep); + + ret = of_graph_parse_endpoint(ep, &endpoint); + if (ret) { + DRM_DEV_ERROR(p2d->dev, + "failed to parse endpoint of port@0: %d\n", ret); + goto out; + } + + p2d->pl_sel = endpoint.id; +out: + of_node_put(ep); + + return ret; +} + +static int imx8qxp_pxl2dpi_parse_dt_companion(struct imx8qxp_pxl2dpi *p2d) +{ + struct imx8qxp_pxl2dpi *companion_p2d; + struct device *dev = p2d->dev; + struct device_node *companion; + struct device_node *port1, *port2; + const struct of_device_id *match; + int dual_link; + int ret = 0; + + /* Locate the companion PXL2DPI for dual-link operation, if any. */ + companion = of_parse_phandle(dev->of_node, "fsl,companion-pxl2dpi", 0); + if (!companion) + return 0; + + if (!of_device_is_available(companion)) { + DRM_DEV_ERROR(dev, "companion PXL2DPI is not available\n"); + ret = -ENODEV; + goto out; + } + + /* + * Sanity check: the companion bridge must have the same compatible + * string. + */ + match = of_match_device(dev->driver->of_match_table, dev); + if (!of_device_is_compatible(companion, match->compatible)) { + DRM_DEV_ERROR(dev, "companion PXL2DPI is incompatible\n"); + ret = -ENXIO; + goto out; + } + + p2d->companion = of_drm_find_bridge(companion); + if (!p2d->companion) { + ret = -EPROBE_DEFER; + DRM_DEV_DEBUG_DRIVER(p2d->dev, + "failed to find companion bridge: %d\n", + ret); + goto out; + } + + companion_p2d = bridge_to_p2d(p2d->companion); + + /* + * We need to work out if the sink is expecting us to function in + * dual-link mode. We do this by looking at the DT port nodes that + * the next bridges are connected to. If they are marked as expecting + * even pixels and odd pixels than we need to use the companion PXL2DPI. + */ + port1 = of_graph_get_port_by_id(p2d->next_bridge->of_node, 1); + port2 = of_graph_get_port_by_id(companion_p2d->next_bridge->of_node, 1); + dual_link = drm_of_lvds_get_dual_link_pixel_order(port1, port2); + of_node_put(port1); + of_node_put(port2); + + if (dual_link < 0) { + ret = dual_link; + DRM_DEV_ERROR(dev, "failed to get dual link pixel order: %d\n", + ret); + goto out; + } + + DRM_DEV_DEBUG_DRIVER(dev, + "dual-link configuration detected (companion bridge %pOF)\n", + companion); +out: + of_node_put(companion); + return ret; +} + +static int imx8qxp_pxl2dpi_bridge_probe(struct platform_device *pdev) +{ + struct imx8qxp_pxl2dpi *p2d; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + int ret; + + p2d = devm_kzalloc(dev, sizeof(*p2d), GFP_KERNEL); + if (!p2d) + return -ENOMEM; + + p2d->regmap = syscon_node_to_regmap(np->parent); + if (IS_ERR(p2d->regmap)) { + ret = PTR_ERR(p2d->regmap); + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(dev, "failed to get regmap: %d\n", ret); + return ret; + } + + ret = imx_scu_get_handle(&p2d->ipc_handle); + if (ret) { + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(dev, "failed to get SCU ipc handle: %d\n", + ret); + return ret; + } + + p2d->dev = dev; + + ret = of_property_read_u32(np, "fsl,sc-resource", &p2d->sc_resource); + if (ret) { + DRM_DEV_ERROR(dev, "failed to get SC resource %d\n", ret); + return ret; + } + + p2d->next_bridge = imx8qxp_pxl2dpi_find_next_bridge(p2d); + if (IS_ERR(p2d->next_bridge)) { + ret = PTR_ERR(p2d->next_bridge); + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(dev, "failed to find next bridge: %d\n", + ret); + return ret; + } + + ret = imx8qxp_pxl2dpi_set_pixel_link_sel(p2d); + if (ret) + return ret; + + ret = imx8qxp_pxl2dpi_parse_dt_companion(p2d); + if (ret) + return ret; + + platform_set_drvdata(pdev, p2d); + pm_runtime_enable(dev); + + p2d->bridge.driver_private = p2d; + p2d->bridge.funcs = &imx8qxp_pxl2dpi_bridge_funcs; + p2d->bridge.of_node = np; + + drm_bridge_add(&p2d->bridge); + + return ret; +} + +static int imx8qxp_pxl2dpi_bridge_remove(struct platform_device *pdev) +{ + struct imx8qxp_pxl2dpi *p2d = platform_get_drvdata(pdev); + + drm_bridge_remove(&p2d->bridge); + + pm_runtime_disable(&pdev->dev); + + return 0; +} + +static const struct of_device_id imx8qxp_pxl2dpi_dt_ids[] = { + { .compatible = "fsl,imx8qxp-pxl2dpi", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx8qxp_pxl2dpi_dt_ids); + +static struct platform_driver imx8qxp_pxl2dpi_bridge_driver = { + .probe = imx8qxp_pxl2dpi_bridge_probe, + .remove = imx8qxp_pxl2dpi_bridge_remove, + .driver = { + .of_match_table = imx8qxp_pxl2dpi_dt_ids, + .name = DRIVER_NAME, + }, +}; +module_platform_driver(imx8qxp_pxl2dpi_bridge_driver); + +MODULE_DESCRIPTION("i.MX8QXP pixel link to DPI bridge driver"); +MODULE_AUTHOR("Liu Ying <victor.liu@nxp.com>"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRIVER_NAME); |