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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018-2019 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
&dma_subsys {
uart4_lpcg: clock-controller@5a4a0000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5a4a0000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>,
<&dma_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "uart4_lpcg_baud_clk",
"uart4_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_UART_4>;
};
};
&lpuart0 {
compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
};
&lpuart1 {
compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
};
&lpuart2 {
compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
};
&lpuart3 {
compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
};
&i2c0 {
compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
};
&i2c1 {
compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
};
&i2c2 {
compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
};
&i2c3 {
compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
};
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