blob: f916dcde457f4cadf5fe75ece9b438d211c0462d (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
*
* Microchip PolarFire SoC (MPFS)
*
* Copyright (c) 2020 Microchip Corporation. All rights reserved.
*
* Author: Conor Dooley <conor.dooley@microchip.com>
*
*/
#ifndef __SOC_MPFS_H__
#define __SOC_MPFS_H__
#include <linux/types.h>
#include <linux/of_device.h>
struct mpfs_sys_controller;
struct mpfs_mss_msg {
u8 cmd_opcode;
u16 cmd_data_size;
struct mpfs_mss_response *response;
u8 *cmd_data;
u16 mbox_offset;
u16 resp_offset;
};
struct mpfs_mss_response {
u32 resp_status;
u32 *resp_msg;
u16 resp_size;
};
#if IS_ENABLED(CONFIG_POLARFIRE_SOC_SYS_CTRL)
int mpfs_blocking_transaction(struct mpfs_sys_controller *mpfs_client, struct mpfs_mss_msg *msg);
struct mpfs_sys_controller *mpfs_sys_controller_get(struct device *dev);
#endif /* if IS_ENABLED(CONFIG_POLARFIRE_SOC_SYS_CTRL) */
#if IS_ENABLED(CONFIG_MCHP_CLK_MPFS)
u32 mpfs_reset_read(struct device *dev);
void mpfs_reset_write(struct device *dev, u32 val);
#endif /* if IS_ENABLED(CONFIG_MCHP_CLK_MPFS) */
#endif /* __SOC_MPFS_H__ */
|
