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| author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-07 18:49:45 +0000 |
|---|---|---|
| committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-07 18:49:45 +0000 |
| commit | 2c3c1048746a4622d8c89a29670120dc8fab93c4 (patch) | |
| tree | 848558de17fb3008cdf4d861b01ac7781903ce39 /arch/arm/mach-socfpga/core.h | |
| parent | Initial commit. (diff) | |
| download | linux-2c3c1048746a4622d8c89a29670120dc8fab93c4.tar.xz linux-2c3c1048746a4622d8c89a29670120dc8fab93c4.zip | |
Adding upstream version 6.1.76.upstream/6.1.76
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'arch/arm/mach-socfpga/core.h')
| -rw-r--r-- | arch/arm/mach-socfpga/core.h | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h new file mode 100644 index 000000000..18f01190d --- /dev/null +++ b/arch/arm/mach-socfpga/core.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright 2012 Pavel Machek <pavel@denx.de> + * Copyright (C) 2012-2015 Altera Corporation + */ + +#ifndef __MACH_CORE_H +#define __MACH_CORE_H + +#define SOCFPGA_RSTMGR_CTRL 0x04 +#define SOCFPGA_RSTMGR_MODMPURST 0x10 +#define SOCFPGA_RSTMGR_MODPERRST 0x14 +#define SOCFPGA_RSTMGR_BRGMODRST 0x1c + +#define SOCFPGA_A10_RSTMGR_CTRL 0xC +#define SOCFPGA_A10_RSTMGR_MODMPURST 0x20 + +/* System Manager bits */ +#define RSTMGR_CTRL_SWCOLDRSTREQ 0x1 /* Cold Reset */ +#define RSTMGR_CTRL_SWWARMRSTREQ 0x2 /* Warm Reset */ + +#define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */ + +void socfpga_init_l2_ecc(void); +void socfpga_init_ocram_ecc(void); +void socfpga_init_arria10_l2_ecc(void); +void socfpga_init_arria10_ocram_ecc(void); + +extern void __iomem *sys_manager_base_addr; +extern void __iomem *rst_manager_base_addr; +extern void __iomem *sdr_ctl_base_addr; + +u32 socfpga_sdram_self_refresh(u32 sdr_base); +extern unsigned int socfpga_sdram_self_refresh_sz; + +extern char secondary_trampoline[], secondary_trampoline_end[]; + +extern unsigned long socfpga_cpu1start_addr; + +#define SOCFPGA_SCU_VIRT_BASE 0xfee00000 + +#endif |