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Diffstat (limited to 'drivers/hwtracing/coresight/Kconfig')
| -rw-r--r-- | drivers/hwtracing/coresight/Kconfig | 204 |
1 files changed, 204 insertions, 0 deletions
diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig new file mode 100644 index 000000000..45c1eb5df --- /dev/null +++ b/drivers/hwtracing/coresight/Kconfig @@ -0,0 +1,204 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Coresight configuration +# +menuconfig CORESIGHT + tristate "CoreSight Tracing Support" + depends on ARM || ARM64 + depends on OF || ACPI + select ARM_AMBA + select PERF_EVENTS + select CONFIGFS_FS + help + This framework provides a kernel interface for the CoreSight debug + and trace drivers to register themselves with. It's intended to build + a topological view of the CoreSight components based on a DT + specification and configure the right series of components when a + trace source gets enabled. + + To compile this driver as a module, choose M here: the + module will be called coresight. + +if CORESIGHT +config CORESIGHT_LINKS_AND_SINKS + tristate "CoreSight Link and Sink drivers" + help + This enables support for CoreSight link and sink drivers that are + responsible for transporting and collecting the trace data + respectively. Link and sinks are dynamically aggregated with a trace + entity at run time to form a complete trace path. + + To compile these drivers as modules, choose M here: the + modules will be called coresight-funnel and coresight-replicator. + +config CORESIGHT_LINK_AND_SINK_TMC + tristate "Coresight generic TMC driver" + + depends on CORESIGHT_LINKS_AND_SINKS + help + This enables support for the Trace Memory Controller driver. + Depending on its configuration the device can act as a link (embedded + trace router - ETR) or sink (embedded trace FIFO). The driver + complies with the generic implementation of the component without + special enhancement or added features. + + To compile this driver as a module, choose M here: the + module will be called coresight-tmc. + +config CORESIGHT_CATU + tristate "Coresight Address Translation Unit (CATU) driver" + depends on CORESIGHT_LINK_AND_SINK_TMC + help + Enable support for the Coresight Address Translation Unit (CATU). + CATU supports a scatter gather table of 4K pages, with forward/backward + lookup. CATU helps TMC ETR to use a large physically non-contiguous trace + buffer by translating the addresses used by ETR to the physical address + by looking up the provided table. CATU can also be used in pass-through + mode where the address is not translated. + + To compile this driver as a module, choose M here: the + module will be called coresight-catu. + +config CORESIGHT_SINK_TPIU + tristate "Coresight generic TPIU driver" + depends on CORESIGHT_LINKS_AND_SINKS + help + This enables support for the Trace Port Interface Unit driver, + responsible for bridging the gap between the on-chip coresight + components and a trace for bridging the gap between the on-chip + coresight components and a trace port collection engine, typically + connected to an external host for use case capturing more traces than + the on-board coresight memory can handle. + + To compile this driver as a module, choose M here: the + module will be called coresight-tpiu. + +config CORESIGHT_SINK_ETBV10 + tristate "Coresight ETBv1.0 driver" + depends on CORESIGHT_LINKS_AND_SINKS + help + This enables support for the Embedded Trace Buffer version 1.0 driver + that complies with the generic implementation of the component without + special enhancement or added features. + + To compile this driver as a module, choose M here: the + module will be called coresight-etb10. + +config CORESIGHT_SOURCE_ETM3X + tristate "CoreSight Embedded Trace Macrocell 3.x driver" + depends on !ARM64 + select CORESIGHT_LINKS_AND_SINKS + help + This driver provides support for processor ETM3.x and PTM1.x modules, + which allows tracing the instructions that a processor is executing + This is primarily useful for instruction level tracing. Depending + the ETM version data tracing may also be available. + + To compile this driver as a module, choose M here: the + module will be called coresight-etm3x. + +config CORESIGHT_SOURCE_ETM4X + tristate "CoreSight ETMv4.x / ETE driver" + depends on ARM64 + select CORESIGHT_LINKS_AND_SINKS + select PID_IN_CONTEXTIDR + help + This driver provides support for the CoreSight Embedded Trace Macrocell + version 4.x and the Embedded Trace Extensions (ETE). Both are CPU tracer + modules, tracing the instructions that a processor is executing. This is + primarily useful for instruction level tracing. + + To compile this driver as a module, choose M here: the + module will be called coresight-etm4x. + +config ETM4X_IMPDEF_FEATURE + bool "Control implementation defined overflow support in ETM 4.x driver" + depends on CORESIGHT_SOURCE_ETM4X + help + This control provides implementation define control for CoreSight + ETM 4.x tracer module that can't reduce commit rate automatically. + This avoids overflow between the ETM tracer module and the cpu core. + +config CORESIGHT_STM + tristate "CoreSight System Trace Macrocell driver" + depends on (ARM && !(CPU_32v3 || CPU_32v4 || CPU_32v4T)) || ARM64 + select CORESIGHT_LINKS_AND_SINKS + select STM + help + This driver provides support for hardware assisted software + instrumentation based tracing. This is primarily used for + logging useful software events or data coming from various entities + in the system, possibly running different OSs + + To compile this driver as a module, choose M here: the + module will be called coresight-stm. + +config CORESIGHT_CPU_DEBUG + tristate "CoreSight CPU Debug driver" + depends on ARM || ARM64 + depends on DEBUG_FS + help + This driver provides support for coresight debugging module. This + is primarily used to dump sample-based profiling registers when + system triggers panic, the driver will parse context registers so + can quickly get to know program counter (PC), secure state, + exception level, etc. Before use debugging functionality, platform + needs to ensure the clock domain and power domain are enabled + properly, please refer Documentation/trace/coresight/coresight-cpu-debug.rst + for detailed description and the example for usage. + + To compile this driver as a module, choose M here: the + module will be called coresight-cpu-debug. + +config CORESIGHT_CPU_DEBUG_DEFAULT_ON + bool "Enable CoreSight CPU Debug by default" + depends on CORESIGHT_CPU_DEBUG + help + Say Y here to enable the CoreSight Debug panic-debug by default. This + can also be enabled via debugfs, but this ensures the debug feature + is enabled as early as possible. + + Has the same effect as setting coresight_cpu_debug.enable=1 on the + kernel command line. + + Say N if unsure. + +config CORESIGHT_CTI + tristate "CoreSight Cross Trigger Interface (CTI) driver" + depends on ARM || ARM64 + help + This driver provides support for CoreSight CTI and CTM components. + These provide hardware triggering events between CoreSight trace + source and sink components. These can be used to halt trace or + inject events into the trace stream. CTI also provides a software + control to trigger the same halt events. This can provide fast trace + halt compared to disabling sources and sinks normally in driver + software. + + To compile this driver as a module, choose M here: the + module will be called coresight-cti. + +config CORESIGHT_CTI_INTEGRATION_REGS + bool "Access CTI CoreSight Integration Registers" + depends on CORESIGHT_CTI + help + This option adds support for the CoreSight integration registers on + this device. The integration registers allow the exploration of the + CTI trigger connections between this and other devices.These + registers are not used in normal operation and can leave devices in + an inconsistent state. + +config CORESIGHT_TRBE + tristate "Trace Buffer Extension (TRBE) driver" + depends on ARM64 && CORESIGHT_SOURCE_ETM4X + help + This driver provides support for percpu Trace Buffer Extension (TRBE). + TRBE always needs to be used along with its corresponding percpu ETE + component. ETE generates trace data which is then captured with TRBE. + Unlike traditional sink devices, TRBE is a CPU feature accessible via + system registers. But its explicit dependency with trace unit (ETE) + requires it to be plugged in as a coresight sink device. + + To compile this driver as a module, choose M here: the module will be + called coresight-trbe. +endif |