1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/adc/renesas,rzg2l-adc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/G2L ADC
maintainers:
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
description: |
A/D Converter block is a successive approximation analog-to-digital converter
with a 12-bit accuracy. Up to eight analog input channels can be selected.
Conversions can be performed in single or repeat mode. Result of the ADC is
stored in a 32-bit data register corresponding to each channel.
properties:
compatible:
items:
- enum:
- renesas,r9a07g043-adc # RZ/G2UL
- renesas,r9a07g044-adc # RZ/G2L
- renesas,r9a07g054-adc # RZ/V2L
- const: renesas,rzg2l-adc
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: converter clock
- description: peripheral clock
clock-names:
items:
- const: adclk
- const: pclk
power-domains:
maxItems: 1
resets:
maxItems: 2
reset-names:
items:
- const: presetn
- const: adrst-n
'#address-cells':
const: 1
'#size-cells':
const: 0
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- power-domains
- resets
- reset-names
patternProperties:
"^channel@[0-7]$":
$ref: "adc.yaml"
type: object
description: |
Represents the external channels which are connected to the ADC.
properties:
reg:
description: |
The channel number.
required:
- reg
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
const: renesas,r9a07g043-adc
then:
patternProperties:
"^channel@[2-7]$": false
"^channel@[0-1]$":
properties:
reg:
minimum: 0
maximum: 1
else:
patternProperties:
"^channel@[0-7]$":
properties:
reg:
minimum: 0
maximum: 7
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/r9a07g044-cpg.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
adc: adc@10059000 {
compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
reg = <0x10059000 0x400>;
interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
<&cpg CPG_MOD R9A07G044_ADC_PCLK>;
clock-names = "adclk", "pclk";
power-domains = <&cpg>;
resets = <&cpg R9A07G044_ADC_PRESETN>,
<&cpg R9A07G044_ADC_ADRST_N>;
reset-names = "presetn", "adrst-n";
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
};
channel@1 {
reg = <1>;
};
channel@2 {
reg = <2>;
};
channel@3 {
reg = <3>;
};
channel@4 {
reg = <4>;
};
channel@5 {
reg = <5>;
};
channel@6 {
reg = <6>;
};
channel@7 {
reg = <7>;
};
};
|
