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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/qca,ar71xx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: QCA AR71XX MAC
allOf:
- $ref: ethernet-controller.yaml#
maintainers:
- Oleksij Rempel <o.rempel@pengutronix.de>
properties:
compatible:
oneOf:
- items:
- enum:
- qca,ar7100-eth # Atheros AR7100
- qca,ar7240-eth # Atheros AR7240
- qca,ar7241-eth # Atheros AR7241
- qca,ar7242-eth # Atheros AR7242
- qca,ar9130-eth # Atheros AR9130
- qca,ar9330-eth # Atheros AR9330
- qca,ar9340-eth # Atheros AR9340
- qca,qca9530-eth # Qualcomm Atheros QCA9530
- qca,qca9550-eth # Qualcomm Atheros QCA9550
- qca,qca9560-eth # Qualcomm Atheros QCA9560
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: MAC main clock
- description: MDIO clock
clock-names:
items:
- const: eth
- const: mdio
resets:
items:
- description: MAC reset
- description: MDIO reset
reset-names:
items:
- const: mac
- const: mdio
mdio:
$ref: mdio.yaml#
unevaluatedProperties: false
required:
- compatible
- reg
- interrupts
- phy-mode
- clocks
- clock-names
- resets
- reset-names
unevaluatedProperties: false
examples:
# Lager board
- |
eth0: ethernet@19000000 {
compatible = "qca,ar9330-eth";
reg = <0x19000000 0x200>;
interrupts = <4>;
resets = <&rst 9>, <&rst 22>;
reset-names = "mac", "mdio";
clocks = <&pll 1>, <&pll 2>;
clock-names = "eth", "mdio";
phy-mode = "mii";
phy-handle = <&phy_port4>;
};
eth1: ethernet@1a000000 {
compatible = "qca,ar9330-eth";
reg = <0x1a000000 0x200>;
interrupts = <5>;
resets = <&rst 13>, <&rst 23>;
reset-names = "mac", "mdio";
clocks = <&pll 1>, <&pll 2>;
clock-names = "eth", "mdio";
phy-mode = "gmii";
fixed-link {
speed = <1000>;
full-duplex;
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch10: switch@10 {
compatible = "qca,ar9331-switch";
reg = <0x10>;
resets = <&rst 8>;
reset-names = "switch";
interrupt-parent = <&miscintc>;
interrupts = <12>;
interrupt-controller;
#interrupt-cells = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
switch_port0: port@0 {
reg = <0x0>;
label = "cpu";
ethernet = <ð1>;
phy-mode = "gmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
switch_port1: port@1 {
reg = <0x1>;
phy-handle = <&phy_port0>;
phy-mode = "internal";
};
switch_port2: port@2 {
reg = <0x2>;
phy-handle = <&phy_port1>;
phy-mode = "internal";
};
switch_port3: port@3 {
reg = <0x3>;
phy-handle = <&phy_port2>;
phy-mode = "internal";
};
switch_port4: port@4 {
reg = <0x4>;
phy-handle = <&phy_port3>;
phy-mode = "internal";
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&switch10>;
phy_port0: ethernet-phy@0 {
reg = <0x0>;
interrupts = <0>;
};
phy_port1: ethernet-phy@1 {
reg = <0x1>;
interrupts = <0>;
};
phy_port2: ethernet-phy@2 {
reg = <0x2>;
interrupts = <0>;
};
phy_port3: ethernet-phy@3 {
reg = <0x3>;
interrupts = <0>;
};
phy_port4: ethernet-phy@4 {
reg = <0x4>;
interrupts = <0>;
};
};
};
};
};
|
