blob: 3b4e6e94cb81147e56f37599e094ed2bd5009779 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/fsl,layerscape-sfp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale Layerscape Security Fuse Processor
maintainers:
- Michael Walle <michael@walle.cc>
description: |
SFP is the security fuse processor which among other things provides a
unique identifier per part.
allOf:
- $ref: "nvmem.yaml#"
properties:
compatible:
oneOf:
- description: Trust architecture 2.1 SFP
items:
- const: fsl,ls1021a-sfp
- description: Trust architecture 3.0 SFP
items:
- const: fsl,ls1028a-sfp
reg:
maxItems: 1
clocks:
maxItems: 1
description:
The SFP clock. Typically, this is the platform clock divided by 4.
clock-names:
const: sfp
ta-prog-sfp-supply:
description:
The regulator for the TA_PROG_SFP pin. It will be enabled for programming
and disabled for reading.
required:
- compatible
- reg
- clock-names
- clocks
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
efuse@1e80000 {
compatible = "fsl,ls1028a-sfp";
reg = <0x1e80000 0x8000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
clock-names = "sfp";
};
|
