path: root/drivers/gpu/drm/msm/adreno/a3xx.xml.h

#ifndef A3XX_XML
#define A3XX_XML

/* Autogenerated file, DO NOT EDIT manually!

This file was generated by the rules-ng-ng headergen tool in this git repository:
http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git

The rules-ng-ng source files this header was generated from are:
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno.xml                     (    594 bytes, from 2021-01-30 18:25:22)
- /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml        (   1572 bytes, from 2020-12-31 19:26:32)
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a2xx.xml                (  90810 bytes, from 2021-06-21 15:24:24)
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_common.xml       (  14609 bytes, from 2021-11-24 23:05:10)
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pm4.xml          (  69086 bytes, from 2022-03-03 16:41:33)
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a3xx.xml                (  84231 bytes, from 2021-11-24 23:05:10)
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a4xx.xml                ( 113358 bytes, from 2022-01-31 23:06:21)
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a5xx.xml                ( 149512 bytes, from 2022-01-31 23:06:21)
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx.xml                ( 184954 bytes, from 2022-03-03 16:41:33)
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml            (  11331 bytes, from 2021-07-22 15:21:56)
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/ocmem.xml               (   1773 bytes, from 2021-01-30 18:25:22)
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml (   6038 bytes, from 2021-07-22 15:21:56)
- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml    (   2924 bytes, from 2021-07-22 15:21:56)

Copyright (C) 2013-2021 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)

Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:

The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/


enum a3xx_tile_mode {
	LINEAR = 0,
	TILE_4X4 = 1,
	TILE_32X32 = 2,
	TILE_4X2 = 3,
};

enum a3xx_state_block_id {
	HLSQ_BLOCK_ID_TP_TEX = 2,
	HLSQ_BLOCK_ID_TP_MIPMAP = 3,
	HLSQ_BLOCK_ID_SP_VS = 4,
	HLSQ_BLOCK_ID_SP_FS = 6,
};

enum a3xx_cache_opcode {
	INVALIDATE = 1,
};

enum a3xx_vtx_fmt {
	VFMT_32_FLOAT = 0,
	VFMT_32_32_FLOAT = 1,
	VFMT_32_32_32_FLOAT = 2,
	VFMT_32_32_32_32_FLOAT = 3,
	VFMT_16_FLOAT = 4,
	VFMT_16_16_FLOAT = 5,
	VFMT_16_16_16_FLOAT = 6,
	VFMT_16_16_16_16_FLOAT = 7,
	VFMT_32_FIXED = 8,
	VFMT_32_32_FIXED = 9,
	VFMT_32_32_32_FIXED = 10,
	VFMT_32_32_32_32_FIXED = 11,
	VFMT_16_SINT = 16,
	VFMT_16_16_SINT = 17,
	VFMT_16_16_16_SINT = 18,
	VFMT_16_16_16_16_SINT = 19,
	VFMT_16_UINT = 20,
	VFMT_16_16_UINT = 21,
	VFMT_16_16_16_UINT = 22,
	VFMT_16_16_16_16_UINT = 23,
	VFMT_16_SNORM = 24,
	VFMT_16_16_SNORM = 25,
	VFMT_16_16_16_SNORM = 26,
	VFMT_16_16_16_16_SNORM = 27,
	VFMT_16_UNORM = 28,
	VFMT_16_16_UNORM = 29,
	VFMT_16_16_16_UNORM = 30,
	VFMT_16_16_16_16_UNORM = 31,
	VFMT_32_UINT = 32,
	VFMT_32_32_UINT = 33,
	VFMT_32_32_32_UINT = 34,
	VFMT_32_32_32_32_UINT = 35,
	VFMT_32_SINT = 36,
	VFMT_32_32_SINT = 37,
	VFMT_32_32_32_SINT = 38,
	VFMT_32_32_32_32_SINT = 39,
	VFMT_8_UINT = 40,
	VFMT_8_8_UINT = 41,
	VFMT_8_8_8_UINT = 42,
	VFMT_8_8_8_8_UINT = 43,
	VFMT_8_UNORM = 44,
	VFMT_8_8_UNORM = 45,
	VFMT_8_8_8_UNORM = 46,
	VFMT_8_8_8_8_UNORM = 47,
	VFMT_8_SINT = 48,
	VFMT_8_8_SINT = 49,
	VFMT_8_8_8_SINT = 50,
	VFMT_8_8_8_8_SINT = 51,
	VFMT_8_SNORM = 52,
	VFMT_8_8_SNORM = 53,
	VFMT_8_8_8_SNORM = 54,
	VFMT_8_8_8_8_SNORM = 55,
	VFMT_10_10_10_2_UINT = 56,
	VFMT_10_10_10_2_UNORM = 57,
	VFMT_10_10_10_2_SINT = 58,
	VFMT_10_10_10_2_SNORM = 59,
	VFMT_2_10_10_10_UINT = 60,
	VFMT_2_10_10_10_UNORM = 61,
	VFMT_2_10_10_10_SINT = 62,
	VFMT_2_10_10_10_SNORM = 63,
	VFMT_NONE = 255,
};

enum a3xx_tex_fmt {
	TFMT_5_6_5_UNORM = 4,
	TFMT_5_5_5_1_UNORM = 5,
	TFMT_4_4_4_4_UNORM = 7,
	TFMT_Z16_UNORM = 9,
	TFMT_X8Z24_UNORM = 10,
	TFMT_Z32_FLOAT = 11,
	TFMT_UV_64X32 = 16,
	TFMT_VU_64X32 = 17,
	TFMT_Y_64X32 = 18,
	TFMT_NV12_64X32 = 19,
	TFMT_UV_LINEAR = 20,
	TFMT_VU_LINEAR = 21,
	TFMT_Y_LINEAR = 22,
	TFMT_NV12_LINEAR = 23,
	TFMT_I420_Y = 24,
	TFMT_I420_U = 26,
	TFMT_I420_V = 27,
	TFMT_ATC_RGB = 32,
	TFMT_ATC_RGBA_EXPLICIT = 33,
	TFMT_ETC1 = 34,
	TFMT_ATC_RGBA_INTERPOLATED = 35,
	TFMT_DXT1 = 36,
	TFMT_DXT3 = 37,
	TFMT_DXT5 = 38,
	TFMT_2_10_10_10_UNORM = 40,
	TFMT_10_10_10_2_UNORM = 41,
	TFMT_9_9_9_E5_FLOAT = 42,
	TFMT_11_11_10_FLOAT = 43,
	TFMT_A8_UNORM = 44,
	TFMT_L8_UNORM = 45,
	TFMT_L8_A8_UNORM = 47,
	TFMT_8_UNORM = 48,
	TFMT_8_8_UNORM = 49,
	TFMT_8_8_8_UNORM = 50,
	TFMT_8_8_8_8_UNORM = 51,
	TFMT_8_SNORM = 52,
	TFMT_8_8_SNORM = 53,
	TFMT_8_8_8_SNORM = 54,
	TFMT_8_8_8_8_SNORM = 55,
	TFMT_8_UINT = 56,
	TFMT_8_8_UINT = 57,
	TFMT_8_8_8_UINT = 58,
	TFMT_8_8_8_8_UINT = 59,
	TFMT_8_SINT = 60,
	TFMT_8_8_SINT = 61,
	TFMT_8_8_8_SINT = 62,
	TFMT_8_8_8_8_SINT = 63,
	TFMT_16_FLOAT = 64,
	TFMT_16_16_FLOAT = 65,
	TFMT_16_16_16_16_FLOAT = 67,
	TFMT_16_UINT = 68,
	TFMT_16_16_UINT = 69,
	TFMT_16_16_16_16_UINT = 71,
	TFMT_16_SINT = 72,
	TFMT_16_16_SINT = 73,
	TFMT_16_16_16_16_SINT = 75,
	TFMT_16_UNORM = 76,
	TFMT_16_16_UNORM = 77,
	TFMT_16_16_16_16_UNORM = 79,
	TFMT_16_SNORM = 80,
	TFMT_16_16_SNORM = 81,
	TFMT_16_16_16_16_SNORM = 83,
	TFMT_32_FLOAT = 84,
	TFMT_32_32_FLOAT = 85,
	TFMT_32_32_32_32_FLOAT = 87,
	TFMT_32_UINT = 88,
	TFMT_32_32_UINT = 89,
	TFMT_32_32_32_32_UINT = 91,
	TFMT_32_SINT = 92,
	TFMT_32_32_SINT = 93,
	TFMT_32_32_32_32_SINT = 95,
	TFMT_2_10_10_10_UINT = 96,
	TFMT_10_10_10_2_UINT = 97,
	TFMT_ETC2_RG11_SNORM = 112,
	TFMT_ETC2_RG11_UNORM = 113,
	TFMT_ETC2_R11_SNORM = 114,
	TFMT_ETC2_R11_UNORM = 115,
	TFMT_ETC2_RGBA8 = 116,
	TFMT_ETC2_RGB8A1 = 117,
	TFMT_ETC2_RGB8 = 118,
	TFMT_NONE = 255,
};

enum a3xx_color_fmt {
	RB_R5G6B5_UNORM = 0,
	RB_R5G5B5A1_UNORM = 1,
	RB_R4G4B4A4_UNORM = 3,
	RB_R8G8B8_UNORM = 4,
	RB_R8G8B8A8_UNORM = 8,
	RB_R8G8B8A8_SNORM = 9,
	RB_R8G8B8A8_UINT = 10,
	RB_R8G8B8A8_SINT = 11,
	RB_R8G8_UNORM = 12,
	RB_R8G8_SNORM = 13,
	RB_R8G8_UINT = 14,
	RB_R8G8_SINT = 15,
	RB_R10G10B10A2_UNORM = 16,
	RB_A2R10G10B10_UNORM = 17,
	RB_R10G10B10A2_UINT = 18,
	RB_A2R10G10B10_UINT = 19,
	RB_A8_UNORM = 20,
	RB_R8_UNORM = 21,
	RB_R16_FLOAT = 24,
	RB_R16G16_FLOAT = 25,
	RB_R16G16B16A16_FLOAT = 27,
	RB_R11G11B10_FLOAT = 28,
	RB_R16_SNORM = 32,
	RB_R16G16_SNORM = 33,
	RB_R16G16B16A16_SNORM = 35,
	RB_R16_UNORM = 36,
	RB_R16G16_UNORM = 37,
	RB_R16G16B16A16_UNORM = 39,
	RB_R16_SINT = 40,
	RB_R16G16_SINT = 41,
	RB_R16G16B16A16_SINT = 43,
	RB_R16_UINT = 44,
	RB_R16G16_UINT = 45,
	RB_R16G16B16A16_UINT = 47,
	RB_R32_FLOAT = 48,
	RB_R32G32_FLOAT = 49,
	RB_R32G32B32A32_FLOAT = 51,
	RB_R32_SINT = 52,
	RB_R32G32_SINT = 53,
	RB_R32G32B32A32_SINT = 55,
	RB_R32_UINT = 56,
	RB_R32G32_UINT = 57,
	RB_R32G32B32A32_UINT = 59,
	RB_NONE = 255,
};

enum a3xx_cp_perfcounter_select {
	CP_ALWAYS_COUNT = 0,
	CP_AHB_PFPTRANS_WAIT = 3,
	CP_AHB_NRTTRANS_WAIT = 6,
	CP_CSF_NRT_READ_WAIT = 8,
	CP_CSF_I1_FIFO_FULL = 9,
	CP_CSF_I2_FIFO_FULL = 10,
	CP_CSF_ST_FIFO_FULL = 11,
	CP_RESERVED_12 = 12,
	CP_CSF_RING_ROQ_FULL = 13,
	CP_CSF_I1_ROQ_FULL = 14,
	CP_CSF_I2_ROQ_FULL = 15,
	CP_CSF_ST_ROQ_FULL = 16,
	CP_RESERVED_17 = 17,
	CP_MIU_TAG_MEM_FULL = 18,
	CP_MIU_NRT_WRITE_STALLED = 22,
	CP_MIU_NRT_READ_STALLED = 23,
	CP_ME_REGS_RB_DONE_FIFO_FULL = 26,
	CP_ME_REGS_VS_EVENT_FIFO_FULL = 27,
	CP_ME_REGS_PS_EVENT_FIFO_FULL = 28,
	CP_ME_REGS_CF_EVENT_FIFO_FULL = 29,
	CP_ME_MICRO_RB_STARVED = 30,
	CP_AHB_RBBM_DWORD_SENT = 40,
	CP_ME_BUSY_CLOCKS = 41,
	CP_ME_WAIT_CONTEXT_AVAIL = 42,
	CP_PFP_TYPE0_PACKET = 43,
	CP_PFP_TYPE3_PACKET = 44,
	CP_CSF_RB_WPTR_NEQ_RPTR = 45,
	CP_CSF_I1_SIZE_NEQ_ZERO = 46,
	CP_CSF_I2_SIZE_NEQ_ZERO = 47,
	CP_CSF_RBI1I2_FETCHING = 48,
};

enum a3xx_gras_tse_perfcounter_select {
	GRAS_TSEPERF_INPUT_PRIM = 0,
	GRAS_TSEPERF_INPUT_NULL_PRIM = 1,
	GRAS_TSEPERF_TRIVAL_REJ_PRIM = 2,
	GRAS_TSEPERF_CLIPPED_PRIM = 3,
	GRAS_TSEPERF_NEW_PRIM = 4,
	GRAS_TSEPERF_ZERO_AREA_PRIM = 5,
	GRAS_TSEPERF_FACENESS_CULLED_PRIM = 6,
	GRAS_TSEPERF_ZERO_PIXEL_PRIM = 7,
	GRAS_TSEPERF_OUTPUT_NULL_PRIM = 8,
	GRAS_TSEPERF_OUTPUT_VISIBLE_PRIM = 9,
	GRAS_TSEPERF_PRE_CLIP_PRIM = 10,
	GRAS_TSEPERF_POST_CLIP_PRIM = 11,
	GRAS_TSEPERF_WORKING_CYCLES = 12,
	GRAS_TSEPERF_PC_STARVE = 13,
	GRAS_TSERASPERF_STALL = 14,
};

enum a3xx_gras_ras_perfcounter_select {
	GRAS_RASPERF_16X16_TILES = 0,
	GRAS_RASPERF_8X8_TILES = 1,
	GRAS_RASPERF_4X4_TILES = 2,
	GRAS_RASPERF_WORKING_CYCLES = 3,
	GRAS_RASPERF_STALL_CYCLES_BY_RB = 4,
	GRAS_RASPERF_STALL_CYCLES_BY_VSC = 5,
	GRAS_RASPERF_STARVE_CYCLES_BY_TSE = 6,
};

enum a3xx_hlsq_perfcounter_select {
	HLSQ_PERF_SP_VS_CONSTANT = 0,
	HLSQ_PERF_SP_VS_INSTRUCTIONS = 1,
	HLSQ_PERF_SP_FS_CONSTANT = 2,
	HLSQ_PERF_SP_FS_INSTRUCTIONS = 3,
	HLSQ_PERF_TP_STATE = 4,
	HLSQ_PERF_QUADS = 5,
	HLSQ_PERF_PIXELS = 6,
	HLSQ_PERF_VERTICES = 7,
	HLSQ_PERF_FS8_THREADS = 8,
	HLSQ_PERF_FS16_THREADS = 9,
	HLSQ_PERF_FS32_THREADS = 10,
	HLSQ_PERF_VS8_THREADS = 11,
	HLSQ_PERF_VS16_THREADS = 12,
	HLSQ_PERF_SP_VS_DATA_BYTES = 13,
	HLSQ_PERF_SP_FS_DATA_BYTES = 14,
	HLSQ_PERF_ACTIVE_CYCLES = 15,
	HLSQ_PERF_STALL_CYCLES_SP_STATE = 16,
	HLSQ_PERF_STALL_CYCLES_SP_VS = 17,
	HLSQ_PERF_STALL_CYCLES_SP_FS = 18,
	HLSQ_PERF_STALL_CYCLES_UCHE = 19,
	HLSQ_PERF_RBBM_LOAD_CYCLES = 20,
	HLSQ_PERF_DI_TO_VS_START_SP0 = 21,
	HLSQ_PERF_DI_TO_FS_START_SP0 = 22,
	HLSQ_PERF_VS_START_TO_DONE_SP0 = 23,
	HLSQ_PERF_FS_START_TO_DONE_SP0 = 24,
	HLSQ_PERF_SP_STATE_COPY_CYCLES_VS = 25,
	HLSQ_PERF_SP_STATE_COPY_CYCLES_FS = 26,
	HLSQ_PERF_UCHE_LATENCY_CYCLES = 27,
	HLSQ_PERF_UCHE_LATENCY_COUNT = 28,
};

enum a3xx_pc_perfcounter_select {
	PC_PCPERF_VISIBILITY_STREAMS = 0,
	PC_PCPERF_TOTAL_INSTANCES = 1,
	PC_PCPERF_PRIMITIVES_PC_VPC = 2,
	PC_PCPERF_PRIMITIVES_KILLED_BY_VS = 3,
	PC_PCPERF_PRIMITIVES_VISIBLE_BY_VS = 4,
	PC_PCPERF_DRAWCALLS_KILLED_BY_VS = 5,
	PC_PCPERF_DRAWCALLS_VISIBLE_BY_VS = 6,
	PC_PCPERF_VERTICES_TO_VFD = 7,
	PC_PCPERF_REUSED_VERTICES = 8,
	PC_PCPERF_CYCLES_STALLED_BY_VFD = 9,
	PC_PCPERF_CYCLES_STALLED_BY_TSE = 10,
	PC_PCPERF_CYCLES_STALLED_BY_VBIF = 11,
	PC_PCPERF_CYCLES_IS_WORKING = 12,
};

enum a3xx_rb_perfcounter_select {
	RB_RBPERF_ACTIVE_CYCLES_ANY = 0,
	RB_RBPERF_ACTIVE_CYCLES_ALL = 1,
	RB_RBPERF_STARVE_CYCLES_BY_SP = 2,
	RB_RBPERF_STARVE_CYCLES_BY_RAS = 3,
	RB_RBPERF_STARVE_CYCLES_BY_MARB = 4,
	RB_RBPERF_STALL_CYCLES_BY_MARB = 5,
	RB_RBPERF_STALL_CYCLES_BY_HLSQ = 6,
	RB_RBPERF_RB_MARB_DATA = 7,
	RB_RBPERF_SP_RB_QUAD = 8,
	RB_RBPERF_RAS_EARLY_Z_QUADS = 9,
	RB_RBPERF_GMEM_CH0_READ = 10,
	RB_RBPERF_GMEM_CH1_READ = 11,
	RB_RBPERF_GMEM_CH0_WRITE = 12,
	RB_RBPERF_GMEM_CH1_WRITE = 13,
	RB_RBPERF_CP_CONTEXT_DONE = 14,
	RB_RBPERF_CP_CACHE_FLUSH = 15,
	RB_RBPERF_CP_ZPASS_DONE = 16,
};

enum a3xx_rbbm_perfcounter_select {
	RBBM_ALAWYS_ON = 0,
	RBBM_VBIF_BUSY = 1,
	RBBM_TSE_BUSY = 2,
	RBBM_RAS_BUSY = 3,
	RBBM_PC_DCALL_BUSY = 4,
	RBBM_PC_VSD_BUSY = 5,
	RBBM_VFD_BUSY = 6,
	RBBM_VPC_BUSY = 7,
	RBBM_UCHE_BUSY = 8,
	RBBM_VSC_BUSY = 9,
	RBBM_HLSQ_BUSY = 10,
	RBBM_ANY_RB_BUSY = 11,
	RBBM_ANY_TEX_BUSY = 12,
	RBBM_ANY_USP_BUSY = 13,
	RBBM_ANY_MARB_BUSY = 14,
	RBBM_ANY_ARB_BUSY = 15,
	RBBM_AHB_STATUS_BUSY = 16,
	RBBM_AHB_STATUS_STALLED = 17,
	RBBM_AHB_STATUS_TXFR = 18,
	RBBM_AHB_STATUS_TXFR_SPLIT = 19,
	RBBM_AHB_STATUS_TXFR_ERROR = 20,
	RBBM_AHB_STATUS_LONG_STALL = 21,
	RBBM_RBBM_STATUS_MASKED = 22,
};

enum a3xx_sp_perfcounter_select {
	SP_LM_LOAD_INSTRUCTIONS = 0,
	SP_LM_STORE_INSTRUCTIONS = 1,
	SP_LM_ATOMICS = 2,
	SP_UCHE_LOAD_INSTRUCTIONS = 3,
	SP_UCHE_STORE_INSTRUCTIONS = 4,
	SP_UCHE_ATOMICS = 5,
	SP_VS_TEX_INSTRUCTIONS = 6,
	SP_VS_CFLOW_INSTRUCTIONS = 7,
	SP_VS_EFU_INSTRUCTIONS = 8,
	SP_VS_FULL_ALU_INSTRUCTIONS = 9,
	SP_VS_HALF_ALU_INSTRUCTIONS = 10,
	SP_FS_TEX_INSTRUCTIONS = 11,
	SP_FS_CFLOW_INSTRUCTIONS = 12,
	SP_FS_EFU_INSTRUCTIONS = 13,
	SP_FS_FULL_ALU_INSTRUCTIONS = 14,
	SP_FS_HALF_ALU_INSTRUCTIONS = 15,
	SP_FS_BARY_INSTRUCTIONS = 16,
	SP_VS_INSTRUCTIONS = 17,
	SP_FS_INSTRUCTIONS = 18,
	SP_ADDR_LOCK_COUNT = 19,
	SP_UCHE_READ_TRANS = 20,
	SP_UCHE_WRITE_TRANS = 21,
	SP_EXPORT_VPC_TRANS = 22,
	SP_EXPORT_RB_TRANS = 23,
	SP_PIXELS_KILLED = 24,
	SP_ICL1_REQUESTS = 25,
	SP_ICL1_MISSES = 26,
	SP_ICL0_REQUESTS = 27,
	SP_ICL0_MISSES = 28,
	SP_ALU_ACTIVE_CYCLES = 29,
	SP_EFU_ACTIVE_CYCLES = 30,
	SP_STALL_CYCLES_BY_VPC = 31,
	SP_STALL_CYCLES_BY_TP = 32,
	SP_STALL_CYCLES_BY_UCHE = 33,
	SP_STALL_CYCLES_BY_RB = 34,
	SP_ACTIVE_CYCLES_ANY = 35,
	SP_ACTIVE_CYCLES_ALL = 36,
};

enum a3xx_tp_perfcounter_select {
	TPL1_TPPERF_L1_REQUESTS = 0,
	TPL1_TPPERF_TP0_L1_REQUESTS = 1,
	TPL1_TPPERF_TP0_L1_MISSES = 2,
	TPL1_TPPERF_TP1_L1_REQUESTS = 3,
	TPL1_TPPERF_TP1_L1_MISSES = 4,
	TPL1_TPPERF_TP2_L1_REQUESTS = 5,
	TPL1_TPPERF_TP2_L1_MISSES = 6,
	TPL1_TPPERF_TP3_L1_REQUESTS = 7,
	TPL1_TPPERF_TP3_L1_MISSES = 8,
	TPL1_TPPERF_OUTPUT_TEXELS_POINT = 9,
	TPL1_TPPERF_OUTPUT_TEXELS_BILINEAR = 10,
	TPL1_TPPERF_OUTPUT_TEXELS_MIP = 11,
	TPL1_TPPERF_OUTPUT_TEXELS_ANISO = 12,
	TPL1_TPPERF_BILINEAR_OPS = 13,
	TPL1_TPPERF_QUADSQUADS_OFFSET = 14,
	TPL1_TPPERF_QUADQUADS_SHADOW = 15,
	TPL1_TPPERF_QUADS_ARRAY = 16,
	TPL1_TPPERF_QUADS_PROJECTION = 17,
	TPL1_TPPERF_QUADS_GRADIENT = 18,
	TPL1_TPPERF_QUADS_1D2D = 19,
	TPL1_TPPERF_QUADS_3DCUBE = 20,
	TPL1_TPPERF_ZERO_LOD = 21,
	TPL1_TPPERF_OUTPUT_TEXELS = 22,
	TPL1_TPPERF_ACTIVE_CYCLES_ANY = 23,
	TPL1_TPPERF_ACTIVE_CYCLES_ALL = 24,
	TPL1_TPPERF_STALL_CYCLES_BY_ARB = 25,
	TPL1_TPPERF_LATENCY = 26,
	TPL1_TPPERF_LATENCY_TRANS = 27,
};

enum a3xx_vfd_perfcounter_select {
	VFD_PERF_UCHE_BYTE_FETCHED = 0,
	VFD_PERF_UCHE_TRANS = 1,
	VFD_PERF_VPC_BYPASS_COMPONENTS = 2,
	VFD_PERF_FETCH_INSTRUCTIONS = 3,
	VFD_PERF_DECODE_INSTRUCTIONS = 4,
	VFD_PERF_ACTIVE_CYCLES = 5,
	VFD_PERF_STALL_CYCLES_UCHE = 6,
	VFD_PERF_STALL_CYCLES_HLSQ = 7,
	VFD_PERF_STALL_CYCLES_VPC_BYPASS = 8,
	VFD_PERF_STALL_CYCLES_VPC_ALLOC = 9,
};

enum a3xx_vpc_perfcounter_select {
	VPC_PERF_SP_LM_PRIMITIVES = 0,
	VPC_PERF_COMPONENTS_FROM_SP = 1,
	VPC_PERF_SP_LM_COMPONENTS = 2,
	VPC_PERF_ACTIVE_CYCLES = 3,
	VPC_PERF_STALL_CYCLES_LM = 4,
	VPC_PERF_STALL_CYCLES_RAS = 5,
};

enum a3xx_uche_perfcounter_select {
	UCHE_UCHEPERF_VBIF_READ_BEATS_TP = 0,
	UCHE_UCHEPERF_VBIF_READ_BEATS_VFD = 1,
	UCHE_UCHEPERF_VBIF_READ_BEATS_HLSQ = 2,
	UCHE_UCHEPERF_VBIF_READ_BEATS_MARB = 3,
	UCHE_UCHEPERF_VBIF_READ_BEATS_SP = 4,
	UCHE_UCHEPERF_READ_REQUESTS_TP = 8,
	UCHE_UCHEPERF_READ_REQUESTS_VFD = 9,
	UCHE_UCHEPERF_READ_REQUESTS_HLSQ = 10,
	UCHE_UCHEPERF_READ_REQUESTS_MARB = 11,
	UCHE_UCHEPERF_READ_REQUESTS_SP = 12,
	UCHE_UCHEPERF_WRITE_REQUESTS_MARB = 13,
	UCHE_UCHEPERF_WRITE_REQUESTS_SP = 14,
	UCHE_UCHEPERF_TAG_CHECK_FAILS = 15,
	UCHE_UCHEPERF_EVICTS = 16,
	UCHE_UCHEPERF_FLUSHES = 17,
	UCHE_UCHEPERF_VBIF_LATENCY_CYCLES = 18,
	UCHE_UCHEPERF_VBIF_LATENCY_SAMPLES = 19,
	UCHE_UCHEPERF_ACTIVE_CYCLES = 20,
};

enum a3xx_intp_mode {
	SMOOTH = 0,
	FLAT = 1,
	ZERO = 2,
	ONE = 3,
};

enum a3xx_repl_mode {
	S = 1,
	T = 2,
	ONE_T = 3,
};

enum a3xx_tex_filter {
	A3XX_TEX_NEAREST = 0,
	A3XX_TEX_LINEAR = 1,
	A3XX_TEX_ANISO = 2,
};

enum a3xx_tex_clamp {
	A3XX_TEX_REPEAT = 0,
	A3XX_TEX_CLAMP_TO_EDGE = 1,
	A3XX_TEX_MIRROR_REPEAT = 2,
	A3XX_TEX_CLAMP_TO_BORDER = 3,
	A3XX_TEX_MIRROR_CLAMP = 4,
};

enum a3xx_tex_aniso {
	A3XX_TEX_ANISO_1 = 0,
	A3XX_TEX_ANISO_2 = 1,
	A3XX_TEX_ANISO_4 = 2,
	A3XX_TEX_ANISO_8 = 3,
	A3XX_TEX_ANISO_16 = 4,
};

enum a3xx_tex_swiz {
	A3XX_TEX_X = 0,
	A3XX_TEX_Y = 1,
	A3XX_TEX_Z = 2,
	A3XX_TEX_W = 3,
	A3XX_TEX_ZERO = 4,
	A3XX_TEX_ONE = 5,
};

enum a3xx_tex_type {
	A3XX_TEX_1D = 0,
	A3XX_TEX_2D = 1,
	A3XX_TEX_CUBE = 2,
	A3XX_TEX_3D = 3,
};

enum a3xx_tex_msaa {
	A3XX_TPL1_MSAA1X = 0,
	A3XX_TPL1_MSAA2X = 1,
	A3XX_TPL1_MSAA4X = 2,
	A3XX_TPL1_MSAA8X = 3,
};

#define A3XX_INT0_RBBM_GPU_IDLE					0x00000001
#define A3XX_INT0_RBBM_AHB_ERROR				0x00000002
#define A3XX_INT0_RBBM_REG_TIMEOUT				0x00000004
#define A3XX_INT0_RBBM_ME_MS_TIMEOUT				0x00000008
#define A3XX_INT0_RBBM_PFP_MS_TIMEOUT				0x00000010
#define A3XX_INT0_RBBM_ATB_BUS_OVERFLOW				0x00000020
#define A3XX_INT0_VFD_ERROR					0x00000040
#define A3XX_INT0_CP_SW_INT					0x00000080
#define A3XX_INT0_CP_T0_PACKET_IN_IB				0x00000100
#define A3XX_INT0_CP_OPCODE_ERROR				0x00000200
#define A3XX_INT0_CP_RESERVED_BIT_ERROR				0x00000400
#define A3XX_INT0_CP_HW_FAULT					0x00000800
#define A3XX_INT0_CP_DMA					0x00001000
#define A3XX_INT0_CP_IB2_INT					0x00002000
#define A3XX_INT0_CP_IB1_INT					0x00004000
#define A3XX_INT0_CP_RB_INT					0x00008000
#define A3XX_INT0_CP_REG_PROTECT_FAULT				0x00010000
#define A3XX_INT0_CP_RB_DONE_TS					0x00020000
#define A3XX_INT0_CP_VS_DONE_TS					0x00040000
#define A3XX_INT0_CP_PS_DONE_TS					0x00080000
#define A3XX_INT0_CACHE_FLUSH_TS				0x00100000
#define A3XX_INT0_CP_AHB_ERROR_HALT				0x00200000
#define A3XX_INT0_MISC_HANG_DETECT				0x01000000
#define A3XX_INT0_UCHE_OOB_ACCESS				0x02000000
#define REG_A3XX_RBBM_HW_VERSION				0x00000000

#define REG_A3XX_RBBM_HW_RELEASE				0x00000001

#define REG_A3XX_RBBM_HW_CONFIGURATION				0x00000002

#define REG_A3XX_RBBM_CLOCK_CTL					0x00000010

#define REG_A3XX_RBBM_SP_HYST_CNT				0x00000012

#define REG_A3XX_RBBM_SW_RESET_CMD				0x00000018

#define REG_A3XX_RBBM_AHB_CTL0					0x00000020

#define REG_A3XX_RBBM_AHB_CTL1					0x00000021

#define REG_A3XX_RBBM_AHB_CMD					0x00000022

#define REG_A3XX_RBBM_AHB_ERROR_STATUS				0x00000027

#define REG_A3XX_RBBM_GPR0_CTL					0x0000002e

#define REG_A3XX_RBBM_STATUS					0x00000030
#define A3XX_RBBM_STATUS_HI_BUSY				0x00000001
#define A3XX_RBBM_STATUS_CP_ME_BUSY				0x00000002
#define A3XX_RBBM_STATUS_CP_PFP_BUSY				0x00000004
#define A3XX_RBBM_STATUS_CP_NRT_BUSY				0x00004000
#define A3XX_RBBM_STATUS_VBIF_BUSY				0x00008000
#define A3XX_RBBM_STATUS_TSE_BUSY				0x00010000
#define A3XX_RBBM_STATUS_RAS_BUSY				0x00020000
#define A3XX_RBBM_STATUS_RB_BUSY				0x00040000
#define A3XX_RBBM_STATUS_PC_DCALL_BUSY				0x00080000
#define A3XX_RBBM_STATUS_PC_VSD_BUSY				0x00100000
#define A3XX_RBBM_STATUS_VFD_BUSY				0x00200000
#define A3XX_RBBM_STATUS_VPC_BUSY				0x00400000
#define A3XX_RBBM_STATUS_UCHE_BUSY				0x00800000
#define A3XX_RBBM_STATUS_SP_BUSY				0x01000000
#define A3XX_RBBM_STATUS_TPL1_BUSY				0x02000000
#define A3XX_RBBM_STATUS_MARB_BUSY				0x04000000
#define A3XX_RBBM_STATUS_VSC_BUSY				0x08000000
#define A3XX_RBBM_STATUS_ARB_BUSY				0x10000000
#define A3XX_RBBM_STATUS_HLSQ_BUSY				0x20000000
#define A3XX_RBBM_STATUS_GPU_BUSY_NOHC				0x40000000
#define A3XX_RBBM_STATUS_GPU_BUSY				0x80000000

#define REG_A3XX_RBBM_NQWAIT_UNTIL				0x00000040

#define REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL			0x00000033

#define REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL			0x00000050

#define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL0			0x00000051

#define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL1			0x00000054

#define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL2			0x00000057

#define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL3			0x0000005a

#define REG_A3XX_RBBM_INT_SET_CMD				0x00000060

#define REG_A3XX_RBBM_INT_CLEAR_CMD				0x00000061

#define REG_A3XX_RBBM_INT_0_MASK				0x00000063

#define REG_A3XX_RBBM_INT_0_STATUS				0x00000064

#define REG_A3XX_RBBM_PERFCTR_CTL				0x00000080
#define A3XX_RBBM_PERFCTR_CTL_ENABLE				0x00000001

#define REG_A3XX_RBBM_PERFCTR_LOAD_CMD0				0x00000081

#define REG_A3XX_RBBM_PERFCTR_LOAD_CMD1				0x00000082

#define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_LO			0x00000084

#define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_HI			0x00000085

#define REG_A3XX_RBBM_PERFCOUNTER0_SELECT			0x00000086

#define REG_A3XX_RBBM_PERFCOUNTER1_SELECT			0x00000087

#define REG_A3XX_RBBM_GPU_BUSY_MASKED				0x00000088

#define REG_A3XX_RBBM_PERFCTR_CP_0_LO				0x00000090

#define REG_A3XX_RBBM_PERFCTR_CP_0_HI				0x00000091

#define REG_A3XX_RBBM_PERFCTR_RBBM_0_LO				0x00000092

#define REG_A3XX_RBBM_PERFCTR_RBBM_0_HI				0x00000093

#define REG_A3XX_RBBM_PERFCTR_RBBM_1_LO				0x00000094

#define REG_A3XX_RBBM_PERFCTR_RBBM_1_HI				0x00000095

#define REG_A3XX_RBBM_PERFCTR_PC_0_LO				0x00000096

#define REG_A3XX_RBBM_PERFCTR_PC_0_HI				0x00000097

#define REG_A3XX_RBBM_PERFCTR_PC_1_LO				0x00000098

#define REG_A3XX_RBBM_PERFCTR_PC_1_HI				0x00000099

#define REG_A3XX_RBBM_PERFCTR_PC_2_LO				0x0000009a

#define REG_A3XX_RBBM_PERFCTR_PC_2_HI				0x0000009b

#define REG_A3XX_RBBM_PERFCTR_PC_3_LO				0x0000009c

#define REG_A3XX_RBBM_PERFCTR_PC_3_HI				0x0000009d

#define REG_A3XX_RBBM_PERFCTR_VFD_0_LO				0x0000009e

#define REG_A3XX_RBBM_PERFCTR_VFD_0_HI				0x0000009f

#define REG_A3XX_RBBM_PERFCTR_VFD_1_LO				0x000000a0

#define REG_A3XX_RBBM_PERFCTR_VFD_1_HI				0x000000a1

#define REG_A3XX_RBBM_PERFCTR_HLSQ_0_LO				0x000000a2

#define REG_A3XX_RBBM_PERFCTR_HLSQ_0_HI				0x000000a3

#define REG_A3XX_RBBM_PERFCTR_HLSQ_1_LO				0x000000a4

#define REG_A3XX_RBBM_PERFCTR_HLSQ_1_HI				0x000000a5

#define REG_A3XX_RBBM_PERFCTR_HLSQ_2_LO				0x000000a6

#define REG_A3XX_RBBM_PERFCTR_HLSQ_2_HI				0x000000a7

#define REG_A3XX_RBBM_PERFCTR_HLSQ_3_LO				0x000000a8

#define REG_A3XX_RBBM_PERFCTR_HLSQ_3_HI				0x000000a9

#define REG_A3XX_RBBM_PERFCTR_HLSQ_4_LO				0x000000aa

#define REG_A3XX_RBBM_PERFCTR_HLSQ_4_HI				0x000000ab

#define REG_A3XX_RBBM_PERFCTR_HLSQ_5_LO				0x000000ac

#define REG_A3XX_RBBM_PERFCTR_HLSQ_5_HI				0x000000ad

#define REG_A3XX_RBBM_PERFCTR_VPC_0_LO				0x000000ae

#define REG_A3XX_RBBM_PERFCTR_VPC_0_HI				0x000000af

#define REG_A3XX_RBBM_PERFCTR_VPC_1_LO				0x000000b0

#define REG_A3XX_RBBM_PERFCTR_VPC_1_HI				0x000000b1

#define REG_A3XX_RBBM_PERFCTR_TSE_0_LO				0x000000b2

#define REG_A3XX_RBBM_PERFCTR_TSE_0_HI				0x000000b3

#define REG_A3XX_RBBM_PERFCTR_TSE_1_LO				0x000000b4

#define REG_A3XX_RBBM_PERFCTR_TSE_1_HI				0x000000b5

#define REG_A3XX_RBBM_PERFCTR_RAS_0_LO				0x000000b6

#define REG_A3XX_RBBM_PERFCTR_RAS_0_HI				0x000000b7

#define REG_A3XX_RBBM_PERFCTR_RAS_1_LO				0x000000b8

#define REG_A3XX_RBBM_PERFCTR_RAS_1_HI				0x000000b9

#define REG_A3XX_RBBM_PERFCTR_UCHE_0_LO				0x000000ba

#define REG_A3XX_RBBM_PERFCTR_UCHE_0_HI				0x000000bb

#define REG_A3XX_RBBM_PERFCTR_UCHE_1_LO				0x000000bc

#define REG_A3XX_RBBM_PERFCTR_UCHE_1_HI				0x000000bd

#define REG_A3XX_RBBM_PERFCTR_UCHE_2_LO				0x000000be

#define REG_A3XX_RBBM_PERFCTR_UCHE_2_HI				0x000000bf

#define REG_A3XX_RBBM_PERFCTR_UCHE_3_LO				0x000000c0

#define REG_A3XX_RBBM_PERFCTR_UCHE_3_HI				0x000000c1

#define REG_A3XX_RBBM_PERFCTR_UCHE_4_LO				0x000000c2

#define REG_A3XX_RBBM_PERFCTR_UCHE_4_HI				0x000000c3

#define REG_A3XX_RBBM_PERFCTR_UCHE_5_LO				0x000000c4

#define REG_A3XX_RBBM_PERFCTR_UCHE_5_HI				0x000000c5

#define REG_A3XX_RBBM_PERFCTR_TP_0_LO				0x000000c6

#define REG_A3XX_RBBM_PERFCTR_TP_0_HI				0x000000c7

#define REG_A3XX_RBBM_PERFCTR_TP_1_LO				0x000000c8

#define REG_A3XX_RBBM_PERFCTR_TP_1_HI				0x000000c9

#define REG_A3XX_RBBM_PERFCTR_TP_2_LO				0x000000ca

#define REG_A3XX_RBBM_PERFCTR_TP_2_HI				0x000000cb

#define REG_A3XX_RBBM_PERFCTR_TP_3_LO				0x000000cc

#define REG_A3XX_RBBM_PERFCTR_TP_3_HI				0x000000cd

#define REG_A3XX_RBBM_PERFCTR_TP_4_LO				0x000000ce

#define REG_A3XX_RBBM_PERFCTR_TP_4_HI				0x000000cf

#define REG_A3XX_RBBM_PERFCTR_TP_5_LO				0x000000d0

#define REG_A3XX_RBBM_PERFCTR_TP_5_HI				0x000000d1

#define REG_A3XX_RBBM_PERFCTR_SP_0_LO				0x000000d2

#define REG_A3XX_RBBM_PERFCTR_SP_0_HI				0x000000d3

#define REG_A3XX_RBBM_PERFCTR_SP_1_LO				0x000000d4

#define REG_A3XX_RBBM_PERFCTR_SP_1_HI				0x000000d5

#define REG_A3XX_RBBM_PERFCTR_SP_2_LO				0x000000d6

#define REG_A3XX_RBBM_PERFCTR_SP_2_HI				0x000000d7

#define REG_A3XX_RBBM_PERFCTR_SP_3_LO				0x000000d8

#define REG_A3XX_RBBM_PERFCTR_SP_3_HI				0x000000d9

#define REG_A3XX_RBBM_PERFCTR_SP_4_LO				0x000000da

#define REG_A3XX_RBBM_PERFCTR_SP_4_HI				0x000000db

#define REG_A3XX_RBBM_PERFCTR_SP_5_LO				0x000000dc

#define REG_A3XX_RBBM_PERFCTR_SP_5_HI				0x000000dd

#define REG_A3XX_RBBM_PERFCTR_SP_6_LO				0x000000de

#define REG_A3XX_RBBM_PERFCTR_SP_6_HI				0x000000df

#define REG_A3XX_RBBM_PERFCTR_SP_7_LO				0x000000e0

#define REG_A3XX_RBBM_PERFCTR_SP_7_HI				0x000000e1

#define REG_A3XX_RBBM_PERFCTR_RB_0_LO				0x000000e2

#define REG_A3XX_RBBM_PERFCTR_RB_0_HI				0x000000e3

#define REG_A3XX_RBBM_PERFCTR_RB_1_LO				0x000000e4

#define REG_A3XX_RBBM_PERFCTR_RB_1_HI				0x000000e5

#define REG_A3XX_RBBM_PERFCTR_PWR_0_LO				0x000000ea

#define REG_A3XX_RBBM_PERFCTR_PWR_0_HI				0x000000eb

#define REG_A3XX_RBBM_PERFCTR_PWR_1_LO				0x000000ec

#define REG_A3XX_RBBM_PERFCTR_PWR_1_HI				0x000000ed

#define REG_A3XX_RBBM_RBBM_CTL					0x00000100

#define REG_A3XX_RBBM_DEBUG_BUS_CTL				0x00000111

#define REG_A3XX_RBBM_DEBUG_BUS_DATA_STATUS			0x00000112

#define REG_A3XX_CP_PFP_UCODE_ADDR				0x000001c9

#define REG_A3XX_CP_PFP_UCODE_DATA				0x000001ca

#define REG_A3XX_CP_ROQ_ADDR					0x000001cc

#define REG_A3XX_CP_ROQ_DATA					0x000001cd

#define REG_A3XX_CP_MERCIU_ADDR					0x000001d1

#define REG_A3XX_CP_MERCIU_DATA					0x000001d2

#define REG_A3XX_CP_MERCIU_DATA2				0x000001d3

#define REG_A3XX_CP_MEQ_ADDR					0x000001da

#define REG_A3XX_CP_MEQ_DATA					0x000001db

#define REG_A3XX_CP_WFI_PEND_CTR				0x000001f5

#define REG_A3XX_RBBM_PM_OVERRIDE2				0x0000039d

#define REG_A3XX_CP_PERFCOUNTER_SELECT				0x00000445

#define REG_A3XX_CP_HW_FAULT					0x0000045c

#define REG_A3XX_CP_PROTECT_CTRL				0x0000045e

#define REG_A3XX_CP_PROTECT_STATUS				0x0000045f

static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0) { return 0x00000460 + 0x1*i0; }

static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; }

#define REG_A3XX_CP_AHB_FAULT					0x0000054d

#define REG_A3XX_SQ_GPR_MANAGEMENT				0x00000d00

#define REG_A3XX_SQ_INST_STORE_MANAGMENT			0x00000d02

#define REG_A3XX_TP0_CHICKEN					0x00000e1e

#define REG_A3XX_SP_GLOBAL_MEM_SIZE				0x00000e22

#define REG_A3XX_SP_GLOBAL_MEM_ADDR				0x00000e23

#define REG_A3XX_GRAS_CL_CLIP_CNTL				0x00002040
#define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER			0x00001000
#define A3XX_GRAS_CL_CLIP_CNTL_IJ_NON_PERSP_CENTER		0x00002000
#define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTROID		0x00004000
#define A3XX_GRAS_CL_CLIP_CNTL_IJ_NON_PERSP_CENTROID		0x00008000
#define A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE			0x00010000
#define A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE		0x00020000
#define A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE		0x00080000
#define A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE			0x00100000
#define A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE		0x00200000
#define A3XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z			0x00400000
#define A3XX_GRAS_CL_CLIP_CNTL_ZCOORD				0x00800000
#define A3XX_GRAS_CL_CLIP_CNTL_WCOORD				0x01000000
#define A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE			0x02000000
#define A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__MASK	0x1c000000
#define A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT	26
static inline uint32_t A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(uint32_t val)
{
	return ((val) << A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT) & A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__MASK;
}

#define REG_A3XX_GRAS_CL_GB_CLIP_ADJ				0x00002044
#define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK			0x000003ff
#define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT			0
static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val)
{
	return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK;
}
#define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK			0x000ffc00
#define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT			10
static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val)
{
	return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK;
}

#define REG_A3XX_GRAS_CL_VPORT_XOFFSET				0x00002048
#define A3XX_GRAS_CL_VPORT_XOFFSET__MASK			0xffffffff
#define A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT			0
static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val)
{
	return ((fui(val)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK;
}

#define REG_A3XX_GRAS_CL_VPORT_XSCALE				0x00002049
#define A3XX_GRAS_CL_VPORT_XSCALE__MASK				0xffffffff
#define A3XX_GRAS_CL_VPORT_XSCALE__SHIFT			0
static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val)
{
	return ((fui(val)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_XSCALE__MASK;
}

#define REG_A3XX_GRAS_CL_VPORT_YOFFSET				0x0000204a
#define A3XX_GRAS_CL_VPORT_YOFFSET__MASK			0xffffffff
#define A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT			0
static inline uint32_t A3XX_GRAS_CL_VPORT_YOFFSET(float val)
{
	return ((fui(val)) << A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_YOFFSET__MASK;
}

#define REG_A3XX_GRAS_CL_VPORT_YSCALE				0x0000204b
#define A3XX_GRAS_CL_VPORT_YSCALE__MASK				0xffffffff
#define A3XX_GRAS_CL_VPORT_YSCALE__SHIFT			0
static inline uint32_t A3XX_GRAS_CL_VPORT_YSCALE(float val)
{
	return ((fui(val)) << A3XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_YSCALE__MASK;
}

#define REG_A3XX_GRAS_CL_VPORT_ZOFFSET				0x0000204c
#define A3XX_GRAS_CL_VPORT_ZOFFSET__MASK			0xffffffff
#define A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT			0
static inline uint32_t A3XX_GRAS_CL_VPORT_ZOFFSET(float val)
{
	return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_ZOFFSET__MASK;
}

#define REG_A3XX_GRAS_CL_VPORT_ZSCALE				0x0000204d
#define A3XX_GRAS_CL_VPORT_ZSCALE__MASK				0xffffffff
#define A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT			0
static inline uint32_t A3XX_GRAS_CL_VPORT_ZSCALE(float val)
{
	return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_ZSCALE__MASK;
}

#define REG_A3XX_GRAS_SU_POINT_MINMAX				0x00002068
#define A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK			0x0000ffff
#define A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT			0
static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MIN(float val)
{
	return ((((uint32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
}
#define A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK			0xffff0000
#define A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT			16
static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MAX(float val)
{
	return ((((uint32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
}

#define REG_A3XX_GRAS_SU_POINT_SIZE				0x00002069
#define A3XX_GRAS_SU_POINT_SIZE__MASK				0xffffffff
#define A3XX_GRAS_SU_POINT_SIZE__SHIFT				0
static inline uint32_t A3XX_GRAS_SU_POINT_SIZE(float val)
{
	return ((((int32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_SIZE__SHIFT) & A3XX_GRAS_SU_POINT_SIZE__MASK;
}

#define REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE			0x0000206c
#define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK		0x00ffffff
#define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT		0
static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val)
{
	return ((((int32_t)(val * 1048576.0))) << A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK;
}

#define REG_A3XX_GRAS_SU_POLY_OFFSET_OFFSET			0x0000206d
#define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK			0xffffffff
#define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT			0
static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
{
	return ((((int32_t)(val * 64.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
}

#define REG_A3XX_GRAS_SU_MODE_CONTROL				0x00002070
#define A3XX_GRAS_SU_MODE_CONTROL_CULL_FRONT			0x00000001
#define A3XX_GRAS_SU_MODE_CONTROL_CULL_BACK			0x00000002
#define A3XX_GRAS_SU_MODE_CONTROL_FRONT_CW			0x00000004
#define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK		0x000007f8
#define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT		3
static inline uint32_t A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val)
{
	return ((((int32_t)(val * 4.0))) << A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK;
}
#define A3XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET			0x00000800

#define REG_A3XX_GRAS_SC_CONTROL				0x00002072
#define A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK			0x000000f0
#define A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT			4
static inline uint32_t A3XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val)
{
	return ((val) << A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK;
}
#define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK			0x00000f00
#define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT		8
static inline uint32_t A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(enum a3xx_msaa_samples val)
{
	return ((val) << A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK;
}
#define A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK			0x0000f000
#define A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT			12
static inline uint32_t A3XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val)
{
	return ((val) << A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK;
}

#define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL			0x00002074
#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE	0x80000000
#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK			0x00007fff
#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT			0
static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
{
	return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK;
}
#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK			0x7fff0000
#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT			16
static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
{
	return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK;
}

#define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_BR			0x00002075
#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE	0x80000000
#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK			0x00007fff
#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT			0
static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
{
	return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK;
}
#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK			0x7fff0000
#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT			16
static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
{
	return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK;
}

#define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL			0x00002079
#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE	0x80000000
#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK			0x00007fff
#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT			0
static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
{
	return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
}
#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK			0x7fff0000
#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT			16
static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
{
	return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
}

#define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_BR			0x0000207a
#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE	0x80000000
#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK			0x00007fff
#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT			0
static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
{
	return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
}
#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK			0x7fff0000
#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT			16
static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
{
	return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
}

#define REG_A3XX_RB_MODE_CONTROL				0x000020c0
#define A3XX_RB_MODE_CONTROL_GMEM_BYPASS			0x00000080
#define A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK			0x00000700
#define A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT			8
static inline uint32_t A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode val)
{
	return ((val) << A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT) & A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK;
}
#define A3XX_RB_MODE_CONTROL_MRT__MASK				0x00003000
#define A3XX_RB_MODE_CONTROL_MRT__SHIFT				12
static inline uint32_t A3XX_RB_MODE_CONTROL_MRT(uint32_t val)
{
	return ((val) << A3XX_RB_MODE_CONTROL_MRT__SHIFT) & A3XX_RB_MODE_CONTROL_MRT__MASK;
}
#define A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE		0x00008000
#define A3XX_RB_MODE_CONTROL_PACKER_TIMER_ENABLE		0x00010000

#define REG_A3XX_RB_RENDER_CONTROL				0x000020c1
#define A3XX_RB_RENDER_CONTROL_DUAL_COLOR_IN_ENABLE		0x00000001
#define A3XX_RB_RENDER_CONTROL_YUV_IN_ENABLE			0x00000002
#define A3XX_RB_RENDER_CONTROL_COV_VALUE_INPUT_ENABLE		0x00000004
#define A3XX_RB_RENDER_CONTROL_FACENESS				0x00000008
#define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK			0x00000ff0
#define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT			4
static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val)
{
	return ((val >> 5) << A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT) & A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK;
}
#define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE		0x00001000
#define A3XX_RB_RENDER_CONTROL_ENABLE_GMEM			0x00002000
#define A3XX_RB_RENDER_CONTROL_COORD_MASK__MASK			0x0003c000
#define A3XX_RB_RENDER_CONTROL_COORD_MASK__SHIFT		14
static inline uint32_t A3XX_RB_RENDER_CONTROL_COORD_MASK(uint32_t val)
{
	return ((val) << A3XX_RB_RENDER_CONTROL_COORD_MASK__SHIFT) & A3XX_RB_RENDER_CONTROL_COORD_MASK__MASK;
}
#define A3XX_RB_RENDER_CONTROL_I_CLAMP_ENABLE			0x00080000
#define A3XX_RB_RENDER_CONTROL_COV_VALUE_OUTPUT_ENABLE		0x00100000
#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST			0x00400000
#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK		0x07000000
#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT		24
static inline uint32_t A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
{
	return ((val) << A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK;
}
#define A3XX_RB_RENDER_CONTROL_ALPHA_TO_COVERAGE		0x40000000
#define A3XX_RB_RENDER_CONTROL_ALPHA_TO_ONE			0x80000000

#define REG_A3XX_RB_MSAA_CONTROL				0x000020c2
#define A3XX_RB_MSAA_CONTROL_DISABLE				0x00000400
#define A3XX_RB_MSAA_CONTROL_SAMPLES__MASK			0x0000f000
#define A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT			12
static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLES(enum a3xx_msaa_samples val)
{
	return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLES__MASK;
}
#define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK			0xffff0000
#define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT			16
static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(uint32_t val)
{
	return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK;
}

#define REG_A3XX_RB_ALPHA_REF					0x000020c3
#define A3XX_RB_ALPHA_REF_UINT__MASK				0x0000ff00
#define A3XX_RB_ALPHA_REF_UINT__SHIFT				8
static inline uint32_t A3XX_RB_ALPHA_REF_UINT(uint32_t val)
{
	return ((val) << A3XX_RB_ALPHA_REF_UINT__SHIFT) & A3XX_RB_ALPHA_REF_UINT__MASK;
}
#define A3XX_RB_ALPHA_REF_FLOAT__MASK				0xffff0000
#define A3XX_RB_ALPHA_REF_FLOAT__SHIFT				16
static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val)
{
	return ((_mesa_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK;
}

static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; }

static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; }
#define A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE			0x00000008
#define A3XX_RB_MRT_CONTROL_BLEND				0x00000010
#define A3XX_RB_MRT_CONTROL_BLEND2				0x00000020
#define A3XX_RB_MRT_CONTROL_ROP_CODE__MASK			0x00000f00
#define A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT			8
static inline uint32_t A3XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
{
	return ((val) << A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A3XX_RB_MRT_CONTROL_ROP_CODE__MASK;
}
#define A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK			0x00003000
#define A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT			12
static inline uint32_t A3XX_RB_MRT_CONTROL_DITHER_MODE(enum adreno_rb_dither_mode val)
{
	return ((val) << A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT) & A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK;
}
#define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK		0x0f000000
#define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT		24
static inline uint32_t A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
{
	return ((val) << A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
}

static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020c5 + 0x4*i0; }
#define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK			0x0000003f
#define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT		0
static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a3xx_color_fmt val)
{
	return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
}
#define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK		0x000000c0
#define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT		6
static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a3xx_tile_mode val)
{
	return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
}
#define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK			0x00000c00
#define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT			10
static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
{
	return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
}
#define A3XX_RB_MRT_BUF_INFO_COLOR_SRGB				0x00004000
#define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK		0xfffe0000
#define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT		17
static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
{
	return ((val >> 5) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK;
}

static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 + 0x4*i0; }
#define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK		0xfffffff0
#define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT		4
static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val)
{
	return ((val >> 5) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK;
}

static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020c7 + 0x4*i0; }
#define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK		0x0000001f
#define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT		0
static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
{
	return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
}
#define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK	0x000000e0
#define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT	5
static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
{
	return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
}
#define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK		0x00001f00
#define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT	8
static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
{
	return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
}
#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK	0x001f0000
#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT	16
static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
{
	return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
}
#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK	0x00e00000
#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT	21
static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
{
	return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
}
#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK	0x1f000000
#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT	24
static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
{
	return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
}
#define A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE			0x20000000

#define REG_A3XX_RB_BLEND_RED					0x000020e4
#define A3XX_RB_BLEND_RED_UINT__MASK				0x000000ff
#define A3XX_RB_BLEND_RED_UINT__SHIFT				0
static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val)
{
	return ((val) << A3XX_RB_BLEND_RED_UINT__SHIFT) & A3XX_RB_BLEND_RED_UINT__MASK;
}
#define A3XX_RB_BLEND_RED_FLOAT__MASK				0xffff0000
#define A3XX_RB_BLEND_RED_FLOAT__SHIFT				16
static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val)
{
	return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK;
}

#define REG_A3XX_RB_BLEND_GREEN					0x000020e5
#define A3XX_RB_BLEND_GREEN_UINT__MASK				0x000000ff
#define A3XX_RB_BLEND_GREEN_UINT__SHIFT				0
static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val)
{
	return ((val) << A3XX_RB_BLEND_GREEN_UINT__SHIFT) & A3XX_RB_BLEND_GREEN_UINT__MASK;
}
#define A3XX_RB_BLEND_GREEN_FLOAT__MASK				0xffff0000
#define A3XX_RB_BLEND_GREEN_FLOAT__SHIFT			16
static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val)
{
	return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK;
}

#define REG_A3XX_RB_BLEND_BLUE					0x000020e6
#define A3XX_RB_BLEND_BLUE_UINT__MASK				0x000000ff
#define A3XX_RB_BLEND_BLUE_UINT__SHIFT				0
static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val)
{
	return ((val) << A3XX_RB_BLEND_BLUE_UINT__SHIFT) & A3XX_RB_BLEND_BLUE_UINT__MASK;
}
#define A3XX_RB_BLEND_BLUE_FLOAT__MASK				0xffff0000
#define A3XX_RB_BLEND_BLUE_FLOAT__SHIFT				16
static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val)
{
	return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK;
}

#define REG_A3XX_RB_BLEND_ALPHA					0x000020e7
#define A3XX_RB_BLEND_ALPHA_UINT__MASK				0x000000ff
#define A3XX_RB_BLEND_ALPHA_UINT__SHIFT				0
static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val)
{
	return ((val) << A3XX_RB_BLEND_ALPHA_UINT__SHIFT) & A3XX_RB_BLEND_ALPHA_UINT__MASK;
}
#define A3XX_RB_BLEND_ALPHA_FLOAT__MASK				0xffff0000
#define A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT			16
static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val)
{
	return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK;
}

#define REG_A3XX_RB_CLEAR_COLOR_DW0				0x000020e8

#define REG_A3XX_RB_CLEAR_COLOR_DW1				0x000020e9

#define REG_A3XX_RB_CLEAR_COLOR_DW2				0x000020ea

#define REG_A3XX_RB_CLEAR_COLOR_DW3				0x000020eb

#define REG_A3XX_RB_COPY_CONTROL				0x000020ec
#define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK			0x00000003
#define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT		0
static inline uint32_t A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val)
{
	return ((val) << A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK;
}
#define A3XX_RB_COPY_CONTROL_DEPTHCLEAR				0x00000008
#define A3XX_RB_COPY_CONTROL_MODE__MASK				0x00000070
#define A3XX_RB_COPY_CONTROL_MODE__SHIFT			4
static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val)
{
	return ((val) << A3XX_RB_COPY_CONTROL_MODE__SHIFT) & A3XX_RB_COPY_CONTROL_MODE__MASK;
}
#define A3XX_RB_COPY_CONTROL_MSAA_SRGB_DOWNSAMPLE		0x00000080
#define A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK			0x00000f00
#define A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT			8
static inline uint32_t A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val)
{
	return ((val) << A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK;
}
#define A3XX_RB_COPY_CONTROL_DEPTH32_RESOLVE			0x00001000
#define A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK			0xffffc000
#define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT			14
static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
{
	return ((val >> 14) << A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK;
}

#define REG_A3XX_RB_COPY_DEST_BASE				0x000020ed
#define A3XX_RB_COPY_DEST_BASE_BASE__MASK			0xfffffff0
#define A3XX_RB_COPY_DEST_BASE_BASE__SHIFT			4
static inline uint32_t A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val)
{
	return ((val >> 5) << A3XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A3XX_RB_COPY_DEST_BASE_BASE__MASK;
}

#define REG_A3XX_RB_COPY_DEST_PITCH				0x000020ee
#define A3XX_RB_COPY_DEST_PITCH_PITCH__MASK			0xffffffff
#define A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT			0
static inline uint32_t A3XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val)
{
	return ((val >> 5) << A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A3XX_RB_COPY_DEST_PITCH_PITCH__MASK;
}

#define REG_A3XX_RB_COPY_DEST_INFO				0x000020ef
#define A3XX_RB_COPY_DEST_INFO_TILE__MASK			0x00000003
#define A3XX_RB_COPY_DEST_INFO_TILE__SHIFT			0
static inline uint32_t A3XX_RB_COPY_DEST_INFO_TILE(enum a3xx_tile_mode val)
{
	return ((val) << A3XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A3XX_RB_COPY_DEST_INFO_TILE__MASK;
}
#define A3XX_RB_COPY_DEST_INFO_FORMAT__MASK			0x000000fc
#define A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT			2
static inline uint32_t A3XX_RB_COPY_DEST_INFO_FORMAT(enum a3xx_color_fmt val)
{
	return ((val) << A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A3XX_RB_COPY_DEST_INFO_FORMAT__MASK;
}
#define A3XX_RB_COPY_DEST_INFO_SWAP__MASK			0x00000300
#define A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT			8
static inline uint32_t A3XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val)
{
	return ((val) << A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A3XX_RB_COPY_DEST_INFO_SWAP__MASK;
}
#define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK		0x00000c00
#define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT		10
static inline uint32_t A3XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
{
	return ((val) << A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK;
}
#define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK		0x0003c000
#define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT		14
static inline uint32_t A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val)
{
	return ((val) << A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK;
}
#define A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK			0x001c0000
#define A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT			18
static inline uint32_t A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val)
{
	return ((val) << A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK;
}

#define REG_A3XX_RB_DEPTH_CONTROL				0x00002100
#define A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z			0x00000001
#define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE			0x00000002
#define A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE			0x00000004
#define A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE			0x00000008
#define A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK			0x00000070
#define A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT			4
static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
{
	return ((val) << A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK;
}
#define A3XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE			0x00000080
#define A3XX_RB_DEPTH_CONTROL_Z_READ_ENABLE			0x80000000

#define REG_A3XX_RB_DEPTH_CLEAR					0x00002101

#define REG_A3XX_RB_DEPTH_INFO					0x00002102
#define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK			0x00000003
#define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT			0
static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val)
{
	return ((val) << A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK;
}
#define A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK			0xfffff800
#define A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT			11
static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
{
	return ((val >> 12) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
}

#define REG_A3XX_RB_DEPTH_PITCH					0x00002103
#define A3XX_RB_DEPTH_PITCH__MASK				0xffffffff
#define A3XX_RB_DEPTH_PITCH__SHIFT				0
static inline uint32_t A3XX_RB_DEPTH_PITCH(uint32_t val)
{
	return ((val >> 3) << A3XX_RB_DEPTH_PITCH__SHIFT) & A3XX_RB_DEPTH_PITCH__MASK;
}

#define REG_A3XX_RB_STENCIL_CONTROL				0x00002104
#define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE			0x00000001
#define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF		0x00000002
#define A3XX_RB_STENCIL_CONTROL_STENCIL_READ			0x00000004
#define A3XX_RB_STENCIL_CONTROL_FUNC__MASK			0x00000700
#define A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT			8
static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
{
	return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC__MASK;
}
#define A3XX_RB_STENCIL_CONTROL_FAIL__MASK			0x00003800
#define A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT			11
static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
{
	return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL__MASK;
}
#define A3XX_RB_STENCIL_CONTROL_ZPASS__MASK			0x0001c000
#define A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT			14
static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
{
	return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS__MASK;
}
#define A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK			0x000e0000
#define A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT			17
static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
{
	return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
}
#define A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK			0x00700000
#define A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT			20
static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
{
	return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
}
#define A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK			0x03800000
#define A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT			23
static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
{
	return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
}
#define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK			0x1c000000
#define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT			26
static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
{
	return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
}
#define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK			0xe0000000
#define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT			29
static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
{
	return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
}

#define REG_A3XX_RB_STENCIL_CLEAR				0x00002105

#define REG_A3XX_RB_STENCIL_INFO				0x00002106
#define A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK			0xfffff800
#define A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT		11
static inline uint32_t A3XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val)
{
	return ((val >> 12) << A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK;
}

#define REG_A3XX_RB_STENCIL_PITCH				0x00002107
#define A3XX_RB_STENCIL_PITCH__MASK				0xffffffff
#define A3XX_RB_STENCIL_PITCH__SHIFT				0
static inline uint32_t A3XX_RB_STENCIL_PITCH(uint32_t val)
{
	return ((val >> 3) << A3XX_RB_STENCIL_PITCH__SHIFT) & A3XX_RB_STENCIL_PITCH__MASK;
}

#define REG_A3XX_RB_STENCILREFMASK				0x00002108
#define A3XX_RB_STENCILREFMASK_STENCILREF__MASK			0x000000ff
#define A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT		0
static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
{
	return ((val) << A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILREF__MASK;
}
#define A3XX_RB_STENCILREFMASK_STENCILMASK__MASK		0x0000ff00
#define A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT		8
static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
{
	return ((val) << A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILMASK__MASK;
}
#define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK		0x00ff0000
#define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT		16
static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
{
	return ((val) << A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
}

#define REG_A3XX_RB_STENCILREFMASK_BF				0x00002109
#define A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK		0x000000ff
#define A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT		0
static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
{
	return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
}
#define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK		0x0000ff00
#define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT		8
static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
{
	return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
}
#define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK	0x00ff0000
#define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT	16
static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
{
	return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
}

#define REG_A3XX_RB_LRZ_VSC_CONTROL				0x0000210c
#define A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE			0x00000002

#define REG_A3XX_RB_WINDOW_OFFSET				0x0000210e
#define A3XX_RB_WINDOW_OFFSET_X__MASK				0x0000ffff
#define A3XX_RB_WINDOW_OFFSET_X__SHIFT				0
static inline uint32_t A3XX_RB_WINDOW_OFFSET_X(uint32_t val)
{
	return ((val) << A3XX_RB_WINDOW_OFFSET_X__SHIFT) & A3XX_RB_WINDOW_OFFSET_X__MASK;
}
#define A3XX_RB_WINDOW_OFFSET_Y__MASK				0xffff0000
#define A3XX_RB_WINDOW_OFFSET_Y__SHIFT				16
static inline uint32_t A3XX_RB_WINDOW_OFFSET_Y(uint32_t val)
{
	return ((val) << A3XX_RB_WINDOW_OFFSET_Y__SHIFT) & A3XX_RB_WINDOW_OFFSET_Y__MASK;
}

#define REG_A3XX_RB_SAMPLE_COUNT_CONTROL			0x00002110
#define A3XX_RB_SAMPLE_COUNT_CONTROL_RESET			0x00000001
#define A3XX_RB_SAMPLE_COUNT_CONTROL_COPY			0x00000002

#define REG_A3XX_RB_SAMPLE_COUNT_ADDR				0x00002111

#define REG_A3XX_RB_Z_CLAMP_MIN					0x00002114

#define REG_A3XX_RB_Z_CLAMP_MAX					0x00002115

#define REG_A3XX_VGT_BIN_BASE					0x000021e1

#define REG_A3XX_VGT_BIN_SIZE					0x000021e2

#define REG_A3XX_PC_VSTREAM_CONTROL				0x000021e4
#define A3XX_PC_VSTREAM_CONTROL_SIZE__MASK			0x003f0000
#define A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT			16
static inline uint32_t A3XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val)
{
	return ((val) << A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A3XX_PC_VSTREAM_CONTROL_SIZE__MASK;
}
#define A3XX_PC_VSTREAM_CONTROL_N__MASK				0x07c00000
#define A3XX_PC_VSTREAM_CONTROL_N__SHIFT			22
static inline uint32_t A3XX_PC_VSTREAM_CONTROL_N(uint32_t val)
{
	return ((val) << A3XX_PC_VSTREAM_CONTROL_N__SHIFT) & A3XX_PC_VSTREAM_CONTROL_N__MASK;
}

#define REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL			0x000021ea

#define REG_A3XX_PC_PRIM_VTX_CNTL				0x000021ec
#define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK		0x0000001f
#define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT		0
static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(uint32_t val)
{
	return ((val) << A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK;
}
#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK	0x000000e0
#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT	5
static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
{
	return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK;
}
#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK		0x00000700
#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT	8
static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
{
	return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK;
}
#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_ENABLE			0x00001000
#define A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART			0x00100000
#define A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST		0x02000000
#define A3XX_PC_PRIM_VTX_CNTL_PSIZE				0x04000000

#define REG_A3XX_PC_RESTART_INDEX				0x000021ed

#define REG_A3XX_HLSQ_CONTROL_0_REG				0x00002200
#define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK		0x00000030
#define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT		4
static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
{
	return ((val) << A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
}
#define A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE		0x00000040
#define A3XX_HLSQ_CONTROL_0_REG_COMPUTEMODE			0x00000100
#define A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART			0x00000200
#define A3XX_HLSQ_CONTROL_0_REG_RESERVED2			0x00000400
#define A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__MASK	0x00fff000
#define A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__SHIFT	12
static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC(uint32_t val)
{
	return ((val) << A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__MASK;
}
#define A3XX_HLSQ_CONTROL_0_REG_FSONLYTEX			0x02000000
#define A3XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE			0x04000000
#define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK			0x08000000
#define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT		27
static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val)
{
	return ((val) << A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK;
}
#define A3XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE		0x10000000
#define A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE		0x20000000
#define A3XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE			0x40000000
#define A3XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT			0x80000000

#define REG_A3XX_HLSQ_CONTROL_1_REG				0x00002201
#define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK		0x000000c0
#define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT		6
static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val)
{
	return ((val) << A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK;
}
#define A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE		0x00000100
#define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__MASK		0x00ff0000
#define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__SHIFT		16
static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID(uint32_t val)
{
	return ((val) << A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__MASK;
}
#define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__MASK		0xff000000
#define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__SHIFT		24
static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID(uint32_t val)
{
	return ((val) << A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__MASK;
}

#define REG_A3XX_HLSQ_CONTROL_2_REG				0x00002202
#define A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__MASK		0x000003fc
#define A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__SHIFT		2
static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID(uint32_t val)
{
	return ((val) << A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__MASK;
}
#define A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__MASK		0x03fc0000
#define A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__SHIFT		18
static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID(uint32_t val)
{
	return ((val) << A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__MASK;
}
#define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK	0xfc000000
#define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT	26
static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val)
{
	return ((val) << A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK;
}

#define REG_A3XX_HLSQ_CONTROL_3_REG				0x00002203
#define A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID__MASK	0x000000ff
#define A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID__SHIFT	0
static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID(uint32_t val)
{
	return ((val) << A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID__MASK;
}
#define A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID__MASK	0x0000ff00
#define A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID__SHIFT	8
static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID(uint32_t val)
{
	return ((val) << A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID__MASK;
}
#define A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID__MASK	0x00ff0000
#define A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID__SHIFT	16
static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID(uint32_t val)
{
	return ((val) << A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID__MASK;
}
#define A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID__MASK	0xff000000
#define A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID__SHIFT	24
static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID(uint32_t val)
{
	return ((val) << A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID__MASK;
}

#define REG_A3XX_HLSQ_VS_CONTROL_REG				0x00002204
#define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK		0x000003ff
#define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT		0
static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val)
{
	return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK;
}
#define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK		0x001ff000
#define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT	12
static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val)
{
	return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK;
}
#define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK		0xff000000
#define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT		24
static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val)
{
	return ((val) << A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK;
}

#define REG_A3XX_HLSQ_FS_CONTROL_REG				0x00002205
#define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK		0x000003ff
#define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT		0
static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val)
{
	return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK;
}
#define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK		0x001ff000
#define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT	12
static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val)
{
	return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK;
}
#define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK		0xff000000
#define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT		24
static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val)
{
	return ((val) << A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK;
}

#define REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG			0x00002206
#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK	0x000001ff
#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT	0
static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val)
{
	return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK;
}
#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK	0x01ff0000
#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT	16
static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
{
	return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK;
}

#define REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG			0x00002207
#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK	0x000001ff
#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT	0
static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val)
{
	return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK;
}
#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK	0x01ff0000
#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT	16
static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
{
	return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK;
}

#define REG_A3XX_HLSQ_CL_NDRANGE_0_REG				0x0000220a
#define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK		0x00000003
#define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT		0
static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM(uint32_t val)
{
	return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK;
}
#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK		0x00000ffc
#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT		2
static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0(uint32_t val)
{
	return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK;
}
#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK		0x003ff000
#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT		12
static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1(uint32_t val)
{
	return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK;
}
#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK		0xffc00000
#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT		22
static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2(uint32_t val)
{
	return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK;
}

static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK(uint32_t i0) { return 0x0000220b + 0x2*i0; }

static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE(uint32_t i0) { return 0x0000220b + 0x2*i0; }

static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET(uint32_t i0) { return 0x0000220c + 0x2*i0; }

#define REG_A3XX_HLSQ_CL_CONTROL_0_REG				0x00002211

#define REG_A3XX_HLSQ_CL_CONTROL_1_REG				0x00002212

#define REG_A3XX_HLSQ_CL_KERNEL_CONST_REG			0x00002214

static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP(uint32_t i0) { return 0x00002215 + 0x1*i0; }

static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP_RATIO(uint32_t i0) { return 0x00002215 + 0x1*i0; }

#define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Y_REG			0x00002216

#define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Z_REG			0x00002217

#define REG_A3XX_HLSQ_CL_WG_OFFSET_REG				0x0000221a

#define REG_A3XX_VFD_CONTROL_0					0x00002240
#define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK			0x0003ffff
#define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT			0
static inline uint32_t A3XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val)
{
	return ((val) << A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK;
}
#define A3XX_VFD_CONTROL_0_PACKETSIZE__MASK			0x003c0000
#define A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT			18
static inline uint32_t A3XX_VFD_CONTROL_0_PACKETSIZE(uint32_t val)
{
	return ((val) << A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT) & A3XX_VFD_CONTROL_0_PACKETSIZE__MASK;
}
#define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK		0x07c00000
#define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT		22
static inline uint32_t A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val)
{
	return ((val) << A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK;
}
#define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK		0xf8000000
#define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT		27
static inline uint32_t A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val)
{
	return ((val) << A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK;
}

#define REG_A3XX_VFD_CONTROL_1					0x00002241
#define A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK			0x0000000f
#define A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT			0
static inline uint32_t A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val)
{
	return ((val) << A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK;
}
#define A3XX_VFD_CONTROL_1_MAXTHRESHOLD__MASK			0x000000f0
#define A3XX_VFD_CONTROL_1_MAXTHRESHOLD__SHIFT			4
static inline uint32_t A3XX_VFD_CONTROL_1_MAXTHRESHOLD(uint32_t val)
{
	return ((val) << A3XX_VFD_CONTROL_1_MAXTHRESHOLD__SHIFT) & A3XX_VFD_CONTROL_1_MAXTHRESHOLD__MASK;
}
#define A3XX_VFD_CONTROL_1_MINTHRESHOLD__MASK			0x00000f00
#define A3XX_VFD_CONTROL_1_MINTHRESHOLD__SHIFT			8
static inline uint32_t A3XX_VFD_CONTROL_1_MINTHRESHOLD(uint32_t val)
{
	return ((val) << A3XX_VFD_CONTROL_1_MINTHRESHOLD__SHIFT) & A3XX_VFD_CONTROL_1_MINTHRESHOLD__MASK;
}
#define A3XX_VFD_CONTROL_1_REGID4VTX__MASK			0x00ff0000
#define A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT			16
static inline uint32_t A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
{
	return ((val) << A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A3XX_VFD_CONTROL_1_REGID4VTX__MASK;
}
#define A3XX_VFD_CONTROL_1_REGID4INST__MASK			0xff000000
#define A3XX_VFD_CONTROL_1_REGID4INST__SHIFT			24
static inline uint32_t A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
{
	return ((val) << A3XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A3XX_VFD_CONTROL_1_REGID4INST__MASK;
}

#define REG_A3XX_VFD_INDEX_MIN					0x00002242

#define REG_A3XX_VFD_INDEX_MAX					0x00002243

#define REG_A3XX_VFD_INSTANCEID_OFFSET				0x00002244

#define REG_A3XX_VFD_INDEX_OFFSET				0x00002245

static inline uint32_t REG_A3XX_VFD_FETCH(uint32_t i0) { return 0x00002246 + 0x2*i0; }

static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x00002246 + 0x2*i0; }
#define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK			0x0000007f
#define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT			0
static inline uint32_t A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val)
{
	return ((val) << A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK;
}
#define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK			0x0000ff80
#define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT			7
static inline uint32_t A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val)
{
	return ((val) << A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK;
}
#define A3XX_VFD_FETCH_INSTR_0_INSTANCED			0x00010000
#define A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT			0x00020000
#define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK			0x00fc0000
#define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT			18
static inline uint32_t A3XX_VFD_FETCH_INSTR_0_INDEXCODE(uint32_t val)
{
	return ((val) << A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK;
}
#define A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK			0xff000000
#define A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT			24
static inline uint32_t A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val)
{
	return ((val) << A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK;
}

static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x00002247 + 0x2*i0; }

static inline uint32_t REG_A3XX_VFD_DECODE(uint32_t i0) { return 0x00002266 + 0x1*i0; }

static inline uint32_t REG_A3XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x00002266 + 0x1*i0; }
#define A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK			0x0000000f
#define A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT			0
static inline uint32_t A3XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val)
{
	return ((val) << A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK;
}
#define A3XX_VFD_DECODE_INSTR_CONSTFILL				0x00000010
#define A3XX_VFD_DECODE_INSTR_FORMAT__MASK			0x00000fc0
#define A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT			6
static inline uint32_t A3XX_VFD_DECODE_INSTR_FORMAT(enum a3xx_vtx_fmt val)
{
	return ((val) << A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A3XX_VFD_DECODE_INSTR_FORMAT__MASK;
}
#define A3XX_VFD_DECODE_INSTR_REGID__MASK			0x000ff000
#define A3XX_VFD_DECODE_INSTR_REGID__SHIFT			12
static inline uint32_t A3XX_VFD_DECODE_INSTR_REGID(uint32_t val)
{
	return ((val) << A3XX_VFD_DECODE_INSTR_REGID__SHIFT) & A3XX_VFD_DECODE_INSTR_REGID__MASK;
}
#define A3XX_VFD_DECODE_INSTR_INT				0x00100000
#define A3XX_VFD_DECODE_INSTR_SWAP__MASK			0x00c00000
#define A3XX_VFD_DECODE_INSTR_SWAP__SHIFT			22
static inline uint32_t A3XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
{
	return ((val) << A3XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A3XX_VFD_DECODE_INSTR_SWAP__MASK;
}
#define A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK			0x1f000000
#define A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT			24
static inline uint32_t A3XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val)
{
	return ((val) << A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK;
}
#define A3XX_VFD_DECODE_INSTR_LASTCOMPVALID			0x20000000
#define A3XX_VFD_DECODE_INSTR_SWITCHNEXT			0x40000000

#define REG_A3XX_VFD_VS_THREADING_THRESHOLD			0x0000227e
#define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK	0x0000000f
#define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT	0
static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(uint32_t val)
{
	return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK;
}
#define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK	0x0000ff00
#define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT	8
static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(uint32_t val)
{
	return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK;
}

#define REG_A3XX_VPC_ATTR					0x00002280
#define A3XX_VPC_ATTR_TOTALATTR__MASK				0x000001ff
#define A3XX_VPC_ATTR_TOTALATTR__SHIFT				0
static inline uint32_t A3XX_VPC_ATTR_TOTALATTR(uint32_t val)
{
	return ((val) << A3XX_VPC_ATTR_TOTALATTR__SHIFT) & A3XX_VPC_ATTR_TOTALATTR__MASK;
}
#define A3XX_VPC_ATTR_PSIZE					0x00000200
#define A3XX_VPC_ATTR_THRDASSIGN__MASK				0x0ffff000
#define A3XX_VPC_ATTR_THRDASSIGN__SHIFT				12
static inline uint32_t A3XX_VPC_ATTR_THRDASSIGN(uint32_t val)
{
	return ((val) << A3XX_VPC_ATTR_THRDASSIGN__SHIFT) & A3XX_VPC_ATTR_THRDASSIGN__MASK;
}
#define A3XX_VPC_ATTR_LMSIZE__MASK				0xf0000000
#define A3XX_VPC_ATTR_LMSIZE__SHIFT				28
static inline uint32_t A3XX_VPC_ATTR_LMSIZE(uint32_t val)
{
	return ((val) << A3XX_VPC_ATTR_LMSIZE__SHIFT) & A3XX_VPC_ATTR_LMSIZE__MASK;
}

#define REG_A3XX_VPC_PACK					0x00002281
#define A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK			0x0000ff00
#define A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT			8
static inline uint32_t A3XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val)
{
	return ((val) << A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK;
}
#define A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK			0x00ff0000
#define A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT			16
static inline uint32_t A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val)
{
	return ((val) << A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK;
}

static inline uint32_t REG_A3XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002282 + 0x1*i0; }

static inline uint32_t REG_A3XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002282 + 0x1*i0; }
#define A3XX_VPC_VARYING_INTERP_MODE_C0__MASK			0x00000003
#define A3XX_VPC_VARYING_INTERP_MODE_C0__SHIFT			0
static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C0(enum a3xx_intp_mode val)
{
	return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C0__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C0__MASK;
}
#define A3XX_VPC_VARYING_INTERP_MODE_C1__MASK			0x0000000c
#define A3XX_VPC_VARYING_INTERP_MODE_C1__SHIFT			2
static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C1(enum a3xx_intp_mode val)
{
	return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C1__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C1__MASK;
}
#define A3XX_VPC_VARYING_INTERP_MODE_C2__MASK			0x00000030
#define A3XX_VPC_VARYING_INTERP_MODE_C2__SHIFT			4
static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C2(enum a3xx_intp_mode val)
{
	return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C2__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C2__MASK;
}
#define A3XX_VPC_VARYING_INTERP_MODE_C3__MASK			0x000000c0
#define A3XX_VPC_VARYING_INTERP_MODE_C3__SHIFT			6
static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C3(enum a3xx_intp_mode val)
{
	return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C3__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C3__MASK;
}
#define A3XX_VPC_VARYING_INTERP_MODE_C4__MASK			0x00000300
#define A3XX_VPC_VARYING_INTERP_MODE_C4__SHIFT			8
static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C4(enum a3xx_intp_mode val)
{
	return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C4__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C4__MASK;
}
#define A3XX_VPC_VARYING_INTERP_MODE_C5__MASK			0x00000c00
#define A3XX_VPC_VARYING_INTERP_MODE_C5__SHIFT			10
static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C5(enum a3xx_intp_mode val)
{
	return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C5__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C5__MASK;
}
#define A3XX_VPC_VARYING_INTERP_MODE_C6__MASK			0x00003000
#define A3XX_VPC_VARYING_INTERP_MODE_C6__SHIFT			12
static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C6(enum a3xx_intp_mode val)
{
	return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C6__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C6__MASK;
}
#define A3XX_VPC_VARYING_INTERP_MODE_C7__MASK			0x0000c000
#define A3XX_VPC_VARYING_INTERP_MODE_C7__SHIFT			14
static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C7(enum a3xx_intp_mode val)
{
	return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C7__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C7__MASK;
}
#define A3XX_VPC_VARYING_INTERP_MODE_C8__MASK			0x00030000
#define A3XX_VPC_VARYING_INTERP_MODE_C8__SHIFT			16
static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C8(enum a3xx_intp_mode val)
{
	return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C8__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C8__MASK;
}
#define A3XX_VPC_VARYING_INTERP_MODE_C9__MASK			0x000c0000
#define A3XX_VPC_VARYING_INTERP_MODE_C9__SHIFT			18
static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C9(enum a3xx_intp_mode val)
{
	return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C9__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C9__MASK;
}
#define A3XX_VPC_VARYING_INTERP_MODE_CA__MASK			0x00300000
#define A3XX_VPC_VARYING_INTERP_MODE_CA__SHIFT			20
static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CA(enum a3xx_intp_mode val)
{
	return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CA__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CA__MASK;
}
#define A3XX_VPC_VARYING_INTERP_MODE_CB__MASK			0x00c00000
#define A3XX_VPC_VARYING_INTERP_MODE_CB__SHIFT			22
static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CB(enum a3xx_intp_mode val)
{
	return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CB__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CB__MASK;
}
#define A3XX_VPC_VARYING_INTERP_MODE_CC__MASK			0x03000000
#define A3XX_VPC_VARYING_INTERP_MODE_CC__SHIFT			24
static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CC(enum a3xx_intp_mode val)
{
	return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CC__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CC__MASK;
}
#define A3XX_VPC_VARYING_INTERP_MODE_CD__MASK			0x0c000000
#define A3XX_VPC_VARYING_INTERP_MODE_CD__SHIFT			26
static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CD(enum a3xx_intp_mode val)
{
	return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CD__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CD__MASK;
}
#define A3XX_VPC_VARYING_INTERP_MODE_CE__MASK			0x30000000
#define A3XX_VPC_VARYING_INTERP_MODE_CE__SHIFT			28
static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CE(enum a3xx_intp_mode val)
{
	return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CE__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CE__MASK;
}
#define A3XX_VPC_VARYING_INTERP_MODE_CF__MASK			0xc0000000
#define A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT			30
static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CF(enum a3xx_intp_mode val)
{
	return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CF__MASK;
}

static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00002286 + 0x1*i0; }

static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00002286 + 0x1*i0; }
#define A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK			0x00000003
#define A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT			0
static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C0(enum a3xx_repl_mode val)
{
	return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK			0x0000000c
#define A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT			2
static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C1(enum a3xx_repl_mode val)
{
	return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK			0x00000030
#define A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT			4
static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C2(enum a3xx_repl_mode val)
{
	return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK			0x000000c0
#define A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT			6
static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C3(enum a3xx_repl_mode val)
{
	return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK			0x00000300
#define A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT			8
static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C4(enum a3xx_repl_mode val)
{
	return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK			0x00000c00
#define A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT			10
static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C5(enum a3xx_repl_mode val)
{
	return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK			0x00003000
#define A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT			12
static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C6(enum a3xx_repl_mode val)
{
	return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK			0x0000c000
#define A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT			14
static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C7(enum a3xx_repl_mode val)
{
	return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK			0x00030000
#define A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT			16
static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C8(enum a3xx_repl_mode val)
{
	return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK			0x000c0000
#define A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT			18
static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C9(enum a3xx_repl_mode val)
{
	return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK			0x00300000
#define A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT			20
static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CA(enum a3xx_repl_mode val)
{
	return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK			0x00c00000
#define A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT			22
static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CB(enum a3xx_repl_mode val)
{
	return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK			0x03000000
#define A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT			24
static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CC(enum a3xx_repl_mode val)
{
	return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK			0x0c000000
#define A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT			26
static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CD(enum a3xx_repl_mode val)
{
	return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK			0x30000000
#define A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT			28
static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CE(enum a3xx_repl_mode val)
{
	return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK			0xc0000000
#define A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT			30
static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CF(enum a3xx_repl_mode val)
{
	return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK;
}

#define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0			0x0000228a

#define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_1			0x0000228b

#define REG_A3XX_SP_SP_CTRL_REG					0x000022c0
#define A3XX_SP_SP_CTRL_REG_RESOLVE				0x00010000
#define A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK			0x00040000
#define A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT			18
static inline uint32_t A3XX_SP_SP_CTRL_REG_CONSTMODE(uint32_t val)
{
	return ((val) << A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK;
}
#define A3XX_SP_SP_CTRL_REG_BINNING				0x00080000
#define A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK			0x00300000
#define A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT			20
static inline uint32_t A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val)
{
	return ((val) << A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK;
}
#define A3XX_SP_SP_CTRL_REG_L0MODE__MASK			0x00c00000
#define A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT			22
static inline uint32_t A3XX_SP_SP_CTRL_REG_L0MODE(uint32_t val)
{
	return ((val) << A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT) & A3XX_SP_SP_CTRL_REG_L0MODE__MASK;
}

#define REG_A3XX_SP_VS_CTRL_REG0				0x000022c4
#define A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK			0x00000001
#define A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT			0
static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
{
	return ((val) << A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK;
}
#define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK		0x00000002
#define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT		1
static inline uint32_t A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val)
{
	return ((val) << A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK;
}
#define A3XX_SP_VS_CTRL_REG0_CACHEINVALID			0x00000004
#define A3XX_SP_VS_CTRL_REG0_ALUSCHMODE				0x00000008
#define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x000003f0
#define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT		4
static inline uint32_t A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
{
	return ((val) << A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
}
#define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x0000fc00
#define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT		10
static inline uint32_t A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
{
	return ((val) << A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
}
#define A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK			0x00100000
#define A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT			20
static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
{
	return ((val) << A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
}
#define A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE			0x00200000
#define A3XX_SP_VS_CTRL_REG0_LENGTH__MASK			0xff000000
#define A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT			24
static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val)
{
	return ((val) << A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG0_LENGTH__MASK;
}

#define REG_A3XX_SP_VS_CTRL_REG1				0x000022c5
#define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK			0x000003ff
#define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT			0
static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val)
{
	return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK;
}
#define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK		0x000ffc00
#define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT		10
static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val)
{
	return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK;
}
#define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK		0x7f000000
#define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT		24
static inline uint32_t A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
{
	return ((val) << A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK;
}

#define REG_A3XX_SP_VS_PARAM_REG				0x000022c6
#define A3XX_SP_VS_PARAM_REG_POSREGID__MASK			0x000000ff
#define A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT			0
static inline uint32_t A3XX_SP_VS_PARAM_REG_POSREGID(uint32_t val)
{
	return ((val) << A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_POSREGID__MASK;
}
#define A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK			0x0000ff00
#define A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT			8
static inline uint32_t A3XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val)
{
	return ((val) << A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK;
}
#define A3XX_SP_VS_PARAM_REG_POS2DMODE				0x00010000
#define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK		0x01f00000
#define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT		20
static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val)
{
	return ((val) << A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK;
}

static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; }

static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
#define A3XX_SP_VS_OUT_REG_A_REGID__MASK			0x000000ff
#define A3XX_SP_VS_OUT_REG_A_REGID__SHIFT			0
static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
{
	return ((val) << A3XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_A_REGID__MASK;
}
#define A3XX_SP_VS_OUT_REG_A_HALF				0x00000100
#define A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK			0x00001e00
#define A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT			9
static inline uint32_t A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
{
	return ((val) << A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
}
#define A3XX_SP_VS_OUT_REG_B_REGID__MASK			0x00ff0000
#define A3XX_SP_VS_OUT_REG_B_REGID__SHIFT			16
static inline uint32_t A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
{
	return ((val) << A3XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_B_REGID__MASK;
}
#define A3XX_SP_VS_OUT_REG_B_HALF				0x01000000
#define A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK			0x1e000000
#define A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT			25
static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
{
	return ((val) << A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
}

static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d0 + 0x1*i0; }

static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d0 + 0x1*i0; }
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK			0x0000007f
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT			0
static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
{
	return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
}
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK			0x00007f00
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT			8
static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
{
	return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
}
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK			0x007f0000
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT			16
static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
{
	return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
}
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK			0x7f000000
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT			24
static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
{
	return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
}

#define REG_A3XX_SP_VS_OBJ_OFFSET_REG				0x000022d4
#define A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK	0x0000ffff
#define A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT	0
static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val)
{
	return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK;
}
#define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK	0x01ff0000
#define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT	16
static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
{
	return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
}
#define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK		0xfe000000
#define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT	25
static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
{
	return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
}

#define REG_A3XX_SP_VS_OBJ_START_REG				0x000022d5

#define REG_A3XX_SP_VS_PVT_MEM_PARAM_REG			0x000022d6
#define A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK	0x000000ff
#define A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT	0
static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val)
{
	return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK;
}
#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK	0x00ffff00
#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT	8
static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val)
{
	return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK;
}
#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK	0xff000000
#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT	24
static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val)
{
	return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK;
}

#define REG_A3XX_SP_VS_PVT_MEM_ADDR_REG				0x000022d7
#define A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__MASK		0x0000001f
#define A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT		0
static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val)
{
	return ((val) << A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__MASK;
}
#define A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK	0xffffffe0
#define A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT	5
static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val)
{
	return ((val >> 5) << A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK;
}

#define REG_A3XX_SP_VS_PVT_MEM_SIZE_REG				0x000022d8

#define REG_A3XX_SP_VS_LENGTH_REG				0x000022df
#define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK		0xffffffff
#define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT		0
static inline uint32_t A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(uint32_t val)
{
	return ((val) << A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK;
}

#define REG_A3XX_SP_FS_CTRL_REG0				0x000022e0
#define A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK			0x00000001
#define A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT			0
static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
{
	return ((val) << A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK;
}
#define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK		0x00000002
#define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT		1
static inline uint32_t A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val)
{
	return ((val) << A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK;
}
#define A3XX_SP_FS_CTRL_REG0_CACHEINVALID			0x00000004
#define A3XX_SP_FS_CTRL_REG0_ALUSCHMODE				0x00000008
#define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x000003f0
#define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT		4
static inline uint32_t A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
{
	return ((val) << A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
}
#define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x0000fc00
#define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT		10
static inline uint32_t A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
{
	return ((val) << A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
}
#define A3XX_SP_FS_CTRL_REG0_FSBYPASSENABLE			0x00020000
#define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP			0x00040000
#define A3XX_SP_FS_CTRL_REG0_OUTORDERED				0x00080000
#define A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK			0x00100000
#define A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT			20
static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
{
	return ((val) << A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
}
#define A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE			0x00200000
#define A3XX_SP_FS_CTRL_REG0_PIXLODENABLE			0x00400000
#define A3XX_SP_FS_CTRL_REG0_COMPUTEMODE			0x00800000
#define A3XX_SP_FS_CTRL_REG0_LENGTH__MASK			0xff000000
#define A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT			24
static inline uint32_t A3XX_SP_FS_CTRL_REG0_LENGTH(uint32_t val)
{
	return ((val) << A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG0_LENGTH__MASK;
}

#define REG_A3XX_SP_FS_CTRL_REG1				0x000022e1
#define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK			0x000003ff
#define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT			0
static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val)
{
	return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK;
}
#define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK		0x000ffc00
#define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT		10
static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val)
{
	return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK;
}
#define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK		0x00f00000
#define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT		20
static inline uint32_t A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
{
	return ((val) << A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK;
}
#define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK		0x7f000000
#define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT		24
static inline uint32_t A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val)
{
	return ((val) << A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT) & A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK;
}

#define REG_A3XX_SP_FS_OBJ_OFFSET_REG				0x000022e2
#define A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK	0x0000ffff
#define A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT	0
static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val)
{
	return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK;
}
#define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK	0x01ff0000
#define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT	16
static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
{
	return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
}
#define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK		0xfe000000
#define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT	25
static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
{
	return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
}

#define REG_A3XX_SP_FS_OBJ_START_REG				0x000022e3

#define REG_A3XX_SP_FS_PVT_MEM_PARAM_REG			0x000022e4
#define A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK	0x000000ff
#define A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT	0
static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val)
{
	return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK;
}
#define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK	0x00ffff00
#define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT	8
static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val)
{
	return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK;
}
#define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK	0xff000000
#define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT	24
static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val)
{
	return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK;
}

#define REG_A3XX_SP_FS_PVT_MEM_ADDR_REG				0x000022e5
#define A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__MASK		0x0000001f
#define A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT		0
static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val)
{
	return ((val) << A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__MASK;
}
#define A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK	0xffffffe0
#define A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT	5
static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val)
{
	return ((val >> 5) << A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK;
}

#define REG_A3XX_SP_FS_PVT_MEM_SIZE_REG				0x000022e6

#define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0			0x000022e8

#define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1			0x000022e9

#define REG_A3XX_SP_FS_OUTPUT_REG				0x000022ec
#define A3XX_SP_FS_OUTPUT_REG_MRT__MASK				0x00000003
#define A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT			0
static inline uint32_t A3XX_SP_FS_OUTPUT_REG_MRT(uint32_t val)
{
	return ((val) << A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A3XX_SP_FS_OUTPUT_REG_MRT__MASK;
}
#define A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE			0x00000080
#define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK			0x0000ff00
#define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT		8
static inline uint32_t A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val)
{
	return ((val) << A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK;
}

static inline uint32_t REG_A3XX_SP_FS_MRT(uint32_t i0) { return 0x000022f0 + 0x1*i0; }

static inline uint32_t REG_A3XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f0 + 0x1*i0; }
#define A3XX_SP_FS_MRT_REG_REGID__MASK				0x000000ff
#define A3XX_SP_FS_MRT_REG_REGID__SHIFT				0
static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val)
{
	return ((val) << A3XX_SP_FS_MRT_REG_REGID__SHIFT) & A3XX_SP_FS_MRT_REG_REGID__MASK;
}
#define A3XX_SP_FS_MRT_REG_HALF_PRECISION			0x00000100
#define A3XX_SP_FS_MRT_REG_SINT					0x00000400
#define A3XX_SP_FS_MRT_REG_UINT					0x00000800

static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT(uint32_t i0) { return 0x000022f4 + 0x1*i0; }

static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(uint32_t i0) { return 0x000022f4 + 0x1*i0; }
#define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK		0x0000003f
#define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT		0
static inline uint32_t A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(enum a3xx_color_fmt val)
{
	return ((val) << A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT) & A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK;
}

#define REG_A3XX_SP_FS_LENGTH_REG				0x000022ff
#define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK		0xffffffff
#define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT		0
static inline uint32_t A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(uint32_t val)
{
	return ((val) << A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK;
}

#define REG_A3XX_PA_SC_AA_CONFIG				0x00002301

#define REG_A3XX_TPL1_TP_VS_TEX_OFFSET				0x00002340
#define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK		0x000000ff
#define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT		0
static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val)
{
	return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK;
}
#define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK		0x0000ff00
#define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT		8
static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val)
{
	return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK;
}
#define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK		0xffff0000
#define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT		16
static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(uint32_t val)
{
	return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK;
}

#define REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR		0x00002341

#define REG_A3XX_TPL1_TP_FS_TEX_OFFSET				0x00002342
#define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK		0x000000ff
#define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT		0
static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val)
{
	return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK;
}
#define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK		0x0000ff00
#define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT		8
static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val)
{
	return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK;
}
#define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK		0xffff0000
#define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT		16
static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val)
{
	return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK;
}

#define REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR		0x00002343

#define REG_A3XX_VBIF_CLKON					0x00003001

#define REG_A3XX_VBIF_FIXED_SORT_EN				0x0000300c

#define REG_A3XX_VBIF_FIXED_SORT_SEL0				0x0000300d

#define REG_A3XX_VBIF_FIXED_SORT_SEL1				0x0000300e

#define REG_A3XX_VBIF_ABIT_SORT					0x0000301c

#define REG_A3XX_VBIF_ABIT_SORT_CONF				0x0000301d

#define REG_A3XX_VBIF_GATE_OFF_WRREQ_EN				0x0000302a

#define REG_A3XX_VBIF_IN_RD_LIM_CONF0				0x0000302c

#define REG_A3XX_VBIF_IN_RD_LIM_CONF1				0x0000302d

#define REG_A3XX_VBIF_IN_WR_LIM_CONF0				0x00003030

#define REG_A3XX_VBIF_IN_WR_LIM_CONF1				0x00003031

#define REG_A3XX_VBIF_OUT_RD_LIM_CONF0				0x00003034

#define REG_A3XX_VBIF_OUT_WR_LIM_CONF0				0x00003035

#define REG_A3XX_VBIF_DDR_OUT_MAX_BURST				0x00003036

#define REG_A3XX_VBIF_ARB_CTL					0x0000303c

#define REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB			0x00003049

#define REG_A3XX_VBIF_OUT_AXI_AMEMTYPE_CONF0			0x00003058

#define REG_A3XX_VBIF_OUT_AXI_AOOO_EN				0x0000305e

#define REG_A3XX_VBIF_OUT_AXI_AOOO				0x0000305f

#define REG_A3XX_VBIF_PERF_CNT_EN				0x00003070
#define A3XX_VBIF_PERF_CNT_EN_CNT0				0x00000001
#define A3XX_VBIF_PERF_CNT_EN_CNT1				0x00000002
#define A3XX_VBIF_PERF_CNT_EN_PWRCNT0				0x00000004
#define A3XX_VBIF_PERF_CNT_EN_PWRCNT1				0x00000008
#define A3XX_VBIF_PERF_CNT_EN_PWRCNT2				0x00000010

#define REG_A3XX_VBIF_PERF_CNT_CLR				0x00003071
#define A3XX_VBIF_PERF_CNT_CLR_CNT0				0x00000001
#define A3XX_VBIF_PERF_CNT_CLR_CNT1				0x00000002
#define A3XX_VBIF_PERF_CNT_CLR_PWRCNT0				0x00000004
#define A3XX_VBIF_PERF_CNT_CLR_PWRCNT1				0x00000008
#define A3XX_VBIF_PERF_CNT_CLR_PWRCNT2				0x00000010

#define REG_A3XX_VBIF_PERF_CNT_SEL				0x00003072

#define REG_A3XX_VBIF_PERF_CNT0_LO				0x00003073

#define REG_A3XX_VBIF_PERF_CNT0_HI				0x00003074

#define REG_A3XX_VBIF_PERF_CNT1_LO				0x00003075

#define REG_A3XX_VBIF_PERF_CNT1_HI				0x00003076

#define REG_A3XX_VBIF_PERF_PWR_CNT0_LO				0x00003077

#define REG_A3XX_VBIF_PERF_PWR_CNT0_HI				0x00003078

#define REG_A3XX_VBIF_PERF_PWR_CNT1_LO				0x00003079

#define REG_A3XX_VBIF_PERF_PWR_CNT1_HI				0x0000307a

#define REG_A3XX_VBIF_PERF_PWR_CNT2_LO				0x0000307b

#define REG_A3XX_VBIF_PERF_PWR_CNT2_HI				0x0000307c

#define REG_A3XX_VSC_BIN_SIZE					0x00000c01
#define A3XX_VSC_BIN_SIZE_WIDTH__MASK				0x0000001f
#define A3XX_VSC_BIN_SIZE_WIDTH__SHIFT				0
static inline uint32_t A3XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
{
	return ((val >> 5) << A3XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A3XX_VSC_BIN_SIZE_WIDTH__MASK;
}
#define A3XX_VSC_BIN_SIZE_HEIGHT__MASK				0x000003e0
#define A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT				5
static inline uint32_t A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
{
	return ((val >> 5) << A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A3XX_VSC_BIN_SIZE_HEIGHT__MASK;
}

#define REG_A3XX_VSC_SIZE_ADDRESS				0x00000c02

static inline uint32_t REG_A3XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; }

static inline uint32_t REG_A3XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
#define A3XX_VSC_PIPE_CONFIG_X__MASK				0x000003ff
#define A3XX_VSC_PIPE_CONFIG_X__SHIFT				0
static inline uint32_t A3XX_VSC_PIPE_CONFIG_X(uint32_t val)
{
	return ((val) << A3XX_VSC_PIPE_CONFIG_X__SHIFT) & A3XX_VSC_PIPE_CONFIG_X__MASK;
}
#define A3XX_VSC_PIPE_CONFIG_Y__MASK				0x000ffc00
#define A3XX_VSC_PIPE_CONFIG_Y__SHIFT				10
static inline uint32_t A3XX_VSC_PIPE_CONFIG_Y(uint32_t val)
{
	return ((val) << A3XX_VSC_PIPE_CONFIG_Y__SHIFT) & A3XX_VSC_PIPE_CONFIG_Y__MASK;
}
#define A3XX_VSC_PIPE_CONFIG_W__MASK				0x00f00000
#define A3XX_VSC_PIPE_CONFIG_W__SHIFT				20
static inline uint32_t A3XX_VSC_PIPE_CONFIG_W(uint32_t val)
{
	return ((val) << A3XX_VSC_PIPE_CONFIG_W__SHIFT) & A3XX_VSC_PIPE_CONFIG_W__MASK;
}
#define A3XX_VSC_PIPE_CONFIG_H__MASK				0x0f000000
#define A3XX_VSC_PIPE_CONFIG_H__SHIFT				24
static inline uint32_t A3XX_VSC_PIPE_CONFIG_H(uint32_t val)
{
	return ((val) << A3XX_VSC_PIPE_CONFIG_H__SHIFT) & A3XX_VSC_PIPE_CONFIG_H__MASK;
}

static inline uint32_t REG_A3XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; }

static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; }

#define REG_A3XX_VSC_BIN_CONTROL				0x00000c3c
#define A3XX_VSC_BIN_CONTROL_BINNING_ENABLE			0x00000001

#define REG_A3XX_UNKNOWN_0C3D					0x00000c3d

#define REG_A3XX_PC_PERFCOUNTER0_SELECT				0x00000c48

#define REG_A3XX_PC_PERFCOUNTER1_SELECT				0x00000c49

#define REG_A3XX_PC_PERFCOUNTER2_SELECT				0x00000c4a

#define REG_A3XX_PC_PERFCOUNTER3_SELECT				0x00000c4b

#define REG_A3XX_GRAS_TSE_DEBUG_ECO				0x00000c81

#define REG_A3XX_GRAS_PERFCOUNTER0_SELECT			0x00000c88

#define REG_A3XX_GRAS_PERFCOUNTER1_SELECT			0x00000c89

#define REG_A3XX_GRAS_PERFCOUNTER2_SELECT			0x00000c8a

#define REG_A3XX_GRAS_PERFCOUNTER3_SELECT			0x00000c8b

static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE(uint32_t i0) { return 0x00000ca0 + 0x4*i0; }

static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_X(uint32_t i0) { return 0x00000ca0 + 0x4*i0; }

static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Y(uint32_t i0) { return 0x00000ca1 + 0x4*i0; }

static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Z(uint32_t i0) { return 0x00000ca2 + 0x4*i0; }

static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_W(uint32_t i0) { return 0x00000ca3 + 0x4*i0; }

#define REG_A3XX_RB_GMEM_BASE_ADDR				0x00000cc0

#define REG_A3XX_RB_DEBUG_ECO_CONTROLS_ADDR			0x00000cc1

#define REG_A3XX_RB_PERFCOUNTER0_SELECT				0x00000cc6

#define REG_A3XX_RB_PERFCOUNTER1_SELECT				0x00000cc7

#define REG_A3XX_RB_FRAME_BUFFER_DIMENSION			0x00000ce0
#define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK		0x00003fff
#define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT		0
static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val)
{
	return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK;
}
#define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK		0x0fffc000
#define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT		14
static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val)
{
	return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK;
}

#define REG_A3XX_HLSQ_PERFCOUNTER0_SELECT			0x00000e00

#define REG_A3XX_HLSQ_PERFCOUNTER1_SELECT			0x00000e01

#define REG_A3XX_HLSQ_PERFCOUNTER2_SELECT			0x00000e02

#define REG_A3XX_HLSQ_PERFCOUNTER3_SELECT			0x00000e03

#define REG_A3XX_HLSQ_PERFCOUNTER4_SELECT			0x00000e04

#define REG_A3XX_HLSQ_PERFCOUNTER5_SELECT			0x00000e05

#define REG_A3XX_UNKNOWN_0E43					0x00000e43

#define REG_A3XX_VFD_PERFCOUNTER0_SELECT			0x00000e44

#define REG_A3XX_VFD_PERFCOUNTER1_SELECT			0x00000e45

#define REG_A3XX_VPC_VPC_DEBUG_RAM_SEL				0x00000e61

#define REG_A3XX_VPC_VPC_DEBUG_RAM_READ				0x00000e62

#define REG_A3XX_VPC_PERFCOUNTER0_SELECT			0x00000e64

#define REG_A3XX_VPC_PERFCOUNTER1_SELECT			0x00000e65

#define REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG			0x00000e82

#define REG_A3XX_UCHE_PERFCOUNTER0_SELECT			0x00000e84

#define REG_A3XX_UCHE_PERFCOUNTER1_SELECT			0x00000e85

#define REG_A3XX_UCHE_PERFCOUNTER2_SELECT			0x00000e86

#define REG_A3XX_UCHE_PERFCOUNTER3_SELECT			0x00000e87

#define REG_A3XX_UCHE_PERFCOUNTER4_SELECT			0x00000e88

#define REG_A3XX_UCHE_PERFCOUNTER5_SELECT			0x00000e89

#define REG_A3XX_UCHE_CACHE_INVALIDATE0_REG			0x00000ea0
#define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK		0x0fffffff
#define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT		0
static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(uint32_t val)
{
	return ((val) << A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK;
}

#define REG_A3XX_UCHE_CACHE_INVALIDATE1_REG			0x00000ea1
#define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK		0x0fffffff
#define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT		0
static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(uint32_t val)
{
	return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK;
}
#define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK		0x30000000
#define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT		28
static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_opcode val)
{
	return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK;
}
#define A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE		0x80000000

#define REG_A3XX_UNKNOWN_0EA6					0x00000ea6

#define REG_A3XX_SP_PERFCOUNTER0_SELECT				0x00000ec4

#define REG_A3XX_SP_PERFCOUNTER1_SELECT				0x00000ec5

#define REG_A3XX_SP_PERFCOUNTER2_SELECT				0x00000ec6

#define REG_A3XX_SP_PERFCOUNTER3_SELECT				0x00000ec7

#define REG_A3XX_SP_PERFCOUNTER4_SELECT				0x00000ec8

#define REG_A3XX_SP_PERFCOUNTER5_SELECT				0x00000ec9

#define REG_A3XX_SP_PERFCOUNTER6_SELECT				0x00000eca

#define REG_A3XX_SP_PERFCOUNTER7_SELECT				0x00000ecb

#define REG_A3XX_UNKNOWN_0EE0					0x00000ee0

#define REG_A3XX_UNKNOWN_0F03					0x00000f03

#define REG_A3XX_TP_PERFCOUNTER0_SELECT				0x00000f04

#define REG_A3XX_TP_PERFCOUNTER1_SELECT				0x00000f05

#define REG_A3XX_TP_PERFCOUNTER2_SELECT				0x00000f06

#define REG_A3XX_TP_PERFCOUNTER3_SELECT				0x00000f07

#define REG_A3XX_TP_PERFCOUNTER4_SELECT				0x00000f08

#define REG_A3XX_TP_PERFCOUNTER5_SELECT				0x00000f09

#define REG_A3XX_VGT_CL_INITIATOR				0x000021f0

#define REG_A3XX_VGT_EVENT_INITIATOR				0x000021f9

#define REG_A3XX_VGT_DRAW_INITIATOR				0x000021fc
#define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK			0x0000003f
#define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT		0
static inline uint32_t A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val)
{
	return ((val) << A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK;
}
#define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK		0x000000c0
#define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT		6
static inline uint32_t A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val)
{
	return ((val) << A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK;
}
#define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK			0x00000600
#define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT			9
static inline uint32_t A3XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val)
{
	return ((val) << A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK;
}
#define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK		0x00000800
#define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT		11
static inline uint32_t A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val)
{
	return ((val) << A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK;
}
#define A3XX_VGT_DRAW_INITIATOR_NOT_EOP				0x00001000
#define A3XX_VGT_DRAW_INITIATOR_SMALL_INDEX			0x00002000
#define A3XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE	0x00004000
#define A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK		0xff000000
#define A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT		24
static inline uint32_t A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val)
{
	return ((val) << A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK;
}

#define REG_A3XX_VGT_IMMED_DATA					0x000021fd

#define REG_A3XX_TEX_SAMP_0					0x00000000
#define A3XX_TEX_SAMP_0_CLAMPENABLE				0x00000001
#define A3XX_TEX_SAMP_0_MIPFILTER_LINEAR			0x00000002
#define A3XX_TEX_SAMP_0_XY_MAG__MASK				0x0000000c
#define A3XX_TEX_SAMP_0_XY_MAG__SHIFT				2
static inline uint32_t A3XX_TEX_SAMP_0_XY_MAG(enum a3xx_tex_filter val)
{
	return ((val) << A3XX_TEX_SAMP_0_XY_MAG__SHIFT) & A3XX_TEX_SAMP_0_XY_MAG__MASK;
}
#define A3XX_TEX_SAMP_0_XY_MIN__MASK				0x00000030
#define A3XX_TEX_SAMP_0_XY_MIN__SHIFT				4
static inline uint32_t A3XX_TEX_SAMP_0_XY_MIN(enum a3xx_tex_filter val)
{
	return ((val) << A3XX_TEX_SAMP_0_XY_MIN__SHIFT) & A3XX_TEX_SAMP_0_XY_MIN__MASK;
}
#define A3XX_TEX_SAMP_0_WRAP_S__MASK				0x000001c0
#define A3XX_TEX_SAMP_0_WRAP_S__SHIFT				6
static inline uint32_t A3XX_TEX_SAMP_0_WRAP_S(enum a3xx_tex_clamp val)
{
	return ((val) << A3XX_TEX_SAMP_0_WRAP_S__SHIFT) & A3XX_TEX_SAMP_0_WRAP_S__MASK;
}
#define A3XX_TEX_SAMP_0_WRAP_T__MASK				0x00000e00
#define A3XX_TEX_SAMP_0_WRAP_T__SHIFT				9
static inline uint32_t A3XX_TEX_SAMP_0_WRAP_T(enum a3xx_tex_clamp val)
{
	return ((val) << A3XX_TEX_SAMP_0_WRAP_T__SHIFT) & A3XX_TEX_SAMP_0_WRAP_T__MASK;
}
#define A3XX_TEX_SAMP_0_WRAP_R__MASK				0x00007000
#define A3XX_TEX_SAMP_0_WRAP_R__SHIFT				12
static inline uint32_t A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val)
{
	return ((val) << A3XX_TEX_SAMP_0_WRAP_R__SHIFT) & A3XX_TEX_SAMP_0_WRAP_R__MASK;
}
#define A3XX_TEX_SAMP_0_ANISO__MASK				0x00038000
#define A3XX_TEX_SAMP_0_ANISO__SHIFT				15
static inline uint32_t A3XX_TEX_SAMP_0_ANISO(enum a3xx_tex_aniso val)
{
	return ((val) << A3XX_TEX_SAMP_0_ANISO__SHIFT) & A3XX_TEX_SAMP_0_ANISO__MASK;
}
#define A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK			0x00700000
#define A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT			20
static inline uint32_t A3XX_TEX_SAMP_0_COMPARE_FUNC(enum adreno_compare_func val)
{
	return ((val) << A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT) & A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK;
}
#define A3XX_TEX_SAMP_0_CUBEMAPSEAMLESSFILTOFF			0x01000000
#define A3XX_TEX_SAMP_0_UNNORM_COORDS				0x80000000

#define REG_A3XX_TEX_SAMP_1					0x00000001
#define A3XX_TEX_SAMP_1_LOD_BIAS__MASK				0x000007ff
#define A3XX_TEX_SAMP_1_LOD_BIAS__SHIFT				0
static inline uint32_t A3XX_TEX_SAMP_1_LOD_BIAS(float val)
{
	return ((((int32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_LOD_BIAS__SHIFT) & A3XX_TEX_SAMP_1_LOD_BIAS__MASK;
}
#define A3XX_TEX_SAMP_1_MAX_LOD__MASK				0x003ff000
#define A3XX_TEX_SAMP_1_MAX_LOD__SHIFT				12
static inline uint32_t A3XX_TEX_SAMP_1_MAX_LOD(float val)
{
	return ((((uint32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A3XX_TEX_SAMP_1_MAX_LOD__MASK;
}
#define A3XX_TEX_SAMP_1_MIN_LOD__MASK				0xffc00000
#define A3XX_TEX_SAMP_1_MIN_LOD__SHIFT				22
static inline uint32_t A3XX_TEX_SAMP_1_MIN_LOD(float val)
{
	return ((((uint32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A3XX_TEX_SAMP_1_MIN_LOD__MASK;
}

#define REG_A3XX_TEX_CONST_0					0x00000000
#define A3XX_TEX_CONST_0_TILE_MODE__MASK			0x00000003
#define A3XX_TEX_CONST_0_TILE_MODE__SHIFT			0
static inline uint32_t A3XX_TEX_CONST_0_TILE_MODE(enum a3xx_tile_mode val)
{
	return ((val) << A3XX_TEX_CONST_0_TILE_MODE__SHIFT) & A3XX_TEX_CONST_0_TILE_MODE__MASK;
}
#define A3XX_TEX_CONST_0_SRGB					0x00000004
#define A3XX_TEX_CONST_0_SWIZ_X__MASK				0x00000070
#define A3XX_TEX_CONST_0_SWIZ_X__SHIFT				4
static inline uint32_t A3XX_TEX_CONST_0_SWIZ_X(enum a3xx_tex_swiz val)
{
	return ((val) << A3XX_TEX_CONST_0_SWIZ_X__SHIFT) & A3XX_TEX_CONST_0_SWIZ_X__MASK;
}
#define A3XX_TEX_CONST_0_SWIZ_Y__MASK				0x00000380
#define A3XX_TEX_CONST_0_SWIZ_Y__SHIFT				7
static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Y(enum a3xx_tex_swiz val)
{
	return ((val) << A3XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Y__MASK;
}
#define A3XX_TEX_CONST_0_SWIZ_Z__MASK				0x00001c00
#define A3XX_TEX_CONST_0_SWIZ_Z__SHIFT				10
static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Z(enum a3xx_tex_swiz val)
{
	return ((val) << A3XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Z__MASK;
}
#define A3XX_TEX_CONST_0_SWIZ_W__MASK				0x0000e000
#define A3XX_TEX_CONST_0_SWIZ_W__SHIFT				13
static inline uint32_t A3XX_TEX_CONST_0_SWIZ_W(enum a3xx_tex_swiz val)
{
	return ((val) << A3XX_TEX_CONST_0_SWIZ_W__SHIFT) & A3XX_TEX_CONST_0_SWIZ_W__MASK;
}
#define A3XX_TEX_CONST_0_MIPLVLS__MASK				0x000f0000
#define A3XX_TEX_CONST_0_MIPLVLS__SHIFT				16
static inline uint32_t A3XX_TEX_CONST_0_MIPLVLS(uint32_t val)
{
	return ((val) << A3XX_TEX_CONST_0_MIPLVLS__SHIFT) & A3XX_TEX_CONST_0_MIPLVLS__MASK;
}
#define A3XX_TEX_CONST_0_MSAATEX__MASK				0x00300000
#define A3XX_TEX_CONST_0_MSAATEX__SHIFT				20
static inline uint32_t A3XX_TEX_CONST_0_MSAATEX(enum a3xx_tex_msaa val)
{
	return ((val) << A3XX_TEX_CONST_0_MSAATEX__SHIFT) & A3XX_TEX_CONST_0_MSAATEX__MASK;
}
#define A3XX_TEX_CONST_0_FMT__MASK				0x1fc00000
#define A3XX_TEX_CONST_0_FMT__SHIFT				22
static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val)
{
	return ((val) << A3XX_TEX_CONST_0_FMT__SHIFT) & A3XX_TEX_CONST_0_FMT__MASK;
}
#define A3XX_TEX_CONST_0_NOCONVERT				0x20000000
#define A3XX_TEX_CONST_0_TYPE__MASK				0xc0000000
#define A3XX_TEX_CONST_0_TYPE__SHIFT				30
static inline uint32_t A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val)
{
	return ((val) << A3XX_TEX_CONST_0_TYPE__SHIFT) & A3XX_TEX_CONST_0_TYPE__MASK;
}

#define REG_A3XX_TEX_CONST_1					0x00000001
#define A3XX_TEX_CONST_1_HEIGHT__MASK				0x00003fff
#define A3XX_TEX_CONST_1_HEIGHT__SHIFT				0
static inline uint32_t A3XX_TEX_CONST_1_HEIGHT(uint32_t val)
{
	return ((val) << A3XX_TEX_CONST_1_HEIGHT__SHIFT) & A3XX_TEX_CONST_1_HEIGHT__MASK;
}
#define A3XX_TEX_CONST_1_WIDTH__MASK				0x0fffc000
#define A3XX_TEX_CONST_1_WIDTH__SHIFT				14
static inline uint32_t A3XX_TEX_CONST_1_WIDTH(uint32_t val)
{
	return ((val) << A3XX_TEX_CONST_1_WIDTH__SHIFT) & A3XX_TEX_CONST_1_WIDTH__MASK;
}
#define A3XX_TEX_CONST_1_PITCHALIGN__MASK			0xf0000000
#define A3XX_TEX_CONST_1_PITCHALIGN__SHIFT			28
static inline uint32_t A3XX_TEX_CONST_1_PITCHALIGN(uint32_t val)
{
	return ((val) << A3XX_TEX_CONST_1_PITCHALIGN__SHIFT) & A3XX_TEX_CONST_1_PITCHALIGN__MASK;
}

#define REG_A3XX_TEX_CONST_2					0x00000002
#define A3XX_TEX_CONST_2_INDX__MASK				0x000001ff
#define A3XX_TEX_CONST_2_INDX__SHIFT				0
static inline uint32_t A3XX_TEX_CONST_2_INDX(uint32_t val)
{
	return ((val) << A3XX_TEX_CONST_2_INDX__SHIFT) & A3XX_TEX_CONST_2_INDX__MASK;
}
#define A3XX_TEX_CONST_2_PITCH__MASK				0x3ffff000
#define A3XX_TEX_CONST_2_PITCH__SHIFT				12
static inline uint32_t A3XX_TEX_CONST_2_PITCH(uint32_t val)
{
	return ((val) << A3XX_TEX_CONST_2_PITCH__SHIFT) & A3XX_TEX_CONST_2_PITCH__MASK;
}
#define A3XX_TEX_CONST_2_SWAP__MASK				0xc0000000
#define A3XX_TEX_CONST_2_SWAP__SHIFT				30
static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)
{
	return ((val) << A3XX_TEX_CONST_2_SWAP__SHIFT) & A3XX_TEX_CONST_2_SWAP__MASK;
}

#define REG_A3XX_TEX_CONST_3					0x00000003
#define A3XX_TEX_CONST_3_LAYERSZ1__MASK				0x0001ffff
#define A3XX_TEX_CONST_3_LAYERSZ1__SHIFT			0
static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ1(uint32_t val)
{
	return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ1__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ1__MASK;
}
#define A3XX_TEX_CONST_3_DEPTH__MASK				0x0ffe0000
#define A3XX_TEX_CONST_3_DEPTH__SHIFT				17
static inline uint32_t A3XX_TEX_CONST_3_DEPTH(uint32_t val)
{
	return ((val) << A3XX_TEX_CONST_3_DEPTH__SHIFT) & A3XX_TEX_CONST_3_DEPTH__MASK;
}
#define A3XX_TEX_CONST_3_LAYERSZ2__MASK				0xf0000000
#define A3XX_TEX_CONST_3_LAYERSZ2__SHIFT			28
static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ2(uint32_t val)
{
	return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ2__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ2__MASK;
}


#endif /* A3XX_XML */