Adding upstream version 16.2.11+ds.upstream/16.2.11+dsupstream

Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>

8 files changed, 3699 insertions, 0 deletions

diff --git a/src/seastar/dpdk/drivers/common/qat/qat_adf/adf_transport_access_macros.h b/src/seastar/dpdk/drivers/common/qat/qat_adf/adf_transport_access_macros.h
new file mode 100644
index 000000000..1eef5513f
--- /dev/null
+++ b/src/seastar/dpdk/drivers/common/qat/qat_adf/adf_transport_access_macros.h
@@ -0,0 +1,136 @@
+/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
+ * Copyright(c) 2015-2018 Intel Corporation
+ */
+#ifndef ADF_TRANSPORT_ACCESS_MACROS_H
+#define ADF_TRANSPORT_ACCESS_MACROS_H
+
+#include <rte_io.h>
+
+/* CSR write macro */
+#define ADF_CSR_WR(csrAddr, csrOffset, val)		\
+	rte_write32(val, (((uint8_t *)csrAddr) + csrOffset))
+
+/* CSR read macro */
+#define ADF_CSR_RD(csrAddr, csrOffset)			\
+	rte_read32((((uint8_t *)csrAddr) + csrOffset))
+
+#define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL
+#define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL
+#define ADF_RING_CSR_RING_CONFIG 0x000
+#define ADF_RING_CSR_RING_LBASE 0x040
+#define ADF_RING_CSR_RING_UBASE 0x080
+#define ADF_RING_CSR_RING_HEAD 0x0C0
+#define ADF_RING_CSR_RING_TAIL 0x100
+#define ADF_RING_CSR_E_STAT 0x14C
+#define ADF_RING_CSR_INT_SRCSEL 0x174
+#define ADF_RING_CSR_INT_SRCSEL_2 0x178
+#define ADF_RING_CSR_INT_COL_EN 0x17C
+#define ADF_RING_CSR_INT_COL_CTL 0x180
+#define ADF_RING_CSR_INT_FLAG_AND_COL 0x184
+#define ADF_RING_CSR_INT_COL_CTL_ENABLE	0x80000000
+#define ADF_RING_BUNDLE_SIZE 0x1000
+#define ADF_RING_CONFIG_NEAR_FULL_WM 0x0A
+#define ADF_RING_CONFIG_NEAR_EMPTY_WM 0x05
+#define ADF_COALESCING_MIN_TIME 0x1FF
+#define ADF_COALESCING_MAX_TIME 0xFFFFF
+#define ADF_COALESCING_DEF_TIME 0x27FF
+#define ADF_RING_NEAR_WATERMARK_512 0x08
+#define ADF_RING_NEAR_WATERMARK_0 0x00
+#define ADF_RING_EMPTY_SIG 0x7F7F7F7F
+#define ADF_RING_EMPTY_SIG_BYTE 0x7F
+
+/* Valid internal ring size values */
+#define ADF_RING_SIZE_128 0x01
+#define ADF_RING_SIZE_256 0x02
+#define ADF_RING_SIZE_512 0x03
+#define ADF_RING_SIZE_4K 0x06
+#define ADF_RING_SIZE_16K 0x08
+#define ADF_RING_SIZE_4M 0x10
+#define ADF_MIN_RING_SIZE ADF_RING_SIZE_128
+#define ADF_MAX_RING_SIZE ADF_RING_SIZE_4M
+#define ADF_DEFAULT_RING_SIZE ADF_RING_SIZE_16K
+
+/* Maximum number of qps on a device for any service type */
+#define ADF_MAX_QPS_ON_ANY_SERVICE	2
+#define ADF_RING_DIR_TX			0
+#define ADF_RING_DIR_RX			1
+
+/* Valid internal msg size values */
+#define ADF_MSG_SIZE_32 0x01
+#define ADF_MSG_SIZE_64 0x02
+#define ADF_MSG_SIZE_128 0x04
+#define ADF_MIN_MSG_SIZE ADF_MSG_SIZE_32
+#define ADF_MAX_MSG_SIZE ADF_MSG_SIZE_128
+
+/* Size to bytes conversion macros for ring and msg size values */
+#define ADF_MSG_SIZE_TO_BYTES(SIZE) (SIZE << 5)
+#define ADF_BYTES_TO_MSG_SIZE(SIZE) (SIZE >> 5)
+#define ADF_SIZE_TO_RING_SIZE_IN_BYTES(SIZE) ((1 << (SIZE - 1)) << 7)
+#define ADF_RING_SIZE_IN_BYTES_TO_SIZE(SIZE) ((1 << (SIZE - 1)) >> 7)
+
+/* Minimum ring bufer size for memory allocation */
+#define ADF_RING_SIZE_BYTES_MIN(SIZE) ((SIZE < ADF_RING_SIZE_4K) ? \
+				ADF_RING_SIZE_4K : SIZE)
+#define ADF_RING_SIZE_MODULO(SIZE) (SIZE + 0x6)
+#define ADF_SIZE_TO_POW(SIZE) ((((SIZE & 0x4) >> 1) | ((SIZE & 0x4) >> 2) | \
+				SIZE) & ~0x4)
+/* Max outstanding requests */
+#define ADF_MAX_INFLIGHTS(RING_SIZE, MSG_SIZE) \
+	((((1 << (RING_SIZE - 1)) << 3) >> ADF_SIZE_TO_POW(MSG_SIZE)) - 1)
+#define BUILD_RING_CONFIG(size)	\
+	((ADF_RING_NEAR_WATERMARK_0 << ADF_RING_CONFIG_NEAR_FULL_WM) \
+	| (ADF_RING_NEAR_WATERMARK_0 << ADF_RING_CONFIG_NEAR_EMPTY_WM) \
+	| size)
+#define BUILD_RESP_RING_CONFIG(size, watermark_nf, watermark_ne) \
+	((watermark_nf << ADF_RING_CONFIG_NEAR_FULL_WM)	\
+	| (watermark_ne << ADF_RING_CONFIG_NEAR_EMPTY_WM) \
+	| size)
+#define BUILD_RING_BASE_ADDR(addr, size) \
+	((addr >> 6) & (0xFFFFFFFFFFFFFFFFULL << size))
+#define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \
+	ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
+			ADF_RING_CSR_RING_HEAD + (ring << 2))
+#define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \
+	ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
+			ADF_RING_CSR_RING_TAIL + (ring << 2))
+#define READ_CSR_E_STAT(csr_base_addr, bank) \
+	ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
+			ADF_RING_CSR_E_STAT)
+#define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \
+	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
+		ADF_RING_CSR_RING_CONFIG + (ring << 2), value)
+#define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \
+do { \
+	uint32_t l_base = 0, u_base = 0; \
+	l_base = (uint32_t)(value & 0xFFFFFFFF); \
+	u_base = (uint32_t)((value & 0xFFFFFFFF00000000ULL) >> 32); \
+	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
+		ADF_RING_CSR_RING_LBASE + (ring << 2), l_base);	\
+	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
+		ADF_RING_CSR_RING_UBASE + (ring << 2), u_base);	\
+} while (0)
+#define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \
+	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
+		ADF_RING_CSR_RING_HEAD + (ring << 2), value)
+#define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \
+	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
+		ADF_RING_CSR_RING_TAIL + (ring << 2), value)
+#define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \
+do { \
+	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
+	ADF_RING_CSR_INT_SRCSEL, ADF_BANK_INT_SRC_SEL_MASK_0);	\
+	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
+	ADF_RING_CSR_INT_SRCSEL_2, ADF_BANK_INT_SRC_SEL_MASK_X); \
+} while (0)
+#define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \
+	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
+			ADF_RING_CSR_INT_COL_EN, value)
+#define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \
+	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
+			ADF_RING_CSR_INT_COL_CTL, \
+			ADF_RING_CSR_INT_COL_CTL_ENABLE | value)
+#define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \
+	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
+			ADF_RING_CSR_INT_FLAG_AND_COL, value)
+
+#endif /*ADF_TRANSPORT_ACCESS_MACROS_H */
diff --git a/src/seastar/dpdk/drivers/common/qat/qat_adf/icp_qat_fw.h b/src/seastar/dpdk/drivers/common/qat/qat_adf/icp_qat_fw.h
new file mode 100644
index 000000000..8f7cb37b4
--- /dev/null
+++ b/src/seastar/dpdk/drivers/common/qat/qat_adf/icp_qat_fw.h
@@ -0,0 +1,318 @@
+/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
+ * Copyright(c) 2015-2018 Intel Corporation
+ */
+#ifndef _ICP_QAT_FW_H_
+#define _ICP_QAT_FW_H_
+#include <sys/types.h>
+#include "icp_qat_hw.h"
+
+#define QAT_FIELD_SET(flags, val, bitpos, mask) \
+{ (flags) = (((flags) & (~((mask) << (bitpos)))) | \
+		(((val) & (mask)) << (bitpos))) ; }
+
+#define QAT_FIELD_GET(flags, bitpos, mask) \
+	(((flags) >> (bitpos)) & (mask))
+
+#define ICP_QAT_FW_REQ_DEFAULT_SZ 128
+#define ICP_QAT_FW_RESP_DEFAULT_SZ 32
+#define ICP_QAT_FW_COMN_ONE_BYTE_SHIFT 8
+#define ICP_QAT_FW_COMN_SINGLE_BYTE_MASK 0xFF
+#define ICP_QAT_FW_NUM_LONGWORDS_1 1
+#define ICP_QAT_FW_NUM_LONGWORDS_2 2
+#define ICP_QAT_FW_NUM_LONGWORDS_3 3
+#define ICP_QAT_FW_NUM_LONGWORDS_4 4
+#define ICP_QAT_FW_NUM_LONGWORDS_5 5
+#define ICP_QAT_FW_NUM_LONGWORDS_6 6
+#define ICP_QAT_FW_NUM_LONGWORDS_7 7
+#define ICP_QAT_FW_NUM_LONGWORDS_10 10
+#define ICP_QAT_FW_NUM_LONGWORDS_13 13
+#define ICP_QAT_FW_NULL_REQ_SERV_ID 1
+
+enum icp_qat_fw_comn_resp_serv_id {
+	ICP_QAT_FW_COMN_RESP_SERV_NULL,
+	ICP_QAT_FW_COMN_RESP_SERV_CPM_FW,
+	ICP_QAT_FW_COMN_RESP_SERV_DELIMITER
+};
+
+enum icp_qat_fw_comn_request_id {
+	ICP_QAT_FW_COMN_REQ_NULL = 0,
+	ICP_QAT_FW_COMN_REQ_CPM_FW_PKE = 3,
+	ICP_QAT_FW_COMN_REQ_CPM_FW_LA = 4,
+	ICP_QAT_FW_COMN_REQ_CPM_FW_DMA = 7,
+	ICP_QAT_FW_COMN_REQ_CPM_FW_COMP = 9,
+	ICP_QAT_FW_COMN_REQ_DELIMITER
+};
+
+struct icp_qat_fw_comn_req_hdr_cd_pars {
+	union {
+		struct {
+			uint64_t content_desc_addr;
+			uint16_t content_desc_resrvd1;
+			uint8_t content_desc_params_sz;
+			uint8_t content_desc_hdr_resrvd2;
+			uint32_t content_desc_resrvd3;
+		} s;
+		struct {
+			uint32_t serv_specif_fields[4];
+		} s1;
+	} u;
+};
+
+struct icp_qat_fw_comn_req_mid {
+	uint64_t opaque_data;
+	uint64_t src_data_addr;
+	uint64_t dest_data_addr;
+	uint32_t src_length;
+	uint32_t dst_length;
+};
+
+struct icp_qat_fw_comn_req_cd_ctrl {
+	uint32_t content_desc_ctrl_lw[ICP_QAT_FW_NUM_LONGWORDS_5];
+};
+
+struct icp_qat_fw_comn_req_hdr {
+	uint8_t resrvd1;
+	uint8_t service_cmd_id;
+	uint8_t service_type;
+	uint8_t hdr_flags;
+	uint16_t serv_specif_flags;
+	uint16_t comn_req_flags;
+};
+
+struct icp_qat_fw_comn_req_rqpars {
+	uint32_t serv_specif_rqpars_lw[ICP_QAT_FW_NUM_LONGWORDS_13];
+};
+
+struct icp_qat_fw_comn_req {
+	struct icp_qat_fw_comn_req_hdr comn_hdr;
+	struct icp_qat_fw_comn_req_hdr_cd_pars cd_pars;
+	struct icp_qat_fw_comn_req_mid comn_mid;
+	struct icp_qat_fw_comn_req_rqpars serv_specif_rqpars;
+	struct icp_qat_fw_comn_req_cd_ctrl cd_ctrl;
+};
+
+struct icp_qat_fw_comn_error {
+	uint8_t xlat_err_code;
+	uint8_t cmp_err_code;
+};
+
+struct icp_qat_fw_comn_resp_hdr {
+	uint8_t resrvd1;
+	uint8_t service_id;
+	uint8_t response_type;
+	uint8_t hdr_flags;
+	struct icp_qat_fw_comn_error comn_error;
+	uint8_t comn_status;
+	uint8_t cmd_id;
+};
+
+struct icp_qat_fw_comn_resp {
+	struct icp_qat_fw_comn_resp_hdr comn_hdr;
+	uint64_t opaque_data;
+	uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_4];
+};
+
+#define ICP_QAT_FW_COMN_REQ_FLAG_SET 1
+#define ICP_QAT_FW_COMN_REQ_FLAG_CLR 0
+#define ICP_QAT_FW_COMN_VALID_FLAG_BITPOS 7
+#define ICP_QAT_FW_COMN_VALID_FLAG_MASK 0x1
+#define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK 0x7F
+#define ICP_QAT_FW_COMN_CNV_FLAG_BITPOS 6
+#define ICP_QAT_FW_COMN_CNV_FLAG_MASK 0x1
+#define ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS 5
+#define ICP_QAT_FW_COMN_CNVNR_FLAG_MASK 0x1
+
+#define ICP_QAT_FW_COMN_OV_SRV_TYPE_GET(icp_qat_fw_comn_req_hdr_t) \
+	icp_qat_fw_comn_req_hdr_t.service_type
+
+#define ICP_QAT_FW_COMN_OV_SRV_TYPE_SET(icp_qat_fw_comn_req_hdr_t, val) \
+	icp_qat_fw_comn_req_hdr_t.service_type = val
+
+#define ICP_QAT_FW_COMN_OV_SRV_CMD_ID_GET(icp_qat_fw_comn_req_hdr_t) \
+	icp_qat_fw_comn_req_hdr_t.service_cmd_id
+
+#define ICP_QAT_FW_COMN_OV_SRV_CMD_ID_SET(icp_qat_fw_comn_req_hdr_t, val) \
+	icp_qat_fw_comn_req_hdr_t.service_cmd_id = val
+
+#define ICP_QAT_FW_COMN_HDR_VALID_FLAG_GET(hdr_t) \
+	ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_t.hdr_flags)
+
+#define ICP_QAT_FW_COMN_HDR_CNVNR_FLAG_GET(hdr_flags) \
+	QAT_FIELD_GET(hdr_flags, \
+		ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS, \
+		ICP_QAT_FW_COMN_CNVNR_FLAG_MASK)
+
+#define ICP_QAT_FW_COMN_HDR_CNV_FLAG_GET(hdr_flags) \
+	QAT_FIELD_GET(hdr_flags, \
+		ICP_QAT_FW_COMN_CNV_FLAG_BITPOS, \
+		ICP_QAT_FW_COMN_CNV_FLAG_MASK)
+
+#define ICP_QAT_FW_COMN_HDR_VALID_FLAG_SET(hdr_t, val) \
+	ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val)
+
+#define ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_flags) \
+	QAT_FIELD_GET(hdr_flags, \
+	ICP_QAT_FW_COMN_VALID_FLAG_BITPOS, \
+	ICP_QAT_FW_COMN_VALID_FLAG_MASK)
+
+#define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_GET(hdr_flags) \
+	(hdr_flags & ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK)
+
+#define ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val) \
+	QAT_FIELD_SET((hdr_t.hdr_flags), (val), \
+	ICP_QAT_FW_COMN_VALID_FLAG_BITPOS, \
+	ICP_QAT_FW_COMN_VALID_FLAG_MASK)
+
+#define ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(valid) \
+	(((valid) & ICP_QAT_FW_COMN_VALID_FLAG_MASK) << \
+	 ICP_QAT_FW_COMN_VALID_FLAG_BITPOS)
+
+#define QAT_COMN_PTR_TYPE_BITPOS 0
+#define QAT_COMN_PTR_TYPE_MASK 0x1
+#define QAT_COMN_CD_FLD_TYPE_BITPOS 1
+#define QAT_COMN_CD_FLD_TYPE_MASK 0x1
+#define QAT_COMN_PTR_TYPE_FLAT 0x0
+#define QAT_COMN_PTR_TYPE_SGL 0x1
+#define QAT_COMN_CD_FLD_TYPE_64BIT_ADR 0x0
+#define QAT_COMN_CD_FLD_TYPE_16BYTE_DATA 0x1
+
+#define ICP_QAT_FW_COMN_FLAGS_BUILD(cdt, ptr) \
+	((((cdt) & QAT_COMN_CD_FLD_TYPE_MASK) << QAT_COMN_CD_FLD_TYPE_BITPOS) \
+	 | (((ptr) & QAT_COMN_PTR_TYPE_MASK) << QAT_COMN_PTR_TYPE_BITPOS))
+
+#define ICP_QAT_FW_COMN_PTR_TYPE_GET(flags) \
+	QAT_FIELD_GET(flags, QAT_COMN_PTR_TYPE_BITPOS, QAT_COMN_PTR_TYPE_MASK)
+
+#define ICP_QAT_FW_COMN_CD_FLD_TYPE_GET(flags) \
+	QAT_FIELD_GET(flags, QAT_COMN_CD_FLD_TYPE_BITPOS, \
+			QAT_COMN_CD_FLD_TYPE_MASK)
+
+#define ICP_QAT_FW_COMN_PTR_TYPE_SET(flags, val) \
+	QAT_FIELD_SET(flags, val, QAT_COMN_PTR_TYPE_BITPOS, \
+			QAT_COMN_PTR_TYPE_MASK)
+
+#define ICP_QAT_FW_COMN_CD_FLD_TYPE_SET(flags, val) \
+	QAT_FIELD_SET(flags, val, QAT_COMN_CD_FLD_TYPE_BITPOS, \
+			QAT_COMN_CD_FLD_TYPE_MASK)
+
+#define ICP_QAT_FW_COMN_NEXT_ID_BITPOS 4
+#define ICP_QAT_FW_COMN_NEXT_ID_MASK 0xF0
+#define ICP_QAT_FW_COMN_CURR_ID_BITPOS 0
+#define ICP_QAT_FW_COMN_CURR_ID_MASK 0x0F
+
+#define ICP_QAT_FW_COMN_NEXT_ID_GET(cd_ctrl_hdr_t) \
+	((((cd_ctrl_hdr_t)->next_curr_id) & ICP_QAT_FW_COMN_NEXT_ID_MASK) \
+	>> (ICP_QAT_FW_COMN_NEXT_ID_BITPOS))
+
+#define ICP_QAT_FW_COMN_NEXT_ID_SET(cd_ctrl_hdr_t, val) \
+	{ ((cd_ctrl_hdr_t)->next_curr_id) = ((((cd_ctrl_hdr_t)->next_curr_id) \
+	& ICP_QAT_FW_COMN_CURR_ID_MASK) | \
+	((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \
+	 & ICP_QAT_FW_COMN_NEXT_ID_MASK)); }
+
+#define ICP_QAT_FW_COMN_CURR_ID_GET(cd_ctrl_hdr_t) \
+	(((cd_ctrl_hdr_t)->next_curr_id) & ICP_QAT_FW_COMN_CURR_ID_MASK)
+
+#define ICP_QAT_FW_COMN_CURR_ID_SET(cd_ctrl_hdr_t, val) \
+	{ ((cd_ctrl_hdr_t)->next_curr_id) = ((((cd_ctrl_hdr_t)->next_curr_id) \
+	& ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
+	((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)); }
+
+#define ICP_QAT_FW_COMN_NEXT_ID_SET_2(next_curr_id, val)                       \
+	do {                                                                   \
+		(next_curr_id) =                                               \
+		    (((next_curr_id) & ICP_QAT_FW_COMN_CURR_ID_MASK) |         \
+		     (((val) << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) &              \
+		      ICP_QAT_FW_COMN_NEXT_ID_MASK))                           \
+	} while (0)
+
+#define ICP_QAT_FW_COMN_CURR_ID_SET_2(next_curr_id, val)                       \
+	do {                                                                   \
+		(next_curr_id) =                                               \
+		    (((next_curr_id) & ICP_QAT_FW_COMN_NEXT_ID_MASK) |         \
+		     ((val) & ICP_QAT_FW_COMN_CURR_ID_MASK))                   \
+	} while (0)
+
+#define QAT_COMN_RESP_CRYPTO_STATUS_BITPOS 7
+#define QAT_COMN_RESP_CRYPTO_STATUS_MASK 0x1
+#define QAT_COMN_RESP_PKE_STATUS_BITPOS 6
+#define QAT_COMN_RESP_PKE_STATUS_MASK 0x1
+#define QAT_COMN_RESP_CMP_STATUS_BITPOS 5
+#define QAT_COMN_RESP_CMP_STATUS_MASK 0x1
+#define QAT_COMN_RESP_XLAT_STATUS_BITPOS 4
+#define QAT_COMN_RESP_XLAT_STATUS_MASK 0x1
+#define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS 3
+#define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK 0x1
+#define QAT_COMN_RESP_UNSUPPORTED_REQUEST_BITPOS 2
+#define QAT_COMN_RESP_UNSUPPORTED_REQUEST_MASK 0x1
+#define QAT_COMN_RESP_XLT_WA_APPLIED_BITPOS 0
+#define QAT_COMN_RESP_XLT_WA_APPLIED_MASK 0x1
+
+#define ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(status) \
+	QAT_FIELD_GET(status, QAT_COMN_RESP_CRYPTO_STATUS_BITPOS, \
+	QAT_COMN_RESP_CRYPTO_STATUS_MASK)
+
+#define ICP_QAT_FW_COMN_RESP_PKE_STAT_GET(status) \
+	QAT_FIELD_GET(status, QAT_COMN_RESP_PKE_STATUS_BITPOS, \
+	QAT_COMN_RESP_PKE_STATUS_MASK)
+
+#define ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(status) \
+	QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_STATUS_BITPOS, \
+	QAT_COMN_RESP_CMP_STATUS_MASK)
+
+#define ICP_QAT_FW_COMN_RESP_XLAT_STAT_GET(status) \
+	QAT_FIELD_GET(status, QAT_COMN_RESP_XLAT_STATUS_BITPOS, \
+	QAT_COMN_RESP_XLAT_STATUS_MASK)
+
+#define ICP_QAT_FW_COMN_RESP_XLT_WA_APPLIED_GET(status) \
+	QAT_FIELD_GET(status, QAT_COMN_RESP_XLT_WA_APPLIED_BITPOS, \
+	QAT_COMN_RESP_XLT_WA_APPLIED_MASK)
+
+#define ICP_QAT_FW_COMN_RESP_CMP_END_OF_LAST_BLK_FLAG_GET(status) \
+	QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS, \
+	QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK)
+
+#define ICP_QAT_FW_COMN_RESP_UNSUPPORTED_REQUEST_STAT_GET(status) \
+	QAT_FIELD_GET(status, QAT_COMN_RESP_UNSUPPORTED_REQUEST_BITPOS, \
+	QAT_COMN_RESP_UNSUPPORTED_REQUEST_MASK)
+
+#define ICP_QAT_FW_COMN_STATUS_FLAG_OK 0
+#define ICP_QAT_FW_COMN_STATUS_FLAG_ERROR 1
+#define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_CLR 0
+#define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_SET 1
+#define ERR_CODE_NO_ERROR 0
+#define ERR_CODE_INVALID_BLOCK_TYPE -1
+#define ERR_CODE_NO_MATCH_ONES_COMP -2
+#define ERR_CODE_TOO_MANY_LEN_OR_DIS -3
+#define ERR_CODE_INCOMPLETE_LEN -4
+#define ERR_CODE_RPT_LEN_NO_FIRST_LEN -5
+#define ERR_CODE_RPT_GT_SPEC_LEN -6
+#define ERR_CODE_INV_LIT_LEN_CODE_LEN -7
+#define ERR_CODE_INV_DIS_CODE_LEN -8
+#define ERR_CODE_INV_LIT_LEN_DIS_IN_BLK -9
+#define ERR_CODE_DIS_TOO_FAR_BACK -10
+#define ERR_CODE_OVERFLOW_ERROR -11
+#define ERR_CODE_SOFT_ERROR -12
+#define ERR_CODE_FATAL_ERROR -13
+#define ERR_CODE_COMP_OUTPUT_CORRUPTION -14
+#define ERR_CODE_HW_INCOMPLETE_FILE -15
+#define ERR_CODE_SSM_ERROR -16
+#define ERR_CODE_ENDPOINT_ERROR -17
+#define ERR_CODE_CNV_ERROR -18
+#define ERR_CODE_EMPTY_DYM_BLOCK -19
+#define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_INVALID_HANDLE -20
+#define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_HMAC_FAILED -21
+#define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_INVALID_WRAPPING_ALGO -22
+#define ERR_CODE_KPT_DRNG_SEED_NOT_LOAD -23
+
+enum icp_qat_fw_slice {
+	ICP_QAT_FW_SLICE_NULL = 0,
+	ICP_QAT_FW_SLICE_CIPHER = 1,
+	ICP_QAT_FW_SLICE_AUTH = 2,
+	ICP_QAT_FW_SLICE_DRAM_RD = 3,
+	ICP_QAT_FW_SLICE_DRAM_WR = 4,
+	ICP_QAT_FW_SLICE_COMP = 5,
+	ICP_QAT_FW_SLICE_XLAT = 6,
+	ICP_QAT_FW_SLICE_DELIMITER
+};
+#endif
diff --git a/src/seastar/dpdk/drivers/common/qat/qat_adf/icp_qat_fw_comp.h b/src/seastar/dpdk/drivers/common/qat/qat_adf/icp_qat_fw_comp.h
new file mode 100644
index 000000000..813817720
--- /dev/null
+++ b/src/seastar/dpdk/drivers/common/qat/qat_adf/icp_qat_fw_comp.h
@@ -0,0 +1,482 @@
+/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
+ * Copyright(c) 2015-2018 Intel Corporation
+ */
+#ifndef _ICP_QAT_FW_COMP_H_
+#define _ICP_QAT_FW_COMP_H_
+
+#include "icp_qat_fw.h"
+
+enum icp_qat_fw_comp_cmd_id {
+	ICP_QAT_FW_COMP_CMD_STATIC = 0,
+	/*!< Static Compress Request */
+
+	ICP_QAT_FW_COMP_CMD_DYNAMIC = 1,
+	/*!< Dynamic Compress Request */
+
+	ICP_QAT_FW_COMP_CMD_DECOMPRESS = 2,
+	/*!< Decompress Request */
+
+	ICP_QAT_FW_COMP_CMD_DELIMITER
+	/**< Delimiter type */
+};
+
+/**< Flag usage */
+
+#define ICP_QAT_FW_COMP_STATELESS_SESSION 0
+/**< @ingroup icp_qat_fw_comp
+ *  Flag representing that session is stateless
+ */
+
+#define ICP_QAT_FW_COMP_STATEFUL_SESSION 1
+/**< @ingroup icp_qat_fw_comp
+ *  Flag representing that session is stateful
+ */
+
+#define ICP_QAT_FW_COMP_NOT_AUTO_SELECT_BEST 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that autoselectbest is NOT used
+ */
+
+#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that autoselectbest is used
+ */
+
+#define ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that enhanced autoselectbest is NOT used
+ */
+
+#define ICP_QAT_FW_COMP_ENH_AUTO_SELECT_BEST 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that enhanced autoselectbest is used
+ */
+
+#define ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that enhanced autoselectbest is NOT used
+ */
+
+#define ICP_QAT_FW_COMP_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that enhanced autoselectbest is used
+ */
+
+#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_USED_AS_INTMD_BUF 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing secure RAM from being used as
+ * an intermediate buffer is DISABLED.
+ */
+
+#define ICP_QAT_FW_COMP_ENABLE_SECURE_RAM_USED_AS_INTMD_BUF 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing secure RAM from being used as
+ * an intermediate buffer is ENABLED.
+ */
+
+/**< Flag mask & bit position */
+
+#define ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS 2
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for the session type
+ */
+
+#define ICP_QAT_FW_COMP_SESSION_TYPE_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask used to determine the session type
+ */
+
+#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS 3
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for auto select best
+ */
+
+#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for auto select best
+ */
+
+#define ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS 4
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for enhanced auto select best
+ */
+
+#define ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for enhanced auto select best
+ */
+
+#define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS 5
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for disabling type zero header write back
+ * when Enhanced autoselect best is enabled. If set firmware does
+ * not return type0 store block header, only copies src to dest.
+ * (if best output is Type0)
+ */
+
+#define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for auto select best
+ */
+
+#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS 7
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for flag used to disable secure ram from
+ *  being used as an intermediate buffer.
+ */
+
+#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for disable secure ram for use as an intermediate
+ * buffer.
+ */
+
+#define ICP_QAT_FW_COMP_FLAGS_BUILD(sesstype, autoselect, enhanced_asb,        \
+				    ret_uncomp, secure_ram)                    \
+	((((sesstype)&ICP_QAT_FW_COMP_SESSION_TYPE_MASK)                       \
+	  << ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS) |                            \
+	 (((autoselect)&ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK)                 \
+	  << ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS) |                        \
+	 (((enhanced_asb)&ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK)      \
+	  << ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS) |               \
+	 (((ret_uncomp)&ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK)    \
+	  << ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS) |           \
+	 (((secure_ram)&ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK)  \
+	  << ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS))
+
+union icp_qat_fw_comp_req_hdr_cd_pars {
+	/**< LWs 2-5 */
+	struct {
+		uint64_t content_desc_addr;
+		/**< Address of the content descriptor */
+
+		uint16_t content_desc_resrvd1;
+		/**< Content descriptor reserved field */
+
+		uint8_t content_desc_params_sz;
+		/**< Size of the content descriptor parameters in quad words.
+		 * These parameters describe the session setup configuration
+		 * info for the slices that this request relies upon i.e.
+		 * the configuration word and cipher key needed by the cipher
+		 * slice if there is a request for cipher processing.
+		 */
+
+		uint8_t content_desc_hdr_resrvd2;
+		/**< Content descriptor reserved field */
+
+		uint32_t content_desc_resrvd3;
+		/**< Content descriptor reserved field */
+	} s;
+
+	struct {
+		uint32_t comp_slice_cfg_word[ICP_QAT_FW_NUM_LONGWORDS_2];
+		/* Compression Slice Config Word */
+
+		uint32_t content_desc_resrvd4;
+		/**< Content descriptor reserved field */
+
+	} sl;
+
+};
+
+struct icp_qat_fw_comp_req_params {
+	/**< LW 14 */
+	uint32_t comp_len;
+	/**< Size of input to process in bytes Note:  Only EOP requests can be
+	 * odd for decompression. IA must set LSB to zero for odd sized
+	 * intermediate inputs
+	 */
+
+	/**< LW 15 */
+	uint32_t out_buffer_sz;
+	/**< Size of output buffer in bytes */
+
+	/**< LW 16 */
+	uint32_t initial_crc32;
+	/**< CRC of previously processed bytes */
+
+	/**< LW 17 */
+	uint32_t initial_adler;
+	/**< Adler of previously processed bytes */
+
+	/**< LW 18 */
+	uint32_t req_par_flags;
+
+	/**< LW 19 */
+	uint32_t rsrvd;
+};
+
+#define ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(sop, eop, bfinal, cnv, cnvnr)    \
+	((((sop)&ICP_QAT_FW_COMP_SOP_MASK) << ICP_QAT_FW_COMP_SOP_BITPOS) |    \
+	 (((eop)&ICP_QAT_FW_COMP_EOP_MASK) << ICP_QAT_FW_COMP_EOP_BITPOS) |    \
+	 (((bfinal)&ICP_QAT_FW_COMP_BFINAL_MASK)                               \
+	  << ICP_QAT_FW_COMP_BFINAL_BITPOS) |                                  \
+	 ((cnv & ICP_QAT_FW_COMP_CNV_MASK) << ICP_QAT_FW_COMP_CNV_BITPOS) |    \
+	 ((cnvnr & ICP_QAT_FW_COMP_CNV_RECOVERY_MASK)                          \
+	  << ICP_QAT_FW_COMP_CNV_RECOVERY_BITPOS))
+
+#define ICP_QAT_FW_COMP_NOT_SOP 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that a request is NOT Start of Packet
+ */
+
+#define ICP_QAT_FW_COMP_SOP 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that a request IS Start of Packet
+ */
+
+#define ICP_QAT_FW_COMP_NOT_EOP 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that a request is NOT Start of Packet
+ */
+
+#define ICP_QAT_FW_COMP_EOP 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing that a request IS End of Packet
+ */
+
+#define ICP_QAT_FW_COMP_NOT_BFINAL 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing to indicate firmware this is not the last block
+ */
+
+#define ICP_QAT_FW_COMP_BFINAL 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag representing to indicate firmware this is the last block
+ */
+
+#define ICP_QAT_FW_COMP_NO_CNV 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag indicating that NO cnv check is to be performed on the request
+ */
+
+#define ICP_QAT_FW_COMP_CNV 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag indicating that a cnv check IS to be performed on the request
+ */
+
+#define ICP_QAT_FW_COMP_NO_CNV_RECOVERY 0
+/**< @ingroup icp_qat_fw_comp
+ * Flag indicating that NO cnv recovery is to be performed on the request
+ */
+
+#define ICP_QAT_FW_COMP_CNV_RECOVERY 1
+/**< @ingroup icp_qat_fw_comp
+ * Flag indicating that a cnv recovery is to be performed on the request
+ */
+
+#define ICP_QAT_FW_COMP_SOP_BITPOS 0
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for SOP
+ */
+
+#define ICP_QAT_FW_COMP_SOP_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ *  One bit mask used to determine SOP
+ */
+
+#define ICP_QAT_FW_COMP_EOP_BITPOS 1
+/**< @ingroup icp_qat_fw_comp
+ *  Starting bit position for EOP
+ */
+
+#define ICP_QAT_FW_COMP_EOP_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ *  One bit mask used to determine EOP
+ */
+
+#define ICP_QAT_FW_COMP_BFINAL_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ *  One bit mask for the bfinal bit
+ */
+
+#define ICP_QAT_FW_COMP_BFINAL_BITPOS 6
+/**< @ingroup icp_qat_fw_comp
+ *  Starting bit position for the bfinal bit
+ */
+
+#define ICP_QAT_FW_COMP_CNV_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for the CNV bit
+ */
+
+#define ICP_QAT_FW_COMP_CNV_BITPOS 16
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for the CNV bit
+ */
+
+#define ICP_QAT_FW_COMP_CNV_RECOVERY_MASK 0x1
+/**< @ingroup icp_qat_fw_comp
+ * One bit mask for the CNV Recovery bit
+ */
+
+#define ICP_QAT_FW_COMP_CNV_RECOVERY_BITPOS 17
+/**< @ingroup icp_qat_fw_comp
+ * Starting bit position for the CNV Recovery bit
+ */
+
+struct icp_qat_fw_xlt_req_params {
+	/**< LWs 20-21 */
+	uint64_t inter_buff_ptr;
+	/**< This field specifies the physical address of an intermediate
+	 *  buffer SGL array. The array contains a pair of 64-bit
+	 *  intermediate buffer pointers to SGL buffer descriptors, one pair
+	 *  per CPM. Please refer to the CPM1.6 Firmware Interface HLD
+	 *  specification for more details.
+	 */
+};
+
+
+struct icp_qat_fw_comp_cd_hdr {
+	/**< LW 24 */
+	uint16_t ram_bank_flags;
+	/**< Flags to show which ram banks to access */
+
+	uint8_t comp_cfg_offset;
+	/**< Quad word offset from the content descriptor parameters address
+	 * to the parameters for the compression processing
+	 */
+
+	uint8_t next_curr_id;
+	/**< This field combines the next and current id (each four bits) -
+	 * the next id is the most significant nibble.
+	 * Next Id:  Set to the next slice to pass the compressed data through.
+	 * Set to ICP_QAT_FW_SLICE_DRAM_WR if the data is not to go through
+	 * anymore slices after compression
+	 * Current Id: Initialised with the compression slice type
+	 */
+
+	/**< LW 25 */
+	uint32_t resrvd;
+	/**< LWs 26-27 */
+
+	uint64_t comp_state_addr;
+	/**< Pointer to compression state */
+
+	/**< LWs 28-29 */
+	uint64_t ram_banks_addr;
+	/**< Pointer to banks */
+
+};
+
+
+struct icp_qat_fw_xlt_cd_hdr {
+	/**< LW 30 */
+	uint16_t resrvd1;
+	/**< Reserved field and assumed set to 0 */
+
+	uint8_t resrvd2;
+	/**< Reserved field and assumed set to 0 */
+
+	uint8_t next_curr_id;
+	/**< This field combines the next and current id (each four bits) -
+	 * the next id is the most significant nibble.
+	 * Next Id:  Set to the next slice to pass the translated data through.
+	 * Set to ICP_QAT_FW_SLICE_DRAM_WR if the data is not to go through
+	 * any more slices after compression
+	 * Current Id: Initialised with the translation slice type
+	 */
+
+	/**< LW 31 */
+	uint32_t resrvd3;
+	/**< Reserved and should be set to zero, needed for quadword
+	 * alignment
+	 */
+};
+
+struct icp_qat_fw_comp_req {
+	/**< LWs 0-1 */
+	struct icp_qat_fw_comn_req_hdr comn_hdr;
+	/**< Common request header - for Service Command Id,
+	 * use service-specific Compression Command Id.
+	 * Service Specific Flags - use Compression Command Flags
+	 */
+
+	/**< LWs 2-5 */
+	union icp_qat_fw_comp_req_hdr_cd_pars cd_pars;
+	/**< Compression service-specific content descriptor field which points
+	 * either to a content descriptor parameter block or contains the
+	 * compression slice config word.
+	 */
+
+	/**< LWs 6-13 */
+	struct icp_qat_fw_comn_req_mid comn_mid;
+	/**< Common request middle section */
+
+	/**< LWs 14-19 */
+	struct icp_qat_fw_comp_req_params comp_pars;
+	/**< Compression request Parameters block */
+
+	/**< LWs 20-21 */
+	union {
+		struct icp_qat_fw_xlt_req_params xlt_pars;
+		/**< Translation request Parameters block */
+		uint32_t resrvd1[ICP_QAT_FW_NUM_LONGWORDS_2];
+		/**< Reserved if not used for translation */
+
+	} u1;
+
+	/**< LWs 22-23 */
+	union {
+		uint32_t resrvd2[ICP_QAT_FW_NUM_LONGWORDS_2];
+		/**< Reserved - not used if Batch and Pack is disabled.*/
+
+		uint64_t bnp_res_table_addr;
+		/**< A generic pointer to the unbounded list of
+		 * icp_qat_fw_resp_comp_pars members. This pointer is only
+		 * used when the Batch and Pack is enabled.
+		 */
+	} u3;
+
+	/**< LWs 24-29 */
+	struct icp_qat_fw_comp_cd_hdr comp_cd_ctrl;
+	/**< Compression request content descriptor control block header */
+
+	/**< LWs 30-31 */
+	union {
+		struct icp_qat_fw_xlt_cd_hdr xlt_cd_ctrl;
+		/**< Translation request content descriptor
+		 * control block header
+		 */
+
+		uint32_t resrvd3[ICP_QAT_FW_NUM_LONGWORDS_2];
+		/**< Reserved if not used for translation */
+	} u2;
+};
+
+struct icp_qat_fw_resp_comp_pars {
+	/**< LW 4 */
+	uint32_t input_byte_counter;
+	/**< Input byte counter */
+
+	/**< LW 5 */
+	uint32_t output_byte_counter;
+	/**< Output byte counter */
+
+	/**< LW 6 & 7*/
+	union {
+		uint64_t curr_chksum;
+		struct {
+			/**< LW 6 */
+			uint32_t curr_crc32;
+			/**< LW 7 */
+			uint32_t curr_adler_32;
+		};
+	};
+};
+
+struct icp_qat_fw_comp_resp {
+	/**< LWs 0-1 */
+	struct icp_qat_fw_comn_resp_hdr comn_resp;
+	/**< Common interface response format see icp_qat_fw.h */
+
+	/**< LWs 2-3 */
+	uint64_t opaque_data;
+	/**< Opaque data passed from the request to the response message */
+
+	/**< LWs 4-7 */
+	struct icp_qat_fw_resp_comp_pars comp_resp_pars;
+	/**< Common response params (checksums and byte counts) */
+};
+
+#endif
diff --git a/src/seastar/dpdk/drivers/common/qat/qat_adf/icp_qat_fw_la.h b/src/seastar/dpdk/drivers/common/qat/qat_adf/icp_qat_fw_la.h
new file mode 100644
index 000000000..c33bc3fe7
--- /dev/null
+++ b/src/seastar/dpdk/drivers/common/qat/qat_adf/icp_qat_fw_la.h
@@ -0,0 +1,361 @@
+/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
+ * Copyright(c) 2015-2018 Intel Corporation
+ */
+#ifndef _ICP_QAT_FW_LA_H_
+#define _ICP_QAT_FW_LA_H_
+#include "icp_qat_fw.h"
+
+enum icp_qat_fw_la_cmd_id {
+	ICP_QAT_FW_LA_CMD_CIPHER = 0,
+	ICP_QAT_FW_LA_CMD_AUTH = 1,
+	ICP_QAT_FW_LA_CMD_CIPHER_HASH = 2,
+	ICP_QAT_FW_LA_CMD_HASH_CIPHER = 3,
+	ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM = 4,
+	ICP_QAT_FW_LA_CMD_TRNG_TEST = 5,
+	ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE = 6,
+	ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE = 7,
+	ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE = 8,
+	ICP_QAT_FW_LA_CMD_MGF1 = 9,
+	ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP = 10,
+	ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP = 11,
+	ICP_QAT_FW_LA_CMD_DELIMITER = 12
+};
+
+#define ICP_QAT_FW_LA_ICV_VER_STATUS_PASS ICP_QAT_FW_COMN_STATUS_FLAG_OK
+#define ICP_QAT_FW_LA_ICV_VER_STATUS_FAIL ICP_QAT_FW_COMN_STATUS_FLAG_ERROR
+#define ICP_QAT_FW_LA_TRNG_STATUS_PASS ICP_QAT_FW_COMN_STATUS_FLAG_OK
+#define ICP_QAT_FW_LA_TRNG_STATUS_FAIL ICP_QAT_FW_COMN_STATUS_FLAG_ERROR
+
+struct icp_qat_fw_la_bulk_req {
+	struct icp_qat_fw_comn_req_hdr comn_hdr;
+	struct icp_qat_fw_comn_req_hdr_cd_pars cd_pars;
+	struct icp_qat_fw_comn_req_mid comn_mid;
+	struct icp_qat_fw_comn_req_rqpars serv_specif_rqpars;
+	struct icp_qat_fw_comn_req_cd_ctrl cd_ctrl;
+};
+
+#define ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS 1
+#define ICP_QAT_FW_LA_GCM_IV_LEN_NOT_12_OCTETS 0
+#define QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS 12
+#define ICP_QAT_FW_LA_ZUC_3G_PROTO 1
+#define QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK 0x1
+#define QAT_LA_GCM_IV_LEN_FLAG_BITPOS 11
+#define QAT_LA_GCM_IV_LEN_FLAG_MASK 0x1
+#define ICP_QAT_FW_LA_DIGEST_IN_BUFFER 1
+#define ICP_QAT_FW_LA_NO_DIGEST_IN_BUFFER 0
+#define QAT_LA_DIGEST_IN_BUFFER_BITPOS	10
+#define QAT_LA_DIGEST_IN_BUFFER_MASK 0x1
+#define ICP_QAT_FW_LA_SNOW_3G_PROTO 4
+#define ICP_QAT_FW_LA_GCM_PROTO	2
+#define ICP_QAT_FW_LA_CCM_PROTO	1
+#define ICP_QAT_FW_LA_NO_PROTO 0
+#define QAT_LA_PROTO_BITPOS 7
+#define QAT_LA_PROTO_MASK 0x7
+#define ICP_QAT_FW_LA_CMP_AUTH_RES 1
+#define ICP_QAT_FW_LA_NO_CMP_AUTH_RES 0
+#define QAT_LA_CMP_AUTH_RES_BITPOS 6
+#define QAT_LA_CMP_AUTH_RES_MASK 0x1
+#define ICP_QAT_FW_LA_RET_AUTH_RES 1
+#define ICP_QAT_FW_LA_NO_RET_AUTH_RES 0
+#define QAT_LA_RET_AUTH_RES_BITPOS 5
+#define QAT_LA_RET_AUTH_RES_MASK 0x1
+#define ICP_QAT_FW_LA_UPDATE_STATE 1
+#define ICP_QAT_FW_LA_NO_UPDATE_STATE 0
+#define QAT_LA_UPDATE_STATE_BITPOS 4
+#define QAT_LA_UPDATE_STATE_MASK 0x1
+#define ICP_QAT_FW_CIPH_AUTH_CFG_OFFSET_IN_CD_SETUP 0
+#define ICP_QAT_FW_CIPH_AUTH_CFG_OFFSET_IN_SHRAM_CP 1
+#define QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS 3
+#define QAT_LA_CIPH_AUTH_CFG_OFFSET_MASK 0x1
+#define ICP_QAT_FW_CIPH_IV_64BIT_PTR 0
+#define ICP_QAT_FW_CIPH_IV_16BYTE_DATA 1
+#define QAT_LA_CIPH_IV_FLD_BITPOS 2
+#define QAT_LA_CIPH_IV_FLD_MASK   0x1
+#define ICP_QAT_FW_LA_PARTIAL_NONE 0
+#define ICP_QAT_FW_LA_PARTIAL_START 1
+#define ICP_QAT_FW_LA_PARTIAL_MID 3
+#define ICP_QAT_FW_LA_PARTIAL_END 2
+#define QAT_LA_PARTIAL_BITPOS 0
+#define QAT_LA_PARTIAL_MASK 0x3
+#define ICP_QAT_FW_LA_FLAGS_BUILD(zuc_proto, gcm_iv_len, auth_rslt, proto, \
+	cmp_auth, ret_auth, update_state, \
+	ciph_iv, ciphcfg, partial) \
+	(((zuc_proto & QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK) << \
+	QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS) | \
+	((gcm_iv_len & QAT_LA_GCM_IV_LEN_FLAG_MASK) << \
+	QAT_LA_GCM_IV_LEN_FLAG_BITPOS) | \
+	((auth_rslt & QAT_LA_DIGEST_IN_BUFFER_MASK) << \
+	QAT_LA_DIGEST_IN_BUFFER_BITPOS) | \
+	((proto & QAT_LA_PROTO_MASK) << \
+	QAT_LA_PROTO_BITPOS)	| \
+	((cmp_auth & QAT_LA_CMP_AUTH_RES_MASK) << \
+	QAT_LA_CMP_AUTH_RES_BITPOS) | \
+	((ret_auth & QAT_LA_RET_AUTH_RES_MASK) << \
+	QAT_LA_RET_AUTH_RES_BITPOS) | \
+	((update_state & QAT_LA_UPDATE_STATE_MASK) << \
+	QAT_LA_UPDATE_STATE_BITPOS) | \
+	((ciph_iv & QAT_LA_CIPH_IV_FLD_MASK) << \
+	QAT_LA_CIPH_IV_FLD_BITPOS) | \
+	((ciphcfg & QAT_LA_CIPH_AUTH_CFG_OFFSET_MASK) << \
+	QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS) | \
+	((partial & QAT_LA_PARTIAL_MASK) << \
+	QAT_LA_PARTIAL_BITPOS))
+
+#define ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_GET(flags) \
+	QAT_FIELD_GET(flags, QAT_LA_CIPH_IV_FLD_BITPOS, \
+	QAT_LA_CIPH_IV_FLD_MASK)
+
+#define ICP_QAT_FW_LA_CIPH_AUTH_CFG_OFFSET_FLAG_GET(flags) \
+	QAT_FIELD_GET(flags, QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS, \
+	QAT_LA_CIPH_AUTH_CFG_OFFSET_MASK)
+
+#define ICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_GET(flags) \
+	QAT_FIELD_GET(flags, QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS, \
+	QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK)
+
+#define ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_GET(flags) \
+	QAT_FIELD_GET(flags, QAT_LA_GCM_IV_LEN_FLAG_BITPOS, \
+	QAT_LA_GCM_IV_LEN_FLAG_MASK)
+
+#define ICP_QAT_FW_LA_PROTO_GET(flags) \
+	QAT_FIELD_GET(flags, QAT_LA_PROTO_BITPOS, QAT_LA_PROTO_MASK)
+
+#define ICP_QAT_FW_LA_CMP_AUTH_GET(flags) \
+	QAT_FIELD_GET(flags, QAT_LA_CMP_AUTH_RES_BITPOS, \
+	QAT_LA_CMP_AUTH_RES_MASK)
+
+#define ICP_QAT_FW_LA_RET_AUTH_GET(flags) \
+	QAT_FIELD_GET(flags, QAT_LA_RET_AUTH_RES_BITPOS, \
+	QAT_LA_RET_AUTH_RES_MASK)
+
+#define ICP_QAT_FW_LA_DIGEST_IN_BUFFER_GET(flags) \
+	QAT_FIELD_GET(flags, QAT_LA_DIGEST_IN_BUFFER_BITPOS, \
+	QAT_LA_DIGEST_IN_BUFFER_MASK)
+
+#define ICP_QAT_FW_LA_UPDATE_STATE_GET(flags) \
+	QAT_FIELD_GET(flags, QAT_LA_UPDATE_STATE_BITPOS, \
+	QAT_LA_UPDATE_STATE_MASK)
+
+#define ICP_QAT_FW_LA_PARTIAL_GET(flags) \
+	QAT_FIELD_GET(flags, QAT_LA_PARTIAL_BITPOS, \
+	QAT_LA_PARTIAL_MASK)
+
+#define ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(flags, val) \
+	QAT_FIELD_SET(flags, val, QAT_LA_CIPH_IV_FLD_BITPOS, \
+	QAT_LA_CIPH_IV_FLD_MASK)
+
+#define ICP_QAT_FW_LA_CIPH_AUTH_CFG_OFFSET_FLAG_SET(flags, val) \
+	QAT_FIELD_SET(flags, val, QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS, \
+	QAT_LA_CIPH_AUTH_CFG_OFFSET_MASK)
+
+#define ICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_SET(flags, val) \
+	QAT_FIELD_SET(flags, val, QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS, \
+	QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK)
+
+#define ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(flags, val) \
+	QAT_FIELD_SET(flags, val, QAT_LA_GCM_IV_LEN_FLAG_BITPOS, \
+	QAT_LA_GCM_IV_LEN_FLAG_MASK)
+
+#define ICP_QAT_FW_LA_PROTO_SET(flags, val) \
+	QAT_FIELD_SET(flags, val, QAT_LA_PROTO_BITPOS, \
+	QAT_LA_PROTO_MASK)
+
+#define ICP_QAT_FW_LA_CMP_AUTH_SET(flags, val) \
+	QAT_FIELD_SET(flags, val, QAT_LA_CMP_AUTH_RES_BITPOS, \
+	QAT_LA_CMP_AUTH_RES_MASK)
+
+#define ICP_QAT_FW_LA_RET_AUTH_SET(flags, val) \
+	QAT_FIELD_SET(flags, val, QAT_LA_RET_AUTH_RES_BITPOS, \
+	QAT_LA_RET_AUTH_RES_MASK)
+
+#define ICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET(flags, val) \
+	QAT_FIELD_SET(flags, val, QAT_LA_DIGEST_IN_BUFFER_BITPOS, \
+	QAT_LA_DIGEST_IN_BUFFER_MASK)
+
+#define ICP_QAT_FW_LA_UPDATE_STATE_SET(flags, val) \
+	QAT_FIELD_SET(flags, val, QAT_LA_UPDATE_STATE_BITPOS, \
+	QAT_LA_UPDATE_STATE_MASK)
+
+#define ICP_QAT_FW_LA_PARTIAL_SET(flags, val) \
+	QAT_FIELD_SET(flags, val, QAT_LA_PARTIAL_BITPOS, \
+	QAT_LA_PARTIAL_MASK)
+
+struct icp_qat_fw_cipher_req_hdr_cd_pars {
+	union {
+		struct {
+			uint64_t content_desc_addr;
+			uint16_t content_desc_resrvd1;
+			uint8_t content_desc_params_sz;
+			uint8_t content_desc_hdr_resrvd2;
+			uint32_t content_desc_resrvd3;
+		} s;
+		struct {
+			uint32_t cipher_key_array[ICP_QAT_FW_NUM_LONGWORDS_4];
+		} s1;
+	} u;
+};
+
+struct icp_qat_fw_cipher_auth_req_hdr_cd_pars {
+	union {
+		struct {
+			uint64_t content_desc_addr;
+			uint16_t content_desc_resrvd1;
+			uint8_t content_desc_params_sz;
+			uint8_t content_desc_hdr_resrvd2;
+			uint32_t content_desc_resrvd3;
+		} s;
+		struct {
+			uint32_t cipher_key_array[ICP_QAT_FW_NUM_LONGWORDS_4];
+		} sl;
+	} u;
+};
+
+struct icp_qat_fw_cipher_cd_ctrl_hdr {
+	uint8_t cipher_state_sz;
+	uint8_t cipher_key_sz;
+	uint8_t cipher_cfg_offset;
+	uint8_t next_curr_id;
+	uint8_t cipher_padding_sz;
+	uint8_t resrvd1;
+	uint16_t resrvd2;
+	uint32_t resrvd3[ICP_QAT_FW_NUM_LONGWORDS_3];
+};
+
+struct icp_qat_fw_auth_cd_ctrl_hdr {
+	uint32_t resrvd1;
+	uint8_t resrvd2;
+	uint8_t hash_flags;
+	uint8_t hash_cfg_offset;
+	uint8_t next_curr_id;
+	uint8_t resrvd3;
+	uint8_t outer_prefix_sz;
+	uint8_t final_sz;
+	uint8_t inner_res_sz;
+	uint8_t resrvd4;
+	uint8_t inner_state1_sz;
+	uint8_t inner_state2_offset;
+	uint8_t inner_state2_sz;
+	uint8_t outer_config_offset;
+	uint8_t outer_state1_sz;
+	uint8_t outer_res_sz;
+	uint8_t outer_prefix_offset;
+};
+
+struct icp_qat_fw_cipher_auth_cd_ctrl_hdr {
+	uint8_t cipher_state_sz;
+	uint8_t cipher_key_sz;
+	uint8_t cipher_cfg_offset;
+	uint8_t next_curr_id_cipher;
+	uint8_t cipher_padding_sz;
+	uint8_t hash_flags;
+	uint8_t hash_cfg_offset;
+	uint8_t next_curr_id_auth;
+	uint8_t resrvd1;
+	uint8_t outer_prefix_sz;
+	uint8_t final_sz;
+	uint8_t inner_res_sz;
+	uint8_t resrvd2;
+	uint8_t inner_state1_sz;
+	uint8_t inner_state2_offset;
+	uint8_t inner_state2_sz;
+	uint8_t outer_config_offset;
+	uint8_t outer_state1_sz;
+	uint8_t outer_res_sz;
+	uint8_t outer_prefix_offset;
+};
+
+#define ICP_QAT_FW_AUTH_HDR_FLAG_DO_NESTED 1
+#define ICP_QAT_FW_AUTH_HDR_FLAG_NO_NESTED 0
+#define ICP_QAT_FW_CCM_GCM_AAD_SZ_MAX	240
+#define ICP_QAT_FW_HASH_REQUEST_PARAMETERS_OFFSET \
+	(sizeof(struct icp_qat_fw_la_cipher_req_params_t))
+#define ICP_QAT_FW_CIPHER_REQUEST_PARAMETERS_OFFSET (0)
+
+struct icp_qat_fw_la_cipher_req_params {
+	uint32_t cipher_offset;
+	uint32_t cipher_length;
+	union {
+		uint32_t cipher_IV_array[ICP_QAT_FW_NUM_LONGWORDS_4];
+		struct {
+			uint64_t cipher_IV_ptr;
+			uint64_t resrvd1;
+		} s;
+	} u;
+};
+
+struct icp_qat_fw_la_auth_req_params {
+	uint32_t auth_off;
+	uint32_t auth_len;
+	union {
+		uint64_t auth_partial_st_prefix;
+		uint64_t aad_adr;
+	} u1;
+	uint64_t auth_res_addr;
+	union {
+		uint8_t inner_prefix_sz;
+		uint8_t aad_sz;
+	} u2;
+	uint8_t resrvd1;
+	uint8_t hash_state_sz;
+	uint8_t auth_res_sz;
+} __rte_packed;
+
+struct icp_qat_fw_la_auth_req_params_resrvd_flds {
+	uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_6];
+	union {
+		uint8_t inner_prefix_sz;
+		uint8_t aad_sz;
+	} u2;
+	uint8_t resrvd1;
+	uint16_t resrvd2;
+};
+
+struct icp_qat_fw_la_resp {
+	struct icp_qat_fw_comn_resp_hdr comn_resp;
+	uint64_t opaque_data;
+	uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_4];
+};
+
+#define ICP_QAT_FW_CIPHER_NEXT_ID_GET(cd_ctrl_hdr_t) \
+	((((cd_ctrl_hdr_t)->next_curr_id_cipher) & \
+	  ICP_QAT_FW_COMN_NEXT_ID_MASK) >> (ICP_QAT_FW_COMN_NEXT_ID_BITPOS))
+
+#define ICP_QAT_FW_CIPHER_NEXT_ID_SET(cd_ctrl_hdr_t, val) \
+{ (cd_ctrl_hdr_t)->next_curr_id_cipher = \
+	((((cd_ctrl_hdr_t)->next_curr_id_cipher) \
+	& ICP_QAT_FW_COMN_CURR_ID_MASK) | \
+	((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \
+	& ICP_QAT_FW_COMN_NEXT_ID_MASK)) }
+
+#define ICP_QAT_FW_CIPHER_CURR_ID_GET(cd_ctrl_hdr_t) \
+	(((cd_ctrl_hdr_t)->next_curr_id_cipher) \
+	& ICP_QAT_FW_COMN_CURR_ID_MASK)
+
+#define ICP_QAT_FW_CIPHER_CURR_ID_SET(cd_ctrl_hdr_t, val) \
+{ (cd_ctrl_hdr_t)->next_curr_id_cipher = \
+	((((cd_ctrl_hdr_t)->next_curr_id_cipher) \
+	& ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
+	((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) }
+
+#define ICP_QAT_FW_AUTH_NEXT_ID_GET(cd_ctrl_hdr_t) \
+	((((cd_ctrl_hdr_t)->next_curr_id_auth) & ICP_QAT_FW_COMN_NEXT_ID_MASK) \
+	>> (ICP_QAT_FW_COMN_NEXT_ID_BITPOS))
+
+#define ICP_QAT_FW_AUTH_NEXT_ID_SET(cd_ctrl_hdr_t, val) \
+{ (cd_ctrl_hdr_t)->next_curr_id_auth = \
+	((((cd_ctrl_hdr_t)->next_curr_id_auth) \
+	& ICP_QAT_FW_COMN_CURR_ID_MASK) | \
+	((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \
+	& ICP_QAT_FW_COMN_NEXT_ID_MASK)) }
+
+#define ICP_QAT_FW_AUTH_CURR_ID_GET(cd_ctrl_hdr_t) \
+	(((cd_ctrl_hdr_t)->next_curr_id_auth) \
+	& ICP_QAT_FW_COMN_CURR_ID_MASK)
+
+#define ICP_QAT_FW_AUTH_CURR_ID_SET(cd_ctrl_hdr_t, val) \
+{ (cd_ctrl_hdr_t)->next_curr_id_auth = \
+	((((cd_ctrl_hdr_t)->next_curr_id_auth) \
+	& ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
+	((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) }
+
+#endif
diff --git a/src/seastar/dpdk/drivers/common/qat/qat_adf/icp_qat_fw_mmp_ids.h b/src/seastar/dpdk/drivers/common/qat/qat_adf/icp_qat_fw_mmp_ids.h
new file mode 100644
index 000000000..00813cffb
--- /dev/null
+++ b/src/seastar/dpdk/drivers/common/qat/qat_adf/icp_qat_fw_mmp_ids.h
@@ -0,0 +1,1538 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Intel Corporation
+ */
+
+/**
+ * @file icp_qat_fw_mmp_ids.h
+ * @ingroup icp_qat_fw_mmp
+ * @brief
+ *      This file documents the external interfaces that the QAT FW running
+ *      on the QAT Acceleration Engine provides to clients wanting to
+ *      accelerate crypto asymmetric applications
+ */
+
+#ifndef _ICP_QAT_FW_MMP_IDS_
+#define _ICP_QAT_FW_MMP_IDS_
+
+#define PKE_INIT 0x09061a09
+/**< Functionality ID for Initialisation sequence
+ * @li 1 input parameters : @link icp_qat_fw_mmp_init_input::z z @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_init_output::zz zz @endlink
+ */
+#define PKE_DH_G2_768 0x1c0b1a10
+/**< Functionality ID for Diffie-Hellman Modular exponentiation base 2 for
+ *768-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_dh_g2_768_input::e e
+ * @endlink @link icp_qat_fw_mmp_dh_g2_768_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_g2_768_output::r r
+ * @endlink
+ */
+#define PKE_DH_768 0x210c1a1b
+/**< Functionality ID for Diffie-Hellman Modular exponentiation for 768-bit
+ *numbers
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dh_768_input::g g @endlink
+ * @link icp_qat_fw_mmp_dh_768_input::e e @endlink @link
+ * icp_qat_fw_mmp_dh_768_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_768_output::r r @endlink
+ */
+#define PKE_DH_G2_1024 0x220b1a27
+/**< Functionality ID for Diffie-Hellman Modular exponentiation base 2 for
+ * 1024-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_dh_g2_1024_input::e e
+ * @endlink @link icp_qat_fw_mmp_dh_g2_1024_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_g2_1024_output::r r
+ * @endlink
+ */
+#define PKE_DH_1024 0x290c1a32
+/**< Functionality ID for Diffie-Hellman Modular exponentiation for 1024-bit
+ * numbers
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dh_1024_input::g g @endlink
+ * @link icp_qat_fw_mmp_dh_1024_input::e e @endlink @link
+ * icp_qat_fw_mmp_dh_1024_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_1024_output::r r @endlink
+ */
+#define PKE_DH_G2_1536 0x2e0b1a3e
+/**< Functionality ID for Diffie-Hellman Modular exponentiation base 2 for
+ * 1536-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_dh_g2_1536_input::e e
+ * @endlink @link icp_qat_fw_mmp_dh_g2_1536_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_g2_1536_output::r r
+ * @endlink
+ */
+#define PKE_DH_1536 0x390c1a49
+/**< Functionality ID for Diffie-Hellman Modular exponentiation for 1536-bit
+ * numbers
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dh_1536_input::g g @endlink
+ * @link icp_qat_fw_mmp_dh_1536_input::e e @endlink @link
+ * icp_qat_fw_mmp_dh_1536_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_1536_output::r r @endlink
+ */
+#define PKE_DH_G2_2048 0x3e0b1a55
+/**< Functionality ID for Diffie-Hellman Modular exponentiation base 2 for
+ * 2048-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_dh_g2_2048_input::e e
+ * @endlink @link icp_qat_fw_mmp_dh_g2_2048_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_g2_2048_output::r r
+ * @endlink
+ */
+#define PKE_DH_2048 0x4d0c1a60
+/**< Functionality ID for Diffie-Hellman Modular exponentiation for 2048-bit
+ * numbers
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dh_2048_input::g g @endlink
+ * @link icp_qat_fw_mmp_dh_2048_input::e e @endlink @link
+ * icp_qat_fw_mmp_dh_2048_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_2048_output::r r @endlink
+ */
+#define PKE_DH_G2_3072 0x3a0b1a6c
+/**< Functionality ID for Diffie-Hellman Modular exponentiation base 2 for
+ * 3072-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_dh_g2_3072_input::e e
+ * @endlink @link icp_qat_fw_mmp_dh_g2_3072_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_g2_3072_output::r r
+ * @endlink
+ */
+#define PKE_DH_3072 0x510c1a77
+/**< Functionality ID for Diffie-Hellman Modular exponentiation for 3072-bit
+ * numbers
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dh_3072_input::g g @endlink
+ * @link icp_qat_fw_mmp_dh_3072_input::e e @endlink @link
+ * icp_qat_fw_mmp_dh_3072_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_3072_output::r r @endlink
+ */
+#define PKE_DH_G2_4096 0x4a0b1a83
+/**< Functionality ID for Diffie-Hellman Modular exponentiation base 2 for
+ * 4096-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_dh_g2_4096_input::e e
+ * @endlink @link icp_qat_fw_mmp_dh_g2_4096_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_g2_4096_output::r r
+ * @endlink
+ */
+#define PKE_DH_4096 0x690c1a8e
+/**< Functionality ID for Diffie-Hellman Modular exponentiation for 4096-bit
+ * numbers
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dh_4096_input::g g @endlink
+ * @link icp_qat_fw_mmp_dh_4096_input::e e @endlink @link
+ * icp_qat_fw_mmp_dh_4096_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dh_4096_output::r r @endlink
+ */
+#define PKE_RSA_KP1_512 0x191d1a9a
+/**< Functionality ID for RSA 512 key generation first form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp1_512_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_512_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp1_512_input::e e @endlink
+ * @li 2 output parameters : @link icp_qat_fw_mmp_rsa_kp1_512_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_512_output::d d @endlink
+ */
+#define PKE_RSA_KP2_512 0x19401acc
+/**< Functionality ID for RSA 512 key generation second form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp2_512_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_512_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_512_input::e e @endlink
+ * @li 5 output parameters : @link icp_qat_fw_mmp_rsa_kp2_512_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_512_output::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_512_output::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_512_output::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_512_output::qinv qinv @endlink
+ */
+#define PKE_RSA_EP_512 0x1c161b21
+/**< Functionality ID for RSA 512 Encryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_ep_512_input::m m
+ * @endlink @link icp_qat_fw_mmp_rsa_ep_512_input::e e @endlink @link
+ * icp_qat_fw_mmp_rsa_ep_512_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_ep_512_output::c c
+ * @endlink
+ */
+#define PKE_RSA_DP1_512 0x1c161b3c
+/**< Functionality ID for RSA 512 Decryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_dp1_512_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp1_512_input::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_dp1_512_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp1_512_output::m m
+ * @endlink
+ */
+#define PKE_RSA_DP2_512 0x1c131b57
+/**< Functionality ID for RSA 1024 Decryption with CRT
+ * @li 6 input parameters : @link icp_qat_fw_mmp_rsa_dp2_512_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp2_512_input::p p @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_512_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_512_input::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_512_input::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_512_input::qinv qinv @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp2_512_output::m m
+ * @endlink
+ */
+#define PKE_RSA_KP1_1024 0x36181b71
+/**< Functionality ID for RSA 1024 key generation first form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp1_1024_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_1024_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp1_1024_input::e e @endlink
+ * @li 2 output parameters : @link icp_qat_fw_mmp_rsa_kp1_1024_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_1024_output::d d @endlink
+ */
+#define PKE_RSA_KP2_1024 0x40451b9e
+/**< Functionality ID for RSA 1024 key generation second form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp2_1024_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_1024_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_1024_input::e e @endlink
+ * @li 5 output parameters : @link icp_qat_fw_mmp_rsa_kp2_1024_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_1024_output::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_1024_output::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_1024_output::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_1024_output::qinv qinv @endlink
+ */
+#define PKE_RSA_EP_1024 0x35111bf7
+/**< Functionality ID for RSA 1024 Encryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_ep_1024_input::m m
+ * @endlink @link icp_qat_fw_mmp_rsa_ep_1024_input::e e @endlink @link
+ * icp_qat_fw_mmp_rsa_ep_1024_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_ep_1024_output::c c
+ * @endlink
+ */
+#define PKE_RSA_DP1_1024 0x35111c12
+/**< Functionality ID for RSA 1024 Decryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_dp1_1024_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp1_1024_input::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_dp1_1024_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp1_1024_output::m m
+ * @endlink
+ */
+#define PKE_RSA_DP2_1024 0x26131c2d
+/**< Functionality ID for RSA 1024 Decryption with CRT
+ * @li 6 input parameters : @link icp_qat_fw_mmp_rsa_dp2_1024_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp2_1024_input::p p @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_1024_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_1024_input::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_1024_input::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_1024_input::qinv qinv @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp2_1024_output::m m
+ * @endlink
+ */
+#define PKE_RSA_KP1_1536 0x531d1c46
+/**< Functionality ID for RSA 1536 key generation first form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp1_1536_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_1536_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp1_1536_input::e e @endlink
+ * @li 2 output parameters : @link icp_qat_fw_mmp_rsa_kp1_1536_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_1536_output::d d @endlink
+ */
+#define PKE_RSA_KP2_1536 0x32391c78
+/**< Functionality ID for RSA 1536 key generation second form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp2_1536_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_1536_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_1536_input::e e @endlink
+ * @li 5 output parameters : @link icp_qat_fw_mmp_rsa_kp2_1536_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_1536_output::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_1536_output::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_1536_output::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_1536_output::qinv qinv @endlink
+ */
+#define PKE_RSA_EP_1536 0x4d111cdc
+/**< Functionality ID for RSA 1536 Encryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_ep_1536_input::m m
+ * @endlink @link icp_qat_fw_mmp_rsa_ep_1536_input::e e @endlink @link
+ * icp_qat_fw_mmp_rsa_ep_1536_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_ep_1536_output::c c
+ * @endlink
+ */
+#define PKE_RSA_DP1_1536 0x4d111cf7
+/**< Functionality ID for RSA 1536 Decryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_dp1_1536_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp1_1536_input::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_dp1_1536_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp1_1536_output::m m
+ *@endlink
+ */
+#define PKE_RSA_DP2_1536 0x45111d12
+/**< Functionality ID for RSA 1536 Decryption with CRT
+ * @li 6 input parameters : @link icp_qat_fw_mmp_rsa_dp2_1536_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp2_1536_input::p p @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_1536_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_1536_input::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_1536_input::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_1536_input::qinv qinv @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp2_1536_output::m m
+ * @endlink
+ */
+#define PKE_RSA_KP1_2048 0x72181d2e
+/**< Functionality ID for RSA 2048 key generation first form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp1_2048_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_2048_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp1_2048_input::e e @endlink
+ * @li 2 output parameters : @link icp_qat_fw_mmp_rsa_kp1_2048_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_2048_output::d d @endlink
+ */
+#define PKE_RSA_KP2_2048 0x42341d5b
+/**< Functionality ID for RSA 2048 key generation second form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp2_2048_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_2048_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_2048_input::e e @endlink
+ * @li 5 output parameters : @link icp_qat_fw_mmp_rsa_kp2_2048_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_2048_output::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_2048_output::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_2048_output::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_2048_output::qinv qinv @endlink
+ */
+#define PKE_RSA_EP_2048 0x6e111dba
+/**< Functionality ID for RSA 2048 Encryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_ep_2048_input::m m
+ * @endlink @link icp_qat_fw_mmp_rsa_ep_2048_input::e e @endlink @link
+ * icp_qat_fw_mmp_rsa_ep_2048_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_ep_2048_output::c c
+ * @endlink
+ */
+#define PKE_RSA_DP1_2048 0x6e111dda
+/**< Functionality ID for RSA 2048 Decryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_dp1_2048_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp1_2048_input::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_dp1_2048_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp1_2048_output::m m
+ * @endlink
+ */
+#define PKE_RSA_DP2_2048 0x59121dfa
+/**< Functionality ID for RSA 2048 Decryption with CRT
+ * @li 6 input parameters : @link icp_qat_fw_mmp_rsa_dp2_2048_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp2_2048_input::p p @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_2048_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_2048_input::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_2048_input::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_2048_input::qinv qinv @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp2_2048_output::m m
+ * @endlink
+ */
+#define PKE_RSA_KP1_3072 0x60191e16
+/**< Functionality ID for RSA 3072 key generation first form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp1_3072_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_3072_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp1_3072_input::e e @endlink
+ * @li 2 output parameters : @link icp_qat_fw_mmp_rsa_kp1_3072_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_3072_output::d d @endlink
+ */
+#define PKE_RSA_KP2_3072 0x68331e45
+/**< Functionality ID for RSA 3072 key generation second form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp2_3072_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_3072_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_3072_input::e e @endlink
+ * @li 5 output parameters : @link icp_qat_fw_mmp_rsa_kp2_3072_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_3072_output::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_3072_output::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_3072_output::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_3072_output::qinv qinv @endlink
+ */
+#define PKE_RSA_EP_3072 0x7d111ea3
+/**< Functionality ID for RSA 3072 Encryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_ep_3072_input::m m
+ * @endlink @link icp_qat_fw_mmp_rsa_ep_3072_input::e e @endlink @link
+ * icp_qat_fw_mmp_rsa_ep_3072_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_ep_3072_output::c c
+ * @endlink
+ */
+#define PKE_RSA_DP1_3072 0x7d111ebe
+/**< Functionality ID for RSA 3072 Decryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_dp1_3072_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp1_3072_input::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_dp1_3072_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp1_3072_output::m m
+ * @endlink
+ */
+#define PKE_RSA_DP2_3072 0x81121ed9
+/**< Functionality ID for RSA 3072 Decryption with CRT
+ * @li 6 input parameters : @link icp_qat_fw_mmp_rsa_dp2_3072_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp2_3072_input::p p @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_3072_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_3072_input::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_3072_input::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_3072_input::qinv qinv @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp2_3072_output::m m
+ * @endlink
+ */
+#define PKE_RSA_KP1_4096 0x7d1f1ef6
+/**< Functionality ID for RSA 4096 key generation first form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp1_4096_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_4096_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp1_4096_input::e e @endlink
+ * @li 2 output parameters : @link icp_qat_fw_mmp_rsa_kp1_4096_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp1_4096_output::d d @endlink
+ */
+#define PKE_RSA_KP2_4096 0x91251f27
+/**< Functionality ID for RSA 4096 key generation second form
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_kp2_4096_input::p p
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_4096_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_4096_input::e e @endlink
+ * @li 5 output parameters : @link icp_qat_fw_mmp_rsa_kp2_4096_output::n n
+ * @endlink @link icp_qat_fw_mmp_rsa_kp2_4096_output::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_4096_output::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_4096_output::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_kp2_4096_output::qinv qinv @endlink
+ */
+#define PKE_RSA_EP_4096 0xa5101f7e
+/**< Functionality ID for RSA 4096 Encryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_ep_4096_input::m m
+ * @endlink @link icp_qat_fw_mmp_rsa_ep_4096_input::e e @endlink @link
+ * icp_qat_fw_mmp_rsa_ep_4096_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_ep_4096_output::c c
+ * @endlink
+ */
+#define PKE_RSA_DP1_4096 0xa5101f98
+/**< Functionality ID for RSA 4096 Decryption
+ * @li 3 input parameters : @link icp_qat_fw_mmp_rsa_dp1_4096_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp1_4096_input::d d @endlink @link
+ * icp_qat_fw_mmp_rsa_dp1_4096_input::n n @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp1_4096_output::m m
+ * @endlink
+ */
+#define PKE_RSA_DP2_4096 0xb1111fb2
+/**< Functionality ID for RSA 4096 Decryption with CRT
+ * @li 6 input parameters : @link icp_qat_fw_mmp_rsa_dp2_4096_input::c c
+ * @endlink @link icp_qat_fw_mmp_rsa_dp2_4096_input::p p @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_4096_input::q q @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_4096_input::dp dp @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_4096_input::dq dq @endlink @link
+ * icp_qat_fw_mmp_rsa_dp2_4096_input::qinv qinv @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_rsa_dp2_4096_output::m m
+ * @endlink
+ */
+#define PKE_GCD_PT_192 0x19201fcd
+/**< Functionality ID for GCD primality test for 192-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_gcd_pt_192_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_GCD_PT_256 0x19201ff7
+/**< Functionality ID for GCD primality test for 256-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_gcd_pt_256_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_GCD_PT_384 0x19202021
+/**< Functionality ID for GCD primality test for 384-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_gcd_pt_384_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_GCD_PT_512 0x1b1b204b
+/**< Functionality ID for GCD primality test for 512-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_gcd_pt_512_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_GCD_PT_768 0x170c2070
+/**< Functionality ID for GCD primality test for 768-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_gcd_pt_768_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_GCD_PT_1024 0x130f2085
+/**< Functionality ID for GCD primality test for 1024-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_gcd_pt_1024_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_GCD_PT_1536 0x1d0c2094
+/**< Functionality ID for GCD primality test for 1536-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_gcd_pt_1536_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_GCD_PT_2048 0x210c20a5
+/**< Functionality ID for GCD primality test for 2048-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_gcd_pt_2048_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_GCD_PT_3072 0x290c20b6
+/**< Functionality ID for GCD primality test for 3072-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_gcd_pt_3072_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_GCD_PT_4096 0x310c20c7
+/**< Functionality ID for GCD primality test for 4096-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_gcd_pt_4096_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_FERMAT_PT_160 0x0e1120d8
+/**< Functionality ID for Fermat primality test for 160-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_fermat_pt_160_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_FERMAT_PT_512 0x121120ee
+/**< Functionality ID for Fermat primality test for 512-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_fermat_pt_512_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_FERMAT_PT_L512 0x19162104
+/**< Functionality ID for Fermat primality test for &lte; 512-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_fermat_pt_l512_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_FERMAT_PT_768 0x19112124
+/**< Functionality ID for Fermat primality test for 768-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_fermat_pt_768_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_FERMAT_PT_1024 0x1f11213a
+/**< Functionality ID for Fermat primality test for 1024-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_fermat_pt_1024_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_FERMAT_PT_1536 0x2b112150
+/**< Functionality ID for Fermat primality test for 1536-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_fermat_pt_1536_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_FERMAT_PT_2048 0x3b112166
+/**< Functionality ID for Fermat primality test for 2048-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_fermat_pt_2048_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_FERMAT_PT_3072 0x3a11217c
+/**< Functionality ID for Fermat primality test for 3072-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_fermat_pt_3072_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_FERMAT_PT_4096 0x4a112192
+/**< Functionality ID for Fermat primality test for 4096-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_fermat_pt_4096_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_MR_PT_160 0x0e1221a8
+/**< Functionality ID for Miller-Rabin primality test for 160-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_mr_pt_160_input::x x
+ * @endlink @link icp_qat_fw_mmp_mr_pt_160_input::m m @endlink
+ * @li no output parameters
+ */
+#define PKE_MR_PT_512 0x111221bf
+/**< Functionality ID for Miller-Rabin primality test for 512-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_mr_pt_512_input::x x
+ * @endlink @link icp_qat_fw_mmp_mr_pt_512_input::m m @endlink
+ * @li no output parameters
+ */
+#define PKE_MR_PT_768 0x1d0d21d6
+/**< Functionality ID for Miller-Rabin primality test for 768-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_mr_pt_768_input::x x
+ * @endlink @link icp_qat_fw_mmp_mr_pt_768_input::m m @endlink
+ * @li no output parameters
+ */
+#define PKE_MR_PT_1024 0x250d21ed
+/**< Functionality ID for Miller-Rabin primality test for 1024-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_mr_pt_1024_input::x x
+ * @endlink @link icp_qat_fw_mmp_mr_pt_1024_input::m m @endlink
+ * @li no output parameters
+ */
+#define PKE_MR_PT_1536 0x350d2204
+/**< Functionality ID for Miller-Rabin primality test for 1536-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_mr_pt_1536_input::x x
+ * @endlink @link icp_qat_fw_mmp_mr_pt_1536_input::m m @endlink
+ * @li no output parameters
+ */
+#define PKE_MR_PT_2048 0x490d221b
+/**< Functionality ID for Miller-Rabin primality test for 2048-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_mr_pt_2048_input::x x
+ * @endlink @link icp_qat_fw_mmp_mr_pt_2048_input::m m @endlink
+ * @li no output parameters
+ */
+#define PKE_MR_PT_3072 0x4d0d2232
+/**< Functionality ID for Miller-Rabin primality test for 3072-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_mr_pt_3072_input::x x
+ * @endlink @link icp_qat_fw_mmp_mr_pt_3072_input::m m @endlink
+ * @li no output parameters
+ */
+#define PKE_MR_PT_4096 0x650d2249
+/**< Functionality ID for Miller-Rabin primality test for 4096-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_mr_pt_4096_input::x x
+ * @endlink @link icp_qat_fw_mmp_mr_pt_4096_input::m m @endlink
+ * @li no output parameters
+ */
+#define PKE_MR_PT_L512 0x18182260
+/**< Functionality ID for Miller-Rabin primality test for 512-bit numbers
+ * @li 2 input parameters : @link icp_qat_fw_mmp_mr_pt_l512_input::x x
+ * @endlink @link icp_qat_fw_mmp_mr_pt_l512_input::m m @endlink
+ * @li no output parameters
+ */
+#define PKE_LUCAS_PT_160 0x0e0c227e
+/**< Functionality ID for Lucas primality test for 160-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_lucas_pt_160_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_LUCAS_PT_512 0x110c228f
+/**< Functionality ID for Lucas primality test for 512-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_lucas_pt_512_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_LUCAS_PT_768 0x130c22a0
+/**< Functionality ID for Lucas primality test for 768-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_lucas_pt_768_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_LUCAS_PT_1024 0x150c22b1
+/**< Functionality ID for Lucas primality test for 1024-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_lucas_pt_1024_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_LUCAS_PT_1536 0x190c22c2
+/**< Functionality ID for Lucas primality test for 1536-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_lucas_pt_1536_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_LUCAS_PT_2048 0x1d0c22d3
+/**< Functionality ID for Lucas primality test for 2048-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_lucas_pt_2048_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_LUCAS_PT_3072 0x250c22e4
+/**< Functionality ID for Lucas primality test for 3072-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_lucas_pt_3072_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_LUCAS_PT_4096 0x661522f5
+/**< Functionality ID for Lucas primality test for 4096-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_lucas_pt_4096_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define PKE_LUCAS_PT_L512 0x1617230a
+/**< Functionality ID for Lucas primality test for L512-bit numbers
+ * @li 1 input parameters : @link icp_qat_fw_mmp_lucas_pt_l512_input::m m
+ * @endlink
+ * @li no output parameters
+ */
+#define MATHS_MODEXP_L512 0x150c2327
+/**< Functionality ID for Modular exponentiation for numbers less than 512-bits
+ * @li 3 input parameters : @link icp_qat_fw_maths_modexp_l512_input::g g
+ * @endlink @link icp_qat_fw_maths_modexp_l512_input::e e @endlink @link
+ * icp_qat_fw_maths_modexp_l512_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modexp_l512_output::r r
+@endlink
+ */
+#define MATHS_MODEXP_L1024 0x2d0c233e
+/**< Functionality ID for Modular exponentiation for numbers less than 1024-bit
+ * @li 3 input parameters : @link icp_qat_fw_maths_modexp_l1024_input::g g
+ * @endlink @link icp_qat_fw_maths_modexp_l1024_input::e e @endlink @link
+ * icp_qat_fw_maths_modexp_l1024_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modexp_l1024_output::r r
+ * @endlink
+ */
+#define MATHS_MODEXP_L1536 0x410c2355
+/**< Functionality ID for Modular exponentiation for numbers less than 1536-bits
+ * @li 3 input parameters : @link icp_qat_fw_maths_modexp_l1536_input::g g
+ * @endlink @link icp_qat_fw_maths_modexp_l1536_input::e e @endlink @link
+ * icp_qat_fw_maths_modexp_l1536_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modexp_l1536_output::r r
+ * @endlink
+ */
+#define MATHS_MODEXP_L2048 0x5e12236c
+/**< Functionality ID for Modular exponentiation for numbers less than 2048-bit
+ * @li 3 input parameters : @link icp_qat_fw_maths_modexp_l2048_input::g g
+ * @endlink @link icp_qat_fw_maths_modexp_l2048_input::e e @endlink @link
+ * icp_qat_fw_maths_modexp_l2048_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modexp_l2048_output::r r
+ * @endlink
+ */
+#define MATHS_MODEXP_L2560 0x60162388
+/**< Functionality ID for Modular exponentiation for numbers less than 2560-bits
+ * @li 3 input parameters : @link icp_qat_fw_maths_modexp_l2560_input::g g
+ * @endlink @link icp_qat_fw_maths_modexp_l2560_input::e e @endlink @link
+ * icp_qat_fw_maths_modexp_l2560_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modexp_l2560_output::r r
+ * @endlink
+ */
+#define MATHS_MODEXP_L3072 0x650c23a9
+/**< Functionality ID for Modular exponentiation for numbers less than 3072-bits
+ * @li 3 input parameters : @link icp_qat_fw_maths_modexp_l3072_input::g g
+ * @endlink @link icp_qat_fw_maths_modexp_l3072_input::e e @endlink @link
+ * icp_qat_fw_maths_modexp_l3072_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modexp_l3072_output::r r
+ * @endlink
+ */
+#define MATHS_MODEXP_L3584 0x801623c0
+/**< Functionality ID for Modular exponentiation for numbers less than 3584-bits
+ * @li 3 input parameters : @link icp_qat_fw_maths_modexp_l3584_input::g g
+ * @endlink @link icp_qat_fw_maths_modexp_l3584_input::e e @endlink @link
+ * icp_qat_fw_maths_modexp_l3584_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modexp_l3584_output::r r
+ * @endlink
+ */
+#define MATHS_MODEXP_L4096 0x850c23e1
+/**< Functionality ID for Modular exponentiation for numbers less than 4096-bit
+ * @li 3 input parameters : @link icp_qat_fw_maths_modexp_l4096_input::g g
+ * @endlink @link icp_qat_fw_maths_modexp_l4096_input::e e @endlink @link
+ * icp_qat_fw_maths_modexp_l4096_input::m m @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modexp_l4096_output::r r
+ * @endlink
+ */
+#define MATHS_MODINV_ODD_L128 0x090623f8
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 128 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_odd_l128_input::a a
+ * @endlink @link icp_qat_fw_maths_modinv_odd_l128_input::b b @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modinv_odd_l128_output::c
+ * c @endlink
+ */
+#define MATHS_MODINV_ODD_L192 0x0a0623fe
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 192 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_odd_l192_input::a a
+ * @endlink @link icp_qat_fw_maths_modinv_odd_l192_input::b b @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modinv_odd_l192_output::c
+ * c @endlink
+ */
+#define MATHS_MODINV_ODD_L256 0x0a062404
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 256 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_odd_l256_input::a a
+ * @endlink @link icp_qat_fw_maths_modinv_odd_l256_input::b b @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modinv_odd_l256_output::c
+ * c @endlink
+ */
+#define MATHS_MODINV_ODD_L384 0x0b06240a
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 384 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_odd_l384_input::a a
+ * @endlink @link icp_qat_fw_maths_modinv_odd_l384_input::b b @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modinv_odd_l384_output::c
+ * c @endlink
+ */
+#define MATHS_MODINV_ODD_L512 0x0c062410
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 512 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_odd_l512_input::a a
+ * @endlink @link icp_qat_fw_maths_modinv_odd_l512_input::b b @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modinv_odd_l512_output::c
+ * c @endlink
+ */
+#define MATHS_MODINV_ODD_L768 0x0e062416
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 768 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_odd_l768_input::a a
+ * @endlink @link icp_qat_fw_maths_modinv_odd_l768_input::b b @endlink
+ * @li 1 output parameters : @link icp_qat_fw_maths_modinv_odd_l768_output::c
+ * c @endlink
+ */
+#define MATHS_MODINV_ODD_L1024 0x1006241c
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 1024 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_odd_l1024_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_odd_l1024_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_odd_l1024_output::c c @endlink
+ */
+#define MATHS_MODINV_ODD_L1536 0x18062422
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 1536 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_odd_l1536_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_odd_l1536_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_odd_l1536_output::c c @endlink
+ */
+#define MATHS_MODINV_ODD_L2048 0x20062428
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 2048 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_odd_l2048_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_odd_l2048_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_odd_l2048_output::c c @endlink
+ */
+#define MATHS_MODINV_ODD_L3072 0x3006242e
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 3072 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_odd_l3072_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_odd_l3072_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_odd_l3072_output::c c @endlink
+ */
+#define MATHS_MODINV_ODD_L4096 0x40062434
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 4096 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_odd_l4096_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_odd_l4096_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_odd_l4096_output::c c @endlink
+ */
+#define MATHS_MODINV_EVEN_L128 0x0906243a
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 128 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_even_l128_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_even_l128_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_even_l128_output::c c @endlink
+ */
+#define MATHS_MODINV_EVEN_L192 0x0a062440
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 192 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_even_l192_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_even_l192_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_even_l192_output::c c @endlink
+ */
+#define MATHS_MODINV_EVEN_L256 0x0a062446
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 256 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_even_l256_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_even_l256_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_even_l256_output::c c @endlink
+ */
+#define MATHS_MODINV_EVEN_L384 0x0e0b244c
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 384 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_even_l384_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_even_l384_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_even_l384_output::c c @endlink
+ */
+#define MATHS_MODINV_EVEN_L512 0x110b2457
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 512 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_even_l512_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_even_l512_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_even_l512_output::c c @endlink
+ */
+#define MATHS_MODINV_EVEN_L768 0x170b2462
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 768 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_even_l768_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_even_l768_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_even_l768_output::c c @endlink
+ */
+#define MATHS_MODINV_EVEN_L1024 0x1d0b246d
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 1024 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_even_l1024_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_even_l1024_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_even_l1024_output::c c @endlink
+ */
+#define MATHS_MODINV_EVEN_L1536 0x290b2478
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 1536 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_even_l1536_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_even_l1536_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_even_l1536_output::c c @endlink
+ */
+#define MATHS_MODINV_EVEN_L2048 0x350b2483
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 2048 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_even_l2048_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_even_l2048_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_even_l2048_output::c c @endlink
+ */
+#define MATHS_MODINV_EVEN_L3072 0x4d0b248e
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 3072 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_even_l3072_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_even_l3072_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_even_l3072_output::c c @endlink
+ */
+#define MATHS_MODINV_EVEN_L4096 0x650b2499
+/**< Functionality ID for Modular multiplicative inverse for numbers less than
+ * 4096 bits
+ * @li 2 input parameters : @link icp_qat_fw_maths_modinv_even_l4096_input::a
+ * a @endlink @link icp_qat_fw_maths_modinv_even_l4096_input::b b @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_maths_modinv_even_l4096_output::c c @endlink
+ */
+#define PKE_DSA_GEN_P_1024_160 0x381824a4
+/**< Functionality ID for DSA parameter generation P
+ * @li 2 input parameters : @link icp_qat_fw_mmp_dsa_gen_p_1024_160_input::x
+ * x @endlink @link icp_qat_fw_mmp_dsa_gen_p_1024_160_input::q q @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_dsa_gen_p_1024_160_output::p p @endlink
+ */
+#define PKE_DSA_GEN_G_1024 0x261424d4
+/**< Functionality ID for DSA key generation G
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dsa_gen_g_1024_input::p p
+ * @endlink @link icp_qat_fw_mmp_dsa_gen_g_1024_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_gen_g_1024_input::h h @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dsa_gen_g_1024_output::g g
+ * @endlink
+ */
+#define PKE_DSA_GEN_Y_1024 0x291224ed
+/**< Functionality ID for DSA key generation Y
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dsa_gen_y_1024_input::p p
+ * @endlink @link icp_qat_fw_mmp_dsa_gen_y_1024_input::g g @endlink @link
+ * icp_qat_fw_mmp_dsa_gen_y_1024_input::x x @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dsa_gen_y_1024_output::y y
+ * @endlink
+ */
+#define PKE_DSA_SIGN_R_1024_160 0x2c1c2504
+/**< Functionality ID for DSA Sign R
+ * @li 4 input parameters : @link icp_qat_fw_mmp_dsa_sign_r_1024_160_input::k
+ * k @endlink @link icp_qat_fw_mmp_dsa_sign_r_1024_160_input::p p @endlink
+ * @link icp_qat_fw_mmp_dsa_sign_r_1024_160_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_1024_160_input::g g @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_1024_160_output::r r @endlink
+ */
+#define PKE_DSA_SIGN_S_160 0x12142526
+/**< Functionality ID for DSA Sign S
+ * @li 5 input parameters : @link icp_qat_fw_mmp_dsa_sign_s_160_input::m m
+ * @endlink @link icp_qat_fw_mmp_dsa_sign_s_160_input::k k @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_s_160_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_s_160_input::r r @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_s_160_input::x x @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dsa_sign_s_160_output::s s
+ * @endlink
+ */
+#define PKE_DSA_SIGN_R_S_1024_160 0x301e2540
+/**< Functionality ID for DSA Sign R S
+ * @li 6 input parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_1024_160_input::m m @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_1024_160_input::k k @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_1024_160_input::p p @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_1024_160_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_1024_160_input::g g @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_1024_160_input::x x @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_1024_160_output::r r @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_1024_160_output::s s @endlink
+ */
+#define PKE_DSA_VERIFY_1024_160 0x323a2570
+/**< Functionality ID for DSA Verify
+ * @li 7 input parameters : @link icp_qat_fw_mmp_dsa_verify_1024_160_input::r
+ * r @endlink @link icp_qat_fw_mmp_dsa_verify_1024_160_input::s s @endlink
+ * @link icp_qat_fw_mmp_dsa_verify_1024_160_input::m m @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_1024_160_input::p p @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_1024_160_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_1024_160_input::g g @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_1024_160_input::y y @endlink
+ * @li no output parameters
+ */
+#define PKE_DSA_GEN_P_2048_224 0x341d25be
+/**< Functionality ID for DSA parameter generation P
+ * @li 2 input parameters : @link icp_qat_fw_mmp_dsa_gen_p_2048_224_input::x
+ * x @endlink @link icp_qat_fw_mmp_dsa_gen_p_2048_224_input::q q @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_dsa_gen_p_2048_224_output::p p @endlink
+ */
+#define PKE_DSA_GEN_Y_2048 0x4d1225ea
+/**< Functionality ID for DSA key generation Y
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dsa_gen_y_2048_input::p p
+ * @endlink @link icp_qat_fw_mmp_dsa_gen_y_2048_input::g g @endlink @link
+ * icp_qat_fw_mmp_dsa_gen_y_2048_input::x x @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dsa_gen_y_2048_output::y y
+ * @endlink
+ */
+#define PKE_DSA_SIGN_R_2048_224 0x511c2601
+/**< Functionality ID for DSA Sign R
+ * @li 4 input parameters : @link icp_qat_fw_mmp_dsa_sign_r_2048_224_input::k
+ * k @endlink @link icp_qat_fw_mmp_dsa_sign_r_2048_224_input::p p @endlink
+ * @link icp_qat_fw_mmp_dsa_sign_r_2048_224_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_2048_224_input::g g @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_2048_224_output::r r @endlink
+ */
+#define PKE_DSA_SIGN_S_224 0x15142623
+/**< Functionality ID for DSA Sign S
+ * @li 5 input parameters : @link icp_qat_fw_mmp_dsa_sign_s_224_input::m m
+ * @endlink @link icp_qat_fw_mmp_dsa_sign_s_224_input::k k @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_s_224_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_s_224_input::r r @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_s_224_input::x x @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dsa_sign_s_224_output::s s
+ * @endlink
+ */
+#define PKE_DSA_SIGN_R_S_2048_224 0x571e263d
+/**< Functionality ID for DSA Sign R S
+ * @li 6 input parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_224_input::m m @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_224_input::k k @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_224_input::p p @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_224_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_224_input::g g @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_224_input::x x @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_224_output::r r @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_224_output::s s @endlink
+ */
+#define PKE_DSA_VERIFY_2048_224 0x6930266d
+/**< Functionality ID for DSA Verify
+ * @li 7 input parameters : @link icp_qat_fw_mmp_dsa_verify_2048_224_input::r
+ * r @endlink @link icp_qat_fw_mmp_dsa_verify_2048_224_input::s s @endlink
+ * @link icp_qat_fw_mmp_dsa_verify_2048_224_input::m m @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_2048_224_input::p p @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_2048_224_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_2048_224_input::g g @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_2048_224_input::y y @endlink
+ * @li no output parameters
+ */
+#define PKE_DSA_GEN_P_2048_256 0x431126b7
+/**< Functionality ID for DSA parameter generation P
+ * @li 2 input parameters : @link icp_qat_fw_mmp_dsa_gen_p_2048_256_input::x
+ * x @endlink @link icp_qat_fw_mmp_dsa_gen_p_2048_256_input::q q @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_dsa_gen_p_2048_256_output::p p @endlink
+ */
+#define PKE_DSA_GEN_G_2048 0x4b1426ed
+/**< Functionality ID for DSA key generation G
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dsa_gen_g_2048_input::p p
+ * @endlink @link icp_qat_fw_mmp_dsa_gen_g_2048_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_gen_g_2048_input::h h @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dsa_gen_g_2048_output::g g
+ * @endlink
+ */
+#define PKE_DSA_SIGN_R_2048_256 0x5b182706
+/**< Functionality ID for DSA Sign R
+ * @li 4 input parameters : @link icp_qat_fw_mmp_dsa_sign_r_2048_256_input::k
+ * k @endlink @link icp_qat_fw_mmp_dsa_sign_r_2048_256_input::p p @endlink
+ * @link icp_qat_fw_mmp_dsa_sign_r_2048_256_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_2048_256_input::g g @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_2048_256_output::r r @endlink
+ */
+#define PKE_DSA_SIGN_S_256 0x15142733
+/**< Functionality ID for DSA Sign S
+ * @li 5 input parameters : @link icp_qat_fw_mmp_dsa_sign_s_256_input::m m
+ * @endlink @link icp_qat_fw_mmp_dsa_sign_s_256_input::k k @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_s_256_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_s_256_input::r r @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_s_256_input::x x @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dsa_sign_s_256_output::s s
+ * @endlink
+ */
+#define PKE_DSA_SIGN_R_S_2048_256 0x5a2a274d
+/**< Functionality ID for DSA Sign R S
+ * @li 6 input parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_256_input::m m @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_256_input::k k @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_256_input::p p @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_256_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_256_input::g g @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_256_input::x x @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_256_output::r r @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_2048_256_output::s s @endlink
+ */
+#define PKE_DSA_VERIFY_2048_256 0x723a2789
+/**< Functionality ID for DSA Verify
+ * @li 7 input parameters : @link icp_qat_fw_mmp_dsa_verify_2048_256_input::r
+ * r @endlink @link icp_qat_fw_mmp_dsa_verify_2048_256_input::s s @endlink
+ * @link icp_qat_fw_mmp_dsa_verify_2048_256_input::m m @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_2048_256_input::p p @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_2048_256_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_2048_256_input::g g @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_2048_256_input::y y @endlink
+ * @li no output parameters
+ */
+#define PKE_DSA_GEN_P_3072_256 0x4b1127e0
+/**< Functionality ID for DSA parameter generation P
+ * @li 2 input parameters : @link icp_qat_fw_mmp_dsa_gen_p_3072_256_input::x
+ * x @endlink @link icp_qat_fw_mmp_dsa_gen_p_3072_256_input::q q @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_dsa_gen_p_3072_256_output::p p @endlink
+ */
+#define PKE_DSA_GEN_G_3072 0x4f142816
+/**< Functionality ID for DSA key generation G
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dsa_gen_g_3072_input::p p
+ * @endlink @link icp_qat_fw_mmp_dsa_gen_g_3072_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_gen_g_3072_input::h h @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dsa_gen_g_3072_output::g g
+ * @endlink
+ */
+#define PKE_DSA_GEN_Y_3072 0x5112282f
+/**< Functionality ID for DSA key generation Y
+ * @li 3 input parameters : @link icp_qat_fw_mmp_dsa_gen_y_3072_input::p p
+ * @endlink @link icp_qat_fw_mmp_dsa_gen_y_3072_input::g g @endlink @link
+ * icp_qat_fw_mmp_dsa_gen_y_3072_input::x x @endlink
+ * @li 1 output parameters : @link icp_qat_fw_mmp_dsa_gen_y_3072_output::y y
+ * @endlink
+ */
+#define PKE_DSA_SIGN_R_3072_256 0x59282846
+/**< Functionality ID for DSA Sign R
+ * @li 4 input parameters : @link icp_qat_fw_mmp_dsa_sign_r_3072_256_input::k
+ * k @endlink @link icp_qat_fw_mmp_dsa_sign_r_3072_256_input::p p @endlink
+ * @link icp_qat_fw_mmp_dsa_sign_r_3072_256_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_3072_256_input::g g @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_3072_256_output::r r @endlink
+ */
+#define PKE_DSA_SIGN_R_S_3072_256 0x61292874
+/**< Functionality ID for DSA Sign R S
+ * @li 6 input parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_3072_256_input::m m @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_3072_256_input::k k @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_3072_256_input::p p @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_3072_256_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_3072_256_input::g g @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_3072_256_input::x x @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_3072_256_output::r r @endlink @link
+ * icp_qat_fw_mmp_dsa_sign_r_s_3072_256_output::s s @endlink
+ */
+#define PKE_DSA_VERIFY_3072_256 0x7f4328ae
+/**< Functionality ID for DSA Verify
+ * @li 7 input parameters : @link icp_qat_fw_mmp_dsa_verify_3072_256_input::r
+ * r @endlink @link icp_qat_fw_mmp_dsa_verify_3072_256_input::s s @endlink
+ * @link  icp_qat_fw_mmp_dsa_verify_3072_256_input::m m @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_3072_256_input::p p @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_3072_256_input::q q @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_3072_256_input::g g @endlink @link
+ * icp_qat_fw_mmp_dsa_verify_3072_256_input::y y @endlink
+ * @li no output parameters
+ */
+#define PKE_ECDSA_SIGN_RS_GF2_L256 0x46512907
+/**< Functionality ID for ECDSA Sign RS for curves B/K-163 and B/K-233
+ * @li 1 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gf2_l256_input::in in @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gf2_l256_output::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gf2_l256_output::s s @endlink
+ */
+#define PKE_ECDSA_SIGN_R_GF2_L256 0x323a298f
+/**< Functionality ID for ECDSA Sign R for curves B/K-163 and B/K-233
+ * @li 7 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l256_input::xg xg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l256_input::yg yg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l256_input::n n @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l256_input::q q @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l256_input::a a @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l256_input::b b @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l256_input::k k @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l256_output::r r @endlink
+ */
+#define PKE_ECDSA_SIGN_S_GF2_L256 0x2b2229e6
+/**< Functionality ID for ECDSA Sign S for curves with n &lt; 2^256
+ * @li 5 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l256_input::e e @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l256_input::d d @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l256_input::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l256_input::k k @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l256_input::n n @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l256_output::s s @endlink
+ */
+#define PKE_ECDSA_VERIFY_GF2_L256 0x337e2a27
+/**< Functionality ID for ECDSA Verify for curves B/K-163 and B/K-233
+ * @li 1 input parameters : @link
+ *icp_qat_fw_mmp_ecdsa_verify_gf2_l256_input::in in @endlink
+ * @li no output parameters
+ */
+#define PKE_ECDSA_SIGN_RS_GF2_L512 0x5e5f2ad7
+/**< Functionality ID for ECDSA Sign RS
+ * @li 1 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gf2_l512_input::in in @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gf2_l512_output::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gf2_l512_output::s s @endlink
+ */
+#define PKE_ECDSA_SIGN_R_GF2_L512 0x84312b6a
+/**< Functionality ID for ECDSA GF2 Sign R
+ * @li 7 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l512_input::xg xg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l512_input::yg yg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l512_input::n n @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l512_input::q q @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l512_input::a a @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l512_input::b b @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l512_input::k k @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_l512_output::r r @endlink
+ */
+#define PKE_ECDSA_SIGN_S_GF2_L512 0x26182bbe
+/**< Functionality ID for ECDSA GF2 Sign S
+ * @li 5 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l512_input::e e @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l512_input::d d @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l512_input::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l512_input::k k @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l512_input::n n @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_l512_output::s s @endlink
+ */
+#define PKE_ECDSA_VERIFY_GF2_L512 0x58892bea
+/**< Functionality ID for ECDSA GF2 Verify
+ * @li 1 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_verify_gf2_l512_input::in in @endlink
+ * @li no output parameters
+ */
+#define PKE_ECDSA_SIGN_RS_GF2_571 0x554a2c93
+/**< Functionality ID for ECDSA GF2 Sign RS for curves B-571/K-571
+ * @li 1 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gf2_571_input::in in @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gf2_571_output::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gf2_571_output::s s @endlink
+ */
+#define PKE_ECDSA_SIGN_S_GF2_571 0x52332d09
+/**< Functionality ID for ECDSA GF2 Sign S for curves with deg(q) &lt; 576
+ * @li 5 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_571_input::e e @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_571_input::d d @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_571_input::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_571_input::k k @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_571_input::n n @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gf2_571_output::s s @endlink
+ */
+#define PKE_ECDSA_SIGN_R_GF2_571 0x731a2d51
+/**< Functionality ID for ECDSA GF2 Sign R for degree 571
+ * @li 7 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_571_input::xg xg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_571_input::yg yg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_571_input::n n @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_571_input::q q @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_571_input::a a @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_571_input::b b @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_571_input::k k @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gf2_571_output::r r @endlink
+ */
+#define PKE_ECDSA_VERIFY_GF2_571 0x4f6c2d91
+/**< Functionality ID for ECDSA GF2 Verify for degree 571
+ * @li 1 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_verify_gf2_571_input::in in @endlink
+ * @li no output parameters
+ */
+#define MATHS_POINT_MULTIPLICATION_GF2_L256 0x3b242e38
+/**< Functionality ID for MATHS GF2 Point Multiplication
+ * @li 7 input parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l256_input::k k @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l256_input::xg xg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l256_input::yg yg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l256_input::a a @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l256_input::b b @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l256_input::q q @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l256_input::h h @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l256_output::xk xk @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l256_output::yk yk @endlink
+ */
+#define MATHS_POINT_VERIFY_GF2_L256 0x231a2e7c
+/**< Functionality ID for MATHS GF2 Point Verification
+ * @li 5 input parameters : @link
+ * icp_qat_fw_maths_point_verify_gf2_l256_input::xq xq @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_l256_input::yq yq @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_l256_input::q q @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_l256_input::a a @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_l256_input::b b @endlink
+ * @li no output parameters
+ */
+#define MATHS_POINT_MULTIPLICATION_GF2_L512 0x722c2e96
+/**< Functionality ID for MATHS GF2 Point Multiplication
+ * @li 7 input parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l512_input::k k @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l512_input::xg xg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l512_input::yg yg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l512_input::a a @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l512_input::b b @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l512_input::q q @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l512_input::h h @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l512_output::xk xk @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_l512_output::yk yk @endlink
+ */
+#define MATHS_POINT_VERIFY_GF2_L512 0x25132ee2
+/**< Functionality ID for MATHS GF2 Point Verification
+ * @li 5 input parameters : @link
+ * icp_qat_fw_maths_point_verify_gf2_l512_input::xq xq @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_l512_input::yq yq @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_l512_input::q q @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_l512_input::a a @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_l512_input::b b @endlink
+ * @li no output parameters
+ */
+#define MATHS_POINT_MULTIPLICATION_GF2_571 0x44152ef5
+/**< Functionality ID for ECC GF2 Point Multiplication for curves B-571/K-571
+ * @li 7 input parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gf2_571_input::k k @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_571_input::xg xg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_571_input::yg yg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_571_input::a a @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_571_input::b b @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_571_input::q q @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_571_input::h h @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gf2_571_output::xk xk @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gf2_571_output::yk yk @endlink
+ */
+#define MATHS_POINT_VERIFY_GF2_571 0x12072f1b
+/**< Functionality ID for ECC GF2 Point Verification for degree 571
+ * @li 5 input parameters : @link
+ * icp_qat_fw_maths_point_verify_gf2_571_input::xq xq @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_571_input::yq yq @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_571_input::q q @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_571_input::a a @endlink @link
+ * icp_qat_fw_maths_point_verify_gf2_571_input::b b @endlink
+ * @li no output parameters
+ */
+#define PKE_KPT_ECDSA_SIGN_RS_GF2_L256 0x515217d9
+/**< Functionality ID for KPT ECDSA Sign RS for curves B/K-163 and B/K-233
+ * @li 3 input parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_l256_input::in in @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_l256_input::d d @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_l256_input::c c @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_l256_output::r r @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_l256_output::s s @endlink
+ */
+#define PKE_KPT_ECDSA_SIGN_RS_GF2_L512 0x4d811987
+/**< Functionality ID for KPT ECDSA Sign RS
+ * @li 3 input parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_l512_input::in in @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_l512_input::d d @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_l512_input::c c @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_l512_output::r r @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_l512_output::s s @endlink
+ */
+#define PKE_KPT_ECDSA_SIGN_RS_GF2_571 0x45731898
+/**< Functionality ID for KPT ECDSA GF2 Sign RS for curves B-571/K-571
+ * @li 3 input parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_571_input::in in @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_571_input::d d @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_571_input::c c @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_571_output::r r @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gf2_571_output::s s @endlink
+ */
+#define PKE_ECDSA_SIGN_R_GFP_L256 0x431b2f22
+/**< Functionality ID for ECDSA GFP Sign R
+ * @li 7 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l256_input::xg xg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l256_input::yg yg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l256_input::n n @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l256_input::q q @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l256_input::a a @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l256_input::b b @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l256_input::k k @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l256_output::r r @endlink
+ */
+#define PKE_ECDSA_SIGN_S_GFP_L256 0x2b252f6d
+/**< Functionality ID for ECDSA GFP Sign S
+ * @li 5 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l256_input::e e @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l256_input::d d @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l256_input::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l256_input::k k @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l256_input::n n @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l256_output::s s @endlink
+ */
+#define PKE_ECDSA_SIGN_RS_GFP_L256 0x6a3c2fa6
+/**< Functionality ID for ECDSA GFP Sign RS
+ * @li 1 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gfp_l256_input::in in @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gfp_l256_output::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gfp_l256_output::s s @endlink
+ */
+#define PKE_ECDSA_VERIFY_GFP_L256 0x325b3023
+/**< Functionality ID for ECDSA GFP Verify
+ * @li 1 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_verify_gfp_l256_input::in in @endlink
+ * @li no output parameters
+ */
+#define PKE_ECDSA_SIGN_R_GFP_L512 0x4e2530b3
+/**< Functionality ID for ECDSA GFP Sign R
+ * @li 7 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l512_input::xg xg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l512_input::yg yg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l512_input::n n @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l512_input::q q @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l512_input::a a @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l512_input::b b @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l512_input::k k @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_l512_output::r r @endlink
+ */
+#define PKE_ECDSA_SIGN_S_GFP_L512 0x251830fa
+/**< Functionality ID for ECDSA GFP Sign S
+ * @li 5 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l512_input::e e @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l512_input::d d @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l512_input::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l512_input::k k @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l512_input::n n @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_l512_output::s s @endlink
+ */
+#define PKE_ECDSA_SIGN_RS_GFP_L512 0x5a2b3127
+/**< Functionality ID for ECDSA GFP Sign RS
+ * @li 1 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gfp_l512_input::in in @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gfp_l512_output::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gfp_l512_output::s s @endlink
+ */
+#define PKE_ECDSA_VERIFY_GFP_L512 0x3553318a
+/**< Functionality ID for ECDSA GFP Verify
+ * @li 1 input parameters : @link
+icp_qat_fw_mmp_ecdsa_verify_gfp_l512_input::in in @endlink
+ * @li no output parameters
+ */
+#define PKE_ECDSA_SIGN_R_GFP_521 0x772c31fe
+/**< Functionality ID for ECDSA GFP Sign R
+ * @li 7 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_521_input::xg xg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_521_input::yg yg @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_521_input::n n @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_521_input::q q @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_521_input::a a @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_521_input::b b @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_521_input::k k @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_r_gfp_521_output::r r @endlink
+ */
+#define PKE_ECDSA_SIGN_S_GFP_521 0x52343251
+/**< Functionality ID for ECDSA GFP Sign S
+ * @li 5 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_521_input::e e @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_521_input::d d @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_521_input::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_521_input::k k @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_521_input::n n @endlink
+ * @li 1 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_s_gfp_521_output::s s @endlink
+ */
+#define PKE_ECDSA_SIGN_RS_GFP_521 0x494a329b
+/**< Functionality ID for ECDSA GFP Sign RS
+ * @li 1 input parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gfp_521_input::in in @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gfp_521_output::r r @endlink @link
+ * icp_qat_fw_mmp_ecdsa_sign_rs_gfp_521_output::s s @endlink
+ */
+#define PKE_ECDSA_VERIFY_GFP_521 0x554c331f
+/**< Functionality ID for ECDSA GFP Verify
+ * @li 1 input parameters : @link
+icp_qat_fw_mmp_ecdsa_verify_gfp_521_input::in in @endlink
+ * @li no output parameters
+ */
+#define MATHS_POINT_MULTIPLICATION_GFP_L256 0x432033a6
+/**< Functionality ID for ECC GFP Point Multiplication
+ * @li 7 input parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l256_input::k k @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l256_input::xg xg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l256_input::yg yg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l256_input::a a @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l256_input::b b @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l256_input::q q @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l256_input::h h @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l256_output::xk xk @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l256_output::yk yk @endlink
+ */
+#define MATHS_POINT_VERIFY_GFP_L256 0x1f0c33fc
+/**< Functionality ID for ECC GFP Partial Point Verification
+ * @li 5 input parameters : @link
+ * icp_qat_fw_maths_point_verify_gfp_l256_input::xq xq @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_l256_input::yq yq @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_l256_input::q q @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_l256_input::a a @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_l256_input::b b @endlink
+ * @li no output parameters
+ */
+#define MATHS_POINT_MULTIPLICATION_GFP_L512 0x41253419
+/**< Functionality ID for ECC GFP Point Multiplication
+ * @li 7 input parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l512_input::k k @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l512_input::xg xg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l512_input::yg yg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l512_input::a a @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l512_input::b b @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l512_input::q q @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l512_input::h h @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l512_output::xk xk @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_l512_output::yk yk @endlink
+ */
+#define MATHS_POINT_VERIFY_GFP_L512 0x2612345c
+/**< Functionality ID for ECC GFP Partial Point
+ * @li 5 input parameters : @link
+ * icp_qat_fw_maths_point_verify_gfp_l512_input::xq xq @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_l512_input::yq yq @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_l512_input::q q @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_l512_input::a a @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_l512_input::b b @endlink
+ * @li no output parameters
+ */
+#define MATHS_POINT_MULTIPLICATION_GFP_521 0x5511346e
+/**< Functionality ID for ECC GFP Point Multiplication
+ * @li 7 input parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gfp_521_input::k k @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_521_input::xg xg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_521_input::yg yg @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_521_input::a a @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_521_input::b b @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_521_input::q q @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_521_input::h h @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_maths_point_multiplication_gfp_521_output::xk xk @endlink @link
+ * icp_qat_fw_maths_point_multiplication_gfp_521_output::yk yk @endlink
+ */
+#define MATHS_POINT_VERIFY_GFP_521 0x0e0734be
+/**< Functionality ID for ECC GFP Partial Point Verification
+ * @li 5 input parameters : @link
+ * icp_qat_fw_maths_point_verify_gfp_521_input::xq xq @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_521_input::yq yq @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_521_input::q q @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_521_input::a a @endlink @link
+ * icp_qat_fw_maths_point_verify_gfp_521_input::b b @endlink
+ * @li no output parameters
+ */
+#define PKE_KPT_ECDSA_SIGN_RS_GFP_L256 0x1b6b182c
+/**< Functionality ID for KPT ECDSA GFP Sign RS
+ * @li 3 input parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_l256_input::in in @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_l256_input::d d @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_l256_input::c c @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_l256_output::r r @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_l256_output::s s @endlink
+ */
+#define PKE_KPT_ECDSA_SIGN_RS_GFP_L512 0x7439179f
+/**< Functionality ID for KPT ECDSA GFP Sign RS
+ * @li 3 input parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_l512_input::in in @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_l512_input::d d @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_l512_input::c c @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_l512_output::r r @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_l512_output::s s @endlink
+ */
+#define PKE_KPT_ECDSA_SIGN_RS_GFP_521 0x3b7a190c
+/**< Functionality ID for KPT ECDSA GFP Sign RS
+ * @li 3 input parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_521_input::in in @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_521_input::d d @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_521_input::c c @endlink
+ * @li 2 output parameters : @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_521_output::r r @endlink @link
+ * icp_qat_fw_mmp_kpt_ecdsa_sign_rs_gfp_521_output::s s @endlink
+ */
+
+#define PKE_LIVENESS 0x00000001
+/**< Functionality ID for PKE_LIVENESS
+ * @li 0 input parameter(s)
+ * @li 1 output parameter(s) (8 qwords)
+ */
+#define PKE_INTERFACE_SIGNATURE 0x972ded54
+/**< Encoded signature of the interface specifications
+ */
+
+#define PKE_INVALID_FUNC_ID 0xffffffff
+
+#endif /* __ICP_QAT_FW_MMP_IDS__ */
diff --git a/src/seastar/dpdk/drivers/common/qat/qat_adf/icp_qat_fw_pke.h b/src/seastar/dpdk/drivers/common/qat/qat_adf/icp_qat_fw_pke.h
new file mode 100644
index 000000000..b2cdf0a0a
--- /dev/null
+++ b/src/seastar/dpdk/drivers/common/qat/qat_adf/icp_qat_fw_pke.h
@@ -0,0 +1,426 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Intel Corporation
+ */
+
+/**
+ * @file icp_qat_fw_pke.h
+ * @defgroup icp_qat_fw_pke ICP QAT FW PKE Processing Definitions
+ * @ingroup icp_qat_fw
+ * Revision: 0.1
+ * @brief
+ *      This file documents the external interfaces that the QAT FW running
+ *      on the QAT Acceleration Engine provides to clients wanting to
+ *      accelerate crypto asymmetric applications
+ */
+
+#ifndef _ICP_QAT_FW_PKE_H_
+#define _ICP_QAT_FW_PKE_H_
+
+/*
+ * Keep all dpdk-specific changes in this section
+ */
+
+#include <stdint.h>
+
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+typedef uint64_t u64;
+
+/* End of DPDK-specific section
+ * Don't modify below this.
+ */
+
+/*
+ ****************************************************************************
+ * Include local header files
+ ****************************************************************************
+ */
+#include "icp_qat_fw.h"
+
+/**
+ *****************************************************************************
+ *
+ * @ingroup icp_qat_fw_pke
+ *
+ * @brief
+ *      PKE response status field structure contained
+ *      within LW1, comprising the common error codes and
+ *      the response flags.
+ *
+ *****************************************************************************/
+struct icp_qat_fw_pke_resp_status {
+	u8 comn_err_code;
+	/**< 8 bit common error code */
+
+	u8 pke_resp_flags;
+	/**< 8-bit PKE response flags  */
+};
+
+/**
+ *****************************************************************************
+ * @ingroup icp_qat_fw_pke
+ *      Definition of the QAT FW PKE request header pars field.
+ *
+ * @description
+ *      PKE request message header pars structure
+ *
+ *****************************************************************************/
+struct icp_qat_fw_req_hdr_pke_cd_pars {
+	/**< LWs 2-3 */
+	u64 content_desc_addr;
+	/**< Content descriptor pointer */
+
+	/**< LW 4 */
+	u32 content_desc_resrvd;
+	/**< Content descriptor reserved field */
+
+	/**< LW 5 */
+	u32 func_id;
+	/**< MMP functionality Id */
+};
+
+/**
+ *****************************************************************************
+ * @ingroup icp_qat_fw_pke
+ *      Definition of the QAT FW PKE request header mid section.
+ *
+ * @description
+ *      PKE request message header middle structure
+ *
+ *****************************************************************************/
+struct icp_qat_fw_req_pke_mid {
+	/**< LWs 6-11 */
+	u64 opaque;
+	/**< Opaque data passed unmodified from the request to response messages
+	 * by firmware (fw)
+	 */
+
+	u64 src_data_addr;
+	/**< Generic definition of the source data supplied to the QAT AE. The
+	 * common flags are used to further describe the attributes of this
+	 * field
+	 */
+
+	u64 dest_data_addr;
+	/**< Generic definition of the destination data supplied to the QAT AE.
+	 * The common flags are used to further describe the attributes of this
+	 * field
+	 */
+};
+
+/**
+ *****************************************************************************
+ * @ingroup icp_qat_fw_pke
+ *      Definition of the QAT FW PKE request header.
+ *
+ * @description
+ *      PKE request message header structure
+ *
+ *****************************************************************************/
+struct icp_qat_fw_req_pke_hdr {
+	/**< LW0 */
+	u8 resrvd1;
+	/**< reserved field */
+
+	u8 resrvd2;
+	/**< reserved field */
+
+	u8 service_type;
+	/**< Service type */
+
+	u8 hdr_flags;
+	/**< This represents a flags field for the Service Request.
+	 * The most significant bit is the 'valid' flag and the only
+	 * one used. All remaining bit positions are unused and
+	 * are therefore reserved and need to be set to 0.
+	 */
+
+	/**< LW1 */
+	u16 comn_req_flags;
+	/**< Common Request flags must indicate flat buffer
+	 * Common Request flags - PKE slice flags no longer used - slice
+	 * allocated to a threadstrand.
+	 */
+
+	u8 kpt_mask;
+	/** < KPT input parameters array mask, indicate which node in array is
+	 *encrypted
+	 */
+
+	u8 kpt_rn_mask;
+	/**< KPT random node(RN) mask - indicate which node is RN that QAT
+	 * should generate itself.
+	 */
+
+	/**< LWs 2-5 */
+	struct icp_qat_fw_req_hdr_pke_cd_pars cd_pars;
+	/**< PKE request message header pars structure */
+};
+
+/**
+ ***************************************************************************
+ *
+ * @ingroup icp_qat_fw_pke
+ *
+ * @brief
+ *      PKE request message structure (64 bytes)
+ *
+ *****************************************************************************/
+struct icp_qat_fw_pke_request {
+	/**< LWs 0-5 */
+	struct icp_qat_fw_req_pke_hdr pke_hdr;
+	/**< Request header for PKE - CD Header/Param size  must be zero */
+
+	/**< LWs 6-11 */
+	struct icp_qat_fw_req_pke_mid pke_mid;
+	/**< Request middle section for PKE */
+
+	/**< LW 12 */
+	u8 output_param_count;
+	/**< Number of output large integers for request */
+
+	u8 input_param_count;
+	/**< Number of input large integers for request */
+
+	u16 resrvd1;
+	/** Reserved **/
+
+	/**< LW 13 */
+	u32 resrvd2;
+	/**< Reserved */
+
+	/**< LWs 14-15 */
+	u64 next_req_adr;
+	/** < PKE - next request address */
+};
+
+/**
+ *****************************************************************************
+ *
+ * @ingroup icp_qat_fw_pke
+ *
+ * @brief
+ *      PKE response message header structure
+ *
+ *****************************************************************************/
+struct icp_qat_fw_resp_pke_hdr {
+	/**< LW0 */
+	u8 resrvd1;
+	/**< Reserved */
+
+	u8 resrvd2;
+	/**< Reserved */
+
+	u8 response_type;
+	/**< Response type - copied from the request to the response message */
+
+	u8 hdr_flags;
+	/**< This represents a flags field for the Response.
+	 * The most significant bit is the 'valid' flag and the only
+	 * one used. All remaining bit positions are unused and
+	 * are therefore reserved
+	 */
+
+	/**< LW1 */
+	struct icp_qat_fw_pke_resp_status resp_status;
+
+	u16 resrvd4;
+	/**< Set to zero. */
+};
+
+/**
+ *****************************************************************************
+ *
+ * @ingroup icp_qat_fw_pke
+ *
+ * @brief
+ *      PKE response message structure (32 bytes)
+ *
+ *****************************************************************************/
+struct icp_qat_fw_pke_resp {
+	/**< LWs 0-1 */
+	struct icp_qat_fw_resp_pke_hdr pke_resp_hdr;
+	/**< Response header for PKE */
+
+	/**< LWs 2-3 */
+	u64 opaque;
+	/**< Opaque data passed from the request to the response message */
+
+	/**< LWs 4-5 */
+	u64 src_data_addr;
+	/**< Generic definition of the source data supplied to the QAT AE. The
+	 * common flags are used to further describe the attributes of this
+	 * field
+	 */
+
+	/**< LWs 6-7 */
+	u64 dest_data_addr;
+	/**< Generic definition of the destination data supplied to the QAT AE.
+	 * The common flags are used to further describe the attributes of this
+	 * field
+	 */
+};
+
+/* ========================================================================= */
+/* MACRO DEFINITIONS                                                         */
+/* ========================================================================= */
+
+/**< @ingroup icp_qat_fw_pke
+ * Macro defining the bit position and mask of the 'valid' flag, within the
+ * hdr_flags field of LW0 (service request and response) of the PKE request
+ */
+#define ICP_QAT_FW_PKE_HDR_VALID_FLAG_BITPOS 7
+#define ICP_QAT_FW_PKE_HDR_VALID_FLAG_MASK 0x1
+
+/**< @ingroup icp_qat_fw_pke
+ * Macro defining the bit position and mask of the PKE status flag, within the
+ * status field LW1 of a PKE response message
+ */
+#define QAT_COMN_RESP_PKE_STATUS_BITPOS 6
+/**< @ingroup icp_qat_fw_pke
+ * Starting bit position indicating the PKE status flag within the PKE response
+ * pke_resp_flags byte.
+ */
+
+#define QAT_COMN_RESP_PKE_STATUS_MASK 0x1
+/**< @ingroup icp_qat_fw_pke
+ * One bit mask used to determine PKE status mask
+ */
+
+/*
+ *  < @ingroup icp_qat_fw_pke
+ *  *** PKE Response Status Field Definition ***
+ *  The PKE response follows the CPM 1.5 message format. The status field is
+ *  16 bits wide, where the status flags are contained within the most
+ *  significant byte of the icp_qat_fw_pke_resp_status structure.
+ *  The lower 8 bits of this word now contain the common error codes,
+ *  which are defined in the common header file(*).
+ */
+/*  +=====+-----+----+-----+-----+-----+-----+-----+-----+---------------------+
+ *  | Bit |  15 | 14 | 13  | 12  | 11  | 10  |  9  |  8  |    [7....0]         |
+ *  +=====+-----+----+-----+-----+-----+-----+-----+-----+---------------------+
+ *  |Flags|Rsrvd|Pke |Rsrvd|Rsrvd|Rsrvd|Rsrvd|Rsrvd|Rsrvd|Common error codes(*)|
+ *  +=====+-----+----+-----+-----+-----+-----+-----+-----+---------------------+
+ */
+
+/**
+ ******************************************************************************
+ * @ingroup icp_qat_fw_pke
+ *
+ * @description
+ *     Macro for extraction of the PKE bit from the 16-bit status field
+ *     particular to a PKE response. The status flags are contained within
+ *     the most significant byte of the word. The lower 8 bits of this status
+ *     word now contain the common error codes, which are defined in the common
+ *     header file. The appropriate macro definition to extract the PKE status
+ *     lag from the PKE response assumes that a single byte i.e. pke_resp_flags
+ *     is passed to the macro.
+ *
+ * @param status
+ *     Status to extract the PKE status bit
+ *
+ *****************************************************************************/
+#define ICP_QAT_FW_PKE_RESP_PKE_STAT_GET(flags)                                \
+	QAT_FIELD_GET((flags), QAT_COMN_RESP_PKE_STATUS_BITPOS,                \
+		      QAT_COMN_RESP_PKE_STATUS_MASK)
+
+/**
+ ******************************************************************************
+ * @ingroup icp_qat_fw_pke
+ *
+ * @description
+ *      Extract the valid flag from the PKE Request's header flags. Note that
+ *      this invokes the common macro which may be used by either the request
+ *      or the response.
+ *
+ * @param icp_qat_fw_req_pke_hdr    Structure passed to extract the valid bit
+ *                                  from the 'hdr_flags' field.
+ *
+ *****************************************************************************/
+#define ICP_QAT_FW_PKE_RQ_VALID_FLAG_GET(icp_qat_fw_req_pke_hdr)               \
+	ICP_QAT_FW_PKE_HDR_VALID_FLAG_GET(icp_qat_fw_req_pke_hdr)
+
+/**
+ ******************************************************************************
+ * @ingroup icp_qat_fw_pke
+ *
+ * @description
+ *      Set the valid bit in the PKE Request's header flags. Note that
+ *      this invokes the common macro which may be used by either the request
+ *      or the response.
+ *
+ * @param icp_qat_fw_req_pke_hdr    Structure passed to set the valid bit.
+ * @param val    Value of the valid bit flag.
+ *
+ *****************************************************************************/
+#define ICP_QAT_FW_PKE_RQ_VALID_FLAG_SET(icp_qat_fw_req_pke_hdr, val)          \
+	ICP_QAT_FW_PKE_HDR_VALID_FLAG_SET(icp_qat_fw_req_pke_hdr, val)
+
+/**
+ ******************************************************************************
+ * @ingroup icp_qat_fw_pke
+ *
+ * @description
+ *      Extract the valid flag from the PKE Response's header flags. Note that
+ *      invokes the common macro which may be used by either the request
+ *      or the response.
+ *
+ * @param icp_qat_fw_resp_pke_hdr    Structure to extract the valid bit
+ *                                   from the 'hdr_flags' field.
+ *
+ *****************************************************************************/
+#define ICP_QAT_FW_PKE_RESP_VALID_FLAG_GET(icp_qat_fw_resp_pke_hdr)            \
+	ICP_QAT_FW_PKE_HDR_VALID_FLAG_GET(icp_qat_fw_resp_pke_hdr)
+
+/**
+ ******************************************************************************
+ * @ingroup icp_qat_fw_pke
+ *
+ * @description
+ *      Set the valid bit in the PKE Response's header flags. Note that
+ *      this invokes the common macro which may be used by either the
+ *      request or the response.
+ *
+ * @param icp_qat_fw_resp_pke_hdr    Structure to set the valid bit
+ * @param val    Value of the valid bit flag.
+ *
+ *****************************************************************************/
+#define ICP_QAT_FW_PKE_RESP_VALID_FLAG_SET(icp_qat_fw_resp_pke_hdr, val)       \
+	ICP_QAT_FW_PKE_HDR_VALID_FLAG_SET(icp_qat_fw_resp_pke_hdr, val)
+
+/**
+ ******************************************************************************
+ * @ingroup icp_qat_fw_pke
+ *
+ * @description
+ *      Common macro to extract the valid flag from the header flags field
+ *      within the header structure (request or response).
+ *
+ * @param hdr    Structure (request or response) to extract the
+ *               valid bit from the 'hdr_flags' field.
+ *
+ *****************************************************************************/
+#define ICP_QAT_FW_PKE_HDR_VALID_FLAG_GET(hdr)                                 \
+	QAT_FIELD_GET(hdr.hdr_flags, ICP_QAT_FW_PKE_HDR_VALID_FLAG_BITPOS,     \
+		      ICP_QAT_FW_PKE_HDR_VALID_FLAG_MASK)
+
+/**
+ ******************************************************************************
+ * @ingroup icp_qat_fw_pke
+ *
+ * @description
+ *      Common macro to set the valid bit in the header flags field within
+ *      the header structure (request or response).
+ *
+ * @param hdr    Structure (request or response) containing the header
+ *               flags field, to allow the valid bit to be set.
+ * @param val    Value of the valid bit flag.
+ *
+ *****************************************************************************/
+#define ICP_QAT_FW_PKE_HDR_VALID_FLAG_SET(hdr, val)                            \
+	QAT_FIELD_SET((hdr.hdr_flags), (val),                                  \
+		      ICP_QAT_FW_PKE_HDR_VALID_FLAG_BITPOS,                    \
+		      ICP_QAT_FW_PKE_HDR_VALID_FLAG_MASK)
+
+#endif /* _ICP_QAT_FW_PKE_H_ */
diff --git a/src/seastar/dpdk/drivers/common/qat/qat_adf/icp_qat_hw.h b/src/seastar/dpdk/drivers/common/qat/qat_adf/icp_qat_hw.h
new file mode 100644
index 000000000..e7961dba2
--- /dev/null
+++ b/src/seastar/dpdk/drivers/common/qat/qat_adf/icp_qat_hw.h
@@ -0,0 +1,386 @@
+/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
+ * Copyright(c) 2015-2018 Intel Corporation
+ */
+#ifndef _ICP_QAT_HW_H_
+#define _ICP_QAT_HW_H_
+
+enum icp_qat_hw_ae_id {
+	ICP_QAT_HW_AE_0 = 0,
+	ICP_QAT_HW_AE_1 = 1,
+	ICP_QAT_HW_AE_2 = 2,
+	ICP_QAT_HW_AE_3 = 3,
+	ICP_QAT_HW_AE_4 = 4,
+	ICP_QAT_HW_AE_5 = 5,
+	ICP_QAT_HW_AE_6 = 6,
+	ICP_QAT_HW_AE_7 = 7,
+	ICP_QAT_HW_AE_8 = 8,
+	ICP_QAT_HW_AE_9 = 9,
+	ICP_QAT_HW_AE_10 = 10,
+	ICP_QAT_HW_AE_11 = 11,
+	ICP_QAT_HW_AE_DELIMITER = 12
+};
+
+enum icp_qat_hw_qat_id {
+	ICP_QAT_HW_QAT_0 = 0,
+	ICP_QAT_HW_QAT_1 = 1,
+	ICP_QAT_HW_QAT_2 = 2,
+	ICP_QAT_HW_QAT_3 = 3,
+	ICP_QAT_HW_QAT_4 = 4,
+	ICP_QAT_HW_QAT_5 = 5,
+	ICP_QAT_HW_QAT_DELIMITER = 6
+};
+
+enum icp_qat_hw_auth_algo {
+	ICP_QAT_HW_AUTH_ALGO_NULL = 0,
+	ICP_QAT_HW_AUTH_ALGO_SHA1 = 1,
+	ICP_QAT_HW_AUTH_ALGO_MD5 = 2,
+	ICP_QAT_HW_AUTH_ALGO_SHA224 = 3,
+	ICP_QAT_HW_AUTH_ALGO_SHA256 = 4,
+	ICP_QAT_HW_AUTH_ALGO_SHA384 = 5,
+	ICP_QAT_HW_AUTH_ALGO_SHA512 = 6,
+	ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC = 7,
+	ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC = 8,
+	ICP_QAT_HW_AUTH_ALGO_AES_F9 = 9,
+	ICP_QAT_HW_AUTH_ALGO_GALOIS_128 = 10,
+	ICP_QAT_HW_AUTH_ALGO_GALOIS_64 = 11,
+	ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 = 12,
+	ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 = 13,
+	ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 = 14,
+	ICP_QAT_HW_AUTH_RESERVED_1 = 15,
+	ICP_QAT_HW_AUTH_RESERVED_2 = 16,
+	ICP_QAT_HW_AUTH_ALGO_SHA3_256 = 17,
+	ICP_QAT_HW_AUTH_RESERVED_3 = 18,
+	ICP_QAT_HW_AUTH_ALGO_SHA3_512 = 19,
+	ICP_QAT_HW_AUTH_ALGO_DELIMITER = 20
+};
+
+enum icp_qat_hw_auth_mode {
+	ICP_QAT_HW_AUTH_MODE0 = 0,
+	ICP_QAT_HW_AUTH_MODE1 = 1,
+	ICP_QAT_HW_AUTH_MODE2 = 2,
+	ICP_QAT_HW_AUTH_MODE_DELIMITER = 3
+};
+
+struct icp_qat_hw_auth_config {
+	uint32_t config;
+	uint32_t reserved;
+};
+
+#define QAT_AUTH_MODE_BITPOS 4
+#define QAT_AUTH_MODE_MASK 0xF
+#define QAT_AUTH_ALGO_BITPOS 0
+#define QAT_AUTH_ALGO_MASK 0xF
+#define QAT_AUTH_CMP_BITPOS 8
+#define QAT_AUTH_CMP_MASK 0x7F
+#define QAT_AUTH_SHA3_PADDING_DISABLE_BITPOS 16
+#define QAT_AUTH_SHA3_PADDING_DISABLE_MASK 0x1
+#define QAT_AUTH_SHA3_PADDING_OVERRIDE_BITPOS 17
+#define QAT_AUTH_SHA3_PADDING_OVERRIDE_MASK 0x1
+#define QAT_AUTH_ALGO_SHA3_BITPOS 22
+#define QAT_AUTH_ALGO_SHA3_MASK 0x3
+#define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_BITPOS 16
+#define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_MASK 0xF
+#define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_BITPOS 24
+#define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_MASK 0xFF
+#define QAT_AUTH_SHA3_HW_PADDING_ENABLE 0
+#define QAT_AUTH_SHA3_HW_PADDING_DISABLE 1
+#define QAT_AUTH_SHA3_PADDING_DISABLE_USE_DEFAULT 0
+#define QAT_AUTH_SHA3_PADDING_OVERRIDE_USE_DEFAULT 0
+#define QAT_AUTH_SHA3_PADDING_OVERRIDE_PROGRAMMABLE 1
+#define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_RESERVED 0
+#define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_RESERVED 0
+
+#define ICP_QAT_HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len)                      \
+	((((mode) & QAT_AUTH_MODE_MASK) << QAT_AUTH_MODE_BITPOS) |             \
+	 (((algo) & QAT_AUTH_ALGO_MASK) << QAT_AUTH_ALGO_BITPOS) |             \
+	 (((algo >> 4) & QAT_AUTH_ALGO_SHA3_MASK)                              \
+			<< QAT_AUTH_ALGO_SHA3_BITPOS) |                        \
+	 (((QAT_AUTH_SHA3_PADDING_DISABLE_USE_DEFAULT) &                       \
+			QAT_AUTH_SHA3_PADDING_DISABLE_MASK)                    \
+			<< QAT_AUTH_SHA3_PADDING_DISABLE_BITPOS) |             \
+	 (((QAT_AUTH_SHA3_PADDING_OVERRIDE_USE_DEFAULT) &                      \
+			QAT_AUTH_SHA3_PADDING_OVERRIDE_MASK)                   \
+			<< QAT_AUTH_SHA3_PADDING_OVERRIDE_BITPOS) |            \
+	 (((cmp_len) & QAT_AUTH_CMP_MASK) << QAT_AUTH_CMP_BITPOS))
+
+#define ICP_QAT_HW_AUTH_CONFIG_BUILD_UPPER                                     \
+	((((QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_RESERVED) &                     \
+		QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_MASK)                       \
+		<< QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_BITPOS) |                \
+	 (((QAT_AUTH_SHA3_PROG_PADDING_PREFIX_RESERVED) &                      \
+		QAT_AUTH_SHA3_PROG_PADDING_PREFIX_MASK)                        \
+		<< QAT_AUTH_SHA3_PROG_PADDING_PREFIX_BITPOS))
+
+struct icp_qat_hw_auth_counter {
+	uint32_t counter;
+	uint32_t reserved;
+};
+
+#define QAT_AUTH_COUNT_MASK 0xFFFFFFFF
+#define QAT_AUTH_COUNT_BITPOS 0
+#define ICP_QAT_HW_AUTH_COUNT_BUILD(val) \
+	(((val) & QAT_AUTH_COUNT_MASK) << QAT_AUTH_COUNT_BITPOS)
+
+struct icp_qat_hw_auth_setup {
+	struct icp_qat_hw_auth_config auth_config;
+	struct icp_qat_hw_auth_counter auth_counter;
+};
+
+#define QAT_HW_DEFAULT_ALIGNMENT 8
+#define QAT_HW_ROUND_UP(val, n) (((val) + ((n) - 1)) & (~(n - 1)))
+#define ICP_QAT_HW_NULL_STATE1_SZ 32
+#define ICP_QAT_HW_MD5_STATE1_SZ 16
+#define ICP_QAT_HW_SHA1_STATE1_SZ 20
+#define ICP_QAT_HW_SHA224_STATE1_SZ 32
+#define ICP_QAT_HW_SHA3_224_STATE1_SZ 28
+#define ICP_QAT_HW_SHA256_STATE1_SZ 32
+#define ICP_QAT_HW_SHA3_256_STATE1_SZ 32
+#define ICP_QAT_HW_SHA384_STATE1_SZ 64
+#define ICP_QAT_HW_SHA3_384_STATE1_SZ 48
+#define ICP_QAT_HW_SHA512_STATE1_SZ 64
+#define ICP_QAT_HW_SHA3_512_STATE1_SZ 64
+#define ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ 16
+#define ICP_QAT_HW_AES_CBC_MAC_STATE1_SZ 16
+#define ICP_QAT_HW_AES_F9_STATE1_SZ 32
+#define ICP_QAT_HW_KASUMI_F9_STATE1_SZ 16
+#define ICP_QAT_HW_GALOIS_128_STATE1_SZ 16
+#define ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ 8
+#define ICP_QAT_HW_ZUC_3G_EIA3_STATE1_SZ 8
+
+#define ICP_QAT_HW_NULL_STATE2_SZ 32
+#define ICP_QAT_HW_MD5_STATE2_SZ 16
+#define ICP_QAT_HW_SHA1_STATE2_SZ 20
+#define ICP_QAT_HW_SHA224_STATE2_SZ 32
+#define ICP_QAT_HW_SHA3_224_STATE2_SZ 0
+#define ICP_QAT_HW_SHA256_STATE2_SZ 32
+#define ICP_QAT_HW_SHA3_256_STATE2_SZ 0
+#define ICP_QAT_HW_SHA384_STATE2_SZ 64
+#define ICP_QAT_HW_SHA3_384_STATE2_SZ 0
+#define ICP_QAT_HW_SHA512_STATE2_SZ 64
+#define ICP_QAT_HW_SHA3_512_STATE2_SZ 0
+#define ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ 48
+#define ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ 16
+#define ICP_QAT_HW_AES_CBC_MAC_KEY_SZ 16
+#define ICP_QAT_HW_AES_CCM_CBC_E_CTR0_SZ 16
+#define ICP_QAT_HW_F9_IK_SZ 16
+#define ICP_QAT_HW_F9_FK_SZ 16
+#define ICP_QAT_HW_KASUMI_F9_STATE2_SZ (ICP_QAT_HW_F9_IK_SZ + \
+	ICP_QAT_HW_F9_FK_SZ)
+#define ICP_QAT_HW_AES_F9_STATE2_SZ ICP_QAT_HW_KASUMI_F9_STATE2_SZ
+#define ICP_QAT_HW_SNOW_3G_UIA2_STATE2_SZ 24
+#define ICP_QAT_HW_ZUC_3G_EIA3_STATE2_SZ 32
+#define ICP_QAT_HW_GALOIS_H_SZ 16
+#define ICP_QAT_HW_GALOIS_LEN_A_SZ 8
+#define ICP_QAT_HW_GALOIS_E_CTR0_SZ 16
+
+struct icp_qat_hw_auth_sha512 {
+	struct icp_qat_hw_auth_setup inner_setup;
+	uint8_t state1[ICP_QAT_HW_SHA512_STATE1_SZ];
+	struct icp_qat_hw_auth_setup outer_setup;
+	uint8_t state2[ICP_QAT_HW_SHA512_STATE2_SZ];
+};
+
+struct icp_qat_hw_auth_sha3_512 {
+	struct icp_qat_hw_auth_setup inner_setup;
+	uint8_t state1[ICP_QAT_HW_SHA3_512_STATE1_SZ];
+	struct icp_qat_hw_auth_setup outer_setup;
+};
+
+struct icp_qat_hw_auth_algo_blk {
+	struct icp_qat_hw_auth_sha512 sha;
+};
+
+#define ICP_QAT_HW_GALOIS_LEN_A_BITPOS 0
+#define ICP_QAT_HW_GALOIS_LEN_A_MASK 0xFFFFFFFF
+
+enum icp_qat_hw_cipher_algo {
+	ICP_QAT_HW_CIPHER_ALGO_NULL = 0,
+	ICP_QAT_HW_CIPHER_ALGO_DES = 1,
+	ICP_QAT_HW_CIPHER_ALGO_3DES = 2,
+	ICP_QAT_HW_CIPHER_ALGO_AES128 = 3,
+	ICP_QAT_HW_CIPHER_ALGO_AES192 = 4,
+	ICP_QAT_HW_CIPHER_ALGO_AES256 = 5,
+	ICP_QAT_HW_CIPHER_ALGO_ARC4 = 6,
+	ICP_QAT_HW_CIPHER_ALGO_KASUMI = 7,
+	ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 = 8,
+	ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3 = 9,
+	ICP_QAT_HW_CIPHER_DELIMITER = 10
+};
+
+enum icp_qat_hw_cipher_mode {
+	ICP_QAT_HW_CIPHER_ECB_MODE = 0,
+	ICP_QAT_HW_CIPHER_CBC_MODE = 1,
+	ICP_QAT_HW_CIPHER_CTR_MODE = 2,
+	ICP_QAT_HW_CIPHER_F8_MODE = 3,
+	ICP_QAT_HW_CIPHER_XTS_MODE = 6,
+	ICP_QAT_HW_CIPHER_MODE_DELIMITER = 7
+};
+
+struct icp_qat_hw_cipher_config {
+	uint32_t val;
+	uint32_t reserved;
+};
+
+enum icp_qat_hw_cipher_dir {
+	ICP_QAT_HW_CIPHER_ENCRYPT = 0,
+	ICP_QAT_HW_CIPHER_DECRYPT = 1,
+};
+
+enum icp_qat_hw_auth_op {
+	ICP_QAT_HW_AUTH_VERIFY = 0,
+	ICP_QAT_HW_AUTH_GENERATE = 1,
+};
+
+enum icp_qat_hw_cipher_convert {
+	ICP_QAT_HW_CIPHER_NO_CONVERT = 0,
+	ICP_QAT_HW_CIPHER_KEY_CONVERT = 1,
+};
+
+#define QAT_CIPHER_MODE_BITPOS 4
+#define QAT_CIPHER_MODE_MASK 0xF
+#define QAT_CIPHER_ALGO_BITPOS 0
+#define QAT_CIPHER_ALGO_MASK 0xF
+#define QAT_CIPHER_CONVERT_BITPOS 9
+#define QAT_CIPHER_CONVERT_MASK 0x1
+#define QAT_CIPHER_DIR_BITPOS 8
+#define QAT_CIPHER_DIR_MASK 0x1
+#define QAT_CIPHER_MODE_F8_KEY_SZ_MULT 2
+#define QAT_CIPHER_MODE_XTS_KEY_SZ_MULT 2
+#define ICP_QAT_HW_CIPHER_CONFIG_BUILD(mode, algo, convert, dir) \
+	(((mode & QAT_CIPHER_MODE_MASK) << QAT_CIPHER_MODE_BITPOS) | \
+	((algo & QAT_CIPHER_ALGO_MASK) << QAT_CIPHER_ALGO_BITPOS) | \
+	((convert & QAT_CIPHER_CONVERT_MASK) << QAT_CIPHER_CONVERT_BITPOS) | \
+	((dir & QAT_CIPHER_DIR_MASK) << QAT_CIPHER_DIR_BITPOS))
+#define ICP_QAT_HW_DES_BLK_SZ 8
+#define ICP_QAT_HW_3DES_BLK_SZ 8
+#define ICP_QAT_HW_NULL_BLK_SZ 8
+#define ICP_QAT_HW_AES_BLK_SZ 16
+#define ICP_QAT_HW_KASUMI_BLK_SZ 8
+#define ICP_QAT_HW_SNOW_3G_BLK_SZ 8
+#define ICP_QAT_HW_ZUC_3G_BLK_SZ 8
+#define ICP_QAT_HW_NULL_KEY_SZ 256
+#define ICP_QAT_HW_DES_KEY_SZ 8
+#define ICP_QAT_HW_3DES_KEY_SZ 24
+#define ICP_QAT_HW_AES_128_KEY_SZ 16
+#define ICP_QAT_HW_AES_192_KEY_SZ 24
+#define ICP_QAT_HW_AES_256_KEY_SZ 32
+#define ICP_QAT_HW_AES_128_F8_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \
+	QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
+#define ICP_QAT_HW_AES_192_F8_KEY_SZ (ICP_QAT_HW_AES_192_KEY_SZ * \
+	QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
+#define ICP_QAT_HW_AES_256_F8_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \
+	QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
+#define ICP_QAT_HW_AES_128_XTS_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \
+	QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
+#define ICP_QAT_HW_AES_256_XTS_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \
+	QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
+#define ICP_QAT_HW_KASUMI_KEY_SZ 16
+#define ICP_QAT_HW_KASUMI_F8_KEY_SZ (ICP_QAT_HW_KASUMI_KEY_SZ * \
+	QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
+#define ICP_QAT_HW_AES_128_XTS_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \
+	QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
+#define ICP_QAT_HW_AES_256_XTS_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \
+	QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
+#define ICP_QAT_HW_ARC4_KEY_SZ 256
+#define ICP_QAT_HW_SNOW_3G_UEA2_KEY_SZ 16
+#define ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ 16
+#define ICP_QAT_HW_ZUC_3G_EEA3_KEY_SZ 16
+#define ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ 16
+#define ICP_QAT_HW_MODE_F8_NUM_REG_TO_CLEAR 2
+
+#define ICP_QAT_HW_CIPHER_MAX_KEY_SZ ICP_QAT_HW_AES_256_F8_KEY_SZ
+
+/* These defines describe position of the bit-fields
+ * in the flags byte in B0
+ */
+#define ICP_QAT_HW_CCM_B0_FLAGS_ADATA_SHIFT      6
+#define ICP_QAT_HW_CCM_B0_FLAGS_T_SHIFT          3
+
+#define ICP_QAT_HW_CCM_BUILD_B0_FLAGS(Adata, t, q)                  \
+	((((Adata) > 0 ? 1 : 0) << ICP_QAT_HW_CCM_B0_FLAGS_ADATA_SHIFT) \
+	| ((((t) - 2) >> 1) << ICP_QAT_HW_CCM_B0_FLAGS_T_SHIFT) \
+	| ((q) - 1))
+
+#define ICP_QAT_HW_CCM_NQ_CONST 15
+#define ICP_QAT_HW_CCM_AAD_B0_LEN 16
+#define ICP_QAT_HW_CCM_AAD_LEN_INFO 2
+#define ICP_QAT_HW_CCM_AAD_DATA_OFFSET (ICP_QAT_HW_CCM_AAD_B0_LEN + \
+		ICP_QAT_HW_CCM_AAD_LEN_INFO)
+#define ICP_QAT_HW_CCM_AAD_ALIGNMENT 16
+#define ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE 4
+#define ICP_QAT_HW_CCM_NONCE_OFFSET 1
+
+struct icp_qat_hw_cipher_algo_blk {
+	struct icp_qat_hw_cipher_config cipher_config;
+	uint8_t key[ICP_QAT_HW_CIPHER_MAX_KEY_SZ];
+} __rte_cache_aligned;
+
+/* ========================================================================= */
+/*                COMPRESSION SLICE                                          */
+/* ========================================================================= */
+
+enum icp_qat_hw_compression_direction {
+	ICP_QAT_HW_COMPRESSION_DIR_COMPRESS = 0,
+	ICP_QAT_HW_COMPRESSION_DIR_DECOMPRESS = 1,
+	ICP_QAT_HW_COMPRESSION_DIR_DELIMITER = 2
+};
+
+enum icp_qat_hw_compression_delayed_match {
+	ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DISABLED = 0,
+	ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_ENABLED = 1,
+	ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DELIMITER = 2
+};
+
+enum icp_qat_hw_compression_algo {
+	ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE = 0,
+	ICP_QAT_HW_COMPRESSION_ALGO_LZS = 1,
+	ICP_QAT_HW_COMPRESSION_ALGO_DELIMITER = 2
+};
+
+
+enum icp_qat_hw_compression_depth {
+	ICP_QAT_HW_COMPRESSION_DEPTH_1 = 0,
+	ICP_QAT_HW_COMPRESSION_DEPTH_4 = 1,
+	ICP_QAT_HW_COMPRESSION_DEPTH_8 = 2,
+	ICP_QAT_HW_COMPRESSION_DEPTH_16 = 3,
+	ICP_QAT_HW_COMPRESSION_DEPTH_DELIMITER = 4
+};
+
+enum icp_qat_hw_compression_file_type {
+	ICP_QAT_HW_COMPRESSION_FILE_TYPE_0 = 0,
+	ICP_QAT_HW_COMPRESSION_FILE_TYPE_1 = 1,
+	ICP_QAT_HW_COMPRESSION_FILE_TYPE_2 = 2,
+	ICP_QAT_HW_COMPRESSION_FILE_TYPE_3 = 3,
+	ICP_QAT_HW_COMPRESSION_FILE_TYPE_4 = 4,
+	ICP_QAT_HW_COMPRESSION_FILE_TYPE_DELIMITER = 5
+};
+
+struct icp_qat_hw_compression_config {
+	uint32_t val;
+	uint32_t reserved;
+};
+
+#define QAT_COMPRESSION_DIR_BITPOS 4
+#define QAT_COMPRESSION_DIR_MASK 0x7
+#define QAT_COMPRESSION_DELAYED_MATCH_BITPOS 16
+#define QAT_COMPRESSION_DELAYED_MATCH_MASK 0x1
+#define QAT_COMPRESSION_ALGO_BITPOS 31
+#define QAT_COMPRESSION_ALGO_MASK 0x1
+#define QAT_COMPRESSION_DEPTH_BITPOS 28
+#define QAT_COMPRESSION_DEPTH_MASK 0x7
+#define QAT_COMPRESSION_FILE_TYPE_BITPOS 24
+#define QAT_COMPRESSION_FILE_TYPE_MASK 0xF
+
+#define ICP_QAT_HW_COMPRESSION_CONFIG_BUILD(                                   \
+	dir, delayed, algo, depth, filetype)                                   \
+	((((dir) & QAT_COMPRESSION_DIR_MASK) << QAT_COMPRESSION_DIR_BITPOS) |  \
+	 (((delayed) & QAT_COMPRESSION_DELAYED_MATCH_MASK)                     \
+	  << QAT_COMPRESSION_DELAYED_MATCH_BITPOS) |                           \
+	 (((algo) & QAT_COMPRESSION_ALGO_MASK)                                 \
+	  << QAT_COMPRESSION_ALGO_BITPOS) |                                    \
+	 (((depth) & QAT_COMPRESSION_DEPTH_MASK)                               \
+	  << QAT_COMPRESSION_DEPTH_BITPOS) |                                   \
+	 (((filetype) & QAT_COMPRESSION_FILE_TYPE_MASK)                        \
+	  << QAT_COMPRESSION_FILE_TYPE_BITPOS))
+
+#endif
diff --git a/src/seastar/dpdk/drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h b/src/seastar/dpdk/drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h
new file mode 100644
index 000000000..8adf20959
--- /dev/null
+++ b/src/seastar/dpdk/drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Intel Corporation
+ */
+
+#ifndef _QAT_PKE_FUNCTIONALITY_ARRAYS_H_
+#define _QAT_PKE_FUNCTIONALITY_ARRAYS_H_
+
+#include "icp_qat_fw_mmp_ids.h"
+
+/*
+ * Modular exponentiation functionality IDs
+ */
+static const uint32_t MOD_EXP_SIZE[][2] = {
+		{ 512,	MATHS_MODEXP_L512 },
+		{ 1024, MATHS_MODEXP_L1024 },
+		{ 1536,	MATHS_MODEXP_L1536 },
+		{ 2048, MATHS_MODEXP_L2048 },
+		{ 2560, MATHS_MODEXP_L2560 },
+		{ 3072, MATHS_MODEXP_L3072 },
+		{ 3584, MATHS_MODEXP_L3584 },
+		{ 4096, MATHS_MODEXP_L4096 }
+};
+
+static const uint32_t MOD_INV_IDS_ODD[][2] = {
+		{ 128,	MATHS_MODINV_ODD_L128 },
+		{ 192,	MATHS_MODINV_ODD_L192 },
+		{ 256,  MATHS_MODINV_ODD_L256 },
+		{ 384,	MATHS_MODINV_ODD_L384 },
+		{ 512,	MATHS_MODINV_ODD_L512 },
+		{ 768,	MATHS_MODINV_ODD_L768 },
+		{ 1024, MATHS_MODINV_ODD_L1024 },
+		{ 1536, MATHS_MODINV_ODD_L1536 },
+		{ 2048, MATHS_MODINV_ODD_L2048 },
+		{ 3072, MATHS_MODINV_ODD_L3072 },
+		{ 4096, MATHS_MODINV_ODD_L4096 },
+};
+
+static const uint32_t MOD_INV_IDS_EVEN[][2] = {
+		{ 128,	MATHS_MODINV_EVEN_L128 },
+		{ 192,	MATHS_MODINV_EVEN_L192 },
+		{ 256,	MATHS_MODINV_EVEN_L256 },
+		{ 384,	MATHS_MODINV_EVEN_L384 },
+		{ 512,	MATHS_MODINV_EVEN_L512 },
+		{ 768,	MATHS_MODINV_EVEN_L768 },
+		{ 1024, MATHS_MODINV_EVEN_L1024 },
+		{ 1536, MATHS_MODINV_EVEN_L1536 },
+		{ 2048, MATHS_MODINV_EVEN_L2048 },
+		{ 3072, MATHS_MODINV_EVEN_L3072 },
+		{ 4096, MATHS_MODINV_EVEN_L4096 },
+};
+
+#endif