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authorDaniel Baumann <daniel.baumann@progress-linux.org>2024-04-07 18:49:45 +0000
committerDaniel Baumann <daniel.baumann@progress-linux.org>2024-04-07 18:49:45 +0000
commit2c3c1048746a4622d8c89a29670120dc8fab93c4 (patch)
tree848558de17fb3008cdf4d861b01ac7781903ce39 /drivers/gpu/drm/stm/ltdc.h
parentInitial commit. (diff)
downloadlinux-2c3c1048746a4622d8c89a29670120dc8fab93c4.tar.xz
linux-2c3c1048746a4622d8c89a29670120dc8fab93c4.zip
Adding upstream version 6.1.76.upstream/6.1.76upstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'drivers/gpu/drm/stm/ltdc.h')
-rw-r--r--drivers/gpu/drm/stm/ltdc.h65
1 files changed, 65 insertions, 0 deletions
diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h
new file mode 100644
index 000000000..9d488043f
--- /dev/null
+++ b/drivers/gpu/drm/stm/ltdc.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ *
+ * Authors: Philippe Cornu <philippe.cornu@st.com>
+ * Yannick Fertre <yannick.fertre@st.com>
+ * Fabien Dessenne <fabien.dessenne@st.com>
+ * Mickael Reulier <mickael.reulier@st.com>
+ */
+
+#ifndef _LTDC_H_
+#define _LTDC_H_
+
+struct ltdc_caps {
+ u32 hw_version; /* hardware version */
+ u32 nb_layers; /* number of supported layers */
+ u32 layer_ofs; /* layer offset for applicable regs */
+ const u32 *layer_regs; /* layer register offset */
+ u32 bus_width; /* bus width (32 or 64 bits) */
+ const u32 *pix_fmt_hw; /* supported hw pixel formats */
+ const u32 *pix_fmt_drm; /* supported drm pixel formats */
+ int pix_fmt_nb; /* number of pixel format */
+ bool pix_fmt_flex; /* pixel format flexibility supported */
+ bool non_alpha_only_l1; /* non-native no-alpha formats on layer 1 */
+ int pad_max_freq_hz; /* max frequency supported by pad */
+ int nb_irq; /* number of hardware interrupts */
+ bool ycbcr_input; /* ycbcr input converter supported */
+ bool ycbcr_output; /* ycbcr output converter supported */
+ bool plane_reg_shadow; /* plane shadow registers ability */
+ bool crc; /* cyclic redundancy check supported */
+ bool dynamic_zorder; /* dynamic z-order */
+ bool plane_rotation; /* plane rotation */
+ bool fifo_threshold; /* fifo underrun threshold supported */
+};
+
+#define LTDC_MAX_LAYER 4
+
+struct fps_info {
+ unsigned int counter;
+ ktime_t last_timestamp;
+};
+
+struct ltdc_device {
+ void __iomem *regs;
+ struct regmap *regmap;
+ struct clk *pixel_clk; /* lcd pixel clock */
+ struct mutex err_lock; /* protecting error_status */
+ struct ltdc_caps caps;
+ u32 irq_status;
+ u32 fifo_err; /* fifo underrun error counter */
+ u32 fifo_warn; /* fifo underrun warning counter */
+ u32 fifo_threshold; /* fifo underrun threshold */
+ u32 transfer_err; /* transfer error counter */
+ struct fps_info plane_fpsi[LTDC_MAX_LAYER];
+ struct drm_atomic_state *suspend_state;
+ int crc_skip_count;
+ bool crc_active;
+};
+
+int ltdc_load(struct drm_device *ddev);
+void ltdc_unload(struct drm_device *ddev);
+void ltdc_suspend(struct drm_device *ddev);
+int ltdc_resume(struct drm_device *ddev);
+
+#endif