diff options
author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-07 18:49:45 +0000 |
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committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-07 18:49:45 +0000 |
commit | 2c3c1048746a4622d8c89a29670120dc8fab93c4 (patch) | |
tree | 848558de17fb3008cdf4d861b01ac7781903ce39 /drivers/staging/r8188eu/hal | |
parent | Initial commit. (diff) | |
download | linux-upstream.tar.xz linux-upstream.zip |
Adding upstream version 6.1.76.upstream/6.1.76upstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'drivers/staging/r8188eu/hal')
20 files changed, 9812 insertions, 0 deletions
diff --git a/drivers/staging/r8188eu/hal/Hal8188ERateAdaptive.c b/drivers/staging/r8188eu/hal/Hal8188ERateAdaptive.c new file mode 100644 index 000000000..1e04de3a6 --- /dev/null +++ b/drivers/staging/r8188eu/hal/Hal8188ERateAdaptive.c @@ -0,0 +1,654 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (c) Realtek Semiconductor Corp. */ + +#include "../include/drv_types.h" + +static u8 RETRY_PENALTY[PERENTRY][RETRYSIZE + 1] = { + {5, 4, 3, 2, 0, 3}, /* 92 , idx = 0 */ + {6, 5, 4, 3, 0, 4}, /* 86 , idx = 1 */ + {6, 5, 4, 2, 0, 4}, /* 81 , idx = 2 */ + {8, 7, 6, 4, 0, 6}, /* 75 , idx = 3 */ + {10, 9, 8, 6, 0, 8}, /* 71 , idx = 4 */ + {10, 9, 8, 4, 0, 8}, /* 66 , idx = 5 */ + {10, 9, 8, 2, 0, 8}, /* 62 , idx = 6 */ + {10, 9, 8, 0, 0, 8}, /* 59 , idx = 7 */ + {18, 17, 16, 8, 0, 16}, /* 53 , idx = 8 */ + {26, 25, 24, 16, 0, 24}, /* 50 , idx = 9 */ + {34, 33, 32, 24, 0, 32}, /* 47 , idx = 0x0a */ + {34, 31, 28, 20, 0, 32}, /* 43 , idx = 0x0b */ + {34, 31, 27, 18, 0, 32}, /* 40 , idx = 0x0c */ + {34, 31, 26, 16, 0, 32}, /* 37 , idx = 0x0d */ + {34, 30, 22, 16, 0, 32}, /* 32 , idx = 0x0e */ + {34, 30, 24, 16, 0, 32}, /* 26 , idx = 0x0f */ + {49, 46, 40, 16, 0, 48}, /* 20 , idx = 0x10 */ + {49, 45, 32, 0, 0, 48}, /* 17 , idx = 0x11 */ + {49, 45, 22, 18, 0, 48}, /* 15 , idx = 0x12 */ + {49, 40, 24, 16, 0, 48}, /* 12 , idx = 0x13 */ + {49, 32, 18, 12, 0, 48}, /* 9 , idx = 0x14 */ + {49, 22, 18, 14, 0, 48}, /* 6 , idx = 0x15 */ + {49, 16, 16, 0, 0, 48} + }; /* 3, idx = 0x16 */ + +static u8 PT_PENALTY[RETRYSIZE + 1] = {34, 31, 30, 24, 0, 32}; + +/* wilson modify */ +static u8 RETRY_PENALTY_IDX[2][RATESIZE] = { + {4, 4, 4, 5, 4, 4, 5, 7, 7, 7, 8, 0x0a, /* SS>TH */ + 4, 4, 4, 4, 6, 0x0a, 0x0b, 0x0d, + 5, 5, 7, 7, 8, 0x0b, 0x0d, 0x0f}, /* 0329 R01 */ + {0x0a, 0x0a, 0x0b, 0x0c, 0x0a, + 0x0a, 0x0b, 0x0c, 0x0d, 0x10, 0x13, 0x14, /* SS<TH */ + 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x11, 0x13, 0x15, + 9, 9, 9, 9, 0x0c, 0x0e, 0x11, 0x13} + }; + +static u8 RETRY_PENALTY_UP_IDX[RATESIZE] = { + 0x0c, 0x0d, 0x0d, 0x0f, 0x0d, 0x0e, + 0x0f, 0x0f, 0x10, 0x12, 0x13, 0x14, /* SS>TH */ + 0x0f, 0x10, 0x10, 0x12, 0x12, 0x13, 0x14, 0x15, + 0x11, 0x11, 0x12, 0x13, 0x13, 0x13, 0x14, 0x15}; + +static u8 RSSI_THRESHOLD[RATESIZE] = { + 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0x24, 0x26, 0x2a, + 0x18, 0x1a, 0x1d, 0x1f, 0x21, 0x27, 0x29, 0x2a, + 0, 0, 0, 0x1f, 0x23, 0x28, 0x2a, 0x2c}; + +static u16 N_THRESHOLD_HIGH[RATESIZE] = { + 4, 4, 8, 16, + 24, 36, 48, 72, 96, 144, 192, 216, + 60, 80, 100, 160, 240, 400, 560, 640, + 300, 320, 480, 720, 1000, 1200, 1600, 2000}; +static u16 N_THRESHOLD_LOW[RATESIZE] = { + 2, 2, 4, 8, + 12, 18, 24, 36, 48, 72, 96, 108, + 30, 40, 50, 80, 120, 200, 280, 320, + 150, 160, 240, 360, 500, 600, 800, 1000}; + +static u8 DROPING_NECESSARY[RATESIZE] = { + 1, 1, 1, 1, + 1, 2, 3, 4, 5, 6, 7, 8, + 1, 2, 3, 4, 5, 6, 7, 8, + 5, 6, 7, 8, 9, 10, 11, 12}; + +static u8 PendingForRateUpFail[5] = {2, 10, 24, 40, 60}; +static u16 DynamicTxRPTTiming[6] = { + 0x186a, 0x30d4, 0x493e, 0x61a8, 0x7a12, 0x927c}; /* 200ms-1200ms */ + +/* End Rate adaptive parameters */ + +static void odm_SetTxRPTTiming_8188E( + struct odm_dm_struct *dm_odm, + struct odm_ra_info *pRaInfo, + u8 extend + ) +{ + u8 idx = 0; + + for (idx = 0; idx < 5; idx++) + if (DynamicTxRPTTiming[idx] == pRaInfo->RptTime) + break; + + if (extend == 0) { /* back to default timing */ + idx = 0; /* 200ms */ + } else if (extend == 1) {/* increase the timing */ + idx += 1; + if (idx > 5) + idx = 5; + } else if (extend == 2) {/* decrease the timing */ + if (idx != 0) + idx -= 1; + } + pRaInfo->RptTime = DynamicTxRPTTiming[idx]; +} + +static int odm_RateDown_8188E(struct odm_dm_struct *dm_odm, struct odm_ra_info *pRaInfo) +{ + u8 RateID, LowestRate, HighestRate; + u8 i; + + if (NULL == pRaInfo) + return -1; + RateID = pRaInfo->PreRate; + LowestRate = pRaInfo->LowestRate; + HighestRate = pRaInfo->HighestRate; + + if (RateID > HighestRate) { + RateID = HighestRate; + } else if (pRaInfo->RateSGI) { + pRaInfo->RateSGI = 0; + } else if (RateID > LowestRate) { + if (RateID > 0) { + for (i = RateID - 1; i > LowestRate; i--) { + if (pRaInfo->RAUseRate & BIT(i)) { + RateID = i; + goto RateDownFinish; + } + } + } + } else if (RateID <= LowestRate) { + RateID = LowestRate; + } +RateDownFinish: + if (pRaInfo->RAWaitingCounter == 1) { + pRaInfo->RAWaitingCounter += 1; + pRaInfo->RAPendingCounter += 1; + } else if (pRaInfo->RAWaitingCounter == 0) { + ; + } else { + pRaInfo->RAWaitingCounter = 0; + pRaInfo->RAPendingCounter = 0; + } + + if (pRaInfo->RAPendingCounter >= 4) + pRaInfo->RAPendingCounter = 4; + + pRaInfo->DecisionRate = RateID; + odm_SetTxRPTTiming_8188E(dm_odm, pRaInfo, 2); + return 0; +} + +static int odm_RateUp_8188E( + struct odm_dm_struct *dm_odm, + struct odm_ra_info *pRaInfo + ) +{ + u8 RateID, HighestRate; + u8 i; + + if (NULL == pRaInfo) + return -1; + RateID = pRaInfo->PreRate; + HighestRate = pRaInfo->HighestRate; + if (pRaInfo->RAWaitingCounter == 1) { + pRaInfo->RAWaitingCounter = 0; + pRaInfo->RAPendingCounter = 0; + } else if (pRaInfo->RAWaitingCounter > 1) { + pRaInfo->PreRssiStaRA = pRaInfo->RssiStaRA; + goto RateUpfinish; + } + odm_SetTxRPTTiming_8188E(dm_odm, pRaInfo, 0); + + if (RateID < HighestRate) { + for (i = RateID + 1; i <= HighestRate; i++) { + if (pRaInfo->RAUseRate & BIT(i)) { + RateID = i; + goto RateUpfinish; + } + } + } else if (RateID == HighestRate) { + if (pRaInfo->SGIEnable && (pRaInfo->RateSGI != 1)) + pRaInfo->RateSGI = 1; + else if ((pRaInfo->SGIEnable) != 1) + pRaInfo->RateSGI = 0; + } else { + RateID = HighestRate; + } +RateUpfinish: + if (pRaInfo->RAWaitingCounter == (4 + PendingForRateUpFail[pRaInfo->RAPendingCounter])) + pRaInfo->RAWaitingCounter = 0; + else + pRaInfo->RAWaitingCounter++; + + pRaInfo->DecisionRate = RateID; + return 0; +} + +static void odm_ResetRaCounter_8188E(struct odm_ra_info *pRaInfo) +{ + u8 RateID; + + RateID = pRaInfo->DecisionRate; + pRaInfo->NscUp = (N_THRESHOLD_HIGH[RateID] + N_THRESHOLD_LOW[RateID]) >> 1; + pRaInfo->NscDown = (N_THRESHOLD_HIGH[RateID] + N_THRESHOLD_LOW[RateID]) >> 1; +} + +static void odm_RateDecision_8188E(struct odm_dm_struct *dm_odm, + struct odm_ra_info *pRaInfo + ) +{ + u8 RateID = 0, RtyPtID = 0, PenaltyID1 = 0, PenaltyID2 = 0; + /* u32 pool_retry; */ + static u8 DynamicTxRPTTimingCounter; + + if (pRaInfo->Active && (pRaInfo->TOTAL > 0)) { /* STA used and data packet exits */ + if ((pRaInfo->RssiStaRA < (pRaInfo->PreRssiStaRA - 3)) || + (pRaInfo->RssiStaRA > (pRaInfo->PreRssiStaRA + 3))) { + pRaInfo->RAWaitingCounter = 0; + pRaInfo->RAPendingCounter = 0; + } + /* Start RA decision */ + if (pRaInfo->PreRate > pRaInfo->HighestRate) + RateID = pRaInfo->HighestRate; + else + RateID = pRaInfo->PreRate; + if (pRaInfo->RssiStaRA > RSSI_THRESHOLD[RateID]) + RtyPtID = 0; + else + RtyPtID = 1; + PenaltyID1 = RETRY_PENALTY_IDX[RtyPtID][RateID]; /* TODO by page */ + + pRaInfo->NscDown += pRaInfo->RTY[0] * RETRY_PENALTY[PenaltyID1][0]; + pRaInfo->NscDown += pRaInfo->RTY[1] * RETRY_PENALTY[PenaltyID1][1]; + pRaInfo->NscDown += pRaInfo->RTY[2] * RETRY_PENALTY[PenaltyID1][2]; + pRaInfo->NscDown += pRaInfo->RTY[3] * RETRY_PENALTY[PenaltyID1][3]; + pRaInfo->NscDown += pRaInfo->RTY[4] * RETRY_PENALTY[PenaltyID1][4]; + if (pRaInfo->NscDown > (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID1][5])) + pRaInfo->NscDown -= pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID1][5]; + else + pRaInfo->NscDown = 0; + + /* rate up */ + PenaltyID2 = RETRY_PENALTY_UP_IDX[RateID]; + pRaInfo->NscUp += pRaInfo->RTY[0] * RETRY_PENALTY[PenaltyID2][0]; + pRaInfo->NscUp += pRaInfo->RTY[1] * RETRY_PENALTY[PenaltyID2][1]; + pRaInfo->NscUp += pRaInfo->RTY[2] * RETRY_PENALTY[PenaltyID2][2]; + pRaInfo->NscUp += pRaInfo->RTY[3] * RETRY_PENALTY[PenaltyID2][3]; + pRaInfo->NscUp += pRaInfo->RTY[4] * RETRY_PENALTY[PenaltyID2][4]; + if (pRaInfo->NscUp > (pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID2][5])) + pRaInfo->NscUp -= pRaInfo->TOTAL * RETRY_PENALTY[PenaltyID2][5]; + else + pRaInfo->NscUp = 0; + + if ((pRaInfo->NscDown < N_THRESHOLD_LOW[RateID]) || + (pRaInfo->DROP > DROPING_NECESSARY[RateID])) + odm_RateDown_8188E(dm_odm, pRaInfo); + else if (pRaInfo->NscUp > N_THRESHOLD_HIGH[RateID]) + odm_RateUp_8188E(dm_odm, pRaInfo); + + if (pRaInfo->DecisionRate > pRaInfo->HighestRate) + pRaInfo->DecisionRate = pRaInfo->HighestRate; + + if ((pRaInfo->DecisionRate) == (pRaInfo->PreRate)) + DynamicTxRPTTimingCounter += 1; + else + DynamicTxRPTTimingCounter = 0; + + if (DynamicTxRPTTimingCounter >= 4) { + odm_SetTxRPTTiming_8188E(dm_odm, pRaInfo, 1); + DynamicTxRPTTimingCounter = 0; + } + + pRaInfo->PreRate = pRaInfo->DecisionRate; /* YJ, add, 120120 */ + + odm_ResetRaCounter_8188E(pRaInfo); + } +} + +static int odm_ARFBRefresh_8188E(struct odm_dm_struct *dm_odm, struct odm_ra_info *pRaInfo) +{ /* Wilson 2011/10/26 */ + u32 MaskFromReg; + s8 i; + int res; + + switch (pRaInfo->RateID) { + case RATR_INX_WIRELESS_NGB: + pRaInfo->RAUseRate = (pRaInfo->RateMask) & 0x0f8ff015; + break; + case RATR_INX_WIRELESS_NG: + pRaInfo->RAUseRate = (pRaInfo->RateMask) & 0x0f8ff010; + break; + case RATR_INX_WIRELESS_NB: + pRaInfo->RAUseRate = (pRaInfo->RateMask) & 0x0f8ff005; + break; + case RATR_INX_WIRELESS_N: + pRaInfo->RAUseRate = (pRaInfo->RateMask) & 0x0f8ff000; + break; + case RATR_INX_WIRELESS_GB: + pRaInfo->RAUseRate = (pRaInfo->RateMask) & 0x00000ff5; + break; + case RATR_INX_WIRELESS_G: + pRaInfo->RAUseRate = (pRaInfo->RateMask) & 0x00000ff0; + break; + case RATR_INX_WIRELESS_B: + pRaInfo->RAUseRate = (pRaInfo->RateMask) & 0x0000000d; + break; + case 12: + res = rtw_read32(dm_odm->Adapter, REG_ARFR0, &MaskFromReg); + if (res) + return res; + + pRaInfo->RAUseRate = (pRaInfo->RateMask) & MaskFromReg; + break; + case 13: + res = rtw_read32(dm_odm->Adapter, REG_ARFR1, &MaskFromReg); + if (res) + return res; + + pRaInfo->RAUseRate = (pRaInfo->RateMask) & MaskFromReg; + break; + case 14: + res = rtw_read32(dm_odm->Adapter, REG_ARFR2, &MaskFromReg); + if (res) + return res; + + pRaInfo->RAUseRate = (pRaInfo->RateMask) & MaskFromReg; + break; + case 15: + res = rtw_read32(dm_odm->Adapter, REG_ARFR3, &MaskFromReg); + if (res) + return res; + + pRaInfo->RAUseRate = (pRaInfo->RateMask) & MaskFromReg; + break; + default: + pRaInfo->RAUseRate = (pRaInfo->RateMask); + break; + } + /* Highest rate */ + if (pRaInfo->RAUseRate) { + for (i = RATESIZE; i >= 0; i--) { + if ((pRaInfo->RAUseRate) & BIT(i)) { + pRaInfo->HighestRate = i; + break; + } + } + } else { + pRaInfo->HighestRate = 0; + } + /* Lowest rate */ + if (pRaInfo->RAUseRate) { + for (i = 0; i < RATESIZE; i++) { + if ((pRaInfo->RAUseRate) & BIT(i)) { + pRaInfo->LowestRate = i; + break; + } + } + } else { + pRaInfo->LowestRate = 0; + } + if (pRaInfo->HighestRate > 0x13) + pRaInfo->PTModeSS = 3; + else if (pRaInfo->HighestRate > 0x0b) + pRaInfo->PTModeSS = 2; + else if (pRaInfo->HighestRate > 0x03) + pRaInfo->PTModeSS = 1; + else + pRaInfo->PTModeSS = 0; + + if (pRaInfo->DecisionRate > pRaInfo->HighestRate) + pRaInfo->DecisionRate = pRaInfo->HighestRate; + + return 0; +} + +static void odm_PTTryState_8188E(struct odm_ra_info *pRaInfo) +{ + pRaInfo->PTTryState = 0; + switch (pRaInfo->PTModeSS) { + case 3: + if (pRaInfo->DecisionRate >= 0x19) + pRaInfo->PTTryState = 1; + break; + case 2: + if (pRaInfo->DecisionRate >= 0x11) + pRaInfo->PTTryState = 1; + break; + case 1: + if (pRaInfo->DecisionRate >= 0x0a) + pRaInfo->PTTryState = 1; + break; + case 0: + if (pRaInfo->DecisionRate >= 0x03) + pRaInfo->PTTryState = 1; + break; + default: + pRaInfo->PTTryState = 0; + break; + } + + if (pRaInfo->RssiStaRA < 48) { + pRaInfo->PTStage = 0; + } else if (pRaInfo->PTTryState == 1) { + if ((pRaInfo->PTStopCount >= 10) || + (pRaInfo->PTPreRssi > pRaInfo->RssiStaRA + 5) || + (pRaInfo->PTPreRssi < pRaInfo->RssiStaRA - 5) || + (pRaInfo->DecisionRate != pRaInfo->PTPreRate)) { + if (pRaInfo->PTStage == 0) + pRaInfo->PTStage = 1; + else if (pRaInfo->PTStage == 1) + pRaInfo->PTStage = 3; + else + pRaInfo->PTStage = 5; + + pRaInfo->PTPreRssi = pRaInfo->RssiStaRA; + pRaInfo->PTStopCount = 0; + } else { + pRaInfo->RAstage = 0; + pRaInfo->PTStopCount++; + } + } else { + pRaInfo->PTStage = 0; + pRaInfo->RAstage = 0; + } + pRaInfo->PTPreRate = pRaInfo->DecisionRate; +} + +static void odm_PTDecision_8188E(struct odm_ra_info *pRaInfo) +{ + u8 j; + u8 temp_stage; + u32 numsc; + u32 num_total; + u8 stage_id; + + numsc = 0; + num_total = pRaInfo->TOTAL * PT_PENALTY[5]; + for (j = 0; j <= 4; j++) { + numsc += pRaInfo->RTY[j] * PT_PENALTY[j]; + if (numsc > num_total) + break; + } + + j = j >> 1; + temp_stage = (pRaInfo->PTStage + 1) >> 1; + if (temp_stage > j) + stage_id = temp_stage - j; + else + stage_id = 0; + + pRaInfo->PTSmoothFactor = (pRaInfo->PTSmoothFactor >> 1) + (pRaInfo->PTSmoothFactor >> 2) + stage_id * 16 + 2; + if (pRaInfo->PTSmoothFactor > 192) + pRaInfo->PTSmoothFactor = 192; + stage_id = pRaInfo->PTSmoothFactor >> 6; + temp_stage = stage_id * 2; + if (temp_stage != 0) + temp_stage -= 1; + if (pRaInfo->DROP > 3) + temp_stage = 0; + pRaInfo->PTStage = temp_stage; +} + +static void +odm_RATxRPTTimerSetting( + struct odm_dm_struct *dm_odm, + u16 minRptTime +) +{ + if (dm_odm->CurrminRptTime != minRptTime) { + rtw_rpt_timer_cfg_cmd(dm_odm->Adapter, minRptTime); + dm_odm->CurrminRptTime = minRptTime; + } +} + +int ODM_RAInfo_Init(struct odm_dm_struct *dm_odm, u8 macid) +{ + struct odm_ra_info *pRaInfo = &dm_odm->RAInfo[macid]; + u8 WirelessMode = 0xFF; /* invalid value */ + u8 max_rate_idx = 0x13; /* MCS7 */ + if (dm_odm->pWirelessMode) + WirelessMode = *dm_odm->pWirelessMode; + + if (WirelessMode != 0xFF) { + if (WirelessMode & ODM_WM_N24G) + max_rate_idx = 0x13; + else if (WirelessMode & ODM_WM_G) + max_rate_idx = 0x0b; + else if (WirelessMode & ODM_WM_B) + max_rate_idx = 0x03; + } + + pRaInfo->DecisionRate = max_rate_idx; + pRaInfo->PreRate = max_rate_idx; + pRaInfo->HighestRate = max_rate_idx; + pRaInfo->LowestRate = 0; + pRaInfo->RateID = 0; + pRaInfo->RateMask = 0xffffffff; + pRaInfo->RssiStaRA = 0; + pRaInfo->PreRssiStaRA = 0; + pRaInfo->SGIEnable = 0; + pRaInfo->RAUseRate = 0xffffffff; + pRaInfo->NscDown = (N_THRESHOLD_HIGH[0x13] + N_THRESHOLD_LOW[0x13]) / 2; + pRaInfo->NscUp = (N_THRESHOLD_HIGH[0x13] + N_THRESHOLD_LOW[0x13]) / 2; + pRaInfo->RateSGI = 0; + pRaInfo->Active = 1; /* Active is not used at present. by page, 110819 */ + pRaInfo->RptTime = 0x927c; + pRaInfo->DROP = 0; + pRaInfo->RTY[0] = 0; + pRaInfo->RTY[1] = 0; + pRaInfo->RTY[2] = 0; + pRaInfo->RTY[3] = 0; + pRaInfo->RTY[4] = 0; + pRaInfo->TOTAL = 0; + pRaInfo->RAWaitingCounter = 0; + pRaInfo->RAPendingCounter = 0; + pRaInfo->PTActive = 1; /* Active when this STA is use */ + pRaInfo->PTTryState = 0; + pRaInfo->PTStage = 5; /* Need to fill into HW_PWR_STATUS */ + pRaInfo->PTSmoothFactor = 192; + pRaInfo->PTStopCount = 0; + pRaInfo->PTPreRate = 0; + pRaInfo->PTPreRssi = 0; + pRaInfo->PTModeSS = 0; + pRaInfo->RAstage = 0; + return 0; +} + +int ODM_RAInfo_Init_all(struct odm_dm_struct *dm_odm) +{ + u8 macid = 0; + + dm_odm->CurrminRptTime = 0; + + for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) + ODM_RAInfo_Init(dm_odm, macid); + + return 0; +} + +u8 ODM_RA_GetShortGI_8188E(struct odm_dm_struct *dm_odm, u8 macid) +{ + if ((NULL == dm_odm) || (macid >= ODM_ASSOCIATE_ENTRY_NUM)) + return 0; + return dm_odm->RAInfo[macid].RateSGI; +} + +u8 ODM_RA_GetDecisionRate_8188E(struct odm_dm_struct *dm_odm, u8 macid) +{ + u8 DecisionRate = 0; + + if ((NULL == dm_odm) || (macid >= ODM_ASSOCIATE_ENTRY_NUM)) + return 0; + DecisionRate = (dm_odm->RAInfo[macid].DecisionRate); + return DecisionRate; +} + +u8 ODM_RA_GetHwPwrStatus_8188E(struct odm_dm_struct *dm_odm, u8 macid) +{ + u8 PTStage = 5; + + if ((NULL == dm_odm) || (macid >= ODM_ASSOCIATE_ENTRY_NUM)) + return 0; + PTStage = (dm_odm->RAInfo[macid].PTStage); + return PTStage; +} + +void ODM_RA_UpdateRateInfo_8188E(struct odm_dm_struct *dm_odm, u8 macid, u8 RateID, u32 RateMask, u8 SGIEnable) +{ + struct odm_ra_info *pRaInfo = NULL; + + if ((NULL == dm_odm) || (macid >= ODM_ASSOCIATE_ENTRY_NUM)) + return; + + pRaInfo = &dm_odm->RAInfo[macid]; + pRaInfo->RateID = RateID; + pRaInfo->RateMask = RateMask; + pRaInfo->SGIEnable = SGIEnable; + odm_ARFBRefresh_8188E(dm_odm, pRaInfo); +} + +void ODM_RA_SetRSSI_8188E(struct odm_dm_struct *dm_odm, u8 macid, u8 Rssi) +{ + struct odm_ra_info *pRaInfo = NULL; + + if ((NULL == dm_odm) || (macid >= ODM_ASSOCIATE_ENTRY_NUM)) + return; + + pRaInfo = &dm_odm->RAInfo[macid]; + pRaInfo->RssiStaRA = Rssi; +} + +void ODM_RA_Set_TxRPT_Time(struct odm_dm_struct *dm_odm, u16 minRptTime) +{ + rtw_write16(dm_odm->Adapter, REG_TX_RPT_TIME, minRptTime); +} + +void ODM_RA_TxRPT2Handle_8188E(struct odm_dm_struct *dm_odm, u8 *TxRPT_Buf, u16 TxRPT_Len, u32 macid_entry0, u32 macid_entry1) +{ + struct odm_ra_info *pRAInfo = NULL; + u8 MacId = 0; + u8 *pBuffer = NULL; + u32 valid = 0, ItemNum = 0; + u16 minRptTime = 0x927c; + + ItemNum = TxRPT_Len >> 3; + pBuffer = TxRPT_Buf; + + do { + if (MacId >= ODM_ASSOCIATE_ENTRY_NUM) + valid = 0; + else if (MacId >= 32) + valid = (1 << (MacId - 32)) & macid_entry1; + else + valid = (1 << MacId) & macid_entry0; + + pRAInfo = &dm_odm->RAInfo[MacId]; + if (valid) { + pRAInfo->RTY[0] = le16_to_cpup((__le16 *)pBuffer); + pRAInfo->RTY[1] = pBuffer[2]; + pRAInfo->RTY[2] = pBuffer[3]; + pRAInfo->RTY[3] = pBuffer[4]; + pRAInfo->RTY[4] = pBuffer[5]; + pRAInfo->DROP = pBuffer[6]; + pRAInfo->TOTAL = pRAInfo->RTY[0] + pRAInfo->RTY[1] + + pRAInfo->RTY[2] + pRAInfo->RTY[3] + + pRAInfo->RTY[4] + pRAInfo->DROP; + if (pRAInfo->TOTAL != 0) { + if (pRAInfo->PTActive) { + if (pRAInfo->RAstage < 5) + odm_RateDecision_8188E(dm_odm, pRAInfo); + else if (pRAInfo->RAstage == 5) /* Power training try state */ + odm_PTTryState_8188E(pRAInfo); + else /* RAstage == 6 */ + odm_PTDecision_8188E(pRAInfo); + + /* Stage_RA counter */ + if (pRAInfo->RAstage <= 5) + pRAInfo->RAstage++; + else + pRAInfo->RAstage = 0; + } else { + odm_RateDecision_8188E(dm_odm, pRAInfo); + } + } + } + + if (minRptTime > pRAInfo->RptTime) + minRptTime = pRAInfo->RptTime; + + pBuffer += TX_RPT2_ITEM_SIZE; + MacId++; + } while (MacId < ItemNum); + + odm_RATxRPTTimerSetting(dm_odm, minRptTime); +} diff --git a/drivers/staging/r8188eu/hal/HalHWImg8188E_BB.c b/drivers/staging/r8188eu/hal/HalHWImg8188E_BB.c new file mode 100644 index 000000000..23b720572 --- /dev/null +++ b/drivers/staging/r8188eu/hal/HalHWImg8188E_BB.c @@ -0,0 +1,733 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright(c) 2007 - 2011 Realtek Corporation. */ + +#include "../include/rtw_iol.h" + +#define read_next_pair(array, v1, v2, i) \ + do { \ + i += 2; \ + v1 = array[i]; \ + v2 = array[i + 1]; \ + } while (0) + +static bool CheckCondition(const u32 condition, const u32 hex) +{ + u32 _interface = (hex & 0x0000FF00) >> 8; + u32 _platform = (hex & 0x00FF0000) >> 16; + u32 cond = condition; + + if (condition == 0xCDCDCDCD) + return true; + + cond = condition & 0x0000FF00; + cond = cond >> 8; + if ((_interface & cond) == 0 && cond != 0x07) + return false; + + cond = condition & 0x00FF0000; + cond = cond >> 16; + if ((_platform & cond) == 0 && cond != 0x0F) + return false; + return true; +} + +/****************************************************************************** +* AGC_TAB_1T.TXT +******************************************************************************/ + +static u32 array_agc_tab_1t_8188e[] = { + 0xC78, 0xFB000001, + 0xC78, 0xFB010001, + 0xC78, 0xFB020001, + 0xC78, 0xFB030001, + 0xC78, 0xFB040001, + 0xC78, 0xFB050001, + 0xC78, 0xFA060001, + 0xC78, 0xF9070001, + 0xC78, 0xF8080001, + 0xC78, 0xF7090001, + 0xC78, 0xF60A0001, + 0xC78, 0xF50B0001, + 0xC78, 0xF40C0001, + 0xC78, 0xF30D0001, + 0xC78, 0xF20E0001, + 0xC78, 0xF10F0001, + 0xC78, 0xF0100001, + 0xC78, 0xEF110001, + 0xC78, 0xEE120001, + 0xC78, 0xED130001, + 0xC78, 0xEC140001, + 0xC78, 0xEB150001, + 0xC78, 0xEA160001, + 0xC78, 0xE9170001, + 0xC78, 0xE8180001, + 0xC78, 0xE7190001, + 0xC78, 0xE61A0001, + 0xC78, 0xE51B0001, + 0xC78, 0xE41C0001, + 0xC78, 0xE31D0001, + 0xC78, 0xE21E0001, + 0xC78, 0xE11F0001, + 0xC78, 0x8A200001, + 0xC78, 0x89210001, + 0xC78, 0x88220001, + 0xC78, 0x87230001, + 0xC78, 0x86240001, + 0xC78, 0x85250001, + 0xC78, 0x84260001, + 0xC78, 0x83270001, + 0xC78, 0x82280001, + 0xC78, 0x6B290001, + 0xC78, 0x6A2A0001, + 0xC78, 0x692B0001, + 0xC78, 0x682C0001, + 0xC78, 0x672D0001, + 0xC78, 0x662E0001, + 0xC78, 0x652F0001, + 0xC78, 0x64300001, + 0xC78, 0x63310001, + 0xC78, 0x62320001, + 0xC78, 0x61330001, + 0xC78, 0x46340001, + 0xC78, 0x45350001, + 0xC78, 0x44360001, + 0xC78, 0x43370001, + 0xC78, 0x42380001, + 0xC78, 0x41390001, + 0xC78, 0x403A0001, + 0xC78, 0x403B0001, + 0xC78, 0x403C0001, + 0xC78, 0x403D0001, + 0xC78, 0x403E0001, + 0xC78, 0x403F0001, + 0xC78, 0xFB400001, + 0xC78, 0xFB410001, + 0xC78, 0xFB420001, + 0xC78, 0xFB430001, + 0xC78, 0xFB440001, + 0xC78, 0xFB450001, + 0xC78, 0xFB460001, + 0xC78, 0xFB470001, + 0xC78, 0xFB480001, + 0xC78, 0xFA490001, + 0xC78, 0xF94A0001, + 0xC78, 0xF84B0001, + 0xC78, 0xF74C0001, + 0xC78, 0xF64D0001, + 0xC78, 0xF54E0001, + 0xC78, 0xF44F0001, + 0xC78, 0xF3500001, + 0xC78, 0xF2510001, + 0xC78, 0xF1520001, + 0xC78, 0xF0530001, + 0xC78, 0xEF540001, + 0xC78, 0xEE550001, + 0xC78, 0xED560001, + 0xC78, 0xEC570001, + 0xC78, 0xEB580001, + 0xC78, 0xEA590001, + 0xC78, 0xE95A0001, + 0xC78, 0xE85B0001, + 0xC78, 0xE75C0001, + 0xC78, 0xE65D0001, + 0xC78, 0xE55E0001, + 0xC78, 0xE45F0001, + 0xC78, 0xE3600001, + 0xC78, 0xE2610001, + 0xC78, 0xC3620001, + 0xC78, 0xC2630001, + 0xC78, 0xC1640001, + 0xC78, 0x8B650001, + 0xC78, 0x8A660001, + 0xC78, 0x89670001, + 0xC78, 0x88680001, + 0xC78, 0x87690001, + 0xC78, 0x866A0001, + 0xC78, 0x856B0001, + 0xC78, 0x846C0001, + 0xC78, 0x676D0001, + 0xC78, 0x666E0001, + 0xC78, 0x656F0001, + 0xC78, 0x64700001, + 0xC78, 0x63710001, + 0xC78, 0x62720001, + 0xC78, 0x61730001, + 0xC78, 0x60740001, + 0xC78, 0x46750001, + 0xC78, 0x45760001, + 0xC78, 0x44770001, + 0xC78, 0x43780001, + 0xC78, 0x42790001, + 0xC78, 0x417A0001, + 0xC78, 0x407B0001, + 0xC78, 0x407C0001, + 0xC78, 0x407D0001, + 0xC78, 0x407E0001, + 0xC78, 0x407F0001, +}; + +static void odm_ConfigBB_AGC_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Bitmask, u32 Data) +{ + rtl8188e_PHY_SetBBReg(pDM_Odm->Adapter, Addr, Bitmask, Data); + /* Add 1us delay between BB/RF register setting. */ + udelay(1); +} + +int ODM_ReadAndConfig_AGC_TAB_1T_8188E(struct odm_dm_struct *dm_odm) +{ + u32 hex = 0; + u32 i = 0; + u32 arraylen = ARRAY_SIZE(array_agc_tab_1t_8188e); + u32 *array = array_agc_tab_1t_8188e; + bool biol = false; + struct adapter *adapter = dm_odm->Adapter; + struct xmit_frame *pxmit_frame = NULL; + u8 bndy_cnt = 1; + + hex += ODM_ITRF_USB << 8; + hex += ODM_CE << 16; + hex += 0xFF000000; + biol = rtw_IOL_applied(adapter); + + if (biol) { + pxmit_frame = rtw_IOL_accquire_xmit_frame(adapter); + if (!pxmit_frame) { + pr_info("rtw_IOL_accquire_xmit_frame failed\n"); + return -ENOMEM; + } + } + + for (i = 0; i < arraylen; i += 2) { + u32 v1 = array[i]; + u32 v2 = array[i + 1]; + + /* This (offset, data) pair meets the condition. */ + if (v1 < 0xCDCDCDCD) { + if (biol) { + if (rtw_IOL_cmd_boundary_handle(pxmit_frame)) + bndy_cnt++; + rtw_IOL_append_WD_cmd(pxmit_frame, (u16)v1, v2, bMaskDWord); + } else { + odm_ConfigBB_AGC_8188E(dm_odm, v1, bMaskDWord, v2); + } + continue; + } else { + /* This line is the start line of branch. */ + if (!CheckCondition(array[i], hex)) { + /* Discard the following (offset, data) pairs. */ + read_next_pair(array, v1, v2, i); + while (v2 != 0xDEAD && + v2 != 0xCDEF && + v2 != 0xCDCD && i < arraylen - 2) + read_next_pair(array, v1, v2, i); + i -= 2; /* prevent from for-loop += 2 */ + } else { /* Configure matched pairs and skip to end of if-else. */ + read_next_pair(array, v1, v2, i); + while (v2 != 0xDEAD && + v2 != 0xCDEF && + v2 != 0xCDCD && i < arraylen - 2) { + if (biol) { + if (rtw_IOL_cmd_boundary_handle(pxmit_frame)) + bndy_cnt++; + rtw_IOL_append_WD_cmd(pxmit_frame, (u16)v1, v2, bMaskDWord); + } else { + odm_ConfigBB_AGC_8188E(dm_odm, v1, bMaskDWord, v2); + } + read_next_pair(array, v1, v2, i); + } + + while (v2 != 0xDEAD && i < arraylen - 2) + read_next_pair(array, v1, v2, i); + } + } + } + if (biol) { + if (!rtl8188e_IOL_exec_cmds_sync(dm_odm->Adapter, pxmit_frame, 1000, bndy_cnt)) { + printk("~~~ %s IOL_exec_cmds Failed !!!\n", __func__); + return -1; + } + } + return 0; +} + +/****************************************************************************** +* PHY_REG_1T.TXT +******************************************************************************/ + +static u32 array_phy_reg_1t_8188e[] = { + 0x800, 0x80040000, + 0x804, 0x00000003, + 0x808, 0x0000FC00, + 0x80C, 0x0000000A, + 0x810, 0x10001331, + 0x814, 0x020C3D10, + 0x818, 0x02200385, + 0x81C, 0x00000000, + 0x820, 0x01000100, + 0x824, 0x00390204, + 0x828, 0x00000000, + 0x82C, 0x00000000, + 0x830, 0x00000000, + 0x834, 0x00000000, + 0x838, 0x00000000, + 0x83C, 0x00000000, + 0x840, 0x00010000, + 0x844, 0x00000000, + 0x848, 0x00000000, + 0x84C, 0x00000000, + 0x850, 0x00000000, + 0x854, 0x00000000, + 0x858, 0x569A11A9, + 0x85C, 0x01000014, + 0x860, 0x66F60110, + 0x864, 0x061F0649, + 0x868, 0x00000000, + 0x86C, 0x27272700, + 0x870, 0x07000760, + 0x874, 0x25004000, + 0x878, 0x00000808, + 0x87C, 0x00000000, + 0x880, 0xB0000C1C, + 0x884, 0x00000001, + 0x888, 0x00000000, + 0x88C, 0xCCC000C0, + 0x890, 0x00000800, + 0x894, 0xFFFFFFFE, + 0x898, 0x40302010, + 0x89C, 0x00706050, + 0x900, 0x00000000, + 0x904, 0x00000023, + 0x908, 0x00000000, + 0x90C, 0x81121111, + 0x910, 0x00000002, + 0x914, 0x00000201, + 0xA00, 0x00D047C8, + 0xA04, 0x80FF000C, + 0xA08, 0x8C838300, + 0xA0C, 0x2E7F120F, + 0xA10, 0x9500BB78, + 0xA14, 0x1114D028, + 0xA18, 0x00881117, + 0xA1C, 0x89140F00, + 0xA20, 0x1A1B0000, + 0xA24, 0x090E1317, + 0xA28, 0x00000204, + 0xA2C, 0x00D30000, + 0xA70, 0x101FBF00, + 0xA74, 0x00000007, + 0xA78, 0x00000900, + 0xA7C, 0x225B0606, + 0xA80, 0x218075B1, + 0xB2C, 0x80000000, + 0xC00, 0x48071D40, + 0xC04, 0x03A05611, + 0xC08, 0x000000E4, + 0xC0C, 0x6C6C6C6C, + 0xC10, 0x08800000, + 0xC14, 0x40000100, + 0xC18, 0x08800000, + 0xC1C, 0x40000100, + 0xC20, 0x00000000, + 0xC24, 0x00000000, + 0xC28, 0x00000000, + 0xC2C, 0x00000000, + 0xC30, 0x69E9AC47, + 0xC34, 0x469652AF, + 0xC38, 0x49795994, + 0xC3C, 0x0A97971C, + 0xC40, 0x1F7C403F, + 0xC44, 0x000100B7, + 0xC48, 0xEC020107, + 0xC4C, 0x007F037F, + 0xC50, 0x69553420, + 0xC54, 0x43BC0094, + 0xC58, 0x00013169, + 0xC5C, 0x00250492, + 0xC60, 0x00000000, + 0xC64, 0x7112848B, + 0xC68, 0x47C00BFF, + 0xC6C, 0x00000036, + 0xC70, 0x2C7F000D, + 0xC74, 0x020610DB, + 0xC78, 0x0000001F, + 0xC7C, 0x00B91612, + 0xC80, 0x390000E4, + 0xC84, 0x20F60000, + 0xC88, 0x40000100, + 0xC8C, 0x20200000, + 0xC90, 0x00091521, + 0xC94, 0x00000000, + 0xC98, 0x00121820, + 0xC9C, 0x00007F7F, + 0xCA0, 0x00000000, + 0xCA4, 0x000300A0, + 0xCA8, 0x00000000, + 0xCAC, 0x00000000, + 0xCB0, 0x00000000, + 0xCB4, 0x00000000, + 0xCB8, 0x00000000, + 0xCBC, 0x28000000, + 0xCC0, 0x00000000, + 0xCC4, 0x00000000, + 0xCC8, 0x00000000, + 0xCCC, 0x00000000, + 0xCD0, 0x00000000, + 0xCD4, 0x00000000, + 0xCD8, 0x64B22427, + 0xCDC, 0x00766932, + 0xCE0, 0x00222222, + 0xCE4, 0x00000000, + 0xCE8, 0x37644302, + 0xCEC, 0x2F97D40C, + 0xD00, 0x00000740, + 0xD04, 0x00020401, + 0xD08, 0x0000907F, + 0xD0C, 0x20010201, + 0xD10, 0xA0633333, + 0xD14, 0x3333BC43, + 0xD18, 0x7A8F5B6F, + 0xD2C, 0xCC979975, + 0xD30, 0x00000000, + 0xD34, 0x80608000, + 0xD38, 0x00000000, + 0xD3C, 0x00127353, + 0xD40, 0x00000000, + 0xD44, 0x00000000, + 0xD48, 0x00000000, + 0xD4C, 0x00000000, + 0xD50, 0x6437140A, + 0xD54, 0x00000000, + 0xD58, 0x00000282, + 0xD5C, 0x30032064, + 0xD60, 0x4653DE68, + 0xD64, 0x04518A3C, + 0xD68, 0x00002101, + 0xD6C, 0x2A201C16, + 0xD70, 0x1812362E, + 0xD74, 0x322C2220, + 0xD78, 0x000E3C24, + 0xE00, 0x2D2D2D2D, + 0xE04, 0x2D2D2D2D, + 0xE08, 0x0390272D, + 0xE10, 0x2D2D2D2D, + 0xE14, 0x2D2D2D2D, + 0xE18, 0x2D2D2D2D, + 0xE1C, 0x2D2D2D2D, + 0xE28, 0x00000000, + 0xE30, 0x1000DC1F, + 0xE34, 0x10008C1F, + 0xE38, 0x02140102, + 0xE3C, 0x681604C2, + 0xE40, 0x01007C00, + 0xE44, 0x01004800, + 0xE48, 0xFB000000, + 0xE4C, 0x000028D1, + 0xE50, 0x1000DC1F, + 0xE54, 0x10008C1F, + 0xE58, 0x02140102, + 0xE5C, 0x28160D05, + 0xE60, 0x00000008, + 0xE68, 0x001B25A4, + 0xE6C, 0x00C00014, + 0xE70, 0x00C00014, + 0xE74, 0x01000014, + 0xE78, 0x01000014, + 0xE7C, 0x01000014, + 0xE80, 0x01000014, + 0xE84, 0x00C00014, + 0xE88, 0x01000014, + 0xE8C, 0x00C00014, + 0xED0, 0x00C00014, + 0xED4, 0x00C00014, + 0xED8, 0x00C00014, + 0xEDC, 0x00000014, + 0xEE0, 0x00000014, + 0xEEC, 0x01C00014, + 0xF14, 0x00000003, + 0xF4C, 0x00000000, + 0xF00, 0x00000300, +}; + +static void odm_ConfigBB_PHY_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Bitmask, u32 Data) +{ + if (Addr == 0xfe) { + msleep(50); + } else if (Addr == 0xfd) { + mdelay(5); + } else if (Addr == 0xfc) { + mdelay(1); + } else if (Addr == 0xfb) { + udelay(50); + } else if (Addr == 0xfa) { + udelay(5); + } else if (Addr == 0xf9) { + udelay(1); + } else { + if (Addr == 0xa24) + pDM_Odm->RFCalibrateInfo.RegA24 = Data; + rtl8188e_PHY_SetBBReg(pDM_Odm->Adapter, Addr, Bitmask, Data); + + /* Add 1us delay between BB/RF register setting. */ + udelay(1); + } +} + +int ODM_ReadAndConfig_PHY_REG_1T_8188E(struct odm_dm_struct *dm_odm) +{ + u32 hex = 0; + u32 i = 0; + u32 arraylen = ARRAY_SIZE(array_phy_reg_1t_8188e); + u32 *array = array_phy_reg_1t_8188e; + bool biol = false; + struct adapter *adapter = dm_odm->Adapter; + struct xmit_frame *pxmit_frame = NULL; + u8 bndy_cnt = 1; + hex += ODM_ITRF_USB << 8; + hex += ODM_CE << 16; + hex += 0xFF000000; + biol = rtw_IOL_applied(adapter); + + if (biol) { + pxmit_frame = rtw_IOL_accquire_xmit_frame(adapter); + if (!pxmit_frame) { + pr_info("rtw_IOL_accquire_xmit_frame failed\n"); + return -ENOMEM; + } + } + + for (i = 0; i < arraylen; i += 2) { + u32 v1 = array[i]; + u32 v2 = array[i + 1]; + + /* This (offset, data) pair meets the condition. */ + if (v1 < 0xCDCDCDCD) { + if (biol) { + if (rtw_IOL_cmd_boundary_handle(pxmit_frame)) + bndy_cnt++; + if (v1 == 0xfe) { + rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 50); + } else if (v1 == 0xfd) { + rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 5); + } else if (v1 == 0xfc) { + rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 1); + } else if (v1 == 0xfb) { + rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 50); + } else if (v1 == 0xfa) { + rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 5); + } else if (v1 == 0xf9) { + rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 1); + } else { + if (v1 == 0xa24) + dm_odm->RFCalibrateInfo.RegA24 = v2; + rtw_IOL_append_WD_cmd(pxmit_frame, (u16)v1, v2, bMaskDWord); + } + } else { + odm_ConfigBB_PHY_8188E(dm_odm, v1, bMaskDWord, v2); + } + continue; + } else { /* This line is the start line of branch. */ + if (!CheckCondition(array[i], hex)) { + /* Discard the following (offset, data) pairs. */ + read_next_pair(array, v1, v2, i); + while (v2 != 0xDEAD && + v2 != 0xCDEF && + v2 != 0xCDCD && i < arraylen - 2) + read_next_pair(array, v1, v2, i); + i -= 2; /* prevent from for-loop += 2 */ + } else { /* Configure matched pairs and skip to end of if-else. */ + read_next_pair(array, v1, v2, i); + while (v2 != 0xDEAD && + v2 != 0xCDEF && + v2 != 0xCDCD && i < arraylen - 2) { + if (biol) { + if (rtw_IOL_cmd_boundary_handle(pxmit_frame)) + bndy_cnt++; + if (v1 == 0xfe) { + rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 50); + } else if (v1 == 0xfd) { + rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 5); + } else if (v1 == 0xfc) { + rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 1); + } else if (v1 == 0xfb) { + rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 50); + } else if (v1 == 0xfa) { + rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 5); + } else if (v1 == 0xf9) { + rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 1); + } else { + if (v1 == 0xa24) + dm_odm->RFCalibrateInfo.RegA24 = v2; + + rtw_IOL_append_WD_cmd(pxmit_frame, (u16)v1, v2, bMaskDWord); + } + } else { + odm_ConfigBB_PHY_8188E(dm_odm, v1, bMaskDWord, v2); + } + read_next_pair(array, v1, v2, i); + } + + while (v2 != 0xDEAD && i < arraylen - 2) + read_next_pair(array, v1, v2, i); + } + } + } + if (biol) { + if (!rtl8188e_IOL_exec_cmds_sync(dm_odm->Adapter, pxmit_frame, 1000, bndy_cnt)) { + pr_info("~~~ IOL Config %s Failed !!!\n", __func__); + return -1; + } + } + return 0; +} + +/****************************************************************************** +* PHY_REG_PG.TXT +******************************************************************************/ + +static u32 array_phy_reg_pg_8188e[] = { + 0xE00, 0xFFFFFFFF, 0x06070809, + 0xE04, 0xFFFFFFFF, 0x02020405, + 0xE08, 0x0000FF00, 0x00000006, + 0x86C, 0xFFFFFF00, 0x00020400, + 0xE10, 0xFFFFFFFF, 0x08090A0B, + 0xE14, 0xFFFFFFFF, 0x01030607, + 0xE18, 0xFFFFFFFF, 0x08090A0B, + 0xE1C, 0xFFFFFFFF, 0x01030607, + 0xE00, 0xFFFFFFFF, 0x00000000, + 0xE04, 0xFFFFFFFF, 0x00000000, + 0xE08, 0x0000FF00, 0x00000000, + 0x86C, 0xFFFFFF00, 0x00000000, + 0xE10, 0xFFFFFFFF, 0x00000000, + 0xE14, 0xFFFFFFFF, 0x00000000, + 0xE18, 0xFFFFFFFF, 0x00000000, + 0xE1C, 0xFFFFFFFF, 0x00000000, + 0xE00, 0xFFFFFFFF, 0x02020202, + 0xE04, 0xFFFFFFFF, 0x00020202, + 0xE08, 0x0000FF00, 0x00000000, + 0x86C, 0xFFFFFF00, 0x00000000, + 0xE10, 0xFFFFFFFF, 0x04040404, + 0xE14, 0xFFFFFFFF, 0x00020404, + 0xE18, 0xFFFFFFFF, 0x00000000, + 0xE1C, 0xFFFFFFFF, 0x00000000, + 0xE00, 0xFFFFFFFF, 0x02020202, + 0xE04, 0xFFFFFFFF, 0x00020202, + 0xE08, 0x0000FF00, 0x00000000, + 0x86C, 0xFFFFFF00, 0x00000000, + 0xE10, 0xFFFFFFFF, 0x04040404, + 0xE14, 0xFFFFFFFF, 0x00020404, + 0xE18, 0xFFFFFFFF, 0x00000000, + 0xE1C, 0xFFFFFFFF, 0x00000000, + 0xE00, 0xFFFFFFFF, 0x00000000, + 0xE04, 0xFFFFFFFF, 0x00000000, + 0xE08, 0x0000FF00, 0x00000000, + 0x86C, 0xFFFFFF00, 0x00000000, + 0xE10, 0xFFFFFFFF, 0x00000000, + 0xE14, 0xFFFFFFFF, 0x00000000, + 0xE18, 0xFFFFFFFF, 0x00000000, + 0xE1C, 0xFFFFFFFF, 0x00000000, + 0xE00, 0xFFFFFFFF, 0x02020202, + 0xE04, 0xFFFFFFFF, 0x00020202, + 0xE08, 0x0000FF00, 0x00000000, + 0x86C, 0xFFFFFF00, 0x00000000, + 0xE10, 0xFFFFFFFF, 0x04040404, + 0xE14, 0xFFFFFFFF, 0x00020404, + 0xE18, 0xFFFFFFFF, 0x00000000, + 0xE1C, 0xFFFFFFFF, 0x00000000, + 0xE00, 0xFFFFFFFF, 0x00000000, + 0xE04, 0xFFFFFFFF, 0x00000000, + 0xE08, 0x0000FF00, 0x00000000, + 0x86C, 0xFFFFFF00, 0x00000000, + 0xE10, 0xFFFFFFFF, 0x00000000, + 0xE14, 0xFFFFFFFF, 0x00000000, + 0xE18, 0xFFFFFFFF, 0x00000000, + 0xE1C, 0xFFFFFFFF, 0x00000000, + 0xE00, 0xFFFFFFFF, 0x00000000, + 0xE04, 0xFFFFFFFF, 0x00000000, + 0xE08, 0x0000FF00, 0x00000000, + 0x86C, 0xFFFFFF00, 0x00000000, + 0xE10, 0xFFFFFFFF, 0x00000000, + 0xE14, 0xFFFFFFFF, 0x00000000, + 0xE18, 0xFFFFFFFF, 0x00000000, + 0xE1C, 0xFFFFFFFF, 0x00000000, + 0xE00, 0xFFFFFFFF, 0x00000000, + 0xE04, 0xFFFFFFFF, 0x00000000, + 0xE08, 0x0000FF00, 0x00000000, + 0x86C, 0xFFFFFF00, 0x00000000, + 0xE10, 0xFFFFFFFF, 0x00000000, + 0xE14, 0xFFFFFFFF, 0x00000000, + 0xE18, 0xFFFFFFFF, 0x00000000, + 0xE1C, 0xFFFFFFFF, 0x00000000, + 0xE00, 0xFFFFFFFF, 0x00000000, + 0xE04, 0xFFFFFFFF, 0x00000000, + 0xE08, 0x0000FF00, 0x00000000, + 0x86C, 0xFFFFFF00, 0x00000000, + 0xE10, 0xFFFFFFFF, 0x00000000, + 0xE14, 0xFFFFFFFF, 0x00000000, + 0xE18, 0xFFFFFFFF, 0x00000000, + 0xE1C, 0xFFFFFFFF, 0x00000000, + 0xE00, 0xFFFFFFFF, 0x00000000, + 0xE04, 0xFFFFFFFF, 0x00000000, + 0xE08, 0x0000FF00, 0x00000000, + 0x86C, 0xFFFFFF00, 0x00000000, + 0xE10, 0xFFFFFFFF, 0x00000000, + 0xE14, 0xFFFFFFFF, 0x00000000, + 0xE18, 0xFFFFFFFF, 0x00000000, + 0xE1C, 0xFFFFFFFF, 0x00000000, + +}; + +static void odm_ConfigBB_PHY_REG_PG_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Bitmask, + u32 Data) +{ + if (Addr == 0xfe) + msleep(50); + else if (Addr == 0xfd) + mdelay(5); + else if (Addr == 0xfc) + mdelay(1); + else if (Addr == 0xfb) + udelay(50); + else if (Addr == 0xfa) + udelay(5); + else if (Addr == 0xf9) + udelay(1); + else + storePwrIndexDiffRateOffset(pDM_Odm->Adapter, Addr, Bitmask, Data); +} + +void ODM_ReadAndConfig_PHY_REG_PG_8188E(struct odm_dm_struct *dm_odm) +{ + u32 hex; + u32 i = 0; + u32 arraylen = ARRAY_SIZE(array_phy_reg_pg_8188e); + u32 *array = array_phy_reg_pg_8188e; + + hex = ODM_ITRF_USB << 8; + hex += (ODM_CE << 16) + 0xFF000000; + + for (i = 0; i < arraylen; i += 3) { + u32 v1 = array[i]; + u32 v2 = array[i + 1]; + u32 v3 = array[i + 2]; + + /* this line is a line of pure_body */ + if (v1 < 0xCDCDCDCD) { + odm_ConfigBB_PHY_REG_PG_8188E(dm_odm, v1, v2, v3); + continue; + } else { /* this line is the start of branch */ + if (!CheckCondition(array[i], hex)) { + /* don't need the hw_body */ + i += 2; /* skip the pair of expression */ + v1 = array[i]; + v2 = array[i + 1]; + v3 = array[i + 2]; + while (v2 != 0xDEAD) { + i += 3; + v1 = array[i]; + v2 = array[i + 1]; + v3 = array[i + 1]; + } + } + } + } +} diff --git a/drivers/staging/r8188eu/hal/HalHWImg8188E_MAC.c b/drivers/staging/r8188eu/hal/HalHWImg8188E_MAC.c new file mode 100644 index 000000000..da71867bc --- /dev/null +++ b/drivers/staging/r8188eu/hal/HalHWImg8188E_MAC.c @@ -0,0 +1,212 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright(c) 2007 - 2011 Realtek Corporation. */ + +#include "../include/rtw_iol.h" + +static bool Checkcondition(const u32 condition, const u32 hex) +{ + u32 _board = (hex & 0x000000FF); + u32 _interface = (hex & 0x0000FF00) >> 8; + u32 _platform = (hex & 0x00FF0000) >> 16; + u32 cond = condition; + + if (condition == 0xCDCDCDCD) + return true; + + cond = condition & 0x000000FF; + if ((_board == cond) && cond != 0x00) + return false; + + cond = condition & 0x0000FF00; + cond = cond >> 8; + if ((_interface & cond) == 0 && cond != 0x07) + return false; + + cond = condition & 0x00FF0000; + cond = cond >> 16; + if ((_platform & cond) == 0 && cond != 0x0F) + return false; + return true; +} + +/****************************************************************************** +* MAC_REG.TXT +******************************************************************************/ + +static u32 array_MAC_REG_8188E[] = { + 0x026, 0x00000041, + 0x027, 0x00000035, + 0x428, 0x0000000A, + 0x429, 0x00000010, + 0x430, 0x00000000, + 0x431, 0x00000001, + 0x432, 0x00000002, + 0x433, 0x00000004, + 0x434, 0x00000005, + 0x435, 0x00000006, + 0x436, 0x00000007, + 0x437, 0x00000008, + 0x438, 0x00000000, + 0x439, 0x00000000, + 0x43A, 0x00000001, + 0x43B, 0x00000002, + 0x43C, 0x00000004, + 0x43D, 0x00000005, + 0x43E, 0x00000006, + 0x43F, 0x00000007, + 0x440, 0x0000005D, + 0x441, 0x00000001, + 0x442, 0x00000000, + 0x444, 0x00000015, + 0x445, 0x000000F0, + 0x446, 0x0000000F, + 0x447, 0x00000000, + 0x458, 0x00000041, + 0x459, 0x000000A8, + 0x45A, 0x00000072, + 0x45B, 0x000000B9, + 0x460, 0x00000066, + 0x461, 0x00000066, + 0x480, 0x00000008, + 0x4C8, 0x000000FF, + 0x4C9, 0x00000008, + 0x4CC, 0x000000FF, + 0x4CD, 0x000000FF, + 0x4CE, 0x00000001, + 0x4D3, 0x00000001, + 0x500, 0x00000026, + 0x501, 0x000000A2, + 0x502, 0x0000002F, + 0x503, 0x00000000, + 0x504, 0x00000028, + 0x505, 0x000000A3, + 0x506, 0x0000005E, + 0x507, 0x00000000, + 0x508, 0x0000002B, + 0x509, 0x000000A4, + 0x50A, 0x0000005E, + 0x50B, 0x00000000, + 0x50C, 0x0000004F, + 0x50D, 0x000000A4, + 0x50E, 0x00000000, + 0x50F, 0x00000000, + 0x512, 0x0000001C, + 0x514, 0x0000000A, + 0x516, 0x0000000A, + 0x525, 0x0000004F, + 0x550, 0x00000010, + 0x551, 0x00000010, + 0x559, 0x00000002, + 0x55D, 0x000000FF, + 0x605, 0x00000030, + 0x608, 0x0000000E, + 0x609, 0x0000002A, + 0x620, 0x000000FF, + 0x621, 0x000000FF, + 0x622, 0x000000FF, + 0x623, 0x000000FF, + 0x624, 0x000000FF, + 0x625, 0x000000FF, + 0x626, 0x000000FF, + 0x627, 0x000000FF, + 0x652, 0x00000020, + 0x63C, 0x0000000A, + 0x63D, 0x0000000A, + 0x63E, 0x0000000E, + 0x63F, 0x0000000E, + 0x640, 0x00000040, + 0x66E, 0x00000005, + 0x700, 0x00000021, + 0x701, 0x00000043, + 0x702, 0x00000065, + 0x703, 0x00000087, + 0x708, 0x00000021, + 0x709, 0x00000043, + 0x70A, 0x00000065, + 0x70B, 0x00000087, +}; + +static void odm_ConfigMAC_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u8 Data) +{ + rtw_write8(pDM_Odm->Adapter, Addr, Data); +} + +int ODM_ReadAndConfig_MAC_REG_8188E(struct odm_dm_struct *dm_odm) +{ + #define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = array[i]; v2 = array[i + 1]; } while (0) + + u32 hex = 0; + u32 i; + u32 array_len = ARRAY_SIZE(array_MAC_REG_8188E); + u32 *array = array_MAC_REG_8188E; + bool biol = false; + + struct adapter *adapt = dm_odm->Adapter; + struct xmit_frame *pxmit_frame = NULL; + u8 bndy_cnt = 1; + hex += ODM_ITRF_USB << 8; + hex += ODM_CE << 16; + hex += 0xFF000000; + + biol = rtw_IOL_applied(adapt); + + if (biol) { + pxmit_frame = rtw_IOL_accquire_xmit_frame(adapt); + if (!pxmit_frame) { + pr_info("rtw_IOL_accquire_xmit_frame failed\n"); + return -ENOMEM; + } + } + + for (i = 0; i < array_len; i += 2) { + u32 v1 = array[i]; + u32 v2 = array[i + 1]; + + /* This (offset, data) pair meets the condition. */ + if (v1 < 0xCDCDCDCD) { + if (biol) { + if (rtw_IOL_cmd_boundary_handle(pxmit_frame)) + bndy_cnt++; + rtw_IOL_append_WB_cmd(pxmit_frame, (u16)v1, (u8)v2, 0xFF); + } else { + odm_ConfigMAC_8188E(dm_odm, v1, (u8)v2); + } + continue; + } else { /* This line is the start line of branch. */ + if (!Checkcondition(array[i], hex)) { + /* Discard the following (offset, data) pairs. */ + READ_NEXT_PAIR(v1, v2, i); + while (v2 != 0xDEAD && + v2 != 0xCDEF && + v2 != 0xCDCD && i < array_len - 2) { + READ_NEXT_PAIR(v1, v2, i); + } + i -= 2; /* prevent from for-loop += 2 */ + } else { /* Configure matched pairs and skip to end of if-else. */ + READ_NEXT_PAIR(v1, v2, i); + while (v2 != 0xDEAD && + v2 != 0xCDEF && + v2 != 0xCDCD && i < array_len - 2) { + if (biol) { + if (rtw_IOL_cmd_boundary_handle(pxmit_frame)) + bndy_cnt++; + rtw_IOL_append_WB_cmd(pxmit_frame, (u16)v1, (u8)v2, 0xFF); + } else { + odm_ConfigMAC_8188E(dm_odm, v1, (u8)v2); + } + + READ_NEXT_PAIR(v1, v2, i); + } + while (v2 != 0xDEAD && i < array_len - 2) + READ_NEXT_PAIR(v1, v2, i); + } + } + } + if (biol) { + if (!rtl8188e_IOL_exec_cmds_sync(dm_odm->Adapter, pxmit_frame, 1000, bndy_cnt)) { + pr_info("~~~ MAC IOL_exec_cmds Failed !!!\n"); + return -1; + } + } + return 0; +} diff --git a/drivers/staging/r8188eu/hal/HalHWImg8188E_RF.c b/drivers/staging/r8188eu/hal/HalHWImg8188E_RF.c new file mode 100644 index 000000000..a4c3d3d14 --- /dev/null +++ b/drivers/staging/r8188eu/hal/HalHWImg8188E_RF.c @@ -0,0 +1,269 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright(c) 2007 - 2011 Realtek Corporation. */ + +#include "../include/rtw_iol.h" + +static bool CheckCondition(const u32 Condition, const u32 Hex) +{ + u32 _interface = (Hex & 0x0000FF00) >> 8; + u32 _platform = (Hex & 0x00FF0000) >> 16; + u32 cond = Condition; + + if (Condition == 0xCDCDCDCD) + return true; + + cond = Condition & 0x0000FF00; + cond = cond >> 8; + if ((_interface & cond) == 0 && cond != 0x07) + return false; + + cond = Condition & 0x00FF0000; + cond = cond >> 16; + if ((_platform & cond) == 0 && cond != 0x0F) + return false; + return true; +} + +/****************************************************************************** +* RadioA_1T.TXT +******************************************************************************/ + +static u32 Array_RadioA_1T_8188E[] = { + 0x000, 0x00030000, + 0x008, 0x00084000, + 0x018, 0x00000407, + 0x019, 0x00000012, + 0x01E, 0x00080009, + 0x01F, 0x00000880, + 0x02F, 0x0001A060, + 0x03F, 0x00000000, + 0x042, 0x000060C0, + 0x057, 0x000D0000, + 0x058, 0x000BE180, + 0x067, 0x00001552, + 0x083, 0x00000000, + 0x0B0, 0x000FF8FC, + 0x0B1, 0x00054400, + 0x0B2, 0x000CCC19, + 0x0B4, 0x00043003, + 0x0B6, 0x0004953E, + 0x0B7, 0x0001C718, + 0x0B8, 0x000060FF, + 0x0B9, 0x00080001, + 0x0BA, 0x00040000, + 0x0BB, 0x00000400, + 0x0BF, 0x000C0000, + 0x0C2, 0x00002400, + 0x0C3, 0x00000009, + 0x0C4, 0x00040C91, + 0x0C5, 0x00099999, + 0x0C6, 0x000000A3, + 0x0C7, 0x00088820, + 0x0C8, 0x00076C06, + 0x0C9, 0x00000000, + 0x0CA, 0x00080000, + 0x0DF, 0x00000180, + 0x0EF, 0x000001A0, + 0x051, 0x0006B27D, + 0xFF0F041F, 0xABCD, + 0x052, 0x0007E4DD, + 0xCDCDCDCD, 0xCDCD, + 0x052, 0x0007E49D, + 0xFF0F041F, 0xDEAD, + 0x053, 0x00000073, + 0x056, 0x00051FF3, + 0x035, 0x00000086, + 0x035, 0x00000186, + 0x035, 0x00000286, + 0x036, 0x00001C25, + 0x036, 0x00009C25, + 0x036, 0x00011C25, + 0x036, 0x00019C25, + 0x0B6, 0x00048538, + 0x018, 0x00000C07, + 0x05A, 0x0004BD00, + 0x019, 0x000739D0, + 0x034, 0x0000ADF3, + 0x034, 0x00009DF0, + 0x034, 0x00008DED, + 0x034, 0x00007DEA, + 0x034, 0x00006DE7, + 0x034, 0x000054EE, + 0x034, 0x000044EB, + 0x034, 0x000034E8, + 0x034, 0x0000246B, + 0x034, 0x00001468, + 0x034, 0x0000006D, + 0x000, 0x00030159, + 0x084, 0x00068200, + 0x086, 0x000000CE, + 0x087, 0x00048A00, + 0x08E, 0x00065540, + 0x08F, 0x00088000, + 0x0EF, 0x000020A0, + 0x03B, 0x000F02B0, + 0x03B, 0x000EF7B0, + 0x03B, 0x000D4FB0, + 0x03B, 0x000CF060, + 0x03B, 0x000B0090, + 0x03B, 0x000A0080, + 0x03B, 0x00090080, + 0x03B, 0x0008F780, + 0x03B, 0x000722B0, + 0x03B, 0x0006F7B0, + 0x03B, 0x00054FB0, + 0x03B, 0x0004F060, + 0x03B, 0x00030090, + 0x03B, 0x00020080, + 0x03B, 0x00010080, + 0x03B, 0x0000F780, + 0x0EF, 0x000000A0, + 0x000, 0x00010159, + 0x018, 0x0000F407, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0x01F, 0x00080003, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0x01E, 0x00000001, + 0x01F, 0x00080000, + 0x000, 0x00033E60, +}; + +static void odm_ConfigRFReg_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, + u32 Data, u32 RegAddr) +{ + if (Addr == 0xffe) { + msleep(50); + } else if (Addr == 0xfd) { + mdelay(5); + } else if (Addr == 0xfc) { + mdelay(1); + } else if (Addr == 0xfb) { + udelay(50); + } else if (Addr == 0xfa) { + udelay(5); + } else if (Addr == 0xf9) { + udelay(1); + } else { + rtl8188e_PHY_SetRFReg(pDM_Odm->Adapter, RegAddr, bRFRegOffsetMask, Data); + /* Add 1us delay between BB/RF register setting. */ + udelay(1); + } +} + +static void odm_ConfigRF_RadioA_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Data) +{ + u32 content = 0x1000; /* RF_Content: radioa_txt */ + u32 maskforPhySet = (u32)(content & 0xE000); + + odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, Addr | maskforPhySet); +} + +int ODM_ReadAndConfig_RadioA_1T_8188E(struct odm_dm_struct *pDM_Odm) +{ + #define READ_NEXT_PAIR(v1, v2, i) do \ + { i += 2; v1 = Array[i]; \ + v2 = Array[i + 1]; } while (0) + + u32 hex = 0; + u32 i = 0; + u32 ArrayLen = ARRAY_SIZE(Array_RadioA_1T_8188E); + u32 *Array = Array_RadioA_1T_8188E; + bool biol = false; + struct adapter *Adapter = pDM_Odm->Adapter; + struct xmit_frame *pxmit_frame = NULL; + u8 bndy_cnt = 1; + + hex += ODM_ITRF_USB << 8; + hex += ODM_CE << 16; + hex += 0xFF000000; + biol = rtw_IOL_applied(Adapter); + + if (biol) { + pxmit_frame = rtw_IOL_accquire_xmit_frame(Adapter); + if (!pxmit_frame) { + pr_info("rtw_IOL_accquire_xmit_frame failed\n"); + return -ENOMEM; + } + } + + for (i = 0; i < ArrayLen; i += 2) { + u32 v1 = Array[i]; + u32 v2 = Array[i + 1]; + + /* This (offset, data) pair meets the condition. */ + if (v1 < 0xCDCDCDCD) { + if (biol) { + if (rtw_IOL_cmd_boundary_handle(pxmit_frame)) + bndy_cnt++; + + if (v1 == 0xffe) + rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 50); + else if (v1 == 0xfd) + rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 5); + else if (v1 == 0xfc) + rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 1); + else if (v1 == 0xfb) + rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 50); + else if (v1 == 0xfa) + rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 5); + else if (v1 == 0xf9) + rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 1); + else + rtw_IOL_append_WRF_cmd(pxmit_frame, RF_PATH_A, (u16)v1, v2, bRFRegOffsetMask); + } else { + odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2); + } + continue; + } else { /* This line is the start line of branch. */ + if (!CheckCondition(Array[i], hex)) { + /* Discard the following (offset, data) pairs. */ + READ_NEXT_PAIR(v1, v2, i); + while (v2 != 0xDEAD && + v2 != 0xCDEF && + v2 != 0xCDCD && i < ArrayLen - 2) + READ_NEXT_PAIR(v1, v2, i); + i -= 2; /* prevent from for-loop += 2 */ + } else { /* Configure matched pairs and skip to end of if-else. */ + READ_NEXT_PAIR(v1, v2, i); + while (v2 != 0xDEAD && + v2 != 0xCDEF && + v2 != 0xCDCD && i < ArrayLen - 2) { + if (biol) { + if (rtw_IOL_cmd_boundary_handle(pxmit_frame)) + bndy_cnt++; + + if (v1 == 0xffe) + rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 50); + else if (v1 == 0xfd) + rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 5); + else if (v1 == 0xfc) + rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 1); + else if (v1 == 0xfb) + rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 50); + else if (v1 == 0xfa) + rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 5); + else if (v1 == 0xf9) + rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 1); + else + rtw_IOL_append_WRF_cmd(pxmit_frame, RF_PATH_A, (u16)v1, v2, bRFRegOffsetMask); + } else { + odm_ConfigRF_RadioA_8188E(pDM_Odm, v1, v2); + } + READ_NEXT_PAIR(v1, v2, i); + } + + while (v2 != 0xDEAD && i < ArrayLen - 2) + READ_NEXT_PAIR(v1, v2, i); + } + } + } + if (biol) { + if (!rtl8188e_IOL_exec_cmds_sync(pDM_Odm->Adapter, pxmit_frame, 1000, bndy_cnt)) { + pr_info("~~~ IOL Config %s Failed !!!\n", __func__); + return -1; + } + } + return 0; +} diff --git a/drivers/staging/r8188eu/hal/HalPhyRf_8188e.c b/drivers/staging/r8188eu/hal/HalPhyRf_8188e.c new file mode 100644 index 000000000..525deab10 --- /dev/null +++ b/drivers/staging/r8188eu/hal/HalPhyRf_8188e.c @@ -0,0 +1,908 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright(c) 2007 - 2011 Realtek Corporation. */ + +#include "../include/drv_types.h" + +/*---------------------------Define Local Constant---------------------------*/ +/* 2010/04/25 MH Define the max tx power tracking tx agc power. */ +#define ODM_TXPWRTRACK_MAX_IDX_88E 6 + +/*---------------------------Define Local Constant---------------------------*/ + +/* 3============================================================ */ +/* 3 Tx Power Tracking */ +/* 3============================================================ */ +/*----------------------------------------------------------------------------- + * Function: ODM_TxPwrTrackAdjust88E() + * + * Overview: 88E we can not write 0xc80/c94/c4c/ 0xa2x. Instead of write TX agc. + * No matter OFDM & CCK use the same method. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 04/23/2012 MHC Create Version 0. + * 04/23/2012 MHC Adjust TX agc directly not throughput BB digital. + * + *---------------------------------------------------------------------------*/ +void ODM_TxPwrTrackAdjust88E(struct odm_dm_struct *dm_odm, u8 Type,/* 0 = OFDM, 1 = CCK */ + u8 *pDirection, /* 1 = +(increase) 2 = -(decrease) */ + u32 *pOutWriteVal /* Tx tracking CCK/OFDM BB swing index adjust */ + ) +{ + u8 pwr_value = 0; + /* Tx power tracking BB swing table. */ + /* The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB */ + if (Type == 0) { /* For OFDM afjust */ + if (dm_odm->BbSwingIdxOfdm <= dm_odm->BbSwingIdxOfdmBase) { + *pDirection = 1; + pwr_value = (dm_odm->BbSwingIdxOfdmBase - dm_odm->BbSwingIdxOfdm); + } else { + *pDirection = 2; + pwr_value = (dm_odm->BbSwingIdxOfdm - dm_odm->BbSwingIdxOfdmBase); + } + } else if (Type == 1) { /* For CCK adjust. */ + if (dm_odm->BbSwingIdxCck <= dm_odm->BbSwingIdxCckBase) { + *pDirection = 1; + pwr_value = (dm_odm->BbSwingIdxCckBase - dm_odm->BbSwingIdxCck); + } else { + *pDirection = 2; + pwr_value = (dm_odm->BbSwingIdxCck - dm_odm->BbSwingIdxCckBase); + } + } + + /* */ + /* 2012/04/25 MH According to Ed/Luke.Lees estimate for EVM the max tx power tracking */ + /* need to be less than 6 power index for 88E. */ + /* */ + if (pwr_value >= ODM_TXPWRTRACK_MAX_IDX_88E && *pDirection == 1) + pwr_value = ODM_TXPWRTRACK_MAX_IDX_88E; + + *pOutWriteVal = pwr_value | (pwr_value << 8) | (pwr_value << 16) | (pwr_value << 24); +} /* ODM_TxPwrTrackAdjust88E */ + +/*----------------------------------------------------------------------------- + * Function: odm_TxPwrTrackSetPwr88E() + * + * Overview: 88E change all channel tx power accordign to flag. + * OFDM & CCK are all different. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 04/23/2012 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +static void odm_TxPwrTrackSetPwr88E(struct odm_dm_struct *dm_odm) +{ + if (dm_odm->BbSwingFlagOfdm || dm_odm->BbSwingFlagCck) { + PHY_SetTxPowerLevel8188E(dm_odm->Adapter, *dm_odm->pChannel); + dm_odm->BbSwingFlagOfdm = false; + dm_odm->BbSwingFlagCck = false; + } +} /* odm_TxPwrTrackSetPwr88E */ + +/* 091212 chiyokolin */ +void +odm_TXPowerTrackingCallback_ThermalMeter_8188E( + struct adapter *Adapter + ) +{ + struct hal_data_8188e *pHalData = &Adapter->haldata; + u8 ThermalValue = 0, delta, delta_LCK, delta_IQK, offset; + u8 ThermalValue_AVG_count = 0; + u32 ThermalValue_AVG = 0; + s32 ele_D, TempCCk; + s8 OFDM_index, CCK_index = 0; + s8 OFDM_index_old = 0, CCK_index_old = 0; + u32 i = 0, j = 0; + + u8 OFDM_min_index = 6; /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */ + s8 OFDM_index_mapping[2][index_mapping_NUM_88E] = { + {0, 0, 2, 3, 4, 4, /* 2.4G, decrease power */ + 5, 6, 7, 7, 8, 9, + 10, 10, 11}, /* For lower temperature, 20120220 updated on 20120220. */ + {0, 0, -1, -2, -3, -4, /* 2.4G, increase power */ + -4, -4, -4, -5, -7, -8, + -9, -9, -10}, + }; + u8 Thermal_mapping[2][index_mapping_NUM_88E] = { + {0, 2, 4, 6, 8, 10, /* 2.4G, decrease power */ + 12, 14, 16, 18, 20, 22, + 24, 26, 27}, + {0, 2, 4, 6, 8, 10, /* 2.4G,, increase power */ + 12, 14, 16, 18, 20, 22, + 25, 25, 25}, + }; + struct odm_dm_struct *dm_odm = &pHalData->odmpriv; + + /* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */ + odm_TxPwrTrackSetPwr88E(dm_odm); + + /* <Kordan> RFCalibrateInfo.RegA24 will be initialized when ODM HW configuring, but MP configures with para files. */ + dm_odm->RFCalibrateInfo.RegA24 = 0x090e1317; + + ThermalValue = (u8)rtl8188e_PHY_QueryRFReg(Adapter, RF_T_METER_88E, 0xfc00); /* 0x42: RF Reg[15:10] 88E */ + + if (ThermalValue) { + /* Query OFDM path A default setting */ + ele_D = rtl8188e_PHY_QueryBBReg(Adapter, rOFDM0_XATxIQImbalance, bMaskDWord) & bMaskOFDM_D; + for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) { /* find the index */ + if (ele_D == (OFDMSwingTable[i] & bMaskOFDM_D)) { + OFDM_index_old = (u8)i; + dm_odm->BbSwingIdxOfdmBase = (u8)i; + break; + } + } + + /* Query CCK default setting From 0xa24 */ + TempCCk = dm_odm->RFCalibrateInfo.RegA24; + + for (i = 0; i < CCK_TABLE_SIZE; i++) { + if (memcmp((void *)&TempCCk, (void *)&cck_swing_table[i][2], 4)) { + CCK_index_old = (u8)i; + dm_odm->BbSwingIdxCckBase = (u8)i; + break; + } + } + + if (!dm_odm->RFCalibrateInfo.ThermalValue) { + dm_odm->RFCalibrateInfo.ThermalValue = pHalData->EEPROMThermalMeter; + dm_odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue; + dm_odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue; + + dm_odm->RFCalibrateInfo.OFDM_index = OFDM_index_old; + dm_odm->RFCalibrateInfo.CCK_index = CCK_index_old; + } + + /* calculate average thermal meter */ + dm_odm->RFCalibrateInfo.ThermalValue_AVG[dm_odm->RFCalibrateInfo.ThermalValue_AVG_index] = ThermalValue; + dm_odm->RFCalibrateInfo.ThermalValue_AVG_index++; + if (dm_odm->RFCalibrateInfo.ThermalValue_AVG_index == AVG_THERMAL_NUM_88E) + dm_odm->RFCalibrateInfo.ThermalValue_AVG_index = 0; + + for (i = 0; i < AVG_THERMAL_NUM_88E; i++) { + if (dm_odm->RFCalibrateInfo.ThermalValue_AVG[i]) { + ThermalValue_AVG += dm_odm->RFCalibrateInfo.ThermalValue_AVG[i]; + ThermalValue_AVG_count++; + } + } + + if (ThermalValue_AVG_count) + ThermalValue = (u8)(ThermalValue_AVG / ThermalValue_AVG_count); + + if (dm_odm->RFCalibrateInfo.bReloadtxpowerindex) { + delta = ThermalValue > pHalData->EEPROMThermalMeter ? + (ThermalValue - pHalData->EEPROMThermalMeter) : + (pHalData->EEPROMThermalMeter - ThermalValue); + dm_odm->RFCalibrateInfo.bReloadtxpowerindex = false; + dm_odm->RFCalibrateInfo.bDoneTxpower = false; + } else if (dm_odm->RFCalibrateInfo.bDoneTxpower) { + delta = (ThermalValue > dm_odm->RFCalibrateInfo.ThermalValue) ? + (ThermalValue - dm_odm->RFCalibrateInfo.ThermalValue) : + (dm_odm->RFCalibrateInfo.ThermalValue - ThermalValue); + } else { + delta = ThermalValue > pHalData->EEPROMThermalMeter ? + (ThermalValue - pHalData->EEPROMThermalMeter) : + (pHalData->EEPROMThermalMeter - ThermalValue); + } + delta_LCK = (ThermalValue > dm_odm->RFCalibrateInfo.ThermalValue_LCK) ? + (ThermalValue - dm_odm->RFCalibrateInfo.ThermalValue_LCK) : + (dm_odm->RFCalibrateInfo.ThermalValue_LCK - ThermalValue); + delta_IQK = (ThermalValue > dm_odm->RFCalibrateInfo.ThermalValue_IQK) ? + (ThermalValue - dm_odm->RFCalibrateInfo.ThermalValue_IQK) : + (dm_odm->RFCalibrateInfo.ThermalValue_IQK - ThermalValue); + + if ((delta_LCK >= 8)) { /* Delta temperature is equal to or larger than 20 centigrade. */ + dm_odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue; + PHY_LCCalibrate_8188E(Adapter); + } + + if (delta > 0 && dm_odm->RFCalibrateInfo.TxPowerTrackControl) { + delta = ThermalValue > pHalData->EEPROMThermalMeter ? + (ThermalValue - pHalData->EEPROMThermalMeter) : + (pHalData->EEPROMThermalMeter - ThermalValue); + /* calculate new OFDM / CCK offset */ + if (ThermalValue > pHalData->EEPROMThermalMeter) + j = 1; + else + j = 0; + for (offset = 0; offset < index_mapping_NUM_88E; offset++) { + if (delta < Thermal_mapping[j][offset]) { + if (offset != 0) + offset--; + break; + } + } + if (offset >= index_mapping_NUM_88E) + offset = index_mapping_NUM_88E - 1; + OFDM_index = dm_odm->RFCalibrateInfo.OFDM_index + OFDM_index_mapping[j][offset]; + CCK_index = dm_odm->RFCalibrateInfo.CCK_index + OFDM_index_mapping[j][offset]; + + if (OFDM_index > OFDM_TABLE_SIZE_92D - 1) + OFDM_index = OFDM_TABLE_SIZE_92D - 1; + else if (OFDM_index < OFDM_min_index) + OFDM_index = OFDM_min_index; + + if (CCK_index > CCK_TABLE_SIZE - 1) + CCK_index = CCK_TABLE_SIZE - 1; + else if (CCK_index < 0) + CCK_index = 0; + + /* 2 temporarily remove bNOPG */ + /* Config by SwingTable */ + if (dm_odm->RFCalibrateInfo.TxPowerTrackControl) { + dm_odm->RFCalibrateInfo.bDoneTxpower = true; + + /* Revse TX power table. */ + dm_odm->BbSwingIdxOfdm = (u8)OFDM_index; + dm_odm->BbSwingIdxCck = (u8)CCK_index; + + if (dm_odm->BbSwingIdxOfdmCurrent != dm_odm->BbSwingIdxOfdm) { + dm_odm->BbSwingIdxOfdmCurrent = dm_odm->BbSwingIdxOfdm; + dm_odm->BbSwingFlagOfdm = true; + } + + if (dm_odm->BbSwingIdxCckCurrent != dm_odm->BbSwingIdxCck) { + dm_odm->BbSwingIdxCckCurrent = dm_odm->BbSwingIdxCck; + dm_odm->BbSwingFlagCck = true; + } + } + } + + if (delta_IQK >= 8) { /* Delta temperature is equal to or larger than 20 centigrade. */ + dm_odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue; + PHY_IQCalibrate_8188E(Adapter, false); + } + /* update thermal meter value */ + if (dm_odm->RFCalibrateInfo.TxPowerTrackControl) + dm_odm->RFCalibrateInfo.ThermalValue = ThermalValue; + } +} + +/* 1 7. IQK */ +#define MAX_TOLERANCE 5 +#define IQK_DELAY_TIME 1 /* ms */ + +static u8 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ +phy_PathA_IQK_8188E(struct adapter *adapt) +{ + u32 regeac, regE94, regE9C; + u8 result = 0x00; + + /* 1 Tx IQK */ + /* path-A IQK setting */ + rtl8188e_PHY_SetBBReg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c); + rtl8188e_PHY_SetBBReg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c); + rtl8188e_PHY_SetBBReg(adapt, rTx_IQK_PI_A, bMaskDWord, 0x8214032a); + rtl8188e_PHY_SetBBReg(adapt, rRx_IQK_PI_A, bMaskDWord, 0x28160000); + + /* LO calibration setting */ + rtl8188e_PHY_SetBBReg(adapt, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); + + /* One shot, path A LOK & IQK */ + rtl8188e_PHY_SetBBReg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + rtl8188e_PHY_SetBBReg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + /* delay x ms */ + /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */ + mdelay(IQK_DELAY_TIME_88E); + + /* Check failed */ + regeac = rtl8188e_PHY_QueryBBReg(adapt, rRx_Power_After_IQK_A_2, bMaskDWord); + regE94 = rtl8188e_PHY_QueryBBReg(adapt, rTx_Power_Before_IQK_A, bMaskDWord); + regE9C = rtl8188e_PHY_QueryBBReg(adapt, rTx_Power_After_IQK_A, bMaskDWord); + + if (!(regeac & BIT(28)) && + (((regE94 & 0x03FF0000) >> 16) != 0x142) && + (((regE9C & 0x03FF0000) >> 16) != 0x42)) + result |= 0x01; + return result; +} + +static u8 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ +phy_PathA_RxIQK(struct adapter *adapt) +{ + u32 regeac, regE94, regE9C, regEA4, u4tmp; + u8 result = 0x00; + + /* 1 Get TXIMR setting */ + /* modify RXIQK mode table */ + rtl8188e_PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000); + rtl8188e_PHY_SetRFReg(adapt, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); + rtl8188e_PHY_SetRFReg(adapt, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + rtl8188e_PHY_SetRFReg(adapt, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + rtl8188e_PHY_SetRFReg(adapt, RF_TXPA_G2, bRFRegOffsetMask, 0xf117B); + + /* PA,PAD off */ + rtl8188e_PHY_SetRFReg(adapt, 0xdf, bRFRegOffsetMask, 0x980); + rtl8188e_PHY_SetRFReg(adapt, 0x56, bRFRegOffsetMask, 0x51000); + + rtl8188e_PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000); + + /* IQK setting */ + rtl8188e_PHY_SetBBReg(adapt, rTx_IQK, bMaskDWord, 0x01007c00); + rtl8188e_PHY_SetBBReg(adapt, rRx_IQK, bMaskDWord, 0x81004800); + + /* path-A IQK setting */ + rtl8188e_PHY_SetBBReg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c); + rtl8188e_PHY_SetBBReg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c); + rtl8188e_PHY_SetBBReg(adapt, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f); + rtl8188e_PHY_SetBBReg(adapt, rRx_IQK_PI_A, bMaskDWord, 0x28160000); + + /* LO calibration setting */ + rtl8188e_PHY_SetBBReg(adapt, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + + /* One shot, path A LOK & IQK */ + rtl8188e_PHY_SetBBReg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + rtl8188e_PHY_SetBBReg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + /* delay x ms */ + mdelay(IQK_DELAY_TIME_88E); + + /* Check failed */ + regeac = rtl8188e_PHY_QueryBBReg(adapt, rRx_Power_After_IQK_A_2, bMaskDWord); + regE94 = rtl8188e_PHY_QueryBBReg(adapt, rTx_Power_Before_IQK_A, bMaskDWord); + regE9C = rtl8188e_PHY_QueryBBReg(adapt, rTx_Power_After_IQK_A, bMaskDWord); + + if (!(regeac & BIT(28)) && + (((regE94 & 0x03FF0000) >> 16) != 0x142) && + (((regE9C & 0x03FF0000) >> 16) != 0x42)) + result |= 0x01; + else /* if Tx not OK, ignore Rx */ + return result; + + u4tmp = 0x80007C00 | (regE94 & 0x3FF0000) | ((regE9C & 0x3FF0000) >> 16); + rtl8188e_PHY_SetBBReg(adapt, rTx_IQK, bMaskDWord, u4tmp); + + /* 1 RX IQK */ + /* modify RXIQK mode table */ + rtl8188e_PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000); + rtl8188e_PHY_SetRFReg(adapt, RF_WE_LUT, bRFRegOffsetMask, 0x800a0); + rtl8188e_PHY_SetRFReg(adapt, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + rtl8188e_PHY_SetRFReg(adapt, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + rtl8188e_PHY_SetRFReg(adapt, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ffa); + rtl8188e_PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000); + + /* IQK setting */ + rtl8188e_PHY_SetBBReg(adapt, rRx_IQK, bMaskDWord, 0x01004800); + + /* path-A IQK setting */ + rtl8188e_PHY_SetBBReg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + rtl8188e_PHY_SetBBReg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + rtl8188e_PHY_SetBBReg(adapt, rTx_IQK_PI_A, bMaskDWord, 0x82160c05); + rtl8188e_PHY_SetBBReg(adapt, rRx_IQK_PI_A, bMaskDWord, 0x28160c1f); + + /* LO calibration setting */ + rtl8188e_PHY_SetBBReg(adapt, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + + /* One shot, path A LOK & IQK */ + rtl8188e_PHY_SetBBReg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + rtl8188e_PHY_SetBBReg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + /* delay x ms */ + /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */ + mdelay(IQK_DELAY_TIME_88E); + + /* Check failed */ + regeac = rtl8188e_PHY_QueryBBReg(adapt, rRx_Power_After_IQK_A_2, bMaskDWord); + regE94 = rtl8188e_PHY_QueryBBReg(adapt, rTx_Power_Before_IQK_A, bMaskDWord); + regE9C = rtl8188e_PHY_QueryBBReg(adapt, rTx_Power_After_IQK_A, bMaskDWord); + regEA4 = rtl8188e_PHY_QueryBBReg(adapt, rRx_Power_Before_IQK_A_2, bMaskDWord); + + /* reload RF 0xdf */ + rtl8188e_PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000); + rtl8188e_PHY_SetRFReg(adapt, 0xdf, bRFRegOffsetMask, 0x180); + + if (!(regeac & BIT(27)) && /* if Tx is OK, check whether Rx is OK */ + (((regEA4 & 0x03FF0000) >> 16) != 0x132) && + (((regeac & 0x03FF0000) >> 16) != 0x36)) + result |= 0x02; + + return result; +} + +static void patha_fill_iqk(struct adapter *adapt, bool iqkok, s32 result[][8], u8 final_candidate, bool txonly) +{ + u32 Oldval_0, X, TX0_A, reg; + s32 Y, TX0_C; + + if (final_candidate == 0xFF) { + return; + } else if (iqkok) { + Oldval_0 = (rtl8188e_PHY_QueryBBReg(adapt, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][0]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX0_A = (X * Oldval_0) >> 8; + rtl8188e_PHY_SetBBReg(adapt, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); + + rtl8188e_PHY_SetBBReg(adapt, rOFDM0_ECCAThreshold, BIT(31), ((X * Oldval_0 >> 7) & 0x1)); + + Y = result[final_candidate][1]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + TX0_C = (Y * Oldval_0) >> 8; + rtl8188e_PHY_SetBBReg(adapt, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C & 0x3C0) >> 6)); + rtl8188e_PHY_SetBBReg(adapt, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C & 0x3F)); + + rtl8188e_PHY_SetBBReg(adapt, rOFDM0_ECCAThreshold, BIT(29), ((Y * Oldval_0 >> 7) & 0x1)); + + if (txonly) + return; + + reg = result[final_candidate][2]; + rtl8188e_PHY_SetBBReg(adapt, rOFDM0_XARxIQImbalance, 0x3FF, reg); + + reg = result[final_candidate][3] & 0x3F; + rtl8188e_PHY_SetBBReg(adapt, rOFDM0_XARxIQImbalance, 0xFC00, reg); + + reg = (result[final_candidate][3] >> 6) & 0xF; + rtl8188e_PHY_SetBBReg(adapt, rOFDM0_RxIQExtAnta, 0xF0000000, reg); + } +} + +void _PHY_SaveADDARegisters(struct adapter *adapt, u32 *ADDAReg, u32 *ADDABackup, u32 RegisterNum) +{ + u32 i; + + for (i = 0; i < RegisterNum; i++) { + ADDABackup[i] = rtl8188e_PHY_QueryBBReg(adapt, ADDAReg[i], bMaskDWord); + } +} + +/* FIXME: return an error to caller */ +static void _PHY_SaveMACRegisters( + struct adapter *adapt, + u32 *MACReg, + u32 *MACBackup + ) +{ + u32 i; + int res; + + for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) { + u8 reg; + + res = rtw_read8(adapt, MACReg[i], ®); + if (res) + return; + + MACBackup[i] = reg; + } + + res = rtw_read32(adapt, MACReg[i], MACBackup + i); + (void)res; +} + +static void reload_adda_reg(struct adapter *adapt, u32 *ADDAReg, u32 *ADDABackup, u32 RegiesterNum) +{ + u32 i; + + for (i = 0; i < RegiesterNum; i++) + rtl8188e_PHY_SetBBReg(adapt, ADDAReg[i], bMaskDWord, ADDABackup[i]); +} + +static void +_PHY_ReloadMACRegisters( + struct adapter *adapt, + u32 *MACReg, + u32 *MACBackup + ) +{ + u32 i; + + for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) + rtw_write8(adapt, MACReg[i], (u8)MACBackup[i]); + + rtw_write32(adapt, MACReg[i], MACBackup[i]); +} + +static void +_PHY_PathADDAOn( + struct adapter *adapt, + u32 *ADDAReg) +{ + u32 i; + + rtl8188e_PHY_SetBBReg(adapt, ADDAReg[0], bMaskDWord, 0x0b1b25a0); + + for (i = 1; i < IQK_ADDA_REG_NUM; i++) + rtl8188e_PHY_SetBBReg(adapt, ADDAReg[i], bMaskDWord, 0x0bdb25a0); +} + +void +_PHY_MACSettingCalibration( + struct adapter *adapt, + u32 *MACReg, + u32 *MACBackup + ) +{ + u32 i = 0; + + rtw_write8(adapt, MACReg[i], 0x3F); + + for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++) + rtw_write8(adapt, MACReg[i], (u8)(MACBackup[i] & (~BIT(3)))); + + rtw_write8(adapt, MACReg[i], (u8)(MACBackup[i] & (~BIT(5)))); +} + +static void _PHY_PIModeSwitch( + struct adapter *adapt, + bool PIMode + ) +{ + u32 mode; + + mode = PIMode ? 0x01000100 : 0x01000000; + rtl8188e_PHY_SetBBReg(adapt, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); + rtl8188e_PHY_SetBBReg(adapt, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode); +} + +static bool phy_SimularityCompare_8188E( + struct adapter *adapt, + s32 resulta[][8], + u8 c1, + u8 c2 + ) +{ + u32 i, j, diff, sim_bitmap, bound = 0; + u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */ + bool result = true; + s32 tmp1 = 0, tmp2 = 0; + + bound = 4; + sim_bitmap = 0; + + for (i = 0; i < bound; i++) { + if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) { + if ((resulta[c1][i] & 0x00000200) != 0) + tmp1 = resulta[c1][i] | 0xFFFFFC00; + else + tmp1 = resulta[c1][i]; + + if ((resulta[c2][i] & 0x00000200) != 0) + tmp2 = resulta[c2][i] | 0xFFFFFC00; + else + tmp2 = resulta[c2][i]; + } else { + tmp1 = resulta[c1][i]; + tmp2 = resulta[c2][i]; + } + + diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); + + if (diff > MAX_TOLERANCE) { + if ((i == 2 || i == 6) && !sim_bitmap) { + if (resulta[c1][i] + resulta[c1][i + 1] == 0) + final_candidate[(i / 4)] = c2; + else if (resulta[c2][i] + resulta[c2][i + 1] == 0) + final_candidate[(i / 4)] = c1; + else + sim_bitmap = sim_bitmap | (1 << i); + } else { + sim_bitmap = sim_bitmap | (1 << i); + } + } + } + + if (sim_bitmap == 0) { + for (i = 0; i < (bound / 4); i++) { + if (final_candidate[i] != 0xFF) { + for (j = i * 4; j < (i + 1) * 4 - 2; j++) + resulta[3][j] = resulta[final_candidate[i]][j]; + result = false; + } + } + return result; + } else { + if (!(sim_bitmap & 0x03)) { /* path A TX OK */ + for (i = 0; i < 2; i++) + resulta[3][i] = resulta[c1][i]; + } + if (!(sim_bitmap & 0x0c)) { /* path A RX OK */ + for (i = 2; i < 4; i++) + resulta[3][i] = resulta[c1][i]; + } + + if (!(sim_bitmap & 0x30)) { /* path B TX OK */ + for (i = 4; i < 6; i++) + resulta[3][i] = resulta[c1][i]; + } + + if (!(sim_bitmap & 0xc0)) { /* path B RX OK */ + for (i = 6; i < 8; i++) + resulta[3][i] = resulta[c1][i]; + } + return false; + } +} + +static void phy_IQCalibrate_8188E(struct adapter *adapt, s32 result[][8], u8 t) +{ + struct hal_data_8188e *pHalData = &adapt->haldata; + struct odm_dm_struct *dm_odm = &pHalData->odmpriv; + u32 i; + u8 PathAOK; + u32 ADDA_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN }; + u32 IQK_MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; + + /* since 92C & 92D have the different define in IQK_BB_REG */ + u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, + rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, + rFPGA0_XB_RFInterfaceOE, rFPGA0_RFMOD + }; + u32 retryCount = 2; + /* Note: IQ calibration must be performed after loading */ + /* PHY_REG.txt , and radio_a, radio_b.txt */ + + if (t == 0) { + /* Save ADDA parameters, turn Path A ADDA on */ + _PHY_SaveADDARegisters(adapt, ADDA_REG, dm_odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + _PHY_SaveMACRegisters(adapt, IQK_MAC_REG, dm_odm->RFCalibrateInfo.IQK_MAC_backup); + _PHY_SaveADDARegisters(adapt, IQK_BB_REG_92C, dm_odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); + } + + _PHY_PathADDAOn(adapt, ADDA_REG); + if (t == 0) + dm_odm->RFCalibrateInfo.bRfPiEnable = (u8)rtl8188e_PHY_QueryBBReg(adapt, rFPGA0_XA_HSSIParameter1, BIT(8)); + + if (!dm_odm->RFCalibrateInfo.bRfPiEnable) { + /* Switch BB to PI mode to do IQ Calibration. */ + _PHY_PIModeSwitch(adapt, true); + } + + /* BB setting */ + rtl8188e_PHY_SetBBReg(adapt, rFPGA0_RFMOD, BIT(24), 0x00); + rtl8188e_PHY_SetBBReg(adapt, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); + rtl8188e_PHY_SetBBReg(adapt, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); + rtl8188e_PHY_SetBBReg(adapt, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000); + + rtl8188e_PHY_SetBBReg(adapt, rFPGA0_XAB_RFInterfaceSW, BIT(10), 0x01); + rtl8188e_PHY_SetBBReg(adapt, rFPGA0_XAB_RFInterfaceSW, BIT(26), 0x01); + rtl8188e_PHY_SetBBReg(adapt, rFPGA0_XA_RFInterfaceOE, BIT(10), 0x00); + rtl8188e_PHY_SetBBReg(adapt, rFPGA0_XB_RFInterfaceOE, BIT(10), 0x00); + + /* MAC settings */ + _PHY_MACSettingCalibration(adapt, IQK_MAC_REG, dm_odm->RFCalibrateInfo.IQK_MAC_backup); + + /* Page B init */ + /* AP or IQK */ + rtl8188e_PHY_SetBBReg(adapt, rConfig_AntA, bMaskDWord, 0x0f600000); + + + /* IQ calibration setting */ + rtl8188e_PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000); + rtl8188e_PHY_SetBBReg(adapt, rTx_IQK, bMaskDWord, 0x01007c00); + rtl8188e_PHY_SetBBReg(adapt, rRx_IQK, bMaskDWord, 0x81004800); + + for (i = 0; i < retryCount; i++) { + PathAOK = phy_PathA_IQK_8188E(adapt); + if (PathAOK == 0x01) { + result[t][0] = (rtl8188e_PHY_QueryBBReg(adapt, rTx_Power_Before_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; + result[t][1] = (rtl8188e_PHY_QueryBBReg(adapt, rTx_Power_After_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; + break; + } + } + + for (i = 0; i < retryCount; i++) { + PathAOK = phy_PathA_RxIQK(adapt); + if (PathAOK == 0x03) { + result[t][2] = (rtl8188e_PHY_QueryBBReg(adapt, rRx_Power_Before_IQK_A_2, bMaskDWord) & 0x3FF0000) >> 16; + result[t][3] = (rtl8188e_PHY_QueryBBReg(adapt, rRx_Power_After_IQK_A_2, bMaskDWord) & 0x3FF0000) >> 16; + break; + } + } + + /* Back to BB mode, load original value */ + rtl8188e_PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0); + + if (t != 0) { + if (!dm_odm->RFCalibrateInfo.bRfPiEnable) { + /* Switch back BB to SI mode after finish IQ Calibration. */ + _PHY_PIModeSwitch(adapt, false); + } + + /* Reload ADDA power saving parameters */ + reload_adda_reg(adapt, ADDA_REG, dm_odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + + /* Reload MAC parameters */ + _PHY_ReloadMACRegisters(adapt, IQK_MAC_REG, dm_odm->RFCalibrateInfo.IQK_MAC_backup); + + reload_adda_reg(adapt, IQK_BB_REG_92C, dm_odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); + + /* Restore RX initial gain */ + rtl8188e_PHY_SetBBReg(adapt, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00032ed3); + + /* load 0xe30 IQC default value */ + rtl8188e_PHY_SetBBReg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + rtl8188e_PHY_SetBBReg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + } +} + +static void phy_LCCalibrate_8188E(struct adapter *adapt) +{ + u8 tmpreg; + u32 RF_Amode = 0, LC_Cal; + int res; + + /* Check continuous TX and Packet TX */ + res = rtw_read8(adapt, 0xd03, &tmpreg); + if (res) + return; + + if ((tmpreg & 0x70) != 0) /* Deal with contisuous TX case */ + rtw_write8(adapt, 0xd03, tmpreg & 0x8F); /* disable all continuous TX */ + else /* Deal with Packet TX case */ + rtw_write8(adapt, REG_TXPAUSE, 0xFF); /* block all queues */ + + if ((tmpreg & 0x70) != 0) { + /* 1. Read original RF mode */ + /* Path-A */ + RF_Amode = rtl8188e_PHY_QueryRFReg(adapt, RF_AC, bMask12Bits); + + /* 2. Set RF mode = standby mode */ + /* Path-A */ + rtl8188e_PHY_SetRFReg(adapt, RF_AC, bMask12Bits, (RF_Amode & 0x8FFFF) | 0x10000); + } + + /* 3. Read RF reg18 */ + LC_Cal = rtl8188e_PHY_QueryRFReg(adapt, RF_CHNLBW, bMask12Bits); + + /* 4. Set LC calibration begin bit15 */ + rtl8188e_PHY_SetRFReg(adapt, RF_CHNLBW, bMask12Bits, LC_Cal | 0x08000); + + msleep(100); + + /* Restore original situation */ + if ((tmpreg & 0x70) != 0) { + /* Deal with continuous TX case */ + /* Path-A */ + rtw_write8(adapt, 0xd03, tmpreg); + rtl8188e_PHY_SetRFReg(adapt, RF_AC, bMask12Bits, RF_Amode); + } else { + /* Deal with Packet TX case */ + rtw_write8(adapt, REG_TXPAUSE, 0x00); + } +} + +void PHY_IQCalibrate_8188E(struct adapter *adapt, bool recovery) +{ + struct hal_data_8188e *pHalData = &adapt->haldata; + struct odm_dm_struct *dm_odm = &pHalData->odmpriv; + s32 result[4][8]; /* last is final result */ + u8 i, final_candidate; + bool pathaok; + s32 RegE94, RegE9C, RegEA4, RegEB4, RegEBC; + bool is12simular, is13simular, is23simular; + u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, + rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, + rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, + rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, + rOFDM0_RxIQExtAnta}; + + if (recovery) { + reload_adda_reg(adapt, IQK_BB_REG_92C, dm_odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); + return; + } + + for (i = 0; i < 8; i++) { + result[0][i] = 0; + result[1][i] = 0; + result[2][i] = 0; + if ((i == 0) || (i == 2) || (i == 4) || (i == 6)) + result[3][i] = 0x100; + else + result[3][i] = 0; + } + final_candidate = 0xff; + pathaok = false; + is12simular = false; + is23simular = false; + is13simular = false; + + for (i = 0; i < 3; i++) { + phy_IQCalibrate_8188E(adapt, result, i); + + if (i == 1) { + is12simular = phy_SimularityCompare_8188E(adapt, result, 0, 1); + if (is12simular) { + final_candidate = 0; + break; + } + } + + if (i == 2) { + is13simular = phy_SimularityCompare_8188E(adapt, result, 0, 2); + if (is13simular) { + final_candidate = 0; + + break; + } + is23simular = phy_SimularityCompare_8188E(adapt, result, 1, 2); + if (is23simular) { + final_candidate = 1; + } else { + final_candidate = 3; + } + } + } + + for (i = 0; i < 4; i++) { + RegE94 = result[i][0]; + RegE9C = result[i][1]; + RegEA4 = result[i][2]; + RegEB4 = result[i][4]; + RegEBC = result[i][5]; + } + + if (final_candidate != 0xff) { + RegE94 = result[final_candidate][0]; + RegE9C = result[final_candidate][1]; + RegEA4 = result[final_candidate][2]; + RegEB4 = result[final_candidate][4]; + RegEBC = result[final_candidate][5]; + dm_odm->RFCalibrateInfo.RegE94 = RegE94; + dm_odm->RFCalibrateInfo.RegE9C = RegE9C; + dm_odm->RFCalibrateInfo.RegEB4 = RegEB4; + dm_odm->RFCalibrateInfo.RegEBC = RegEBC; + pathaok = true; + } else { + dm_odm->RFCalibrateInfo.RegE94 = 0x100; + dm_odm->RFCalibrateInfo.RegEB4 = 0x100; /* X default value */ + dm_odm->RFCalibrateInfo.RegE9C = 0x0; + dm_odm->RFCalibrateInfo.RegEBC = 0x0; /* Y default value */ + } + if (RegE94 != 0) + patha_fill_iqk(adapt, pathaok, result, final_candidate, (RegEA4 == 0)); + +/* To Fix BSOD when final_candidate is 0xff */ +/* by sherry 20120321 */ + if (final_candidate < 4) { + for (i = 0; i < IQK_Matrix_REG_NUM; i++) + dm_odm->RFCalibrateInfo.IQKMatrixRegSetting.Value[0][i] = result[final_candidate][i]; + dm_odm->RFCalibrateInfo.IQKMatrixRegSetting.bIQKDone = true; + } + + _PHY_SaveADDARegisters(adapt, IQK_BB_REG_92C, dm_odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); +} + +void PHY_LCCalibrate_8188E(struct adapter *adapt) +{ + u32 timeout = 2000, timecount = 0; + struct hal_data_8188e *pHalData = &adapt->haldata; + struct odm_dm_struct *dm_odm = &pHalData->odmpriv; + + while (*dm_odm->pbScanInProcess && timecount < timeout) { + mdelay(50); + timecount += 50; + } + + phy_LCCalibrate_8188E(adapt); +} diff --git a/drivers/staging/r8188eu/hal/HalPwrSeqCmd.c b/drivers/staging/r8188eu/hal/HalPwrSeqCmd.c new file mode 100644 index 000000000..6c0b13683 --- /dev/null +++ b/drivers/staging/r8188eu/hal/HalPwrSeqCmd.c @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright(c) 2007 - 2011 Realtek Corporation. */ + +#include "../include/HalPwrSeqCmd.h" + +#define PWR_CMD_WRITE 0x01 + /* offset: the read register offset */ + /* msk: the mask of the write bits */ + /* value: write value */ + /* note: driver shall implement this cmd by read & msk after write */ + +#define PWR_CMD_POLLING 0x02 + /* offset: the read register offset */ + /* msk: the mask of the polled value */ + /* value: the value to be polled, masked by the msd field. */ + /* note: driver shall implement this cmd by */ + /* do{ */ + /* if ( (Read(offset) & msk) == (value & msk) ) */ + /* break; */ + /* } while (not timeout); */ + +#define PWR_CMD_DELAY 0x03 + /* offset: the value to delay (in us) */ + /* msk: N/A */ + /* value: N/A */ + +struct wl_pwr_cfg { + u16 offset; + u8 cmd:4; + u8 msk; + u8 value; +}; + +#define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset +#define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd +#define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk +#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value + +static struct wl_pwr_cfg rtl8188E_power_on_flow[] = { + { 0x0006, PWR_CMD_POLLING, BIT(1), BIT(1) }, + { 0x0002, PWR_CMD_WRITE, BIT(0) | BIT(1), 0 }, /* reset BB */ + { 0x0026, PWR_CMD_WRITE, BIT(7), BIT(7) }, /* schmitt trigger */ + { 0x0005, PWR_CMD_WRITE, BIT(7), 0 }, /* disable HWPDN (control by DRV)*/ + { 0x0005, PWR_CMD_WRITE, BIT(4) | BIT(3), 0 }, /* disable WL suspend*/ + { 0x0005, PWR_CMD_WRITE, BIT(0), BIT(0) }, + { 0x0005, PWR_CMD_POLLING, BIT(0), 0 }, + { 0x0023, PWR_CMD_WRITE, BIT(4), 0 }, +}; + +static struct wl_pwr_cfg rtl8188E_card_disable_flow[] = { + { 0x001F, PWR_CMD_WRITE, 0xFF, 0 }, /* turn off RF */ + { 0x0023, PWR_CMD_WRITE, BIT(4), BIT(4) }, /* LDO Sleep mode */ + { 0x0005, PWR_CMD_WRITE, BIT(1), BIT(1) }, /* turn off MAC by HW state machine */ + { 0x0005, PWR_CMD_POLLING, BIT(1), 0 }, + { 0x0026, PWR_CMD_WRITE, BIT(7), BIT(7) }, /* schmitt trigger */ + { 0x0005, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) }, /* enable WL suspend */ + { 0x0007, PWR_CMD_WRITE, 0xFF, 0 }, /* enable bandgap mbias in suspend */ + { 0x0041, PWR_CMD_WRITE, BIT(4), 0 }, /* Clear SIC_EN register */ + { 0xfe10, PWR_CMD_WRITE, BIT(4), BIT(4) }, /* Set USB suspend enable local register */ +}; + +/* This is used by driver for LPSRadioOff Procedure, not for FW LPS Step */ +static struct wl_pwr_cfg rtl8188E_enter_lps_flow[] = { + { 0x0522, PWR_CMD_WRITE, 0xFF, 0x7F },/* Tx Pause */ + { 0x05F8, PWR_CMD_POLLING, 0xFF, 0 }, /* Should be zero if no packet is transmitted */ + { 0x05F9, PWR_CMD_POLLING, 0xFF, 0 }, /* Should be zero if no packet is transmitted */ + { 0x05FA, PWR_CMD_POLLING, 0xFF, 0 }, /* Should be zero if no packet is transmitted */ + { 0x05FB, PWR_CMD_POLLING, 0xFF, 0 }, /* Should be zero if no packet is transmitted */ + { 0x0002, PWR_CMD_WRITE, BIT(0), 0 }, /* CCK and OFDM are disabled, clocks are gated */ + { 0x0002, PWR_CMD_DELAY, 0, 0 }, + { 0x0100, PWR_CMD_WRITE, 0xFF, 0x3F }, /* Reset MAC TRX */ + { 0x0101, PWR_CMD_WRITE, BIT(1), 0 }, /* check if removed later */ + { 0x0553, PWR_CMD_WRITE, BIT(5), BIT(5) }, /* Respond TxOK to scheduler */ +}; + +u8 HalPwrSeqCmdParsing(struct adapter *padapter, enum r8188eu_pwr_seq seq) +{ + struct wl_pwr_cfg pwrcfgcmd = {0}; + struct wl_pwr_cfg *pwrseqcmd; + u8 poll_bit = false; + u8 idx, num_steps; + u8 value = 0; + u32 offset = 0; + u32 poll_count = 0; /* polling autoload done. */ + u32 max_poll_count = 5000; + int res; + + switch (seq) { + case PWR_ON_FLOW: + pwrseqcmd = rtl8188E_power_on_flow; + num_steps = ARRAY_SIZE(rtl8188E_power_on_flow); + break; + case DISABLE_FLOW: + pwrseqcmd = rtl8188E_card_disable_flow; + num_steps = ARRAY_SIZE(rtl8188E_card_disable_flow); + break; + case LPS_ENTER_FLOW: + pwrseqcmd = rtl8188E_enter_lps_flow; + num_steps = ARRAY_SIZE(rtl8188E_enter_lps_flow); + break; + default: + return false; + } + + for (idx = 0; idx < num_steps; idx++) { + pwrcfgcmd = pwrseqcmd[idx]; + + switch (GET_PWR_CFG_CMD(pwrcfgcmd)) { + case PWR_CMD_WRITE: + offset = GET_PWR_CFG_OFFSET(pwrcfgcmd); + + /* Read the value from system register */ + res = rtw_read8(padapter, offset, &value); + if (res) + return false; + + value &= ~(GET_PWR_CFG_MASK(pwrcfgcmd)); + value |= (GET_PWR_CFG_VALUE(pwrcfgcmd) & GET_PWR_CFG_MASK(pwrcfgcmd)); + + /* Write the value back to system register */ + rtw_write8(padapter, offset, value); + break; + case PWR_CMD_POLLING: + poll_bit = false; + offset = GET_PWR_CFG_OFFSET(pwrcfgcmd); + do { + res = rtw_read8(padapter, offset, &value); + if (res) + return false; + + value &= GET_PWR_CFG_MASK(pwrcfgcmd); + if (value == (GET_PWR_CFG_VALUE(pwrcfgcmd) & GET_PWR_CFG_MASK(pwrcfgcmd))) + poll_bit = true; + else + udelay(10); + + if (poll_count++ > max_poll_count) + return false; + } while (!poll_bit); + break; + case PWR_CMD_DELAY: + udelay(GET_PWR_CFG_OFFSET(pwrcfgcmd)); + break; + default: + break; + } + } + return true; +} diff --git a/drivers/staging/r8188eu/hal/hal_com.c b/drivers/staging/r8188eu/hal/hal_com.c new file mode 100644 index 000000000..33967eb3c --- /dev/null +++ b/drivers/staging/r8188eu/hal/hal_com.c @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright(c) 2007 - 2011 Realtek Corporation. */ + +#include "../include/osdep_service.h" +#include "../include/drv_types.h" + +#include "../include/hal_intf.h" +#include "../include/hal_com.h" +#include "../include/rtl8188e_hal.h" + +#define _HAL_INIT_C_ + +#define CHAN_PLAN_HW 0x80 + +u8 /* return the final channel plan decision */ +hal_com_get_channel_plan(struct adapter *padapter, u8 hw_channel_plan, + u8 sw_channel_plan, u8 def_channel_plan, + bool load_fail) +{ + u8 sw_cfg; + u8 chnlplan; + + sw_cfg = true; + if (!load_fail) { + if (!rtw_is_channel_plan_valid(sw_channel_plan)) + sw_cfg = false; + if (hw_channel_plan & CHAN_PLAN_HW) + sw_cfg = false; + } + + if (sw_cfg) + chnlplan = sw_channel_plan; + else + chnlplan = hw_channel_plan & (~CHAN_PLAN_HW); + + if (!rtw_is_channel_plan_valid(chnlplan)) + chnlplan = def_channel_plan; + + return chnlplan; +} + +u8 MRateToHwRate(u8 rate) +{ + u8 ret = DESC_RATE1M; + + switch (rate) { + /* CCK and OFDM non-HT rates */ + case IEEE80211_CCK_RATE_1MB: + ret = DESC_RATE1M; + break; + case IEEE80211_CCK_RATE_2MB: + ret = DESC_RATE2M; + break; + case IEEE80211_CCK_RATE_5MB: + ret = DESC_RATE5_5M; + break; + case IEEE80211_CCK_RATE_11MB: + ret = DESC_RATE11M; + break; + case IEEE80211_OFDM_RATE_6MB: + ret = DESC_RATE6M; + break; + case IEEE80211_OFDM_RATE_9MB: + ret = DESC_RATE9M; + break; + case IEEE80211_OFDM_RATE_12MB: + ret = DESC_RATE12M; + break; + case IEEE80211_OFDM_RATE_18MB: + ret = DESC_RATE18M; + break; + case IEEE80211_OFDM_RATE_24MB: + ret = DESC_RATE24M; + break; + case IEEE80211_OFDM_RATE_36MB: + ret = DESC_RATE36M; + break; + case IEEE80211_OFDM_RATE_48MB: + ret = DESC_RATE48M; + break; + case IEEE80211_OFDM_RATE_54MB: + ret = DESC_RATE54M; + break; + default: + break; + } + return ret; +} + +void HalSetBrateCfg(struct adapter *adapt, u8 *brates, u16 *rate_cfg) +{ + u8 i, is_brate, brate; + + for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) { + is_brate = brates[i] & IEEE80211_BASIC_RATE_MASK; + brate = brates[i] & 0x7f; + + if (is_brate) { + switch (brate) { + case IEEE80211_CCK_RATE_1MB: + *rate_cfg |= RATE_1M; + break; + case IEEE80211_CCK_RATE_2MB: + *rate_cfg |= RATE_2M; + break; + case IEEE80211_CCK_RATE_5MB: + *rate_cfg |= RATE_5_5M; + break; + case IEEE80211_CCK_RATE_11MB: + *rate_cfg |= RATE_11M; + break; + case IEEE80211_OFDM_RATE_6MB: + *rate_cfg |= RATE_6M; + break; + case IEEE80211_OFDM_RATE_9MB: + *rate_cfg |= RATE_9M; + break; + case IEEE80211_OFDM_RATE_12MB: + *rate_cfg |= RATE_12M; + break; + case IEEE80211_OFDM_RATE_18MB: + *rate_cfg |= RATE_18M; + break; + case IEEE80211_OFDM_RATE_24MB: + *rate_cfg |= RATE_24M; + break; + case IEEE80211_OFDM_RATE_36MB: + *rate_cfg |= RATE_36M; + break; + case IEEE80211_OFDM_RATE_48MB: + *rate_cfg |= RATE_48M; + break; + case IEEE80211_OFDM_RATE_54MB: + *rate_cfg |= RATE_54M; + break; + } + } + } +} diff --git a/drivers/staging/r8188eu/hal/hal_intf.c b/drivers/staging/r8188eu/hal/hal_intf.c new file mode 100644 index 000000000..37935aef7 --- /dev/null +++ b/drivers/staging/r8188eu/hal/hal_intf.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright(c) 2007 - 2012 Realtek Corporation. */ + +#define _HAL_INTF_C_ +#include "../include/osdep_service.h" +#include "../include/drv_types.h" +#include "../include/hal_intf.h" + +uint rtw_hal_init(struct adapter *adapt) +{ + uint status = _SUCCESS; + + adapt->hw_init_completed = false; + + status = rtl8188eu_hal_init(adapt); + + if (status == _SUCCESS) { + adapt->hw_init_completed = true; + + if (adapt->registrypriv.notch_filter == 1) + hal_notch_filter_8188e(adapt, 1); + } else { + adapt->hw_init_completed = false; + } + + return status; +} + +uint rtw_hal_deinit(struct adapter *adapt) +{ + uint status = _SUCCESS; + + status = rtl8188eu_hal_deinit(adapt); + + if (status == _SUCCESS) + adapt->hw_init_completed = false; + + return status; +} + +void rtw_hal_update_ra_mask(struct adapter *adapt, u32 mac_id, u8 rssi_level) +{ + struct mlme_priv *pmlmepriv = &adapt->mlmepriv; + + if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { + struct sta_info *psta = NULL; + struct sta_priv *pstapriv = &adapt->stapriv; + if (mac_id >= 2) + psta = pstapriv->sta_aid[(mac_id - 1) - 1]; + if (psta) + add_RATid(adapt, psta, 0);/* todo: based on rssi_level*/ + } else { + UpdateHalRAMask8188EUsb(adapt, mac_id, rssi_level); + } +} diff --git a/drivers/staging/r8188eu/hal/odm.c b/drivers/staging/r8188eu/hal/odm.c new file mode 100644 index 000000000..94f9b125d --- /dev/null +++ b/drivers/staging/r8188eu/hal/odm.c @@ -0,0 +1,821 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright(c) 2007 - 2011 Realtek Corporation. */ + +#include "../include/drv_types.h" + +/* avoid to warn in FreeBSD ==> To DO modify */ +static u32 EDCAParam[HT_IOT_PEER_MAX][3] = { + /* UL DL */ + {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 0:unknown AP */ + {0xa44f, 0x5ea44f, 0x5e431c}, /* 1:realtek AP */ + {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 2:unknown AP => realtek_92SE */ + {0x5ea32b, 0x5ea42b, 0x5e4322}, /* 3:broadcom AP */ + {0x5ea422, 0x00a44f, 0x00a44f}, /* 4:ralink AP */ + {0x5ea322, 0x00a630, 0x00a44f}, /* 5:atheros AP */ + {0x5e4322, 0x5e4322, 0x5e4322},/* 6:cisco AP */ + {0x5ea44f, 0x00a44f, 0x5ea42b}, /* 8:marvell AP */ + {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 10:unknown AP=> 92U AP */ + {0x5ea42b, 0xa630, 0x5e431c}, /* 11:airgocap AP */ +}; + +/* Global var */ +u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D] = { + 0x7f8001fe, /* 0, +6.0dB */ + 0x788001e2, /* 1, +5.5dB */ + 0x71c001c7, /* 2, +5.0dB */ + 0x6b8001ae, /* 3, +4.5dB */ + 0x65400195, /* 4, +4.0dB */ + 0x5fc0017f, /* 5, +3.5dB */ + 0x5a400169, /* 6, +3.0dB */ + 0x55400155, /* 7, +2.5dB */ + 0x50800142, /* 8, +2.0dB */ + 0x4c000130, /* 9, +1.5dB */ + 0x47c0011f, /* 10, +1.0dB */ + 0x43c0010f, /* 11, +0.5dB */ + 0x40000100, /* 12, +0dB */ + 0x3c8000f2, /* 13, -0.5dB */ + 0x390000e4, /* 14, -1.0dB */ + 0x35c000d7, /* 15, -1.5dB */ + 0x32c000cb, /* 16, -2.0dB */ + 0x300000c0, /* 17, -2.5dB */ + 0x2d4000b5, /* 18, -3.0dB */ + 0x2ac000ab, /* 19, -3.5dB */ + 0x288000a2, /* 20, -4.0dB */ + 0x26000098, /* 21, -4.5dB */ + 0x24000090, /* 22, -5.0dB */ + 0x22000088, /* 23, -5.5dB */ + 0x20000080, /* 24, -6.0dB */ + 0x1e400079, /* 25, -6.5dB */ + 0x1c800072, /* 26, -7.0dB */ + 0x1b00006c, /* 27. -7.5dB */ + 0x19800066, /* 28, -8.0dB */ + 0x18000060, /* 29, -8.5dB */ + 0x16c0005b, /* 30, -9.0dB */ + 0x15800056, /* 31, -9.5dB */ + 0x14400051, /* 32, -10.0dB */ + 0x1300004c, /* 33, -10.5dB */ + 0x12000048, /* 34, -11.0dB */ + 0x11000044, /* 35, -11.5dB */ + 0x10000040, /* 36, -12.0dB */ + 0x0f00003c,/* 37, -12.5dB */ + 0x0e400039,/* 38, -13.0dB */ + 0x0d800036,/* 39, -13.5dB */ + 0x0cc00033,/* 40, -14.0dB */ + 0x0c000030,/* 41, -14.5dB */ + 0x0b40002d,/* 42, -15.0dB */ +}; + +u8 cck_swing_table[CCK_TABLE_SIZE][8] = { + {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */ + {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */ + {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */ + {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */ + {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */ + {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */ + {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */ + {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */ + {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */ + {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */ + {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */ + {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */ + {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB */ + {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */ + {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */ + {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */ + {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ + {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */ + {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */ + {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */ + {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */ + {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */ + {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */ + {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */ + {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */ + {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */ + {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */ + {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */ + {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */ + {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */ + {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */ + {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */ + {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */ +}; + +#define RxDefaultAnt1 0x65a9 +#define RxDefaultAnt2 0x569a + +static void odm_DIGInit(struct odm_dm_struct *pDM_Odm) +{ + struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; + struct adapter *adapter = pDM_Odm->Adapter; + + pDM_DigTable->CurIGValue = (u8)rtl8188e_PHY_QueryBBReg(adapter, ODM_REG_IGI_A_11N, ODM_BIT_IGI_11N); + pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; + pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC; + pDM_DigTable->CurCCK_CCAThres = 0x83; + pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC; + pDM_DigTable->LargeFAHit = 0; + pDM_DigTable->Recover_cnt = 0; + pDM_DigTable->DIG_Dynamic_MIN_0 = DM_DIG_MIN_NIC; + pDM_DigTable->bMediaConnect_0 = false; + + /* To Initialize pDM_Odm->bDMInitialGainEnable == false to avoid DIG error */ + pDM_Odm->bDMInitialGainEnable = true; +} + +static void odm_DIG(struct odm_dm_struct *pDM_Odm) +{ + struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; + struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt; + u8 DIG_Dynamic_MIN; + u8 DIG_MaxOfMin; + bool FirstConnect, FirstDisConnect; + u8 dm_dig_max, dm_dig_min; + u8 CurrentIGI = pDM_DigTable->CurIGValue; + + if (*pDM_Odm->pbScanInProcess) + return; + + /* add by Neil Chen to avoid PSD is processing */ + if (!pDM_Odm->bDMInitialGainEnable) + return; + + DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0; + FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0); + FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0); + + /* 1 Boundary Decision */ + dm_dig_max = DM_DIG_MAX_NIC; + dm_dig_min = DM_DIG_MIN_NIC; + DIG_MaxOfMin = DM_DIG_MAX_AP; + + if (pDM_Odm->bLinked) { + /* 2 8723A Series, offset need to be 10 */ + /* 2 Modify DIG upper bound */ + if ((pDM_Odm->RSSI_Min + 20) > dm_dig_max) + pDM_DigTable->rx_gain_range_max = dm_dig_max; + else if ((pDM_Odm->RSSI_Min + 20) < dm_dig_min) + pDM_DigTable->rx_gain_range_max = dm_dig_min; + else + pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 20; + /* 2 Modify DIG lower bound */ + if (pDM_Odm->bOneEntryOnly) { + if (pDM_Odm->RSSI_Min < dm_dig_min) + DIG_Dynamic_MIN = dm_dig_min; + else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin) + DIG_Dynamic_MIN = DIG_MaxOfMin; + else + DIG_Dynamic_MIN = pDM_Odm->RSSI_Min; + } else if (pDM_Odm->SupportAbility & ODM_BB_ANT_DIV) { + /* 1 Lower Bound for 88E AntDiv */ + if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) + DIG_Dynamic_MIN = (u8)pDM_DigTable->AntDiv_RSSI_max; + } else { + DIG_Dynamic_MIN = dm_dig_min; + } + } else { + pDM_DigTable->rx_gain_range_max = dm_dig_max; + DIG_Dynamic_MIN = dm_dig_min; + } + + /* 1 Modify DIG lower bound, deal with abnormally large false alarm */ + if (pFalseAlmCnt->Cnt_all > 10000) { + if (pDM_DigTable->LargeFAHit != 3) + pDM_DigTable->LargeFAHit++; + if (pDM_DigTable->ForbiddenIGI < CurrentIGI) { + pDM_DigTable->ForbiddenIGI = CurrentIGI; + pDM_DigTable->LargeFAHit = 1; + } + + if (pDM_DigTable->LargeFAHit >= 3) { + if ((pDM_DigTable->ForbiddenIGI + 1) > pDM_DigTable->rx_gain_range_max) + pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max; + else + pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1); + pDM_DigTable->Recover_cnt = 3600; /* 3600=2hr */ + } + + } else { + /* Recovery mechanism for IGI lower bound */ + if (pDM_DigTable->Recover_cnt != 0) { + pDM_DigTable->Recover_cnt--; + } else { + if (pDM_DigTable->LargeFAHit < 3) { + if ((pDM_DigTable->ForbiddenIGI - 1) < DIG_Dynamic_MIN) { /* DM_DIG_MIN) */ + pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; /* DM_DIG_MIN; */ + pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; /* DM_DIG_MIN; */ + } else { + pDM_DigTable->ForbiddenIGI--; + pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1); + } + } else { + pDM_DigTable->LargeFAHit = 0; + } + } + } + + /* 1 Adjust initial gain by false alarm */ + if (pDM_Odm->bLinked) { + if (FirstConnect) { + CurrentIGI = pDM_Odm->RSSI_Min; + } else { + if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2) + CurrentIGI = CurrentIGI + 4;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */ + else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1) + CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */ + else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0) + CurrentIGI = CurrentIGI - 2;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */ + } + } else { + if (FirstDisConnect) { + CurrentIGI = pDM_DigTable->rx_gain_range_min; + } else { + /* 2012.03.30 LukeLee: enable DIG before link but with very high thresholds */ + if (pFalseAlmCnt->Cnt_all > 10000) + CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */ + else if (pFalseAlmCnt->Cnt_all > 8000) + CurrentIGI = CurrentIGI + 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */ + else if (pFalseAlmCnt->Cnt_all < 500) + CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */ + } + } + /* 1 Check initial gain by upper/lower bound */ + if (CurrentIGI > pDM_DigTable->rx_gain_range_max) + CurrentIGI = pDM_DigTable->rx_gain_range_max; + if (CurrentIGI < pDM_DigTable->rx_gain_range_min) + CurrentIGI = pDM_DigTable->rx_gain_range_min; + + /* 2 High power RSSI threshold */ + + ODM_Write_DIG(pDM_Odm, CurrentIGI);/* ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); */ + pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked; + pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN; +} + +static void odm_CommonInfoSelfInit(struct odm_dm_struct *pDM_Odm) +{ + struct adapter *adapter = pDM_Odm->Adapter; + + pDM_Odm->bCckHighPower = (bool)rtl8188e_PHY_QueryBBReg(adapter, 0x824, BIT(9)); + pDM_Odm->RFPathRxEnable = (u8)rtl8188e_PHY_QueryBBReg(adapter, 0xc04, 0x0F); +} + +static void odm_CommonInfoSelfUpdate(struct odm_dm_struct *pDM_Odm) +{ + u8 EntryCnt = 0; + u8 i; + struct sta_info *pEntry; + + if (*pDM_Odm->pBandWidth == HT_CHANNEL_WIDTH_40) { + if (*pDM_Odm->pSecChOffset == 1) + pDM_Odm->ControlChannel = *pDM_Odm->pChannel - 2; + else if (*pDM_Odm->pSecChOffset == 2) + pDM_Odm->ControlChannel = *pDM_Odm->pChannel + 2; + } else { + pDM_Odm->ControlChannel = *pDM_Odm->pChannel; + } + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + pEntry = pDM_Odm->pODM_StaInfo[i]; + if (IS_STA_VALID(pEntry)) + EntryCnt++; + } + if (EntryCnt == 1) + pDM_Odm->bOneEntryOnly = true; + else + pDM_Odm->bOneEntryOnly = false; +} + +static void odm_RateAdaptiveMaskInit(struct odm_dm_struct *pDM_Odm) +{ + struct odm_rate_adapt *pOdmRA = &pDM_Odm->RateAdaptive; + + pOdmRA->RATRState = DM_RATR_STA_INIT; + pOdmRA->HighRSSIThresh = 50; + pOdmRA->LowRSSIThresh = 20; +} + +static void odm_RefreshRateAdaptiveMask(struct odm_dm_struct *pDM_Odm) +{ + u8 i; + struct adapter *pAdapter = pDM_Odm->Adapter; + + if (pAdapter->bDriverStopped) + return; + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + struct sta_info *pstat = pDM_Odm->pODM_StaInfo[i]; + + if (IS_STA_VALID(pstat)) { + if (ODM_RAStateCheck(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, false, &pstat->rssi_level)) + rtw_hal_update_ra_mask(pAdapter, i, pstat->rssi_level); + } + } +} + +static void odm_DynamicBBPowerSavingInit(struct odm_dm_struct *pDM_Odm) +{ + struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable; + + pDM_PSTable->pre_rf_state = RF_MAX; + pDM_PSTable->cur_rf_state = RF_MAX; + pDM_PSTable->initialize = 0; +} + +static void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm) +{ + u32 ret_value; + struct false_alarm_stats *FalseAlmCnt = &pDM_Odm->FalseAlmCnt; + struct adapter *adapter = pDM_Odm->Adapter; + + /* hold ofdm counter */ + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1); /* hold page C counter */ + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 1); /* hold page D counter */ + + ret_value = rtl8188e_PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord); + FalseAlmCnt->Cnt_Fast_Fsync = (ret_value & 0xffff); + FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value & 0xffff0000) >> 16); + ret_value = rtl8188e_PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord); + FalseAlmCnt->Cnt_OFDM_CCA = (ret_value & 0xffff); + FalseAlmCnt->Cnt_Parity_Fail = ((ret_value & 0xffff0000) >> 16); + ret_value = rtl8188e_PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord); + FalseAlmCnt->Cnt_Rate_Illegal = (ret_value & 0xffff); + FalseAlmCnt->Cnt_Crc8_fail = ((ret_value & 0xffff0000) >> 16); + ret_value = rtl8188e_PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord); + FalseAlmCnt->Cnt_Mcs_fail = (ret_value & 0xffff); + + FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal + + FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->Cnt_Mcs_fail + + FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail; + + ret_value = rtl8188e_PHY_QueryBBReg(adapter, ODM_REG_SC_CNT_11N, bMaskDWord); + FalseAlmCnt->Cnt_BW_LSC = (ret_value & 0xffff); + FalseAlmCnt->Cnt_BW_USC = ((ret_value & 0xffff0000) >> 16); + + /* hold cck counter */ + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT(12), 1); + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT(14), 1); + + ret_value = rtl8188e_PHY_QueryBBReg(adapter, ODM_REG_CCK_FA_LSB_11N, bMaskByte0); + FalseAlmCnt->Cnt_Cck_fail = ret_value; + ret_value = rtl8188e_PHY_QueryBBReg(adapter, ODM_REG_CCK_FA_MSB_11N, bMaskByte3); + FalseAlmCnt->Cnt_Cck_fail += (ret_value & 0xff) << 8; + + ret_value = rtl8188e_PHY_QueryBBReg(adapter, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord); + FalseAlmCnt->Cnt_CCK_CCA = ((ret_value & 0xFF) << 8) | ((ret_value & 0xFF00) >> 8); + + FalseAlmCnt->Cnt_all = (FalseAlmCnt->Cnt_Fast_Fsync + + FalseAlmCnt->Cnt_SB_Search_fail + + FalseAlmCnt->Cnt_Parity_Fail + + FalseAlmCnt->Cnt_Rate_Illegal + + FalseAlmCnt->Cnt_Crc8_fail + + FalseAlmCnt->Cnt_Mcs_fail + + FalseAlmCnt->Cnt_Cck_fail); + + FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA; +} + +static void odm_CCKPacketDetectionThresh(struct odm_dm_struct *pDM_Odm) +{ + u8 CurCCK_CCAThres; + struct false_alarm_stats *FalseAlmCnt = &pDM_Odm->FalseAlmCnt; + + if (pDM_Odm->bLinked) { + if (pDM_Odm->RSSI_Min > 25) { + CurCCK_CCAThres = 0xcd; + } else if ((pDM_Odm->RSSI_Min <= 25) && (pDM_Odm->RSSI_Min > 10)) { + CurCCK_CCAThres = 0x83; + } else { + if (FalseAlmCnt->Cnt_Cck_fail > 1000) + CurCCK_CCAThres = 0x83; + else + CurCCK_CCAThres = 0x40; + } + } else { + if (FalseAlmCnt->Cnt_Cck_fail > 1000) + CurCCK_CCAThres = 0x83; + else + CurCCK_CCAThres = 0x40; + } + ODM_Write_CCK_CCA_Thres(pDM_Odm, CurCCK_CCAThres); +} + +static void FindMinimumRSSI(struct adapter *pAdapter) +{ + struct hal_data_8188e *pHalData = &pAdapter->haldata; + struct dm_priv *pdmpriv = &pHalData->dmpriv; + struct mlme_priv *pmlmepriv = &pAdapter->mlmepriv; + + /* 1 1.Determine the minimum RSSI */ + if (!check_fwstate(pmlmepriv, _FW_LINKED) && + pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0) + pdmpriv->MinUndecoratedPWDBForDM = 0; + + pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB; +} + +static void odm_RSSIMonitorCheck(struct odm_dm_struct *pDM_Odm) +{ + struct adapter *Adapter = pDM_Odm->Adapter; + struct hal_data_8188e *pHalData = &Adapter->haldata; + struct dm_priv *pdmpriv = &pHalData->dmpriv; + int i; + int tmpEntryMaxPWDB = 0, tmpEntryMinPWDB = 0xff; + u8 sta_cnt = 0; + u32 PWDB_rssi[NUM_STA] = {0};/* 0~15]:MACID, [16~31]:PWDB_rssi */ + struct sta_info *psta; + + if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR)) + return; + + if (!check_fwstate(&Adapter->mlmepriv, _FW_LINKED)) + return; + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + psta = pDM_Odm->pODM_StaInfo[i]; + if (IS_STA_VALID(psta) && + (psta->state & WIFI_ASOC_STATE) && + !is_broadcast_ether_addr(psta->hwaddr) && + memcmp(psta->hwaddr, myid(&Adapter->eeprompriv), ETH_ALEN)) { + if (psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB) + tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB; + + if (psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB) + tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB; + if (psta->rssi_stat.UndecoratedSmoothedPWDB != (-1)) + PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB << 16)); + } + } + + for (i = 0; i < sta_cnt; i++) { + if (PWDB_rssi[i] != (0)) { + if (pHalData->fw_ractrl) { + /* Report every sta's RSSI to FW */ + } else { + ODM_RA_SetRSSI_8188E( + &pHalData->odmpriv, (PWDB_rssi[i] & 0xFF), (u8)((PWDB_rssi[i] >> 16) & 0xFF)); + } + } + } + + if (tmpEntryMinPWDB != 0xff) /* If associated entry is found */ + pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB; + else + pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0; + + FindMinimumRSSI(Adapter); + pHalData->odmpriv.RSSI_Min = pdmpriv->MinUndecoratedPWDBForDM; +} + +static void odm_TXPowerTrackingThermalMeterInit(struct odm_dm_struct *pDM_Odm) +{ + pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true; +} + +static void odm_InitHybridAntDiv(struct odm_dm_struct *pDM_Odm) +{ + if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) + return; + + ODM_AntennaDiversityInit_88E(pDM_Odm); +} + +static void odm_HwAntDiv(struct odm_dm_struct *pDM_Odm) +{ + if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) + return; + + ODM_AntennaDiversity_88E(pDM_Odm); +} + +static void ODM_EdcaTurboInit(struct odm_dm_struct *pDM_Odm) +{ + struct adapter *Adapter = pDM_Odm->Adapter; + pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false; + pDM_Odm->DM_EDCA_Table.bIsCurRDLState = false; + Adapter->recvpriv.bIsAnyNonBEPkts = false; +} + +static void odm_EdcaTurboCheck(struct odm_dm_struct *pDM_Odm) +{ + struct adapter *Adapter = pDM_Odm->Adapter; + u32 trafficIndex; + u32 edca_param; + u64 cur_tx_bytes = 0; + u64 cur_rx_bytes = 0; + u8 bbtchange = false; + struct hal_data_8188e *pHalData = &Adapter->haldata; + struct xmit_priv *pxmitpriv = &Adapter->xmitpriv; + struct recv_priv *precvpriv = &Adapter->recvpriv; + struct registry_priv *pregpriv = &Adapter->registrypriv; + struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + + if (pregpriv->wifi_spec == 1) + goto dm_CheckEdcaTurbo_EXIT; + + if (pmlmeinfo->assoc_AP_vendor >= HT_IOT_PEER_MAX) + goto dm_CheckEdcaTurbo_EXIT; + + /* Check if the status needs to be changed. */ + if ((bbtchange) || (!precvpriv->bIsAnyNonBEPkts)) { + cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes; + cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes; + + /* traffic, TX or RX */ + if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_RALINK) || + (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS)) { + if (cur_tx_bytes > (cur_rx_bytes << 2)) { + /* Uplink TP is present. */ + trafficIndex = UP_LINK; + } else { + /* Balance TP is present. */ + trafficIndex = DOWN_LINK; + } + } else { + if (cur_rx_bytes > (cur_tx_bytes << 2)) { + /* Downlink TP is present. */ + trafficIndex = DOWN_LINK; + } else { + /* Balance TP is present. */ + trafficIndex = UP_LINK; + } + } + + if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) || (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)) { + if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_CISCO) && (pmlmeext->cur_wireless_mode & WIRELESS_11_24N)) + edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex]; + else + edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex]; + + rtw_write32(Adapter, REG_EDCA_BE_PARAM, edca_param); + + pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex; + } + + pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = true; + } else { + /* Turn Off EDCA turbo here. */ + /* Restore original EDCA according to the declaration of AP. */ + if (pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) { + rtw_write32(Adapter, REG_EDCA_BE_PARAM, pHalData->AcParam_BE); + pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false; + } + } + +dm_CheckEdcaTurbo_EXIT: + /* Set variables for next time. */ + precvpriv->bIsAnyNonBEPkts = false; + pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes; + precvpriv->last_rx_bytes = precvpriv->rx_bytes; +} + +/* 2011/09/21 MH Add to describe different team necessary resource allocate?? */ +void ODM_DMInit(struct odm_dm_struct *pDM_Odm) +{ + /* 2012.05.03 Luke: For all IC series */ + odm_CommonInfoSelfInit(pDM_Odm); + odm_DIGInit(pDM_Odm); + odm_RateAdaptiveMaskInit(pDM_Odm); + + odm_DynamicBBPowerSavingInit(pDM_Odm); + odm_TXPowerTrackingThermalMeterInit(pDM_Odm); + ODM_EdcaTurboInit(pDM_Odm); + ODM_RAInfo_Init_all(pDM_Odm); + if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) || + (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) || + (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)) + odm_InitHybridAntDiv(pDM_Odm); +} + +/* 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. */ +/* You can not add any dummy function here, be care, you can only use DM structure */ +/* to perform any new ODM_DM. */ +void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm) +{ + /* 2012.05.03 Luke: For all IC series */ + odm_CommonInfoSelfUpdate(pDM_Odm); + odm_FalseAlarmCounterStatistics(pDM_Odm); + odm_RSSIMonitorCheck(pDM_Odm); + + odm_DIG(pDM_Odm); + odm_CCKPacketDetectionThresh(pDM_Odm); + + if (*pDM_Odm->pbPowerSaving) + return; + + odm_RefreshRateAdaptiveMask(pDM_Odm); + + if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) || + (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) || + (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)) + odm_HwAntDiv(pDM_Odm); + + ODM_TXPowerTrackingCheck(pDM_Odm); + odm_EdcaTurboCheck(pDM_Odm); +} + +/* Init /.. Fixed HW value. Only init time. */ +void ODM_CmnInfoInit(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, u32 Value) +{ + /* This section is used for init value */ + switch (CmnInfo) { + /* Fixed ODM value. */ + case ODM_CMNINFO_MP_TEST_CHIP: + pDM_Odm->bIsMPChip = (u8)Value; + break; + case ODM_CMNINFO_RF_ANTENNA_TYPE: + pDM_Odm->AntDivType = (u8)Value; + break; + default: + /* do nothing */ + break; + } + + /* Tx power tracking BB swing table. */ + /* The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB */ + pDM_Odm->BbSwingIdxOfdm = 12; /* Set defalut value as index 12. */ + pDM_Odm->BbSwingIdxOfdmCurrent = 12; + pDM_Odm->BbSwingFlagOfdm = false; +} + +void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI) +{ + struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; + struct adapter *adapter = pDM_Odm->Adapter; + + if (pDM_DigTable->CurIGValue != CurrentIGI) { + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, ODM_BIT_IGI_11N, CurrentIGI); + pDM_DigTable->CurIGValue = CurrentIGI; + } +} + +void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres) +{ + struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; + + if (pDM_DigTable->CurCCK_CCAThres != CurCCK_CCAThres) /* modify by Guo.Mingzhi 2012-01-03 */ + rtw_write8(pDM_Odm->Adapter, ODM_REG_CCK_CCA_11N, CurCCK_CCAThres); + pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres; +} + +void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal) +{ + struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable; + struct adapter *adapter = pDM_Odm->Adapter; + u8 Rssi_Up_bound = 30; + u8 Rssi_Low_bound = 25; + + if (pDM_PSTable->initialize == 0) { + pDM_PSTable->reg_874 = (rtl8188e_PHY_QueryBBReg(adapter, 0x874, bMaskDWord) & 0x1CC000) >> 14; + pDM_PSTable->reg_c70 = (rtl8188e_PHY_QueryBBReg(adapter, 0xc70, bMaskDWord) & BIT(3)) >> 3; + pDM_PSTable->reg_85c = (rtl8188e_PHY_QueryBBReg(adapter, 0x85c, bMaskDWord) & 0xFF000000) >> 24; + pDM_PSTable->reg_a74 = (rtl8188e_PHY_QueryBBReg(adapter, 0xa74, bMaskDWord) & 0xF000) >> 12; + pDM_PSTable->initialize = 1; + } + + if (!bForceInNormal) { + if (pDM_Odm->RSSI_Min != 0xFF) { + if (pDM_PSTable->pre_rf_state == RF_Normal) { + if (pDM_Odm->RSSI_Min >= Rssi_Up_bound) + pDM_PSTable->cur_rf_state = RF_Save; + else + pDM_PSTable->cur_rf_state = RF_Normal; + } else { + if (pDM_Odm->RSSI_Min <= Rssi_Low_bound) + pDM_PSTable->cur_rf_state = RF_Normal; + else + pDM_PSTable->cur_rf_state = RF_Save; + } + } else { + pDM_PSTable->cur_rf_state = RF_MAX; + } + } else { + pDM_PSTable->cur_rf_state = RF_Normal; + } + + if (pDM_PSTable->pre_rf_state != pDM_PSTable->cur_rf_state) { + if (pDM_PSTable->cur_rf_state == RF_Save) { + rtl8188e_PHY_SetBBReg(adapter, 0x874, 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */ + rtl8188e_PHY_SetBBReg(adapter, 0xc70, BIT(3), 0); /* RegC70[3]=1'b0 */ + rtl8188e_PHY_SetBBReg(adapter, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]=0x63 */ + rtl8188e_PHY_SetBBReg(adapter, 0x874, 0xC000, 0x2); /* Reg874[15:14]=2'b10 */ + rtl8188e_PHY_SetBBReg(adapter, 0xa74, 0xF000, 0x3); /* RegA75[7:4]=0x3 */ + rtl8188e_PHY_SetBBReg(adapter, 0x818, BIT(28), 0x0); /* Reg818[28]=1'b0 */ + rtl8188e_PHY_SetBBReg(adapter, 0x818, BIT(28), 0x1); /* Reg818[28]=1'b1 */ + } else { + rtl8188e_PHY_SetBBReg(adapter, 0x874, 0x1CC000, pDM_PSTable->reg_874); + rtl8188e_PHY_SetBBReg(adapter, 0xc70, BIT(3), pDM_PSTable->reg_c70); + rtl8188e_PHY_SetBBReg(adapter, 0x85c, 0xFF000000, pDM_PSTable->reg_85c); + rtl8188e_PHY_SetBBReg(adapter, 0xa74, 0xF000, pDM_PSTable->reg_a74); + rtl8188e_PHY_SetBBReg(adapter, 0x818, BIT(28), 0x0); + } + pDM_PSTable->pre_rf_state = pDM_PSTable->cur_rf_state; + } +} + +u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid, u32 ra_mask, u8 rssi_level) +{ + struct sta_info *pEntry; + u32 rate_bitmap = 0x0fffffff; + u8 WirelessMode; + + pEntry = pDM_Odm->pODM_StaInfo[macid]; + if (!IS_STA_VALID(pEntry)) + return ra_mask; + + WirelessMode = pEntry->wireless_mode; + + switch (WirelessMode) { + case ODM_WM_B: + if (ra_mask & 0x0000000c) /* 11M or 5.5M enable */ + rate_bitmap = 0x0000000d; + else + rate_bitmap = 0x0000000f; + break; + case (ODM_WM_B | ODM_WM_G): + if (rssi_level == DM_RATR_STA_HIGH) + rate_bitmap = 0x00000f00; + else if (rssi_level == DM_RATR_STA_MIDDLE) + rate_bitmap = 0x00000ff0; + else + rate_bitmap = 0x00000ff5; + break; + case (ODM_WM_B | ODM_WM_G | ODM_WM_N24G): + if (rssi_level == DM_RATR_STA_HIGH) { + rate_bitmap = 0x000f0000; + } else if (rssi_level == DM_RATR_STA_MIDDLE) { + rate_bitmap = 0x000ff000; + } else { + if (*pDM_Odm->pBandWidth == HT_CHANNEL_WIDTH_40) + rate_bitmap = 0x000ff015; + else + rate_bitmap = 0x000ff005; + } + break; + default: + /* case WIRELESS_11_24N: */ + rate_bitmap = 0x0fffffff; + break; + } + + return rate_bitmap; +} + +/* Return Value: bool */ +/* - true: RATRState is changed. */ +bool ODM_RAStateCheck(struct odm_dm_struct *pDM_Odm, s32 RSSI, bool bForceUpdate, u8 *pRATRState) +{ + struct odm_rate_adapt *pRA = &pDM_Odm->RateAdaptive; + const u8 GoUpGap = 5; + u8 HighRSSIThreshForRA = pRA->HighRSSIThresh; + u8 LowRSSIThreshForRA = pRA->LowRSSIThresh; + u8 RATRState; + + /* Threshold Adjustment: */ + /* when RSSI state trends to go up one or two levels, make sure RSSI is high enough. */ + /* Here GoUpGap is added to solve the boundary's level alternation issue. */ + switch (*pRATRState) { + case DM_RATR_STA_INIT: + case DM_RATR_STA_HIGH: + break; + case DM_RATR_STA_MIDDLE: + HighRSSIThreshForRA += GoUpGap; + break; + case DM_RATR_STA_LOW: + HighRSSIThreshForRA += GoUpGap; + LowRSSIThreshForRA += GoUpGap; + break; + default: + break; + } + + /* Decide RATRState by RSSI. */ + if (RSSI > HighRSSIThreshForRA) + RATRState = DM_RATR_STA_HIGH; + else if (RSSI > LowRSSIThreshForRA) + RATRState = DM_RATR_STA_MIDDLE; + else + RATRState = DM_RATR_STA_LOW; + + if (*pRATRState != RATRState || bForceUpdate) { + *pRATRState = RATRState; + return true; + } + return false; +} + +void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm) +{ + struct adapter *Adapter = pDM_Odm->Adapter; + + if (!pDM_Odm->RFCalibrateInfo.TM_Trigger) { /* at least delay 1 sec */ + rtl8188e_PHY_SetRFReg(Adapter, RF_T_METER_88E, BIT(17) | BIT(16), 0x03); + + pDM_Odm->RFCalibrateInfo.TM_Trigger = 1; + return; + } else { + odm_TXPowerTrackingCallback_ThermalMeter_8188E(Adapter); + pDM_Odm->RFCalibrateInfo.TM_Trigger = 0; + } +} diff --git a/drivers/staging/r8188eu/hal/odm_HWConfig.c b/drivers/staging/r8188eu/hal/odm_HWConfig.c new file mode 100644 index 000000000..38f357e8a --- /dev/null +++ b/drivers/staging/r8188eu/hal/odm_HWConfig.c @@ -0,0 +1,349 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright(c) 2007 - 2011 Realtek Corporation. */ + +#include "../include/drv_types.h" + +static u8 odm_query_rxpwrpercentage(s8 antpower) +{ + if ((antpower <= -100) || (antpower >= 20)) + return 0; + else if (antpower >= 0) + return 100; + else + return 100 + antpower; +} + +static s32 odm_signal_scale_mapping(struct odm_dm_struct *dm_odm, s32 currsig) +{ + s32 retsig; + + if (currsig >= 51 && currsig <= 100) + retsig = 100; + else if (currsig >= 41 && currsig <= 50) + retsig = 80 + ((currsig - 40) * 2); + else if (currsig >= 31 && currsig <= 40) + retsig = 66 + (currsig - 30); + else if (currsig >= 21 && currsig <= 30) + retsig = 54 + (currsig - 20); + else if (currsig >= 10 && currsig <= 20) + retsig = 42 + (((currsig - 10) * 2) / 3); + else if (currsig >= 5 && currsig <= 9) + retsig = 22 + (((currsig - 5) * 3) / 2); + else if (currsig >= 1 && currsig <= 4) + retsig = 6 + (((currsig - 1) * 3) / 2); + else + retsig = currsig; + + return retsig; +} + +static u8 odm_evm_db_to_percentage(s8 value) +{ + /* -33dB~0dB to 0%~99% */ + s8 ret_val = clamp(-value, 0, 33) * 3; + + if (ret_val == 99) + ret_val = 100; + + return ret_val; +} + +static void odm_RxPhyStatus92CSeries_Parsing(struct odm_dm_struct *dm_odm, + struct phy_info *pPhyInfo, + u8 *pPhyStatus, + struct odm_per_pkt_info *pPktinfo, + struct adapter *adapt) +{ + u8 i, Max_spatial_stream; + s8 rx_pwr[4], rx_pwr_all = 0; + u8 EVM, PWDB_ALL = 0; + u8 RSSI, total_rssi = 0; + u8 isCCKrate = 0; + u8 rf_rx_num = 0; + u8 cck_highpwr = 0; + u8 LNA_idx, VGA_idx; + + struct phy_status_rpt *pPhyStaRpt = (struct phy_status_rpt *)pPhyStatus; + + isCCKrate = pPktinfo->Rate >= DESC92C_RATE1M && pPktinfo->Rate <= DESC92C_RATE11M; + + if (isCCKrate) { + u8 cck_agc_rpt; + + /* (1)Hardware does not provide RSSI for CCK */ + /* (2)PWDB, Average PWDB calculated by hardware (for rate adaptive) */ + + cck_highpwr = dm_odm->bCckHighPower; + + cck_agc_rpt = pPhyStaRpt->cck_agc_rpt_ofdm_cfosho_a; + + /* 2011.11.28 LukeLee: 88E use different LNA & VGA gain table */ + /* The RSSI formula should be modified according to the gain table */ + /* In 88E, cck_highpwr is always set to 1 */ + LNA_idx = ((cck_agc_rpt & 0xE0) >> 5); + VGA_idx = (cck_agc_rpt & 0x1F); + switch (LNA_idx) { + case 7: + if (VGA_idx <= 27) + rx_pwr_all = -100 + 2 * (27 - VGA_idx); /* VGA_idx = 27~2 */ + else + rx_pwr_all = -100; + break; + case 6: + rx_pwr_all = -48 + 2 * (2 - VGA_idx); /* VGA_idx = 2~0 */ + break; + case 5: + rx_pwr_all = -42 + 2 * (7 - VGA_idx); /* VGA_idx = 7~5 */ + break; + case 4: + rx_pwr_all = -36 + 2 * (7 - VGA_idx); /* VGA_idx = 7~4 */ + break; + case 3: + rx_pwr_all = -24 + 2 * (7 - VGA_idx); /* VGA_idx = 7~0 */ + break; + case 2: + if (cck_highpwr) + rx_pwr_all = -12 + 2 * (5 - VGA_idx); /* VGA_idx = 5~0 */ + else + rx_pwr_all = -6 + 2 * (5 - VGA_idx); + break; + case 1: + rx_pwr_all = 8 - 2 * VGA_idx; + break; + case 0: + rx_pwr_all = 14 - 2 * VGA_idx; + break; + default: + break; + } + rx_pwr_all += 6; + PWDB_ALL = odm_query_rxpwrpercentage(rx_pwr_all); + if (!cck_highpwr) { + if (PWDB_ALL >= 80) + PWDB_ALL = ((PWDB_ALL - 80) << 1) + ((PWDB_ALL - 80) >> 1) + 80; + else if ((PWDB_ALL <= 78) && (PWDB_ALL >= 20)) + PWDB_ALL += 3; + if (PWDB_ALL > 100) + PWDB_ALL = 100; + } + + pPhyInfo->RxPWDBAll = PWDB_ALL; + pPhyInfo->recvpower = rx_pwr_all; + /* (3) Get Signal Quality (EVM) */ + if (pPktinfo->bPacketMatchBSSID) { + u8 SQ, SQ_rpt; + + if (pPhyInfo->RxPWDBAll > 40) { + SQ = 100; + } else { + SQ_rpt = pPhyStaRpt->cck_sig_qual_ofdm_pwdb_all; + + if (SQ_rpt > 64) + SQ = 0; + else if (SQ_rpt < 20) + SQ = 100; + else + SQ = ((64 - SQ_rpt) * 100) / 44; + } + pPhyInfo->SignalQuality = SQ; + } + } else { /* is OFDM rate */ + /* (1)Get RSSI for HT rate */ + + for (i = RF_PATH_A; i < RF_PATH_MAX; i++) { + /* 2008/01/30 MH we will judge RF RX path now. */ + if (dm_odm->RFPathRxEnable & BIT(i)) + rf_rx_num++; + + rx_pwr[i] = ((pPhyStaRpt->path_agc[i].gain & 0x3F) * 2) - 110; + if (i == RF_PATH_A) + adapt->signal_strength = rx_pwr[i]; + + pPhyInfo->RxPwr[i] = rx_pwr[i]; + + /* Translate DBM to percentage. */ + RSSI = odm_query_rxpwrpercentage(rx_pwr[i]); + total_rssi += RSSI; + + pPhyInfo->RxMIMOSignalStrength[i] = (u8)RSSI; + + /* Get Rx snr value in DB */ + dm_odm->PhyDbgInfo.RxSNRdB[i] = (s32)(pPhyStaRpt->path_rxsnr[i] / 2); + } + /* (2)PWDB, Average PWDB calculated by hardware (for rate adaptive) */ + rx_pwr_all = (((pPhyStaRpt->cck_sig_qual_ofdm_pwdb_all) >> 1) & 0x7f) - 110; + + PWDB_ALL = odm_query_rxpwrpercentage(rx_pwr_all); + + pPhyInfo->RxPWDBAll = PWDB_ALL; + pPhyInfo->RxPower = rx_pwr_all; + pPhyInfo->recvpower = rx_pwr_all; + + /* (3)EVM of HT rate */ + if (pPktinfo->Rate >= DESC92C_RATEMCS8 && pPktinfo->Rate <= DESC92C_RATEMCS15) + Max_spatial_stream = 2; /* both spatial stream make sense */ + else + Max_spatial_stream = 1; /* only spatial stream 1 makes sense */ + + for (i = 0; i < Max_spatial_stream; i++) { + /* Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment */ + /* fill most significant bit to "zero" when doing shifting operation which may change a negative */ + /* value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore. */ + EVM = odm_evm_db_to_percentage((pPhyStaRpt->stream_rxevm[i])); /* dbm */ + + if (pPktinfo->bPacketMatchBSSID) { + if (i == RF_PATH_A) /* Fill value in RFD, Get the first spatial stream only */ + pPhyInfo->SignalQuality = (u8)(EVM & 0xff); + } + } + } + /* UI BSS List signal strength(in percentage), make it good looking, from 0~100. */ + /* It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp(). */ + if (isCCKrate) { + pPhyInfo->SignalStrength = (u8)(odm_signal_scale_mapping(dm_odm, PWDB_ALL));/* PWDB_ALL; */ + } else { + if (rf_rx_num != 0) + pPhyInfo->SignalStrength = (u8)(odm_signal_scale_mapping(dm_odm, total_rssi /= rf_rx_num)); + } + + /* For 88E HW Antenna Diversity */ + dm_odm->DM_FatTable.antsel_rx_keep_0 = pPhyStaRpt->ant_sel; + dm_odm->DM_FatTable.antsel_rx_keep_1 = pPhyStaRpt->ant_sel_b; + dm_odm->DM_FatTable.antsel_rx_keep_2 = pPhyStaRpt->antsel_rx_keep_2; +} + +static void odm_Process_RSSIForDM(struct odm_dm_struct *dm_odm, + struct phy_info *pPhyInfo, + struct odm_per_pkt_info *pPktinfo) +{ + s32 UndecoratedSmoothedPWDB, UndecoratedSmoothedCCK; + s32 UndecoratedSmoothedOFDM, RSSI_Ave; + u8 isCCKrate = 0; + u8 RSSI_max, RSSI_min, i; + u32 OFDM_pkt = 0; + u32 Weighting = 0; + struct sta_info *pEntry; + u8 antsel_tr_mux; + struct fast_ant_train *pDM_FatTable = &dm_odm->DM_FatTable; + + if (pPktinfo->StationID == 0xFF) + return; + pEntry = dm_odm->pODM_StaInfo[pPktinfo->StationID]; + if (!IS_STA_VALID(pEntry)) + return; + if ((!pPktinfo->bPacketMatchBSSID)) + return; + + isCCKrate = pPktinfo->Rate >= DESC92C_RATE1M && pPktinfo->Rate <= DESC92C_RATE11M; + + /* Smart Antenna Debug Message------------------ */ + if ((dm_odm->AntDivType == CG_TRX_HW_ANTDIV) || (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV)) { + if (pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon) { + antsel_tr_mux = (pDM_FatTable->antsel_rx_keep_2 << 2) | + (pDM_FatTable->antsel_rx_keep_1 << 1) | pDM_FatTable->antsel_rx_keep_0; + ODM_AntselStatistics_88E(dm_odm, antsel_tr_mux, pPktinfo->StationID, pPhyInfo->RxPWDBAll); + } + } + + /* Smart Antenna Debug Message------------------ */ + + UndecoratedSmoothedCCK = pEntry->rssi_stat.UndecoratedSmoothedCCK; + UndecoratedSmoothedOFDM = pEntry->rssi_stat.UndecoratedSmoothedOFDM; + UndecoratedSmoothedPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB; + + if (pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon) { + if (!isCCKrate) { /* ofdm rate */ + if (pPhyInfo->RxMIMOSignalStrength[RF_PATH_B] == 0) { + RSSI_Ave = pPhyInfo->RxMIMOSignalStrength[RF_PATH_A]; + } else { + if (pPhyInfo->RxMIMOSignalStrength[RF_PATH_A] > pPhyInfo->RxMIMOSignalStrength[RF_PATH_B]) { + RSSI_max = pPhyInfo->RxMIMOSignalStrength[RF_PATH_A]; + RSSI_min = pPhyInfo->RxMIMOSignalStrength[RF_PATH_B]; + } else { + RSSI_max = pPhyInfo->RxMIMOSignalStrength[RF_PATH_B]; + RSSI_min = pPhyInfo->RxMIMOSignalStrength[RF_PATH_A]; + } + if ((RSSI_max - RSSI_min) < 3) + RSSI_Ave = RSSI_max; + else if ((RSSI_max - RSSI_min) < 6) + RSSI_Ave = RSSI_max - 1; + else if ((RSSI_max - RSSI_min) < 10) + RSSI_Ave = RSSI_max - 2; + else + RSSI_Ave = RSSI_max - 3; + } + + /* 1 Process OFDM RSSI */ + if (UndecoratedSmoothedOFDM <= 0) { /* initialize */ + UndecoratedSmoothedOFDM = pPhyInfo->RxPWDBAll; + } else { + if (pPhyInfo->RxPWDBAll > (u32)UndecoratedSmoothedOFDM) { + UndecoratedSmoothedOFDM = + (((UndecoratedSmoothedOFDM) * (Rx_Smooth_Factor - 1)) + + (RSSI_Ave)) / (Rx_Smooth_Factor); + UndecoratedSmoothedOFDM = UndecoratedSmoothedOFDM + 1; + } else { + UndecoratedSmoothedOFDM = + (((UndecoratedSmoothedOFDM) * (Rx_Smooth_Factor - 1)) + + (RSSI_Ave)) / (Rx_Smooth_Factor); + } + } + + pEntry->rssi_stat.PacketMap = (pEntry->rssi_stat.PacketMap << 1) | BIT(0); + + } else { + RSSI_Ave = pPhyInfo->RxPWDBAll; + + /* 1 Process CCK RSSI */ + if (UndecoratedSmoothedCCK <= 0) { /* initialize */ + UndecoratedSmoothedCCK = pPhyInfo->RxPWDBAll; + } else { + if (pPhyInfo->RxPWDBAll > (u32)UndecoratedSmoothedCCK) { + UndecoratedSmoothedCCK = + ((UndecoratedSmoothedCCK * (Rx_Smooth_Factor - 1)) + + pPhyInfo->RxPWDBAll) / Rx_Smooth_Factor; + UndecoratedSmoothedCCK = UndecoratedSmoothedCCK + 1; + } else { + UndecoratedSmoothedCCK = + ((UndecoratedSmoothedCCK * (Rx_Smooth_Factor - 1)) + + pPhyInfo->RxPWDBAll) / Rx_Smooth_Factor; + } + } + pEntry->rssi_stat.PacketMap = pEntry->rssi_stat.PacketMap << 1; + } + /* 2011.07.28 LukeLee: modified to prevent unstable CCK RSSI */ + if (pEntry->rssi_stat.ValidBit >= 64) + pEntry->rssi_stat.ValidBit = 64; + else + pEntry->rssi_stat.ValidBit++; + + for (i = 0; i < pEntry->rssi_stat.ValidBit; i++) + OFDM_pkt += (u8)(pEntry->rssi_stat.PacketMap >> i) & BIT(0); + + if (pEntry->rssi_stat.ValidBit == 64) { + Weighting = ((OFDM_pkt << 4) > 64) ? 64 : (OFDM_pkt << 4); + UndecoratedSmoothedPWDB = (Weighting * UndecoratedSmoothedOFDM + (64 - Weighting) * UndecoratedSmoothedCCK) >> 6; + } else { + if (pEntry->rssi_stat.ValidBit != 0) + UndecoratedSmoothedPWDB = (OFDM_pkt * UndecoratedSmoothedOFDM + + (pEntry->rssi_stat.ValidBit - OFDM_pkt) * + UndecoratedSmoothedCCK) / pEntry->rssi_stat.ValidBit; + else + UndecoratedSmoothedPWDB = 0; + } + pEntry->rssi_stat.UndecoratedSmoothedCCK = UndecoratedSmoothedCCK; + pEntry->rssi_stat.UndecoratedSmoothedOFDM = UndecoratedSmoothedOFDM; + pEntry->rssi_stat.UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB; + } +} + +/* Endianness before calling this API */ +void ODM_PhyStatusQuery(struct odm_dm_struct *dm_odm, + struct phy_info *pPhyInfo, + u8 *pPhyStatus, + struct odm_per_pkt_info *pPktinfo, + struct adapter *adapt) +{ + odm_RxPhyStatus92CSeries_Parsing(dm_odm, pPhyInfo, pPhyStatus, pPktinfo, adapt); + odm_Process_RSSIForDM(dm_odm, pPhyInfo, pPktinfo); +} diff --git a/drivers/staging/r8188eu/hal/odm_RTL8188E.c b/drivers/staging/r8188eu/hal/odm_RTL8188E.c new file mode 100644 index 000000000..c8a3c521b --- /dev/null +++ b/drivers/staging/r8188eu/hal/odm_RTL8188E.c @@ -0,0 +1,264 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright(c) 2007 - 2011 Realtek Corporation. */ + +#include "../include/drv_types.h" + +static void odm_RX_HWAntDivInit(struct odm_dm_struct *dm_odm) +{ + struct adapter *adapter = dm_odm->Adapter; + u32 value32; + + /* MAC Setting */ + value32 = rtl8188e_PHY_QueryBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord); + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */ + /* Pin Settings */ + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */ + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* Reg864[10]=1'b0 antsel2 by HW */ + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(22), 1); /* Regb2c[22]=1'b0 disable CS/CG switch */ + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* Regb2c[31]=1'b1 output at CG only */ + /* OFDM Settings */ + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, 0x000000a0); + /* CCK Settings */ + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* Fix CCK PHY status report issue */ + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */ + ODM_UpdateRxIdleAnt_88E(dm_odm, MAIN_ANT); + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0201); /* antenna mapping table */ +} + +static void odm_TRX_HWAntDivInit(struct odm_dm_struct *dm_odm) +{ + struct adapter *adapter = dm_odm->Adapter; + u32 value32; + + /* MAC Setting */ + value32 = rtl8188e_PHY_QueryBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord); + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */ + /* Pin Settings */ + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */ + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* Reg864[10]=1'b0 antsel2 by HW */ + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(22), 0); /* Regb2c[22]=1'b0 disable CS/CG switch */ + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* Regb2c[31]=1'b1 output at CG only */ + /* OFDM Settings */ + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, 0x000000a0); + /* CCK Settings */ + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* Fix CCK PHY status report issue */ + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */ + /* Tx Settings */ + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT(21), 0); /* Reg80c[21]=1'b0 from TX Reg */ + ODM_UpdateRxIdleAnt_88E(dm_odm, MAIN_ANT); + + /* antenna mapping table */ + if (!dm_odm->bIsMPChip) { /* testchip */ + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_DEFUALT_A_11N, BIT(10) | BIT(9) | BIT(8), 1); /* Reg858[10:8]=3'b001 */ + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_DEFUALT_A_11N, BIT(13) | BIT(12) | BIT(11), 2); /* Reg858[13:11]=3'b010 */ + } else { /* MPchip */ + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANT_MAPPING1_11N, bMaskDWord, 0x0201); /* Reg914=3'b010, Reg915=3'b001 */ + } +} + +static void odm_FastAntTrainingInit(struct odm_dm_struct *dm_odm) +{ + struct adapter *adapter = dm_odm->Adapter; + u32 value32; + + /* MAC Setting */ + value32 = rtl8188e_PHY_QueryBBReg(adapter, 0x4c, bMaskDWord); + rtl8188e_PHY_SetBBReg(adapter, 0x4c, bMaskDWord, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */ + value32 = rtl8188e_PHY_QueryBBReg(adapter, 0x7B4, bMaskDWord); + rtl8188e_PHY_SetBBReg(adapter, 0x7b4, bMaskDWord, value32 | (BIT(16) | BIT(17))); /* Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match */ + + /* Match MAC ADDR */ + rtl8188e_PHY_SetBBReg(adapter, 0x7b4, 0xFFFF, 0); + rtl8188e_PHY_SetBBReg(adapter, 0x7b0, bMaskDWord, 0); + + rtl8188e_PHY_SetBBReg(adapter, 0x870, BIT(9) | BIT(8), 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */ + rtl8188e_PHY_SetBBReg(adapter, 0x864, BIT(10), 0); /* Reg864[10]=1'b0 antsel2 by HW */ + rtl8188e_PHY_SetBBReg(adapter, 0xb2c, BIT(22), 0); /* Regb2c[22]=1'b0 disable CS/CG switch */ + rtl8188e_PHY_SetBBReg(adapter, 0xb2c, BIT(31), 1); /* Regb2c[31]=1'b1 output at CG only */ + rtl8188e_PHY_SetBBReg(adapter, 0xca4, bMaskDWord, 0x000000a0); + + if (!dm_odm->bIsMPChip) { /* testchip */ + rtl8188e_PHY_SetBBReg(adapter, 0x858, BIT(10) | BIT(9) | BIT(8), 1); /* Reg858[10:8]=3'b001 */ + rtl8188e_PHY_SetBBReg(adapter, 0x858, BIT(13) | BIT(12) | BIT(11), 2); /* Reg858[13:11]=3'b010 */ + } else { /* MPchip */ + rtl8188e_PHY_SetBBReg(adapter, 0x914, bMaskByte0, 1); + rtl8188e_PHY_SetBBReg(adapter, 0x914, bMaskByte1, 2); + } + + /* Default Ant Setting when no fast training */ + rtl8188e_PHY_SetBBReg(adapter, 0x80c, BIT(21), 1); /* Reg80c[21]=1'b1 from TX Info */ + rtl8188e_PHY_SetBBReg(adapter, 0x864, BIT(5) | BIT(4) | BIT(3), 0); /* Default RX */ + rtl8188e_PHY_SetBBReg(adapter, 0x864, BIT(8) | BIT(7) | BIT(6), 1); /* Optional RX */ + + /* Enter Training state */ + rtl8188e_PHY_SetBBReg(adapter, 0x864, BIT(2) | BIT(1) | BIT(0), 1); + rtl8188e_PHY_SetBBReg(adapter, 0xc50, BIT(7), 1); /* RegC50[7]=1'b1 enable HW AntDiv */ +} + +void ODM_AntennaDiversityInit_88E(struct odm_dm_struct *dm_odm) +{ + if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) + odm_RX_HWAntDivInit(dm_odm); + else if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) + odm_TRX_HWAntDivInit(dm_odm); + else if (dm_odm->AntDivType == CG_TRX_SMART_ANTDIV) + odm_FastAntTrainingInit(dm_odm); +} + +void ODM_UpdateRxIdleAnt_88E(struct odm_dm_struct *dm_odm, u8 Ant) +{ + struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable; + struct adapter *adapter = dm_odm->Adapter; + u32 DefaultAnt, OptionalAnt; + + if (dm_fat_tbl->RxIdleAnt != Ant) { + if (Ant == MAIN_ANT) { + DefaultAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX; + OptionalAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX; + } else { + DefaultAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX; + OptionalAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX; + } + + if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) { + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(5) | BIT(4) | BIT(3), DefaultAnt); /* Default RX */ + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(8) | BIT(7) | BIT(6), OptionalAnt); /* Optional RX */ + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_ANTSEL_CTRL_11N, BIT(14) | BIT(13) | BIT(12), DefaultAnt); /* Default TX */ + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RESP_TX_11N, BIT(6) | BIT(7), DefaultAnt); /* Resp Tx */ + } else if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) { + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(5) | BIT(4) | BIT(3), DefaultAnt); /* Default RX */ + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(8) | BIT(7) | BIT(6), OptionalAnt); /* Optional RX */ + } + } + dm_fat_tbl->RxIdleAnt = Ant; + if (Ant != MAIN_ANT) + pr_info("RxIdleAnt=AUX_ANT\n"); +} + +static void odm_UpdateTxAnt_88E(struct odm_dm_struct *dm_odm, u8 Ant, u32 MacId) +{ + struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable; + u8 TargetAnt; + + if (Ant == MAIN_ANT) + TargetAnt = MAIN_ANT_CG_TRX; + else + TargetAnt = AUX_ANT_CG_TRX; + dm_fat_tbl->antsel_a[MacId] = TargetAnt & BIT(0); + dm_fat_tbl->antsel_b[MacId] = (TargetAnt & BIT(1)) >> 1; + dm_fat_tbl->antsel_c[MacId] = (TargetAnt & BIT(2)) >> 2; +} + +void ODM_SetTxAntByTxInfo_88E(struct odm_dm_struct *dm_odm, u8 *pDesc, u8 macId) +{ + struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable; + + if ((dm_odm->AntDivType == CG_TRX_HW_ANTDIV) || (dm_odm->AntDivType == CG_TRX_SMART_ANTDIV)) { + SET_TX_DESC_ANTSEL_A_88E(pDesc, dm_fat_tbl->antsel_a[macId]); + SET_TX_DESC_ANTSEL_B_88E(pDesc, dm_fat_tbl->antsel_b[macId]); + SET_TX_DESC_ANTSEL_C_88E(pDesc, dm_fat_tbl->antsel_c[macId]); + } +} + +void ODM_AntselStatistics_88E(struct odm_dm_struct *dm_odm, u8 antsel_tr_mux, u32 MacId, u8 RxPWDBAll) +{ + struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable; + if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) { + if (antsel_tr_mux == MAIN_ANT_CG_TRX) { + dm_fat_tbl->MainAnt_Sum[MacId] += RxPWDBAll; + dm_fat_tbl->MainAnt_Cnt[MacId]++; + } else { + dm_fat_tbl->AuxAnt_Sum[MacId] += RxPWDBAll; + dm_fat_tbl->AuxAnt_Cnt[MacId]++; + } + } else if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) { + if (antsel_tr_mux == MAIN_ANT_CGCS_RX) { + dm_fat_tbl->MainAnt_Sum[MacId] += RxPWDBAll; + dm_fat_tbl->MainAnt_Cnt[MacId]++; + } else { + dm_fat_tbl->AuxAnt_Sum[MacId] += RxPWDBAll; + dm_fat_tbl->AuxAnt_Cnt[MacId]++; + } + } +} + +static void odm_HWAntDiv(struct odm_dm_struct *dm_odm) +{ + u32 i, MinRSSI = 0xFF, AntDivMaxRSSI = 0, MaxRSSI = 0, LocalMinRSSI, LocalMaxRSSI; + u32 Main_RSSI, Aux_RSSI; + u8 RxIdleAnt = 0, TargetAnt = 7; + struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable; + struct rtw_dig *pDM_DigTable = &dm_odm->DM_DigTable; + struct sta_info *pEntry; + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + pEntry = dm_odm->pODM_StaInfo[i]; + if (IS_STA_VALID(pEntry)) { + /* 2 Caculate RSSI per Antenna */ + Main_RSSI = (dm_fat_tbl->MainAnt_Cnt[i] != 0) ? (dm_fat_tbl->MainAnt_Sum[i] / dm_fat_tbl->MainAnt_Cnt[i]) : 0; + Aux_RSSI = (dm_fat_tbl->AuxAnt_Cnt[i] != 0) ? (dm_fat_tbl->AuxAnt_Sum[i] / dm_fat_tbl->AuxAnt_Cnt[i]) : 0; + TargetAnt = (Main_RSSI >= Aux_RSSI) ? MAIN_ANT : AUX_ANT; + /* 2 Select MaxRSSI for DIG */ + LocalMaxRSSI = (Main_RSSI > Aux_RSSI) ? Main_RSSI : Aux_RSSI; + if ((LocalMaxRSSI > AntDivMaxRSSI) && (LocalMaxRSSI < 40)) + AntDivMaxRSSI = LocalMaxRSSI; + if (LocalMaxRSSI > MaxRSSI) + MaxRSSI = LocalMaxRSSI; + + /* 2 Select RX Idle Antenna */ + if ((dm_fat_tbl->RxIdleAnt == MAIN_ANT) && (Main_RSSI == 0)) + Main_RSSI = Aux_RSSI; + else if ((dm_fat_tbl->RxIdleAnt == AUX_ANT) && (Aux_RSSI == 0)) + Aux_RSSI = Main_RSSI; + + LocalMinRSSI = (Main_RSSI > Aux_RSSI) ? Aux_RSSI : Main_RSSI; + if (LocalMinRSSI < MinRSSI) { + MinRSSI = LocalMinRSSI; + RxIdleAnt = TargetAnt; + } + /* 2 Select TRX Antenna */ + if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) + odm_UpdateTxAnt_88E(dm_odm, TargetAnt, i); + } + dm_fat_tbl->MainAnt_Sum[i] = 0; + dm_fat_tbl->AuxAnt_Sum[i] = 0; + dm_fat_tbl->MainAnt_Cnt[i] = 0; + dm_fat_tbl->AuxAnt_Cnt[i] = 0; + } + + /* 2 Set RX Idle Antenna */ + ODM_UpdateRxIdleAnt_88E(dm_odm, RxIdleAnt); + + pDM_DigTable->AntDiv_RSSI_max = AntDivMaxRSSI; + pDM_DigTable->RSSI_max = MaxRSSI; +} + +void ODM_AntennaDiversity_88E(struct odm_dm_struct *dm_odm) +{ + struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable; + struct adapter *adapter = dm_odm->Adapter; + + if (!(dm_odm->SupportAbility & ODM_BB_ANT_DIV)) + return; + if (!dm_odm->bLinked) { + if (dm_fat_tbl->bBecomeLinked) { + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, BIT(7), 0); /* RegC50[7]=1'b1 enable HW AntDiv */ + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT(15), 0); /* Enable CCK AntDiv */ + if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT(21), 0); /* Reg80c[21]=1'b0 from TX Reg */ + dm_fat_tbl->bBecomeLinked = dm_odm->bLinked; + } + return; + } else { + if (!dm_fat_tbl->bBecomeLinked) { + /* Because HW AntDiv is disabled before Link, we enable HW AntDiv after link */ + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, BIT(7), 1); /* RegC50[7]=1'b1 enable HW AntDiv */ + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT(15), 1); /* Enable CCK AntDiv */ + if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) + rtl8188e_PHY_SetBBReg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT(21), 1); /* Reg80c[21]=1'b1 from TX Info */ + dm_fat_tbl->bBecomeLinked = dm_odm->bLinked; + } + } + if ((dm_odm->AntDivType == CG_TRX_HW_ANTDIV) || (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV)) + odm_HWAntDiv(dm_odm); +} diff --git a/drivers/staging/r8188eu/hal/rtl8188e_cmd.c b/drivers/staging/r8188eu/hal/rtl8188e_cmd.c new file mode 100644 index 000000000..8310d7f53 --- /dev/null +++ b/drivers/staging/r8188eu/hal/rtl8188e_cmd.c @@ -0,0 +1,694 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright(c) 2007 - 2011 Realtek Corporation. */ + +#define _RTL8188E_CMD_C_ + +#include "../include/osdep_service.h" +#include "../include/drv_types.h" +#include "../include/rtw_ioctl_set.h" + +#include "../include/rtl8188e_hal.h" + +#define RTL88E_MAX_H2C_BOX_NUMS 4 +#define RTL88E_MAX_CMD_LEN 7 +#define RTL88E_MESSAGE_BOX_SIZE 4 +#define RTL88E_EX_MESSAGE_BOX_SIZE 4 + +static u8 _is_fw_read_cmd_down(struct adapter *adapt, u8 msgbox_num) +{ + u8 read_down = false, reg; + int retry_cnts = 100; + int res; + + u8 valid; + + do { + res = rtw_read8(adapt, REG_HMETFR, ®); + if (res) + continue; + + valid = reg & BIT(msgbox_num); + if (0 == valid) + read_down = true; + } while ((!read_down) && (retry_cnts--)); + + return read_down; +} + +/***************************************** +* H2C Msg format : +* 0x1DF - 0x1D0 +*| 31 - 8 | 7-5 4 - 0 | +*| h2c_msg |Class_ID CMD_ID | +* +* Extend 0x1FF - 0x1F0 +*|31 - 0 | +*|ext_msg| +******************************************/ +static s32 FillH2CCmd_88E(struct adapter *adapt, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer) +{ + u8 bcmd_down = false; + s32 retry_cnts = 100; + u8 h2c_box_num; + u32 msgbox_addr; + u32 msgbox_ex_addr; + struct hal_data_8188e *haldata = &adapt->haldata; + u8 cmd_idx, ext_cmd_len; + u32 h2c_cmd = 0; + u32 h2c_cmd_ex = 0; + + if (!adapt->bFWReady) + return _FAIL; + + if (!pCmdBuffer || CmdLen > RTL88E_MAX_CMD_LEN || adapt->bSurpriseRemoved) + return _FAIL; + + /* pay attention to if race condition happened in H2C cmd setting. */ + do { + h2c_box_num = haldata->LastHMEBoxNum; + + if (!_is_fw_read_cmd_down(adapt, h2c_box_num)) + return _FAIL; + + *(u8 *)(&h2c_cmd) = ElementID; + + if (CmdLen <= 3) { + memcpy((u8 *)(&h2c_cmd) + 1, pCmdBuffer, CmdLen); + } else { + memcpy((u8 *)(&h2c_cmd) + 1, pCmdBuffer, 3); + ext_cmd_len = CmdLen - 3; + memcpy((u8 *)(&h2c_cmd_ex), pCmdBuffer + 3, ext_cmd_len); + + /* Write Ext command */ + msgbox_ex_addr = REG_HMEBOX_EXT_0 + (h2c_box_num * RTL88E_EX_MESSAGE_BOX_SIZE); + for (cmd_idx = 0; cmd_idx < ext_cmd_len; cmd_idx++) { + rtw_write8(adapt, msgbox_ex_addr + cmd_idx, *((u8 *)(&h2c_cmd_ex) + cmd_idx)); + } + } + /* Write command */ + msgbox_addr = REG_HMEBOX_0 + (h2c_box_num * RTL88E_MESSAGE_BOX_SIZE); + for (cmd_idx = 0; cmd_idx < RTL88E_MESSAGE_BOX_SIZE; cmd_idx++) { + rtw_write8(adapt, msgbox_addr + cmd_idx, *((u8 *)(&h2c_cmd) + cmd_idx)); + } + bcmd_down = true; + + haldata->LastHMEBoxNum = (h2c_box_num + 1) % RTL88E_MAX_H2C_BOX_NUMS; + + } while ((!bcmd_down) && (retry_cnts--)); + + return _SUCCESS; +} + +u8 rtl8188e_set_raid_cmd(struct adapter *adapt, u32 mask) +{ + u8 buf[3]; + u8 res = _SUCCESS; + struct hal_data_8188e *haldata = &adapt->haldata; + + if (haldata->fw_ractrl) { + __le32 lmask; + + memset(buf, 0, 3); + lmask = cpu_to_le32(mask); + memcpy(buf, &lmask, 3); + + FillH2CCmd_88E(adapt, H2C_DM_MACID_CFG, 3, buf); + } else { + res = _FAIL; + } + + return res; +} + +/* bitmap[0:27] = tx_rate_bitmap */ +/* bitmap[28:31]= Rate Adaptive id */ +/* arg[0:4] = macid */ +/* arg[5] = Short GI */ +void rtl8188e_Add_RateATid(struct adapter *pAdapter, u32 bitmap, u8 arg, u8 rssi_level) +{ + struct hal_data_8188e *haldata = &pAdapter->haldata; + + u8 macid, raid, short_gi_rate = false; + + macid = arg & 0x1f; + + raid = (bitmap >> 28) & 0x0f; + bitmap &= 0x0fffffff; + + if (rssi_level != DM_RATR_STA_INIT) + bitmap = ODM_Get_Rate_Bitmap(&haldata->odmpriv, macid, bitmap, rssi_level); + + bitmap |= ((raid << 28) & 0xf0000000); + + short_gi_rate = (arg & BIT(5)) ? true : false; + + raid = (bitmap >> 28) & 0x0f; + + bitmap &= 0x0fffffff; + + ODM_RA_UpdateRateInfo_8188E(&haldata->odmpriv, macid, raid, bitmap, short_gi_rate); +} + +void rtl8188e_set_FwPwrMode_cmd(struct adapter *adapt, u8 Mode) +{ + struct setpwrmode_parm H2CSetPwrMode; + struct pwrctrl_priv *pwrpriv = &adapt->pwrctrlpriv; + u8 RLBM = 0; /* 0:Min, 1:Max, 2:User define */ + + switch (Mode) { + case PS_MODE_ACTIVE: + H2CSetPwrMode.Mode = 0; + break; + case PS_MODE_MIN: + H2CSetPwrMode.Mode = 1; + break; + case PS_MODE_MAX: + RLBM = 1; + H2CSetPwrMode.Mode = 1; + break; + case PS_MODE_DTIM: + RLBM = 2; + H2CSetPwrMode.Mode = 1; + break; + case PS_MODE_UAPSD_WMM: + H2CSetPwrMode.Mode = 2; + break; + default: + H2CSetPwrMode.Mode = 0; + break; + } + + H2CSetPwrMode.SmartPS_RLBM = (((pwrpriv->smart_ps << 4) & 0xf0) | (RLBM & 0x0f)); + + H2CSetPwrMode.AwakeInterval = 1; + + H2CSetPwrMode.bAllQueueUAPSD = adapt->registrypriv.uapsd_enable; + + if (Mode > 0) + H2CSetPwrMode.PwrState = 0x00;/* AllON(0x0C), RFON(0x04), RFOFF(0x00) */ + else + H2CSetPwrMode.PwrState = 0x0C;/* AllON(0x0C), RFON(0x04), RFOFF(0x00) */ + + FillH2CCmd_88E(adapt, H2C_PS_PWR_MODE, sizeof(H2CSetPwrMode), (u8 *)&H2CSetPwrMode); + +} + +void rtl8188e_set_FwMediaStatus_cmd(struct adapter *adapt, __le16 mstatus_rpt) +{ + u16 mst_rpt = le16_to_cpu(mstatus_rpt); + + FillH2CCmd_88E(adapt, H2C_COM_MEDIA_STATUS_RPT, sizeof(mst_rpt), (u8 *)&mst_rpt); +} + +static void ConstructBeacon(struct adapter *adapt, u8 *pframe, u32 *pLength) +{ + struct ieee80211_hdr *pwlanhdr; + __le16 *fctrl; + u32 rate_len, pktlen; + struct mlme_ext_priv *pmlmeext = &adapt->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + struct wlan_bssid_ex *cur_network = &pmlmeinfo->network; + + pwlanhdr = (struct ieee80211_hdr *)pframe; + + fctrl = &pwlanhdr->frame_control; + *(fctrl) = 0; + + eth_broadcast_addr(pwlanhdr->addr1); + memcpy(pwlanhdr->addr2, myid(&adapt->eeprompriv), ETH_ALEN); + memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN); + + SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/); + SetFrameSubType(pframe, WIFI_BEACON); + + pframe += sizeof(struct ieee80211_hdr_3addr); + pktlen = sizeof(struct ieee80211_hdr_3addr); + + /* timestamp will be inserted by hardware */ + pframe += 8; + pktlen += 8; + + /* beacon interval: 2 bytes */ + memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2); + + pframe += 2; + pktlen += 2; + + /* capability info: 2 bytes */ + memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2); + + pframe += 2; + pktlen += 2; + + if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) { + pktlen += cur_network->IELength - sizeof(struct ndis_802_11_fixed_ie); + memcpy(pframe, cur_network->IEs + sizeof(struct ndis_802_11_fixed_ie), pktlen); + + goto _ConstructBeacon; + } + + /* below for ad-hoc mode */ + + /* SSID */ + pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pktlen); + + /* supported rates... */ + rate_len = rtw_get_rateset_len(cur_network->SupportedRates); + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &pktlen); + + /* DS parameter set */ + pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&cur_network->Configuration.DSConfig, &pktlen); + + if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) { + u32 ATIMWindow; + /* IBSS Parameter Set... */ + ATIMWindow = 0; + pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pktlen); + } + + /* todo: ERP IE */ + + /* EXTERNDED SUPPORTED RATE */ + if (rate_len > 8) + pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pktlen); + + /* todo:HT for adhoc */ + +_ConstructBeacon: + + if ((pktlen + TXDESC_SIZE) > 512) + return; + + *pLength = pktlen; +} + +static void ConstructPSPoll(struct adapter *adapt, u8 *pframe, u32 *pLength) +{ + struct ieee80211_hdr *pwlanhdr; + struct mlme_ext_priv *pmlmeext = &adapt->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + __le16 *fctrl; + + pwlanhdr = (struct ieee80211_hdr *)pframe; + + /* Frame control. */ + fctrl = &pwlanhdr->frame_control; + *(fctrl) = 0; + SetPwrMgt(fctrl); + SetFrameSubType(pframe, WIFI_PSPOLL); + + /* AID. */ + SetDuration(pframe, (pmlmeinfo->aid | 0xc000)); + + /* BSSID. */ + memcpy(pwlanhdr->addr1, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); + + /* TA. */ + memcpy(pwlanhdr->addr2, myid(&adapt->eeprompriv), ETH_ALEN); + + *pLength = 16; +} + +static void ConstructNullFunctionData(struct adapter *adapt, u8 *pframe, + u32 *pLength, + u8 *StaAddr, + u8 bQoS, + u8 AC, + u8 bEosp, + u8 bForcePowerSave) +{ + struct ieee80211_hdr *pwlanhdr; + __le16 *fctrl; + u32 pktlen; + struct mlme_priv *pmlmepriv = &adapt->mlmepriv; + struct wlan_network *cur_network = &pmlmepriv->cur_network; + struct mlme_ext_priv *pmlmeext = &adapt->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + + pwlanhdr = (struct ieee80211_hdr *)pframe; + + fctrl = &pwlanhdr->frame_control; + *(fctrl) = 0; + if (bForcePowerSave) + SetPwrMgt(fctrl); + + switch (cur_network->network.InfrastructureMode) { + case Ndis802_11Infrastructure: + SetToDs(fctrl); + memcpy(pwlanhdr->addr1, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); + memcpy(pwlanhdr->addr2, myid(&adapt->eeprompriv), ETH_ALEN); + memcpy(pwlanhdr->addr3, StaAddr, ETH_ALEN); + break; + case Ndis802_11APMode: + SetFrDs(fctrl); + memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); + memcpy(pwlanhdr->addr2, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); + memcpy(pwlanhdr->addr3, myid(&adapt->eeprompriv), ETH_ALEN); + break; + case Ndis802_11IBSS: + default: + memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); + memcpy(pwlanhdr->addr2, myid(&adapt->eeprompriv), ETH_ALEN); + memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); + break; + } + + SetSeqNum(pwlanhdr, 0); + + if (bQoS) { + struct ieee80211_qos_hdr *pwlanqoshdr; + + SetFrameSubType(pframe, WIFI_QOS_DATA_NULL); + + pwlanqoshdr = (struct ieee80211_qos_hdr *)pframe; + SetPriority(&pwlanqoshdr->qos_ctrl, AC); + SetEOSP(&pwlanqoshdr->qos_ctrl, bEosp); + + pktlen = sizeof(struct ieee80211_qos_hdr); + } else { + SetFrameSubType(pframe, WIFI_DATA_NULL); + + pktlen = sizeof(struct ieee80211_qos_hdr); + } + + *pLength = pktlen; +} + +static void ConstructProbeRsp(struct adapter *adapt, u8 *pframe, u32 *pLength, u8 *StaAddr, bool bHideSSID) +{ + struct ieee80211_hdr *pwlanhdr; + __le16 *fctrl; + u8 *mac, *bssid; + u32 pktlen; + struct mlme_ext_priv *pmlmeext = &adapt->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + struct wlan_bssid_ex *cur_network = &pmlmeinfo->network; + + pwlanhdr = (struct ieee80211_hdr *)pframe; + + mac = myid(&adapt->eeprompriv); + bssid = cur_network->MacAddress; + + fctrl = &pwlanhdr->frame_control; + *(fctrl) = 0; + memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); + memcpy(pwlanhdr->addr2, mac, ETH_ALEN); + memcpy(pwlanhdr->addr3, bssid, ETH_ALEN); + + SetSeqNum(pwlanhdr, 0); + SetFrameSubType(fctrl, WIFI_PROBERSP); + + pktlen = sizeof(struct ieee80211_hdr_3addr); + pframe += pktlen; + + if (cur_network->IELength > MAX_IE_SZ) + return; + + memcpy(pframe, cur_network->IEs, cur_network->IELength); + pframe += cur_network->IELength; + pktlen += cur_network->IELength; + + *pLength = pktlen; +} + +/* To check if reserved page content is destroyed by beacon because beacon is too large. */ +/* 2010.06.23. Added by tynli. */ +void CheckFwRsvdPageContent(struct adapter *Adapter) +{ +} + +/* */ +/* Description: Fill the reserved packets that FW will use to RSVD page. */ +/* Now we just send 4 types packet to rsvd page. */ +/* (1)Beacon, (2)Ps-poll, (3)Null data, (4)ProbeRsp. */ +/* Input: */ +/* bDLFinished - false: At the first time we will send all the packets as a large packet to Hw, */ +/* so we need to set the packet length to total length. */ +/* true: At the second time, we should send the first packet (default:beacon) */ +/* to Hw again and set the length in descriptor to the real beacon length. */ +/* 2009.10.15 by tynli. */ +static void SetFwRsvdPagePkt(struct adapter *adapt, bool bDLFinished) +{ + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct xmit_priv *pxmitpriv; + struct mlme_ext_priv *pmlmeext; + struct mlme_ext_info *pmlmeinfo; + u32 BeaconLength = 0, ProbeRspLength = 0, PSPollLength; + u32 NullDataLength, QosNullLength; + u8 *ReservedPagePacket; + u8 PageNum, PageNeed, TxDescLen; + u16 BufIndex; + u32 TotalPacketLen; + struct rsvdpage_loc RsvdPageLoc; + + ReservedPagePacket = kzalloc(1000, GFP_KERNEL); + if (!ReservedPagePacket) + return; + + pxmitpriv = &adapt->xmitpriv; + pmlmeext = &adapt->mlmeextpriv; + pmlmeinfo = &pmlmeext->mlmext_info; + + TxDescLen = TXDESC_SIZE; + PageNum = 0; + + /* 3 (1) beacon * 2 pages */ + BufIndex = TXDESC_OFFSET; + ConstructBeacon(adapt, &ReservedPagePacket[BufIndex], &BeaconLength); + + /* When we count the first page size, we need to reserve description size for the RSVD */ + /* packet, it will be filled in front of the packet in TXPKTBUF. */ + PageNeed = (u8)PageNum_128(TxDescLen + BeaconLength); + /* To reserved 2 pages for beacon buffer. 2010.06.24. */ + if (PageNeed == 1) + PageNeed += 1; + PageNum += PageNeed; + + BufIndex += PageNeed * 128; + + /* 3 (2) ps-poll *1 page */ + RsvdPageLoc.LocPsPoll = PageNum; + ConstructPSPoll(adapt, &ReservedPagePacket[BufIndex], &PSPollLength); + rtl8188e_fill_fake_txdesc(adapt, &ReservedPagePacket[BufIndex - TxDescLen], PSPollLength, true, false); + + PageNeed = (u8)PageNum_128(TxDescLen + PSPollLength); + PageNum += PageNeed; + + BufIndex += PageNeed * 128; + + /* 3 (3) null data * 1 page */ + RsvdPageLoc.LocNullData = PageNum; + ConstructNullFunctionData(adapt, &ReservedPagePacket[BufIndex], &NullDataLength, get_my_bssid(&pmlmeinfo->network), false, 0, 0, false); + rtl8188e_fill_fake_txdesc(adapt, &ReservedPagePacket[BufIndex - TxDescLen], NullDataLength, false, false); + + PageNeed = (u8)PageNum_128(TxDescLen + NullDataLength); + PageNum += PageNeed; + + BufIndex += PageNeed * 128; + + /* 3 (4) probe response * 1page */ + RsvdPageLoc.LocProbeRsp = PageNum; + ConstructProbeRsp(adapt, &ReservedPagePacket[BufIndex], &ProbeRspLength, get_my_bssid(&pmlmeinfo->network), false); + rtl8188e_fill_fake_txdesc(adapt, &ReservedPagePacket[BufIndex - TxDescLen], ProbeRspLength, false, false); + + PageNeed = (u8)PageNum_128(TxDescLen + ProbeRspLength); + PageNum += PageNeed; + + BufIndex += PageNeed * 128; + + /* 3 (5) Qos null data */ + RsvdPageLoc.LocQosNull = PageNum; + ConstructNullFunctionData(adapt, &ReservedPagePacket[BufIndex], + &QosNullLength, get_my_bssid(&pmlmeinfo->network), true, 0, 0, false); + rtl8188e_fill_fake_txdesc(adapt, &ReservedPagePacket[BufIndex - TxDescLen], QosNullLength, false, false); + + PageNeed = (u8)PageNum_128(TxDescLen + QosNullLength); + PageNum += PageNeed; + + TotalPacketLen = BufIndex + QosNullLength; + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (!pmgntframe) + goto exit; + + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(adapt, pattrib); + pattrib->qsel = 0x10; + pattrib->last_txcmdsz = TotalPacketLen - TXDESC_OFFSET; + pattrib->pktlen = pattrib->last_txcmdsz; + memcpy(pmgntframe->buf_addr, ReservedPagePacket, TotalPacketLen); + + rtl8188eu_mgnt_xmit(adapt, pmgntframe); + + FillH2CCmd_88E(adapt, H2C_COM_RSVD_PAGE, sizeof(RsvdPageLoc), (u8 *)&RsvdPageLoc); + +exit: + kfree(ReservedPagePacket); +} + +void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *adapt, u8 mstatus) +{ + struct hal_data_8188e *haldata = &adapt->haldata; + struct mlme_ext_priv *pmlmeext = &adapt->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + bool bSendBeacon = false; + bool bcn_valid = false; + u8 DLBcnCount = 0; + u32 poll = 0; + u8 reg; + int res; + + if (mstatus == 1) { + /* We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 88/92C. */ + /* Suggested by filen. Added by tynli. */ + rtw_write16(adapt, REG_BCN_PSR_RPT, (0xC000 | pmlmeinfo->aid)); + /* Do not set TSF again here or vWiFi beacon DMA INT will not work. */ + + /* Set REG_CR bit 8. DMA beacon by SW. */ + haldata->RegCR_1 |= BIT(0); + rtw_write8(adapt, REG_CR + 1, haldata->RegCR_1); + + /* Disable Hw protection for a time which revserd for Hw sending beacon. */ + /* Fix download reserved page packet fail that access collision with the protection time. */ + /* 2010.05.11. Added by tynli. */ + res = rtw_read8(adapt, REG_BCN_CTRL, ®); + if (res) + return; + + rtw_write8(adapt, REG_BCN_CTRL, reg & (~BIT(3))); + + res = rtw_read8(adapt, REG_BCN_CTRL, ®); + if (res) + return; + + rtw_write8(adapt, REG_BCN_CTRL, reg | BIT(4)); + + if (haldata->RegFwHwTxQCtrl & BIT(6)) + bSendBeacon = true; + + /* Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame. */ + rtw_write8(adapt, REG_FWHW_TXQ_CTRL + 2, (haldata->RegFwHwTxQCtrl & (~BIT(6)))); + haldata->RegFwHwTxQCtrl &= (~BIT(6)); + + clear_beacon_valid_bit(adapt); + DLBcnCount = 0; + poll = 0; + do { + /* download rsvd page. */ + SetFwRsvdPagePkt(adapt, false); + DLBcnCount++; + do { + yield(); + /* mdelay(10); */ + /* check rsvd page download OK. */ + bcn_valid = get_beacon_valid_bit(adapt); + poll++; + } while (!bcn_valid && (poll % 10) != 0 && !adapt->bSurpriseRemoved && !adapt->bDriverStopped); + } while (!bcn_valid && DLBcnCount <= 100 && !adapt->bSurpriseRemoved && !adapt->bDriverStopped); + + /* */ + /* We just can send the reserved page twice during the time that Tx thread is stopped (e.g. pnpsetpower) */ + /* because we need to free the Tx BCN Desc which is used by the first reserved page packet. */ + /* At run time, we cannot get the Tx Desc until it is released in TxHandleInterrupt() so we will return */ + /* the beacon TCB in the following code. 2011.11.23. by tynli. */ + /* */ + + /* Enable Bcn */ + res = rtw_read8(adapt, REG_BCN_CTRL, ®); + if (res) + return; + + rtw_write8(adapt, REG_BCN_CTRL, reg | BIT(3)); + + res = rtw_read8(adapt, REG_BCN_CTRL, ®); + if (res) + return; + + rtw_write8(adapt, REG_BCN_CTRL, reg & (~BIT(4))); + + /* To make sure that if there exists an adapter which would like to send beacon. */ + /* If exists, the origianl value of 0x422[6] will be 1, we should check this to */ + /* prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */ + /* the beacon cannot be sent by HW. */ + /* 2010.06.23. Added by tynli. */ + if (bSendBeacon) { + rtw_write8(adapt, REG_FWHW_TXQ_CTRL + 2, (haldata->RegFwHwTxQCtrl | BIT(6))); + haldata->RegFwHwTxQCtrl |= BIT(6); + } + + /* Update RSVD page location H2C to Fw. */ + if (bcn_valid) + clear_beacon_valid_bit(adapt); + + /* Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli. */ + /* Clear CR[8] or beacon packet will not be send to TxBuf anymore. */ + haldata->RegCR_1 &= (~BIT(0)); + rtw_write8(adapt, REG_CR + 1, haldata->RegCR_1); + } + +} + +void rtl8188e_set_p2p_ps_offload_cmd(struct adapter *adapt, u8 p2p_ps_state) +{ + struct hal_data_8188e *haldata = &adapt->haldata; + struct wifidirect_info *pwdinfo = &adapt->wdinfo; + struct P2P_PS_Offload_t *p2p_ps_offload = &haldata->p2p_ps_offload; + u8 i; + + switch (p2p_ps_state) { + case P2P_PS_DISABLE: + memset(p2p_ps_offload, 0, 1); + break; + case P2P_PS_ENABLE: + /* update CTWindow value. */ + if (pwdinfo->ctwindow > 0) { + p2p_ps_offload->CTWindow_En = 1; + rtw_write8(adapt, REG_P2P_CTWIN, pwdinfo->ctwindow); + } + + /* hw only support 2 set of NoA */ + for (i = 0; i < pwdinfo->noa_num; i++) { + /* To control the register setting for which NOA */ + rtw_write8(adapt, REG_NOA_DESC_SEL, (i << 4)); + if (i == 0) + p2p_ps_offload->NoA0_En = 1; + else + p2p_ps_offload->NoA1_En = 1; + + /* config P2P NoA Descriptor Register */ + rtw_write32(adapt, REG_NOA_DESC_DURATION, pwdinfo->noa_duration[i]); + rtw_write32(adapt, REG_NOA_DESC_INTERVAL, pwdinfo->noa_interval[i]); + rtw_write32(adapt, REG_NOA_DESC_START, pwdinfo->noa_start_time[i]); + rtw_write8(adapt, REG_NOA_DESC_COUNT, pwdinfo->noa_count[i]); + } + + if ((pwdinfo->opp_ps == 1) || (pwdinfo->noa_num > 0)) { + /* rst p2p circuit */ + rtw_write8(adapt, REG_DUAL_TSF_RST, BIT(4)); + + p2p_ps_offload->Offload_En = 1; + + if (pwdinfo->role == P2P_ROLE_GO) { + p2p_ps_offload->role = 1; + p2p_ps_offload->AllStaSleep = 0; + } else { + p2p_ps_offload->role = 0; + } + + p2p_ps_offload->discovery = 0; + } + break; + case P2P_PS_SCAN: + p2p_ps_offload->discovery = 1; + break; + case P2P_PS_SCAN_DONE: + p2p_ps_offload->discovery = 0; + pwdinfo->p2p_ps_state = P2P_PS_ENABLE; + break; + default: + break; + } + + FillH2CCmd_88E(adapt, H2C_PS_P2P_OFFLOAD, 1, (u8 *)p2p_ps_offload); +} diff --git a/drivers/staging/r8188eu/hal/rtl8188e_dm.c b/drivers/staging/r8188eu/hal/rtl8188e_dm.c new file mode 100644 index 000000000..0399872c4 --- /dev/null +++ b/drivers/staging/r8188eu/hal/rtl8188e_dm.c @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright(c) 2007 - 2011 Realtek Corporation. */ + +/* This file is for 92CE/92CU dynamic mechanism only */ +#define _RTL8188E_DM_C_ + +#include "../include/osdep_service.h" +#include "../include/drv_types.h" +#include "../include/rtl8188e_hal.h" + +/* Initialize GPIO setting registers */ +static void dm_InitGPIOSetting(struct adapter *Adapter) +{ + u8 tmp1byte; + int res; + + res = rtw_read8(Adapter, REG_GPIO_MUXCFG, &tmp1byte); + if (res) + return; + + tmp1byte &= (GPIOSEL_GPIO | ~GPIOSEL_ENBT); + + rtw_write8(Adapter, REG_GPIO_MUXCFG, tmp1byte); +} + +/* */ +/* functions */ +/* */ +static void Update_ODM_ComInfo_88E(struct adapter *Adapter) +{ + struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; + struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; + struct pwrctrl_priv *pwrctrlpriv = &Adapter->pwrctrlpriv; + struct hal_data_8188e *hal_data = &Adapter->haldata; + struct odm_dm_struct *dm_odm = &hal_data->odmpriv; + struct dm_priv *pdmpriv = &hal_data->dmpriv; + int i; + + pdmpriv->InitODMFlag = ODM_BB_RSSI_MONITOR; + if (hal_data->AntDivCfg) + pdmpriv->InitODMFlag |= ODM_BB_ANT_DIV; + + dm_odm->SupportAbility = pdmpriv->InitODMFlag; + + dm_odm->pWirelessMode = &pmlmeext->cur_wireless_mode; + dm_odm->pSecChOffset = &hal_data->nCur40MhzPrimeSC; + dm_odm->pBandWidth = &hal_data->CurrentChannelBW; + dm_odm->pChannel = &hal_data->CurrentChannel; + dm_odm->pbScanInProcess = &pmlmepriv->bScanInProcess; + dm_odm->pbPowerSaving = &pwrctrlpriv->bpower_saving; + + ODM_CmnInfoInit(dm_odm, ODM_CMNINFO_RF_ANTENNA_TYPE, hal_data->TRxAntDivType); + + for (i = 0; i < NUM_STA; i++) + dm_odm->pODM_StaInfo[i] = NULL; +} + +void rtl8188e_InitHalDm(struct adapter *Adapter) +{ + struct hal_data_8188e *hal_data = &Adapter->haldata; + struct odm_dm_struct *dm_odm = &hal_data->odmpriv; + + dm_InitGPIOSetting(Adapter); + Update_ODM_ComInfo_88E(Adapter); + ODM_DMInit(dm_odm); +} + +void rtl8188e_HalDmWatchDog(struct adapter *Adapter) +{ + u8 hw_init_completed = Adapter->hw_init_completed; + struct hal_data_8188e *hal_data = &Adapter->haldata; + struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; + u8 bLinked = false; + + if (!hw_init_completed) + return; + + if ((check_fwstate(pmlmepriv, WIFI_AP_STATE)) || + (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE))) { + if (Adapter->stapriv.asoc_sta_count > 2) + bLinked = true; + } else {/* Station mode */ + if (check_fwstate(pmlmepriv, _FW_LINKED)) + bLinked = true; + } + + hal_data->odmpriv.bLinked = bLinked; + ODM_DMWatchdog(&hal_data->odmpriv); +} + +void rtl8188e_init_dm_priv(struct adapter *Adapter) +{ + struct hal_data_8188e *hal_data = &Adapter->haldata; + struct dm_priv *pdmpriv = &hal_data->dmpriv; + struct odm_dm_struct *dm_odm = &hal_data->odmpriv; + + memset(pdmpriv, 0, sizeof(struct dm_priv)); + memset(dm_odm, 0, sizeof(*dm_odm)); + + dm_odm->Adapter = Adapter; + ODM_CmnInfoInit(dm_odm, ODM_CMNINFO_MP_TEST_CHIP, IS_NORMAL_CHIP(hal_data->VersionID)); + ODM_CmnInfoInit(dm_odm, ODM_CMNINFO_RF_ANTENNA_TYPE, hal_data->TRxAntDivType); +} + +/* Add new function to reset the state of antenna diversity before link. */ +/* Compare RSSI for deciding antenna */ +void AntDivCompare8188E(struct adapter *Adapter, struct wlan_bssid_ex *dst, struct wlan_bssid_ex *src) +{ + struct hal_data_8188e *hal_data = &Adapter->haldata; + + if (0 != hal_data->AntDivCfg) { + /* select optimum_antenna for before linked =>For antenna diversity */ + if (dst->Rssi >= src->Rssi) {/* keep org parameter */ + src->Rssi = dst->Rssi; + src->PhyInfo.Optimum_antenna = dst->PhyInfo.Optimum_antenna; + } + } +} + +/* Add new function to reset the state of antenna diversity before link. */ +u8 AntDivBeforeLink8188E(struct adapter *Adapter) +{ + struct hal_data_8188e *hal_data = &Adapter->haldata; + struct odm_dm_struct *dm_odm = &hal_data->odmpriv; + struct sw_ant_switch *dm_swat_tbl = &dm_odm->DM_SWAT_Table; + struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; + + /* Condition that does not need to use antenna diversity. */ + if (hal_data->AntDivCfg == 0) + return false; + + if (check_fwstate(pmlmepriv, _FW_LINKED)) + return false; + + if (dm_swat_tbl->SWAS_NoLink_State == 0) { + /* switch channel */ + dm_swat_tbl->SWAS_NoLink_State = 1; + dm_swat_tbl->CurAntenna = (dm_swat_tbl->CurAntenna == Antenna_A) ? Antenna_B : Antenna_A; + + rtw_antenna_select_cmd(Adapter, dm_swat_tbl->CurAntenna, false); + return true; + } else { + dm_swat_tbl->SWAS_NoLink_State = 0; + return false; + } +} diff --git a/drivers/staging/r8188eu/hal/rtl8188e_hal_init.c b/drivers/staging/r8188eu/hal/rtl8188e_hal_init.c new file mode 100644 index 000000000..158260547 --- /dev/null +++ b/drivers/staging/r8188eu/hal/rtl8188e_hal_init.c @@ -0,0 +1,926 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright(c) 2007 - 2011 Realtek Corporation. */ + +#define _HAL_INIT_C_ + +#include "../include/drv_types.h" +#include "../include/rtw_efuse.h" +#include "../include/rtl8188e_hal.h" +#include "../include/rtw_iol.h" +#include "../include/usb_ops.h" +#include "../include/rtw_fw.h" + +static void iol_mode_enable(struct adapter *padapter, u8 enable) +{ + u8 reg_0xf0 = 0; + int res; + + if (enable) { + /* Enable initial offload */ + res = rtw_read8(padapter, REG_SYS_CFG, ®_0xf0); + if (res) + return; + + rtw_write8(padapter, REG_SYS_CFG, reg_0xf0 | SW_OFFLOAD_EN); + + if (!padapter->bFWReady) + rtw_reset_8051(padapter); + + } else { + /* disable initial offload */ + res = rtw_read8(padapter, REG_SYS_CFG, ®_0xf0); + if (res) + return; + + rtw_write8(padapter, REG_SYS_CFG, reg_0xf0 & ~SW_OFFLOAD_EN); + } +} + +static s32 iol_execute(struct adapter *padapter, u8 control) +{ + s32 status = _FAIL; + u8 reg_0x88 = 0; + unsigned long timeout; + int res; + + control = control & 0x0f; + res = rtw_read8(padapter, REG_HMEBOX_E0, ®_0x88); + if (res) + return _FAIL; + + rtw_write8(padapter, REG_HMEBOX_E0, reg_0x88 | control); + + timeout = jiffies + msecs_to_jiffies(1000); + + do { + res = rtw_read8(padapter, REG_HMEBOX_E0, ®_0x88); + if (res) + continue; + + if (!(reg_0x88 & control)) + break; + + } while (time_before(jiffies, timeout)); + + res = rtw_read8(padapter, REG_HMEBOX_E0, ®_0x88); + if (res) + return _FAIL; + + status = (reg_0x88 & control) ? _FAIL : _SUCCESS; + if (reg_0x88 & control << 4) + status = _FAIL; + return status; +} + +static s32 iol_InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy) +{ + s32 rst = _SUCCESS; + iol_mode_enable(padapter, 1); + rtw_write8(padapter, REG_TDECTRL + 1, txpktbuf_bndy); + rst = iol_execute(padapter, CMD_INIT_LLT); + iol_mode_enable(padapter, 0); + return rst; +} + +static void +efuse_phymap_to_logical(u8 *phymap, u16 _size_byte, u8 *pbuf) +{ + u8 *efuseTbl = NULL; + u8 rtemp8; + u16 eFuse_Addr = 0; + u8 offset, wren; + u16 i, j; + u16 **eFuseWord = NULL; + u8 u1temp = 0; + + efuseTbl = kzalloc(EFUSE_MAP_LEN_88E, GFP_KERNEL); + if (!efuseTbl) + goto exit; + + eFuseWord = rtw_malloc2d(EFUSE_MAX_SECTION_88E, EFUSE_MAX_WORD_UNIT, sizeof(u16)); + if (!eFuseWord) + goto exit; + + /* 0. Refresh efuse init map as all oxFF. */ + for (i = 0; i < EFUSE_MAX_SECTION_88E; i++) + for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++) + eFuseWord[i][j] = 0xFFFF; + + /* */ + /* 1. Read the first byte to check if efuse is empty!!! */ + /* */ + /* */ + rtemp8 = *(phymap + eFuse_Addr); + if (rtemp8 != 0xFF) { + eFuse_Addr++; + } else { + goto exit; + } + + /* */ + /* 2. Read real efuse content. Filter PG header and every section data. */ + /* */ + while ((rtemp8 != 0xFF) && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E)) { + /* Check PG header for section num. */ + if ((rtemp8 & 0x1F) == 0x0F) { /* extended header */ + u1temp = ((rtemp8 & 0xE0) >> 5); + rtemp8 = *(phymap + eFuse_Addr); + if ((rtemp8 & 0x0F) == 0x0F) { + eFuse_Addr++; + rtemp8 = *(phymap + eFuse_Addr); + + if (rtemp8 != 0xFF && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E)) + eFuse_Addr++; + continue; + } else { + offset = ((rtemp8 & 0xF0) >> 1) | u1temp; + wren = (rtemp8 & 0x0F); + eFuse_Addr++; + } + } else { + offset = ((rtemp8 >> 4) & 0x0f); + wren = (rtemp8 & 0x0f); + } + + if (offset < EFUSE_MAX_SECTION_88E) { + /* Get word enable value from PG header */ + for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) { + /* Check word enable condition in the section */ + if (!(wren & 0x01)) { + rtemp8 = *(phymap + eFuse_Addr); + eFuse_Addr++; + eFuseWord[offset][i] = (rtemp8 & 0xff); + if (eFuse_Addr >= EFUSE_REAL_CONTENT_LEN_88E) + break; + rtemp8 = *(phymap + eFuse_Addr); + eFuse_Addr++; + eFuseWord[offset][i] |= (((u16)rtemp8 << 8) & 0xff00); + + if (eFuse_Addr >= EFUSE_REAL_CONTENT_LEN_88E) + break; + } + wren >>= 1; + } + } + /* Read next PG header */ + rtemp8 = *(phymap + eFuse_Addr); + + if (rtemp8 != 0xFF && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E)) { + eFuse_Addr++; + } + } + + /* */ + /* 3. Collect 16 sections and 4 word unit into Efuse map. */ + /* */ + for (i = 0; i < EFUSE_MAX_SECTION_88E; i++) { + for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++) { + efuseTbl[(i * 8) + (j * 2)] = (eFuseWord[i][j] & 0xff); + efuseTbl[(i * 8) + ((j * 2) + 1)] = ((eFuseWord[i][j] >> 8) & 0xff); + } + } + + /* */ + /* 4. Copy from Efuse map to output pointer memory!!! */ + /* */ + memcpy(pbuf, efuseTbl, _size_byte); + +exit: + kfree(efuseTbl); + kfree(eFuseWord); +} + +/* FIXME: add error handling in callers */ +static int efuse_read_phymap_from_txpktbuf( + struct adapter *adapter, + u8 *content, /* buffer to store efuse physical map */ + u16 *size /* for efuse content: the max byte to read. will update to byte read */ + ) +{ + unsigned long timeout; + __le32 lo32 = 0, hi32 = 0; + u16 len = 0, count = 0; + int i = 0, res; + u16 limit = *size; + u8 reg; + u8 *pos = content; + u32 reg32; + + rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, TXPKT_BUF_SELECT); + + while (1) { + rtw_write16(adapter, REG_PKTBUF_DBG_ADDR, i); + + rtw_write8(adapter, REG_TXPKTBUF_DBG, 0); + timeout = jiffies + msecs_to_jiffies(1000); + do { + res = rtw_read8(adapter, REG_TXPKTBUF_DBG, ®); + if (res) + continue; + + if (reg) + break; + + msleep(1); + } while (time_before(jiffies, timeout)); + + /* data from EEPROM needs to be in LE */ + res = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_L, ®32); + if (res) + return res; + + lo32 = cpu_to_le32(reg32); + + res = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H, ®32); + if (res) + return res; + + hi32 = cpu_to_le32(reg32); + + if (i == 0) { + u16 reg; + + /* Although lenc is only used in a debug statement, + * do not remove it as the rtw_read16() call consumes + * 2 bytes from the EEPROM source. + */ + res = rtw_read16(adapter, REG_PKTBUF_DBG_DATA_L, ®); + if (res) + return res; + + len = le32_to_cpu(lo32) & 0x0000ffff; + + limit = (len - 2 < limit) ? len - 2 : limit; + + memcpy(pos, ((u8 *)&lo32) + 2, (limit >= count + 2) ? 2 : limit - count); + count += (limit >= count + 2) ? 2 : limit - count; + pos = content + count; + } else { + memcpy(pos, ((u8 *)&lo32), (limit >= count + 4) ? 4 : limit - count); + count += (limit >= count + 4) ? 4 : limit - count; + pos = content + count; + } + + if (limit > count && len - 2 > count) { + memcpy(pos, (u8 *)&hi32, (limit >= count + 4) ? 4 : limit - count); + count += (limit >= count + 4) ? 4 : limit - count; + pos = content + count; + } + + if (limit <= count || len - 2 <= count) + break; + i++; + } + rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, DISABLE_TRXPKT_BUF_ACCESS); + *size = count; + + return 0; +} + +static s32 iol_read_efuse(struct adapter *padapter, u16 size_byte, u8 *logical_map) +{ + s32 status = _FAIL; + u8 physical_map[512]; + u16 size = 512; + + rtw_write8(padapter, REG_TDECTRL + 1, 0); + memset(physical_map, 0xFF, 512); + rtw_write8(padapter, REG_PKT_BUFF_ACCESS_CTRL, TXPKT_BUF_SELECT); + status = iol_execute(padapter, CMD_READ_EFUSE_MAP); + if (status == _SUCCESS) + efuse_read_phymap_from_txpktbuf(padapter, physical_map, &size); + efuse_phymap_to_logical(physical_map, size_byte, logical_map); + return status; +} + +s32 rtl8188e_iol_efuse_patch(struct adapter *padapter) +{ + s32 result = _SUCCESS; + + if (rtw_IOL_applied(padapter)) { + iol_mode_enable(padapter, 1); + result = iol_execute(padapter, CMD_READ_EFUSE_MAP); + if (result == _SUCCESS) + result = iol_execute(padapter, CMD_EFUSE_PATCH); + + iol_mode_enable(padapter, 0); + } + return result; +} + +static s32 iol_ioconfig(struct adapter *padapter, u8 iocfg_bndy) +{ + s32 rst = _SUCCESS; + + rtw_write8(padapter, REG_TDECTRL + 1, iocfg_bndy); + rst = iol_execute(padapter, CMD_IOCONFIG); + return rst; +} + +int rtl8188e_IOL_exec_cmds_sync(struct adapter *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt) +{ + struct pkt_attrib *pattrib = &xmit_frame->attrib; + u8 i; + int ret = _FAIL; + + if (rtw_IOL_append_END_cmd(xmit_frame) != _SUCCESS) + goto exit; + if (rtw_usb_bulk_size_boundary(adapter, TXDESC_SIZE + pattrib->last_txcmdsz)) { + if (rtw_IOL_append_END_cmd(xmit_frame) != _SUCCESS) + goto exit; + } + + dump_mgntframe_and_wait(adapter, xmit_frame, max_wating_ms); + + iol_mode_enable(adapter, 1); + for (i = 0; i < bndy_cnt; i++) { + u8 page_no = 0; + page_no = i * 2; + ret = iol_ioconfig(adapter, page_no); + if (ret != _SUCCESS) + break; + } + iol_mode_enable(adapter, 0); +exit: + /* restore BCN_HEAD */ + rtw_write8(adapter, REG_TDECTRL + 1, 0); + return ret; +} + +void rtl8188e_EfusePowerSwitch(struct adapter *pAdapter, u8 PwrState) +{ + u16 tmpV16; + int res; + + if (PwrState) { + rtw_write8(pAdapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON); + + /* 1.2V Power: From VDDON with Power Cut(0x0000h[15]), defualt valid */ + res = rtw_read16(pAdapter, REG_SYS_ISO_CTRL, &tmpV16); + if (res) + return; + + if (!(tmpV16 & PWC_EV12V)) { + tmpV16 |= PWC_EV12V; + rtw_write16(pAdapter, REG_SYS_ISO_CTRL, tmpV16); + } + /* Reset: 0x0000h[28], default valid */ + res = rtw_read16(pAdapter, REG_SYS_FUNC_EN, &tmpV16); + if (res) + return; + + if (!(tmpV16 & FEN_ELDR)) { + tmpV16 |= FEN_ELDR; + rtw_write16(pAdapter, REG_SYS_FUNC_EN, tmpV16); + } + + /* Clock: Gated(0x0008h[5]) 8M(0x0008h[1]) clock from ANA, default valid */ + res = rtw_read16(pAdapter, REG_SYS_CLKR, &tmpV16); + if (res) + return; + + if ((!(tmpV16 & LOADER_CLK_EN)) || (!(tmpV16 & ANA8M))) { + tmpV16 |= (LOADER_CLK_EN | ANA8M); + rtw_write16(pAdapter, REG_SYS_CLKR, tmpV16); + } + } else { + rtw_write8(pAdapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF); + } +} + +static void Hal_EfuseReadEFuse88E(struct adapter *Adapter, + u16 _offset, + u16 _size_byte, + u8 *pbuf) +{ + u8 *efuseTbl = NULL; + u8 rtemp8[1]; + u16 eFuse_Addr = 0; + u8 offset, wren; + u16 i, j; + u16 **eFuseWord = NULL; + u16 efuse_utilized = 0; + u8 u1temp = 0; + + /* */ + /* Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10. */ + /* */ + if ((_offset + _size_byte) > EFUSE_MAP_LEN_88E) /* total E-Fuse table is 512bytes */ + goto exit; + + efuseTbl = kzalloc(EFUSE_MAP_LEN_88E, GFP_KERNEL); + if (!efuseTbl) + goto exit; + + eFuseWord = rtw_malloc2d(EFUSE_MAX_SECTION_88E, EFUSE_MAX_WORD_UNIT, sizeof(u16)); + if (!eFuseWord) + goto exit; + + /* 0. Refresh efuse init map as all oxFF. */ + for (i = 0; i < EFUSE_MAX_SECTION_88E; i++) + for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++) + eFuseWord[i][j] = 0xFFFF; + + /* */ + /* 1. Read the first byte to check if efuse is empty!!! */ + /* */ + /* */ + ReadEFuseByte(Adapter, eFuse_Addr, rtemp8); + if (*rtemp8 != 0xFF) { + efuse_utilized++; + eFuse_Addr++; + } else { + goto exit; + } + + /* */ + /* 2. Read real efuse content. Filter PG header and every section data. */ + /* */ + while ((*rtemp8 != 0xFF) && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E)) { + /* Check PG header for section num. */ + if ((*rtemp8 & 0x1F) == 0x0F) { /* extended header */ + u1temp = ((*rtemp8 & 0xE0) >> 5); + + ReadEFuseByte(Adapter, eFuse_Addr, rtemp8); + + if ((*rtemp8 & 0x0F) == 0x0F) { + eFuse_Addr++; + ReadEFuseByte(Adapter, eFuse_Addr, rtemp8); + + if (*rtemp8 != 0xFF && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E)) + eFuse_Addr++; + continue; + } else { + offset = ((*rtemp8 & 0xF0) >> 1) | u1temp; + wren = (*rtemp8 & 0x0F); + eFuse_Addr++; + } + } else { + offset = ((*rtemp8 >> 4) & 0x0f); + wren = (*rtemp8 & 0x0f); + } + + if (offset < EFUSE_MAX_SECTION_88E) { + /* Get word enable value from PG header */ + + for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) { + /* Check word enable condition in the section */ + if (!(wren & 0x01)) { + ReadEFuseByte(Adapter, eFuse_Addr, rtemp8); + eFuse_Addr++; + efuse_utilized++; + eFuseWord[offset][i] = (*rtemp8 & 0xff); + if (eFuse_Addr >= EFUSE_REAL_CONTENT_LEN_88E) + break; + ReadEFuseByte(Adapter, eFuse_Addr, rtemp8); + eFuse_Addr++; + efuse_utilized++; + eFuseWord[offset][i] |= (((u16)*rtemp8 << 8) & 0xff00); + if (eFuse_Addr >= EFUSE_REAL_CONTENT_LEN_88E) + break; + } + wren >>= 1; + } + } + + /* Read next PG header */ + ReadEFuseByte(Adapter, eFuse_Addr, rtemp8); + + if (*rtemp8 != 0xFF && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E)) { + efuse_utilized++; + eFuse_Addr++; + } + } + + /* 3. Collect 16 sections and 4 word unit into Efuse map. */ + for (i = 0; i < EFUSE_MAX_SECTION_88E; i++) { + for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++) { + efuseTbl[(i * 8) + (j * 2)] = (eFuseWord[i][j] & 0xff); + efuseTbl[(i * 8) + ((j * 2) + 1)] = ((eFuseWord[i][j] >> 8) & 0xff); + } + } + + /* 4. Copy from Efuse map to output pointer memory!!! */ + for (i = 0; i < _size_byte; i++) + pbuf[i] = efuseTbl[_offset + i]; + +exit: + kfree(efuseTbl); + kfree(eFuseWord); +} + +void rtl8188e_ReadEFuse(struct adapter *Adapter, u16 _size_byte, u8 *pbuf) +{ + int ret = _FAIL; + if (rtw_IOL_applied(Adapter)) { + rtl8188eu_InitPowerOn(Adapter); + + iol_mode_enable(Adapter, 1); + ret = iol_read_efuse(Adapter, _size_byte, pbuf); + iol_mode_enable(Adapter, 0); + + if (_SUCCESS == ret) + return; + } + + Hal_EfuseReadEFuse88E(Adapter, 0, _size_byte, pbuf); +} + +static void dump_chip_info(struct adapter *adapter, struct HAL_VERSION chip_vers) +{ + struct net_device *netdev = adapter->pnetdev; + char *cut = NULL; + char buf[25]; + + switch (chip_vers.CUTVersion) { + case A_CUT_VERSION: + cut = "A_CUT"; + break; + case B_CUT_VERSION: + cut = "B_CUT"; + break; + case C_CUT_VERSION: + cut = "C_CUT"; + break; + case D_CUT_VERSION: + cut = "D_CUT"; + break; + case E_CUT_VERSION: + cut = "E_CUT"; + break; + default: + snprintf(buf, sizeof(buf), "UNKNOWN_CUT(%d)", chip_vers.CUTVersion); + cut = buf; + break; + } + + netdev_dbg(netdev, "Chip Version Info: CHIP_8188E_%s_%s_%s_1T1R_RomVer(%d)\n", + IS_NORMAL_CHIP(chip_vers) ? "Normal_Chip" : "Test_Chip", + IS_CHIP_VENDOR_TSMC(chip_vers) ? "TSMC" : "UMC", + cut, 0); +} + +void rtl8188e_read_chip_version(struct adapter *padapter) +{ + u32 value32; + struct HAL_VERSION ChipVersion; + struct hal_data_8188e *pHalData = &padapter->haldata; + int res; + + res = rtw_read32(padapter, REG_SYS_CFG, &value32); + if (res) + return; + + ChipVersion.ChipType = ((value32 & RTL_ID) ? TEST_CHIP : NORMAL_CHIP); + + ChipVersion.VendorType = ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : CHIP_VENDOR_TSMC); + ChipVersion.CUTVersion = (value32 & CHIP_VER_RTL_MASK) >> CHIP_VER_RTL_SHIFT; /* IC version (CUT) */ + + dump_chip_info(padapter, ChipVersion); + + pHalData->VersionID = ChipVersion; +} + +void rtl8188e_SetHalODMVar(struct adapter *Adapter, void *pValue1, bool bSet) +{ + struct hal_data_8188e *pHalData = &Adapter->haldata; + struct odm_dm_struct *podmpriv = &pHalData->odmpriv; + struct sta_info *psta = (struct sta_info *)pValue1; + + if (bSet) { + podmpriv->pODM_StaInfo[psta->mac_id] = psta; + ODM_RAInfo_Init(podmpriv, psta->mac_id); + } else { + podmpriv->pODM_StaInfo[psta->mac_id] = NULL; + } +} + +void hal_notch_filter_8188e(struct adapter *adapter, bool enable) +{ + int res; + u8 reg; + + res = rtw_read8(adapter, rOFDM0_RxDSP + 1, ®); + if (res) + return; + + if (enable) + rtw_write8(adapter, rOFDM0_RxDSP + 1, reg | BIT(1)); + else + rtw_write8(adapter, rOFDM0_RxDSP + 1, reg & ~BIT(1)); +} + +/* */ +/* */ +/* LLT R/W/Init function */ +/* */ +/* */ +static s32 _LLTWrite(struct adapter *padapter, u32 address, u32 data) +{ + s32 count; + u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS); + u16 LLTReg = REG_LLT_INIT; + int res; + + rtw_write32(padapter, LLTReg, value); + + /* polling */ + for (count = 0; count <= POLLING_LLT_THRESHOLD; count++) { + res = rtw_read32(padapter, LLTReg, &value); + if (res) + continue; + + if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) + break; + } + + return count > POLLING_LLT_THRESHOLD ? _FAIL : _SUCCESS; +} + +s32 InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy) +{ + s32 status = _FAIL; + u32 i; + u32 Last_Entry_Of_TxPktBuf = LAST_ENTRY_OF_TX_PKT_BUFFER;/* 176, 22k */ + + if (rtw_IOL_applied(padapter)) { + status = iol_InitLLTTable(padapter, txpktbuf_bndy); + } else { + for (i = 0; i < (txpktbuf_bndy - 1); i++) { + status = _LLTWrite(padapter, i, i + 1); + if (_SUCCESS != status) + return status; + } + + /* end of list */ + status = _LLTWrite(padapter, (txpktbuf_bndy - 1), 0xFF); + if (_SUCCESS != status) + return status; + + /* Make the other pages as ring buffer */ + /* This ring buffer is used as beacon buffer if we config this MAC as two MAC transfer. */ + /* Otherwise used as local loopback buffer. */ + for (i = txpktbuf_bndy; i < Last_Entry_Of_TxPktBuf; i++) { + status = _LLTWrite(padapter, i, (i + 1)); + if (_SUCCESS != status) + return status; + } + + /* Let last entry point to the start entry of ring buffer */ + status = _LLTWrite(padapter, Last_Entry_Of_TxPktBuf, txpktbuf_bndy); + if (_SUCCESS != status) { + return status; + } + } + + return status; +} + +void +Hal_EfuseParseIDCode88E( + struct adapter *padapter, + u8 *hwinfo + ) +{ + struct eeprom_priv *pEEPROM = &padapter->eeprompriv; + struct net_device *netdev = padapter->pnetdev; + u16 EEPROMId; + + /* Check 0x8129 again for making sure autoload status!! */ + EEPROMId = le16_to_cpu(*((__le16 *)hwinfo)); + if (EEPROMId != RTL_EEPROM_ID) { + pr_err("EEPROM ID(%#x) is invalid!!\n", EEPROMId); + pEEPROM->bautoload_fail_flag = true; + } else { + pEEPROM->bautoload_fail_flag = false; + } + + netdev_dbg(netdev, "EEPROM ID = 0x%04x\n", EEPROMId); +} + +static void Hal_ReadPowerValueFromPROM_8188E(struct txpowerinfo24g *pwrInfo24G, u8 *PROMContent, bool AutoLoadFail) +{ + u32 rfPath, eeAddr = EEPROM_TX_PWR_INX_88E, group, TxCount = 0; + + memset(pwrInfo24G, 0, sizeof(struct txpowerinfo24g)); + + if (AutoLoadFail) { + for (rfPath = 0; rfPath < RF_PATH_MAX; rfPath++) { + /* 2.4G default value */ + for (group = 0; group < MAX_CHNL_GROUP_24G; group++) { + pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX; + pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX; + } + for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) { + if (TxCount == 0) { + pwrInfo24G->BW20_Diff[rfPath][0] = EEPROM_DEFAULT_24G_HT20_DIFF; + pwrInfo24G->OFDM_Diff[rfPath][0] = EEPROM_DEFAULT_24G_OFDM_DIFF; + } else { + pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; + pwrInfo24G->BW40_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; + pwrInfo24G->CCK_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; + pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; + } + } + } + return; + } + + for (rfPath = 0; rfPath < RF_PATH_MAX; rfPath++) { + /* 2.4G default value */ + for (group = 0; group < MAX_CHNL_GROUP_24G; group++) { + pwrInfo24G->IndexCCK_Base[rfPath][group] = PROMContent[eeAddr++]; + if (pwrInfo24G->IndexCCK_Base[rfPath][group] == 0xFF) + pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX; + } + for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) { + pwrInfo24G->IndexBW40_Base[rfPath][group] = PROMContent[eeAddr++]; + if (pwrInfo24G->IndexBW40_Base[rfPath][group] == 0xFF) + pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX; + } + for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) { + if (TxCount == 0) { + pwrInfo24G->BW40_Diff[rfPath][TxCount] = 0; + if (PROMContent[eeAddr] == 0xFF) { + pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_24G_HT20_DIFF; + } else { + pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr] & 0xf0) >> 4; + if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */ + pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0; + } + + if (PROMContent[eeAddr] == 0xFF) { + pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_24G_OFDM_DIFF; + } else { + pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr] & 0x0f); + if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */ + pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0; + } + pwrInfo24G->CCK_Diff[rfPath][TxCount] = 0; + eeAddr++; + } else { + if (PROMContent[eeAddr] == 0xFF) { + pwrInfo24G->BW40_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; + } else { + pwrInfo24G->BW40_Diff[rfPath][TxCount] = (PROMContent[eeAddr] & 0xf0) >> 4; + if (pwrInfo24G->BW40_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */ + pwrInfo24G->BW40_Diff[rfPath][TxCount] |= 0xF0; + } + + if (PROMContent[eeAddr] == 0xFF) { + pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; + } else { + pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr] & 0x0f); + if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */ + pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0; + } + eeAddr++; + + if (PROMContent[eeAddr] == 0xFF) { + pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; + } else { + pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr] & 0xf0) >> 4; + if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */ + pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0; + } + + if (PROMContent[eeAddr] == 0xFF) { + pwrInfo24G->CCK_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; + } else { + pwrInfo24G->CCK_Diff[rfPath][TxCount] = (PROMContent[eeAddr] & 0x0f); + if (pwrInfo24G->CCK_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */ + pwrInfo24G->CCK_Diff[rfPath][TxCount] |= 0xF0; + } + eeAddr++; + } + } + } +} + +static void hal_get_chnl_group_88e(u8 chnl, u8 *group) +{ + if (chnl < 3) /* Channel 1-2 */ + *group = 0; + else if (chnl < 6) /* Channel 3-5 */ + *group = 1; + else if (chnl < 9) /* Channel 6-8 */ + *group = 2; + else if (chnl < 12) /* Channel 9-11 */ + *group = 3; + else if (chnl < 14) /* Channel 12-13 */ + *group = 4; + else if (chnl == 14) /* Channel 14 */ + *group = 5; +} + +void Hal_ReadPowerSavingMode88E(struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail) +{ + if (AutoLoadFail) + padapter->pwrctrlpriv.bSupportRemoteWakeup = false; + else + /* hw power down mode selection , 0:rf-off / 1:power down */ + + /* decide hw if support remote wakeup function */ + /* if hw supported, 8051 (SIE) will generate WeakUP signal(D+/D- toggle) when autoresume */ + padapter->pwrctrlpriv.bSupportRemoteWakeup = (hwinfo[EEPROM_USB_OPTIONAL_FUNCTION0] & BIT(1)) ? true : false; +} + +void Hal_ReadTxPowerInfo88E(struct adapter *padapter, u8 *PROMContent, bool AutoLoadFail) +{ + struct hal_data_8188e *pHalData = &padapter->haldata; + struct txpowerinfo24g pwrInfo24G; + u8 ch, group; + u8 TxCount; + + Hal_ReadPowerValueFromPROM_8188E(&pwrInfo24G, PROMContent, AutoLoadFail); + + for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) { + hal_get_chnl_group_88e(ch, &group); + + pHalData->Index24G_CCK_Base[ch] = pwrInfo24G.IndexCCK_Base[0][group]; + if (ch == 14) + pHalData->Index24G_BW40_Base[ch] = pwrInfo24G.IndexBW40_Base[0][4]; + else + pHalData->Index24G_BW40_Base[ch] = pwrInfo24G.IndexBW40_Base[0][group]; + } + for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) { + pHalData->OFDM_24G_Diff[TxCount] = pwrInfo24G.OFDM_Diff[0][TxCount]; + pHalData->BW20_24G_Diff[TxCount] = pwrInfo24G.BW20_Diff[0][TxCount]; + } + + /* 2010/10/19 MH Add Regulator recognize for CU. */ + if (!AutoLoadFail) { + pHalData->EEPROMRegulatory = (PROMContent[EEPROM_RF_BOARD_OPTION_88E] & 0x7); /* bit0~2 */ + if (PROMContent[EEPROM_RF_BOARD_OPTION_88E] == 0xFF) + pHalData->EEPROMRegulatory = (EEPROM_DEFAULT_BOARD_OPTION & 0x7); /* bit0~2 */ + } else { + pHalData->EEPROMRegulatory = 0; + } +} + +void Hal_EfuseParseXtal_8188E(struct adapter *pAdapter, u8 *hwinfo, bool AutoLoadFail) +{ + struct hal_data_8188e *pHalData = &pAdapter->haldata; + + if (!AutoLoadFail) { + pHalData->CrystalCap = hwinfo[EEPROM_XTAL_88E]; + if (pHalData->CrystalCap == 0xFF) + pHalData->CrystalCap = EEPROM_Default_CrystalCap_88E; + } else { + pHalData->CrystalCap = EEPROM_Default_CrystalCap_88E; + } +} + +void rtl8188e_EfuseParseChnlPlan(struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail) +{ + padapter->mlmepriv.ChannelPlan = + hal_com_get_channel_plan(padapter, + hwinfo ? hwinfo[EEPROM_ChannelPlan_88E] : 0xFF, + padapter->registrypriv.channel_plan, + RT_CHANNEL_DOMAIN_WORLD_WIDE_13, AutoLoadFail); +} + +void Hal_ReadAntennaDiversity88E(struct adapter *pAdapter, u8 *PROMContent, bool AutoLoadFail) +{ + struct hal_data_8188e *pHalData = &pAdapter->haldata; + struct registry_priv *registry_par = &pAdapter->registrypriv; + + if (!AutoLoadFail) { + /* Antenna Diversity setting. */ + if (registry_par->antdiv_cfg == 2) { /* 2:By EFUSE */ + pHalData->AntDivCfg = (PROMContent[EEPROM_RF_BOARD_OPTION_88E] & 0x18) >> 3; + if (PROMContent[EEPROM_RF_BOARD_OPTION_88E] == 0xFF) + pHalData->AntDivCfg = (EEPROM_DEFAULT_BOARD_OPTION & 0x18) >> 3; + } else { + pHalData->AntDivCfg = registry_par->antdiv_cfg; /* 0:OFF , 1:ON, 2:By EFUSE */ + } + + if (registry_par->antdiv_type == 0) { + /* If TRxAntDivType is AUTO in advanced setting, use EFUSE value instead. */ + pHalData->TRxAntDivType = PROMContent[EEPROM_RF_ANTENNA_OPT_88E]; + if (pHalData->TRxAntDivType == 0xFF) + pHalData->TRxAntDivType = CG_TRX_HW_ANTDIV; /* For 88EE, 1Tx and 1RxCG are fixed.(1Ant, Tx and RxCG are both on aux port) */ + } else { + pHalData->TRxAntDivType = registry_par->antdiv_type; + } + + if (pHalData->TRxAntDivType == CG_TRX_HW_ANTDIV || pHalData->TRxAntDivType == CGCS_RX_HW_ANTDIV) + pHalData->AntDivCfg = 1; /* 0xC1[3] is ignored. */ + } else { + pHalData->AntDivCfg = 0; + } +} + +void Hal_ReadThermalMeter_88E(struct adapter *Adapter, u8 *PROMContent, bool AutoloadFail) +{ + struct hal_data_8188e *pHalData = &Adapter->haldata; + + /* ThermalMeter from EEPROM */ + if (!AutoloadFail) + pHalData->EEPROMThermalMeter = PROMContent[EEPROM_THERMAL_METER_88E]; + else + pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_88E; + + if (pHalData->EEPROMThermalMeter == 0xff || AutoloadFail) + pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_88E; +} diff --git a/drivers/staging/r8188eu/hal/rtl8188e_phycfg.c b/drivers/staging/r8188eu/hal/rtl8188e_phycfg.c new file mode 100644 index 000000000..532c63bce --- /dev/null +++ b/drivers/staging/r8188eu/hal/rtl8188e_phycfg.c @@ -0,0 +1,704 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright(c) 2007 - 2011 Realtek Corporation. */ + +#define _RTL8188E_PHYCFG_C_ + +#include "../include/osdep_service.h" +#include "../include/drv_types.h" +#include "../include/rtw_iol.h" +#include "../include/rtl8188e_hal.h" + +/* */ +/* 1. BB register R/W API */ +/* */ + +/* Get shifted position of the bit mask */ +static u32 phy_calculate_bit_shift(u32 bitmask) +{ + u32 i = ffs(bitmask); + + return i ? i - 1 : 32; +} + +/** +* Function: PHY_QueryBBReg +* +* OverView: Read "sepcific bits" from BB register +* +* Input: +* struct adapter *Adapter, +* u32 RegAddr, The target address to be readback +* u32 BitMask The target bit position in the target address +* to be readback +* Output: None +* Return: u32 Data The readback register value +* Note: This function is equal to "GetRegSetting" in PHY programming guide +*/ +u32 +rtl8188e_PHY_QueryBBReg( + struct adapter *Adapter, + u32 RegAddr, + u32 BitMask + ) +{ + u32 ReturnValue = 0, OriginalValue, BitShift; + int res; + + res = rtw_read32(Adapter, RegAddr, &OriginalValue); + if (res) + return 0; + + BitShift = phy_calculate_bit_shift(BitMask); + ReturnValue = (OriginalValue & BitMask) >> BitShift; + return ReturnValue; +} + +/** +* Function: PHY_SetBBReg +* +* OverView: Write "Specific bits" to BB register (page 8~) +* +* Input: +* struct adapter *Adapter, +* u32 RegAddr, The target address to be modified +* u32 BitMask The target bit position in the target address +* to be modified +* u32 Data The new register value in the target bit position +* of the target address +* +* Output: None +* Return: None +* Note: This function is equal to "PutRegSetting" in PHY programming guide +*/ + +void rtl8188e_PHY_SetBBReg(struct adapter *Adapter, u32 RegAddr, u32 BitMask, u32 Data) +{ + u32 OriginalValue, BitShift; + int res; + + if (BitMask != bMaskDWord) { /* if not "double word" write */ + res = rtw_read32(Adapter, RegAddr, &OriginalValue); + if (res) + return; + + BitShift = phy_calculate_bit_shift(BitMask); + Data = ((OriginalValue & (~BitMask)) | (Data << BitShift)); + } + + rtw_write32(Adapter, RegAddr, Data); +} + +/* */ +/* 2. RF register R/W API */ +/* */ +/** +* Function: phy_RFSerialRead +* +* OverView: Read regster from RF chips +* +* Input: +* struct adapter *Adapter, +* u32 Offset, The target address to be read +* +* Output: None +* Return: u32 reback value +* Note: Threre are three types of serial operations: +* 1. Software serial write +* 2. Hardware LSSI-Low Speed Serial Interface +* 3. Hardware HSSI-High speed +* serial write. Driver need to implement (1) and (2). +* This function is equal to the combination of RF_ReadReg() and RFLSSIRead() +*/ +static u32 +phy_RFSerialRead( + struct adapter *Adapter, + u32 Offset + ) +{ + u32 retValue = 0; + struct hal_data_8188e *pHalData = &Adapter->haldata; + struct bb_reg_def *pPhyReg = &pHalData->PHYRegDef; + u32 NewOffset; + u32 tmplong, tmplong2; + u8 RfPiEnable = 0; + /* */ + /* Make sure RF register offset is correct */ + /* */ + Offset &= 0xff; + + /* */ + /* Switch page for 8256 RF IC */ + /* */ + NewOffset = Offset; + + /* For 92S LSSI Read RFLSSIRead */ + /* For RF A/B write 0x824/82c(does not work in the future) */ + /* We must use 0x824 for RF A and B to execute read trigger */ + tmplong = rtl8188e_PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord); + tmplong2 = tmplong; + + tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge; /* T65 RF */ + + rtl8188e_PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong & (~bLSSIReadEdge)); + udelay(10);/* PlatformStallExecution(10); */ + + rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2); + udelay(100);/* PlatformStallExecution(100); */ + + udelay(10);/* PlatformStallExecution(10); */ + + RfPiEnable = (u8)rtl8188e_PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1, BIT(8)); + + if (RfPiEnable) { /* Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */ + retValue = rtl8188e_PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi, bLSSIReadBackData); + } else { /* Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF */ + retValue = rtl8188e_PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack, bLSSIReadBackData); + } + return retValue; +} + +/** +* Function: phy_RFSerialWrite +* +* OverView: Write data to RF register (page 8~) +* +* Input: +* struct adapter *Adapter, +* enum rf_radio_path eRFPath, Radio path of A/B/C/D +* u32 Offset, The target address to be read +* u32 Data The new register Data in the target bit position +* of the target to be read +* +* Output: None +* Return: None +* Note: Threre are three types of serial operations: +* 1. Software serial write +* 2. Hardware LSSI-Low Speed Serial Interface +* 3. Hardware HSSI-High speed +* serial write. Driver need to implement (1) and (2). +* This function is equal to the combination of RF_ReadReg() and RFLSSIRead() + * + * Note: For RF8256 only + * The total count of RTL8256(Zebra4) register is around 36 bit it only employs + * 4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10]) + * to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration + * programming guide" for more details. + * Thus, we define a sub-finction for RTL8526 register address conversion + * =========================================================== + * Register Mode RegCTL[1] RegCTL[0] Note + * (Reg00[12]) (Reg00[10]) + * =========================================================== + * Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf) + * ------------------------------------------------------------------ + * Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf) + * ------------------------------------------------------------------ + * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf) + * ------------------------------------------------------------------ + * + * 2008/09/02 MH Add 92S RF definition + * + * + * +*/ +static void +phy_RFSerialWrite( + struct adapter *Adapter, + u32 Offset, + u32 Data + ) +{ + u32 DataAndAddr = 0; + struct hal_data_8188e *pHalData = &Adapter->haldata; + struct bb_reg_def *pPhyReg = &pHalData->PHYRegDef; + u32 NewOffset; + + /* 2009/06/17 MH We can not execute IO for power save or other accident mode. */ + + Offset &= 0xff; + + /* */ + /* Switch page for 8256 RF IC */ + /* */ + NewOffset = Offset; + + /* */ + /* Put write addr in [5:0] and write data in [31:16] */ + /* */ + DataAndAddr = ((NewOffset << 20) | (Data & 0x000fffff)) & 0x0fffffff; /* T65 RF */ + + /* */ + /* Write Operation */ + /* */ + rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); +} + +/** +* Function: PHY_QueryRFReg +* +* OverView: Query "Specific bits" to RF register (page 8~) +* +* Input: +* struct adapter *Adapter, +* u32 RegAddr, The target address to be read +* u32 BitMask The target bit position in the target address +* to be read +* +* Output: None +* Return: u32 Readback value +* Note: This function is equal to "GetRFRegSetting" in PHY programming guide +*/ +u32 rtl8188e_PHY_QueryRFReg(struct adapter *Adapter, u32 RegAddr, u32 BitMask) +{ + u32 Original_Value, Readback_Value, BitShift; + + Original_Value = phy_RFSerialRead(Adapter, RegAddr); + + BitShift = phy_calculate_bit_shift(BitMask); + Readback_Value = (Original_Value & BitMask) >> BitShift; + return Readback_Value; +} + +/** +* Function: PHY_SetRFReg +* +* OverView: Write "Specific bits" to RF register (page 8~) +* +* Input: +* struct adapter *Adapter, +* u32 RegAddr, The target address to be modified +* u32 BitMask The target bit position in the target address +* to be modified +* u32 Data The new register Data in the target bit position +* of the target address +* +* Output: None +* Return: None +* Note: This function is equal to "PutRFRegSetting" in PHY programming guide +*/ +void +rtl8188e_PHY_SetRFReg( + struct adapter *Adapter, + u32 RegAddr, + u32 BitMask, + u32 Data + ) +{ + u32 Original_Value, BitShift; + + /* RF data is 12 bits only */ + if (BitMask != bRFRegOffsetMask) { + Original_Value = phy_RFSerialRead(Adapter, RegAddr); + BitShift = phy_calculate_bit_shift(BitMask); + Data = ((Original_Value & (~BitMask)) | (Data << BitShift)); + } + + phy_RFSerialWrite(Adapter, RegAddr, Data); +} + +/* */ +/* 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt. */ +/* */ + +/*----------------------------------------------------------------------------- + * Function: PHY_MACConfig8192C + * + * Overview: Condig MAC by header file or parameter file. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 08/12/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +s32 PHY_MACConfig8188E(struct adapter *Adapter) +{ + struct hal_data_8188e *pHalData = &Adapter->haldata; + int rtStatus = _SUCCESS; + + /* */ + /* Config MAC */ + /* */ + if (ODM_ReadAndConfig_MAC_REG_8188E(&pHalData->odmpriv)) + rtStatus = _FAIL; + + /* 2010.07.13 AMPDU aggregation number B */ + rtw_write16(Adapter, REG_MAX_AGGR_NUM, MAX_AGGR_NUM); + + return rtStatus; +} + +/** +* Function: phy_InitBBRFRegisterDefinition +* +* OverView: Initialize Register definition offset for Radio Path A/B/C/D +* +* Input: +* struct adapter *Adapter, +* +* Output: None +* Return: None +* Note: The initialization value is constant and it should never be changes +*/ +static void +phy_InitBBRFRegisterDefinition( + struct adapter *Adapter +) +{ + struct hal_data_8188e *pHalData = &Adapter->haldata; + + /* RF Interface Sowrtware Control */ + pHalData->PHYRegDef.rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 LSBs if read 32-bit from 0x870 */ + + /* RF Interface Readback Value */ + pHalData->PHYRegDef.rfintfi = rFPGA0_XAB_RFInterfaceRB; /* 16 LSBs if read 32-bit from 0x8E0 */ + + /* RF Interface Output (and Enable) */ + pHalData->PHYRegDef.rfintfo = rFPGA0_XA_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x860 */ + + /* RF Interface (Output and) Enable */ + pHalData->PHYRegDef.rfintfe = rFPGA0_XA_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */ + + /* Addr of LSSI. Wirte RF register by driver */ + pHalData->PHYRegDef.rf3wireOffset = rFPGA0_XA_LSSIParameter; /* LSSI Parameter */ + + /* RF parameter */ + pHalData->PHYRegDef.rfLSSI_Select = rFPGA0_XAB_RFParameter; /* BB Band Select */ + + /* Tx AGC Gain Stage (same for all path. Should we remove this?) */ + pHalData->PHYRegDef.rfTxGainStage = rFPGA0_TxGainStage; /* Tx gain stage */ + + /* Transceiver A~D HSSI Parameter-1 */ + pHalData->PHYRegDef.rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; /* wire control parameter1 */ + + /* Transceiver A~D HSSI Parameter-2 */ + pHalData->PHYRegDef.rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; /* wire control parameter2 */ + + /* RF switch Control */ + pHalData->PHYRegDef.rfSwitchControl = rFPGA0_XAB_SwitchControl; /* TR/Ant switch control */ + + /* AGC control 1 */ + pHalData->PHYRegDef.rfAGCControl1 = rOFDM0_XAAGCCore1; + + /* AGC control 2 */ + pHalData->PHYRegDef.rfAGCControl2 = rOFDM0_XAAGCCore2; + + /* RX AFE control 1 */ + pHalData->PHYRegDef.rfRxIQImbalance = rOFDM0_XARxIQImbalance; + + /* RX AFE control 1 */ + pHalData->PHYRegDef.rfRxAFE = rOFDM0_XARxAFE; + + /* Tx AFE control 1 */ + pHalData->PHYRegDef.rfTxIQImbalance = rOFDM0_XATxIQImbalance; + + /* Tx AFE control 2 */ + pHalData->PHYRegDef.rfTxAFE = rOFDM0_XATxAFE; + + /* Transceiver LSSI Readback SI mode */ + pHalData->PHYRegDef.rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; + + /* Transceiver LSSI Readback PI mode */ + pHalData->PHYRegDef.rfLSSIReadBackPi = TransceiverA_HSPI_Readback; +} + +void storePwrIndexDiffRateOffset(struct adapter *Adapter, u32 RegAddr, u32 BitMask, u32 Data) +{ + struct hal_data_8188e *pHalData = &Adapter->haldata; + + if (RegAddr == rTxAGC_A_Rate18_06) + pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0] = Data; + if (RegAddr == rTxAGC_A_Rate54_24) + pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][1] = Data; + if (RegAddr == rTxAGC_A_CCK1_Mcs32) + pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][6] = Data; + if (RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0xffffff00) + pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][7] = Data; + if (RegAddr == rTxAGC_A_Mcs03_Mcs00) + pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][2] = Data; + if (RegAddr == rTxAGC_A_Mcs07_Mcs04) + pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][3] = Data; + if (RegAddr == rTxAGC_A_Mcs11_Mcs08) + pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][4] = Data; + if (RegAddr == rTxAGC_A_Mcs15_Mcs12) { + pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][5] = Data; + pHalData->pwrGroupCnt++; + } + if (RegAddr == rTxAGC_B_Rate18_06) + pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][8] = Data; + if (RegAddr == rTxAGC_B_Rate54_24) + pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][9] = Data; + if (RegAddr == rTxAGC_B_CCK1_55_Mcs32) + pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][14] = Data; + if (RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0x000000ff) + pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][15] = Data; + if (RegAddr == rTxAGC_B_Mcs03_Mcs00) + pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][10] = Data; + if (RegAddr == rTxAGC_B_Mcs07_Mcs04) + pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][11] = Data; + if (RegAddr == rTxAGC_B_Mcs11_Mcs08) + pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][12] = Data; + if (RegAddr == rTxAGC_B_Mcs15_Mcs12) + pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][13] = Data; +} + +static int phy_BB8188E_Config_ParaFile(struct adapter *Adapter) +{ + struct eeprom_priv *pEEPROM = &Adapter->eeprompriv; + struct hal_data_8188e *pHalData = &Adapter->haldata; + + /* */ + /* 1. Read PHY_REG.TXT BB INIT!! */ + /* We will separate as 88C / 92C according to chip version */ + /* */ + if (ODM_ReadAndConfig_PHY_REG_1T_8188E(&pHalData->odmpriv)) + return _FAIL; + + /* 2. If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt */ + if (!pEEPROM->bautoload_fail_flag) { + pHalData->pwrGroupCnt = 0; + ODM_ReadAndConfig_PHY_REG_PG_8188E(&pHalData->odmpriv); + } + + /* 3. BB AGC table Initialization */ + if (ODM_ReadAndConfig_AGC_TAB_1T_8188E(&pHalData->odmpriv)) + return _FAIL; + + return _SUCCESS; +} + +int +PHY_BBConfig8188E( + struct adapter *Adapter + ) +{ + int rtStatus = _SUCCESS; + struct hal_data_8188e *pHalData = &Adapter->haldata; + u16 RegVal; + u8 CrystalCap; + int res; + + phy_InitBBRFRegisterDefinition(Adapter); + + /* Enable BB and RF */ + res = rtw_read16(Adapter, REG_SYS_FUNC_EN, &RegVal); + if (res) + return _FAIL; + + rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal | BIT(13) | BIT(0) | BIT(1))); + + /* 20090923 Joseph: Advised by Steven and Jenyu. Power sequence before init RF. */ + + rtw_write8(Adapter, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB); + + rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB); + + /* Config BB and AGC */ + rtStatus = phy_BB8188E_Config_ParaFile(Adapter); + + /* write 0x24[16:11] = 0x24[22:17] = CrystalCap */ + CrystalCap = pHalData->CrystalCap & 0x3F; + rtl8188e_PHY_SetBBReg(Adapter, REG_AFE_XTAL_CTRL, 0x7ff800, (CrystalCap | (CrystalCap << 6))); + + return rtStatus; +} + +static void getTxPowerIndex88E(struct adapter *Adapter, u8 channel, u8 *cckPowerLevel, + u8 *ofdmPowerLevel, u8 *BW20PowerLevel, + u8 *BW40PowerLevel) +{ + struct hal_data_8188e *pHalData = &Adapter->haldata; + u8 index = (channel - 1); + + /* 1. CCK */ + cckPowerLevel[RF_PATH_A] = pHalData->Index24G_CCK_Base[index]; + /* 2. OFDM */ + ofdmPowerLevel[RF_PATH_A] = pHalData->Index24G_BW40_Base[index] + + pHalData->OFDM_24G_Diff[RF_PATH_A]; + /* 1. BW20 */ + BW20PowerLevel[RF_PATH_A] = pHalData->Index24G_BW40_Base[index] + + pHalData->BW20_24G_Diff[RF_PATH_A]; + /* 2. BW40 */ + BW40PowerLevel[RF_PATH_A] = pHalData->Index24G_BW40_Base[index]; +} + +/*----------------------------------------------------------------------------- + * Function: SetTxPowerLevel8190() + * + * Overview: This function is export to "HalCommon" moudule + * We must consider RF path later!!!!!!! + * + * Input: struct adapter *Adapter + * u8 channel + * + * Output: NONE + * + * Return: NONE + * 2008/11/04 MHC We remove EEPROM_93C56. + * We need to move CCX relative code to independet file. + * 2009/01/21 MHC Support new EEPROM format from SD3 requirement. + * + *---------------------------------------------------------------------------*/ +void +PHY_SetTxPowerLevel8188E( + struct adapter *Adapter, + u8 channel + ) +{ + u8 cckPowerLevel[MAX_TX_COUNT] = {0}; + u8 ofdmPowerLevel[MAX_TX_COUNT] = {0};/* [0]:RF-A, [1]:RF-B */ + u8 BW20PowerLevel[MAX_TX_COUNT] = {0}; + u8 BW40PowerLevel[MAX_TX_COUNT] = {0}; + + getTxPowerIndex88E(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0], &BW20PowerLevel[0], &BW40PowerLevel[0]); + + rtl8188e_PHY_RF6052SetCckTxPower(Adapter, &cckPowerLevel[0]); + rtl8188e_PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0], &BW20PowerLevel[0], &BW40PowerLevel[0], channel); +} + +/*----------------------------------------------------------------------------- + * Function: PHY_SetBWModeCallback8192C() + * + * Overview: Timer callback function for SetSetBWMode + * + * Input: PRT_TIMER pTimer + * + * Output: NONE + * + * Return: NONE + * + * Note: (1) We do not take j mode into consideration now + * (2) Will two workitem of "switch channel" and "switch channel bandwidth" run + * concurrently? + *---------------------------------------------------------------------------*/ +static void +_PHY_SetBWMode92C( + struct adapter *Adapter +) +{ + struct hal_data_8188e *pHalData = &Adapter->haldata; + u8 regBwOpMode; + u8 regRRSR_RSC; + int res; + + if (Adapter->bDriverStopped) + return; + + /* 3 */ + /* 3<1>Set MAC register */ + /* 3 */ + + res = rtw_read8(Adapter, REG_BWOPMODE, ®BwOpMode); + if (res) + return; + + res = rtw_read8(Adapter, REG_RRSR + 2, ®RRSR_RSC); + if (res) + return; + + switch (pHalData->CurrentChannelBW) { + case HT_CHANNEL_WIDTH_20: + regBwOpMode |= BW_OPMODE_20MHZ; + /* 2007/02/07 Mark by Emily because we have not verify whether this register works */ + rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode); + break; + case HT_CHANNEL_WIDTH_40: + regBwOpMode &= ~BW_OPMODE_20MHZ; + /* 2007/02/07 Mark by Emily because we have not verify whether this register works */ + rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode); + regRRSR_RSC = (regRRSR_RSC & 0x90) | (pHalData->nCur40MhzPrimeSC << 5); + rtw_write8(Adapter, REG_RRSR + 2, regRRSR_RSC); + break; + default: + break; + } + + /* 3 */ + /* 3 <2>Set PHY related register */ + /* 3 */ + switch (pHalData->CurrentChannelBW) { + /* 20 MHz channel*/ + case HT_CHANNEL_WIDTH_20: + rtl8188e_PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0); + rtl8188e_PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0); + break; + /* 40 MHz channel*/ + case HT_CHANNEL_WIDTH_40: + rtl8188e_PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1); + rtl8188e_PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1); + /* Set Control channel to upper or lower. These settings are required only for 40MHz */ + rtl8188e_PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC >> 1)); + rtl8188e_PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC); + rtl8188e_PHY_SetBBReg(Adapter, 0x818, (BIT(26) | BIT(27)), + (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1); + break; + default: + break; + } + /* Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315 */ + + rtl8188e_PHY_RF6052SetBandwidth(Adapter, pHalData->CurrentChannelBW); +} + + /*----------------------------------------------------------------------------- + * Function: SetBWMode8190Pci() + * + * Overview: This function is export to "HalCommon" moudule + * + * Input: struct adapter *Adapter + * enum ht_channel_width Bandwidth 20M or 40M + * + * Output: NONE + * + * Return: NONE + * + * Note: We do not take j mode into consideration now + *---------------------------------------------------------------------------*/ +void PHY_SetBWMode8188E(struct adapter *Adapter, enum ht_channel_width Bandwidth, /* 20M or 40M */ + unsigned char Offset) /* Upper, Lower, or Don't care */ +{ + struct hal_data_8188e *pHalData = &Adapter->haldata; + enum ht_channel_width tmpBW = pHalData->CurrentChannelBW; + + pHalData->CurrentChannelBW = Bandwidth; + + pHalData->nCur40MhzPrimeSC = Offset; + + if ((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved)) + _PHY_SetBWMode92C(Adapter); + else + pHalData->CurrentChannelBW = tmpBW; +} + +static void _PHY_SwChnl8192C(struct adapter *Adapter, u8 channel) +{ + u32 param1, param2; + struct hal_data_8188e *pHalData = &Adapter->haldata; + + /* s1. pre common command - CmdID_SetTxPowerLevel */ + PHY_SetTxPowerLevel8188E(Adapter, channel); + + /* s2. RF dependent command - CmdID_RF_WriteReg, param1=RF_CHNLBW, param2=channel */ + param1 = RF_CHNLBW; + param2 = channel; + pHalData->RfRegChnlVal = ((pHalData->RfRegChnlVal & 0xfffffc00) | param2); + rtl8188e_PHY_SetRFReg(Adapter, param1, bRFRegOffsetMask, pHalData->RfRegChnlVal); +} + +void PHY_SwChnl8188E(struct adapter *Adapter, u8 channel) +{ + /* Call after initialization */ + struct hal_data_8188e *pHalData = &Adapter->haldata; + + if (channel == 0) + channel = 1; + + if ((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved)) { + pHalData->CurrentChannel = channel; + _PHY_SwChnl8192C(Adapter, channel); + } +} diff --git a/drivers/staging/r8188eu/hal/rtl8188e_rf6052.c b/drivers/staging/r8188eu/hal/rtl8188e_rf6052.c new file mode 100644 index 000000000..e5ec6e563 --- /dev/null +++ b/drivers/staging/r8188eu/hal/rtl8188e_rf6052.c @@ -0,0 +1,406 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright(c) 2007 - 2011 Realtek Corporation. */ + +/****************************************************************************** + * + * + * Module: rtl8192c_rf6052.c ( Source C File) + * + * Note: Provide RF 6052 series relative API. + * + * Function: + * + * Export: + * + * Abbrev: + * + * History: + * Data Who Remark + * + * 09/25/2008 MHC Create initial version. + * 11/05/2008 MHC Add API for tw power setting. + * + * +******************************************************************************/ + +#define _RTL8188E_RF6052_C_ + +#include "../include/osdep_service.h" +#include "../include/drv_types.h" +#include "../include/rtl8188e_hal.h" + +/*----------------------------------------------------------------------------- + * Function: PHY_RF6052SetBandwidth() + * + * Overview: This function is called by SetBWModeCallback8190Pci() only + * + * Input: struct adapter *Adapter + * WIRELESS_BANDWIDTH_E Bandwidth 20M or 40M + * + * Output: NONE + * + * Return: NONE + * + * Note: For RF type 0222D + *---------------------------------------------------------------------------*/ +void rtl8188e_PHY_RF6052SetBandwidth(struct adapter *Adapter, + enum ht_channel_width Bandwidth) +{ + struct hal_data_8188e *pHalData = &Adapter->haldata; + + switch (Bandwidth) { + case HT_CHANNEL_WIDTH_20: + pHalData->RfRegChnlVal = ((pHalData->RfRegChnlVal & 0xfffff3ff) | BIT(10) | BIT(11)); + rtl8188e_PHY_SetRFReg(Adapter, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal); + break; + case HT_CHANNEL_WIDTH_40: + pHalData->RfRegChnlVal = ((pHalData->RfRegChnlVal & 0xfffff3ff) | BIT(10)); + rtl8188e_PHY_SetRFReg(Adapter, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal); + break; + default: + break; + } +} + +/*----------------------------------------------------------------------------- + * Function: PHY_RF6052SetCckTxPower + * + * Overview: + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/05/2008 MHC Simulate 8192series.. + * + *---------------------------------------------------------------------------*/ + +void +rtl8188e_PHY_RF6052SetCckTxPower( + struct adapter *Adapter, + u8 *pPowerlevel) +{ + struct hal_data_8188e *pHalData = &Adapter->haldata; + struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; + u32 TxAGC[2] = {0, 0}, tmpval = 0, pwrtrac_value; + u8 idx1, idx2; + u8 *ptr; + u8 direction; + + if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) { + TxAGC[RF_PATH_A] = 0x3f3f3f3f; + TxAGC[RF_PATH_B] = 0x3f3f3f3f; + + for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) { + TxAGC[idx1] = + pPowerlevel[idx1] | (pPowerlevel[idx1] << 8) | + (pPowerlevel[idx1] << 16) | (pPowerlevel[idx1] << 24); + } + } else { + for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) { + TxAGC[idx1] = + pPowerlevel[idx1] | (pPowerlevel[idx1] << 8) | + (pPowerlevel[idx1] << 16) | (pPowerlevel[idx1] << 24); + } + if (pHalData->EEPROMRegulatory == 0) { + tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][6]) + + (pHalData->MCSTxPowerLevelOriginalOffset[0][7] << 8); + TxAGC[RF_PATH_A] += tmpval; + + tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][14]) + + (pHalData->MCSTxPowerLevelOriginalOffset[0][15] << 24); + TxAGC[RF_PATH_B] += tmpval; + } + } + for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) { + ptr = (u8 *)(&TxAGC[idx1]); + for (idx2 = 0; idx2 < 4; idx2++) { + if (*ptr > RF6052_MAX_TX_PWR) + *ptr = RF6052_MAX_TX_PWR; + ptr++; + } + } + ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 1, &direction, &pwrtrac_value); + + if (direction == 1) { + /* Increase TX power */ + TxAGC[0] += pwrtrac_value; + TxAGC[1] += pwrtrac_value; + } else if (direction == 2) { + /* Decrease TX power */ + TxAGC[0] -= pwrtrac_value; + TxAGC[1] -= pwrtrac_value; + } + + /* rf-A cck tx power */ + tmpval = TxAGC[RF_PATH_A] & 0xff; + rtl8188e_PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval); + tmpval = TxAGC[RF_PATH_A] >> 8; + rtl8188e_PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval); + + /* rf-B cck tx power */ + tmpval = TxAGC[RF_PATH_B] >> 24; + rtl8188e_PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval); + tmpval = TxAGC[RF_PATH_B] & 0x00ffffff; + rtl8188e_PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval); +} /* PHY_RF6052SetCckTxPower */ + +/* */ +/* powerbase0 for OFDM rates */ +/* powerbase1 for HT MCS rates */ +/* */ +static void getpowerbase88e(struct adapter *Adapter, u8 *pPowerLevelOFDM, + u8 *pPowerLevelBW20, u8 *pPowerLevelBW40, u8 Channel, u32 *OfdmBase, u32 *MCSBase) +{ + struct hal_data_8188e *pHalData = &Adapter->haldata; + u32 powerBase0, powerBase1; + u8 i; + + for (i = 0; i < 2; i++) { + powerBase0 = pPowerLevelOFDM[i]; + + powerBase0 = (powerBase0 << 24) | (powerBase0 << 16) | (powerBase0 << 8) | powerBase0; + *(OfdmBase + i) = powerBase0; + } + + /* Check HT20 to HT40 diff */ + if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20) + powerBase1 = pPowerLevelBW20[0]; + else + powerBase1 = pPowerLevelBW40[0]; + powerBase1 = (powerBase1 << 24) | (powerBase1 << 16) | (powerBase1 << 8) | powerBase1; + *MCSBase = powerBase1; +} + +static void get_rx_power_val_by_reg(struct adapter *Adapter, u8 Channel, + u8 index, u32 *powerBase0, u32 *powerBase1, + u32 *pOutWriteVal) +{ + struct hal_data_8188e *pHalData = &Adapter->haldata; + u8 i, chnlGroup = 0, pwr_diff_limit[4], customer_pwr_limit; + s8 pwr_diff = 0; + u32 writeVal, customer_limit, rf; + u8 Regulatory = pHalData->EEPROMRegulatory; + + /* Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate */ + + for (rf = 0; rf < 2; rf++) { + switch (Regulatory) { + case 0: /* Realtek better performance */ + /* increase power diff defined by Realtek for large power */ + chnlGroup = 0; + writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index + (rf ? 8 : 0)] + + ((index < 2) ? powerBase0[rf] : powerBase1[rf]); + break; + case 1: /* Realtek regulatory */ + /* increase power diff defined by Realtek for regulatory */ + if (pHalData->pwrGroupCnt == 1) + chnlGroup = 0; + if (pHalData->pwrGroupCnt >= MAX_PG_GROUP) { + if (Channel < 3) /* Channel 1-2 */ + chnlGroup = 0; + else if (Channel < 6) /* Channel 3-5 */ + chnlGroup = 1; + else if (Channel < 9) /* Channel 6-8 */ + chnlGroup = 2; + else if (Channel < 12) /* Channel 9-11 */ + chnlGroup = 3; + else if (Channel < 14) /* Channel 12-13 */ + chnlGroup = 4; + else if (Channel == 14) /* Channel 14 */ + chnlGroup = 5; + } + writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index + (rf ? 8 : 0)] + + ((index < 2) ? powerBase0[rf] : powerBase1[rf]); + break; + case 2: /* Better regulatory */ + /* don't increase any power diff */ + writeVal = ((index < 2) ? powerBase0[rf] : powerBase1[rf]); + break; + case 3: /* Customer defined power diff. */ + /* increase power diff defined by customer. */ + chnlGroup = 0; + + if (index < 2) + pwr_diff = pHalData->TxPwrLegacyHtDiff[rf][Channel - 1]; + else if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20) + pwr_diff = pHalData->TxPwrHt20Diff[rf][Channel - 1]; + + if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40) + customer_pwr_limit = pHalData->PwrGroupHT40[rf][Channel - 1]; + else + customer_pwr_limit = pHalData->PwrGroupHT20[rf][Channel - 1]; + + if (pwr_diff >= customer_pwr_limit) + pwr_diff = 0; + else + pwr_diff = customer_pwr_limit - pwr_diff; + + for (i = 0; i < 4; i++) { + pwr_diff_limit[i] = (u8)((pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index + (rf ? 8 : 0)] & (0x7f << (i * 8))) >> (i * 8)); + + if (pwr_diff_limit[i] > pwr_diff) + pwr_diff_limit[i] = pwr_diff; + } + customer_limit = (pwr_diff_limit[3] << 24) | (pwr_diff_limit[2] << 16) | + (pwr_diff_limit[1] << 8) | (pwr_diff_limit[0]); + writeVal = customer_limit + ((index < 2) ? powerBase0[rf] : powerBase1[rf]); + break; + default: + chnlGroup = 0; + writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index + (rf ? 8 : 0)] + + ((index < 2) ? powerBase0[rf] : powerBase1[rf]); + break; + } + + *(pOutWriteVal + rf) = writeVal; + } +} +static void writeOFDMPowerReg88E(struct adapter *Adapter, u8 index, u32 *pValue) +{ + u16 regoffset_a[6] = { + rTxAGC_A_Rate18_06, rTxAGC_A_Rate54_24, + rTxAGC_A_Mcs03_Mcs00, rTxAGC_A_Mcs07_Mcs04, + rTxAGC_A_Mcs11_Mcs08, rTxAGC_A_Mcs15_Mcs12}; + u16 regoffset_b[6] = { + rTxAGC_B_Rate18_06, rTxAGC_B_Rate54_24, + rTxAGC_B_Mcs03_Mcs00, rTxAGC_B_Mcs07_Mcs04, + rTxAGC_B_Mcs11_Mcs08, rTxAGC_B_Mcs15_Mcs12}; + u8 i, rf, pwr_val[4]; + u32 writeVal; + u16 regoffset; + + for (rf = 0; rf < 2; rf++) { + writeVal = pValue[rf]; + for (i = 0; i < 4; i++) { + pwr_val[i] = (u8)((writeVal & (0x7f << (i * 8))) >> (i * 8)); + if (pwr_val[i] > RF6052_MAX_TX_PWR) + pwr_val[i] = RF6052_MAX_TX_PWR; + } + writeVal = (pwr_val[3] << 24) | (pwr_val[2] << 16) | (pwr_val[1] << 8) | pwr_val[0]; + + if (rf == 0) + regoffset = regoffset_a[index]; + else + regoffset = regoffset_b[index]; + + rtl8188e_PHY_SetBBReg(Adapter, regoffset, bMaskDWord, writeVal); + + /* 201005115 Joseph: Set Tx Power diff for Tx power training mechanism. */ + if (regoffset == rTxAGC_A_Mcs07_Mcs04 || regoffset == rTxAGC_B_Mcs07_Mcs04) { + writeVal = pwr_val[3]; + if (regoffset == rTxAGC_A_Mcs15_Mcs12 || regoffset == rTxAGC_A_Mcs07_Mcs04) + regoffset = 0xc90; + if (regoffset == rTxAGC_B_Mcs15_Mcs12 || regoffset == rTxAGC_B_Mcs07_Mcs04) + regoffset = 0xc98; + for (i = 0; i < 3; i++) { + if (i != 2) + writeVal = (writeVal > 8) ? (writeVal - 8) : 0; + else + writeVal = (writeVal > 6) ? (writeVal - 6) : 0; + rtw_write8(Adapter, (u32)(regoffset + i), (u8)writeVal); + } + } + } +} + +/*----------------------------------------------------------------------------- + * Function: PHY_RF6052SetOFDMTxPower + * + * Overview: For legacy and HY OFDM, we must read EEPROM TX power index for + * different channel and read original value in TX power register area from + * 0xe00. We increase offset and original value to be correct tx pwr. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/05/2008 MHC Simulate 8192 series method. + * 01/06/2009 MHC 1. Prevent Path B tx power overflow or underflow dure to + * A/B pwr difference or legacy/HT pwr diff. + * 2. We concern with path B legacy/HT OFDM difference. + * 01/22/2009 MHC Support new EPRO format from SD3. + * + *---------------------------------------------------------------------------*/ + +void +rtl8188e_PHY_RF6052SetOFDMTxPower( + struct adapter *Adapter, + u8 *pPowerLevelOFDM, + u8 *pPowerLevelBW20, + u8 *pPowerLevelBW40, + u8 Channel) +{ + struct hal_data_8188e *pHalData = &Adapter->haldata; + u32 writeVal[2], powerBase0[2], powerBase1[2], pwrtrac_value; + u8 direction; + u8 index = 0; + + getpowerbase88e(Adapter, pPowerLevelOFDM, pPowerLevelBW20, pPowerLevelBW40, Channel, &powerBase0[0], &powerBase1[0]); + + /* 2012/04/23 MH According to power tracking value, we need to revise OFDM tx power. */ + /* This is ued to fix unstable power tracking mode. */ + ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 0, &direction, &pwrtrac_value); + + for (index = 0; index < 6; index++) { + get_rx_power_val_by_reg(Adapter, Channel, index, + &powerBase0[0], &powerBase1[0], + &writeVal[0]); + + if (direction == 1) { + writeVal[0] += pwrtrac_value; + writeVal[1] += pwrtrac_value; + } else if (direction == 2) { + writeVal[0] -= pwrtrac_value; + writeVal[1] -= pwrtrac_value; + } + writeOFDMPowerReg88E(Adapter, index, &writeVal[0]); + } +} + +int phy_RF6052_Config_ParaFile(struct adapter *Adapter) +{ + struct bb_reg_def *pPhyReg; + struct hal_data_8188e *pHalData = &Adapter->haldata; + u32 u4RegValue = 0; + int rtStatus = _SUCCESS; + + /* Initialize RF */ + + pPhyReg = &pHalData->PHYRegDef; + + /*----Store original RFENV control type----*/ + u4RegValue = rtl8188e_PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV); + + /*----Set RF_ENV enable----*/ + rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV << 16, 0x1); + udelay(1);/* PlatformStallExecution(1); */ + + /*----Set RF_ENV output high----*/ + rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); + udelay(1);/* PlatformStallExecution(1); */ + + /* Set bit number of Address and Data for RF register */ + rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 1 to 4 bits for 8255 */ + udelay(1);/* PlatformStallExecution(1); */ + + rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for 8255 */ + udelay(1);/* PlatformStallExecution(1); */ + + /*----Initialize RF fom connfiguration file----*/ + if (ODM_ReadAndConfig_RadioA_1T_8188E(&pHalData->odmpriv)) + rtStatus = _FAIL; + + /*----Restore RFENV control type----*/; + rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); + + return rtStatus; +} diff --git a/drivers/staging/r8188eu/hal/rtl8188e_rxdesc.c b/drivers/staging/r8188eu/hal/rtl8188e_rxdesc.c new file mode 100644 index 000000000..dff0cba75 --- /dev/null +++ b/drivers/staging/r8188eu/hal/rtl8188e_rxdesc.c @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright(c) 2007 - 2011 Realtek Corporation. */ + +#define _RTL8188E_REDESC_C_ + +#include "../include/osdep_service.h" +#include "../include/drv_types.h" +#include "../include/rtl8188e_hal.h" + +static void process_rssi(struct adapter *padapter, struct recv_frame *prframe) +{ + struct rx_pkt_attrib *pattrib = &prframe->attrib; + struct signal_stat *signal_stat = &padapter->recvpriv.signal_strength_data; + + if (signal_stat->update_req) { + signal_stat->total_num = 0; + signal_stat->total_val = 0; + signal_stat->update_req = 0; + } + + signal_stat->total_num++; + signal_stat->total_val += pattrib->phy_info.SignalStrength; + signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num; +} /* Process_UI_RSSI_8192C */ + +static void process_link_qual(struct adapter *padapter, struct recv_frame *prframe) +{ + struct rx_pkt_attrib *pattrib; + struct signal_stat *signal_stat; + + if (!prframe || !padapter) + return; + + pattrib = &prframe->attrib; + signal_stat = &padapter->recvpriv.signal_qual_data; + + if (signal_stat->update_req) { + signal_stat->total_num = 0; + signal_stat->total_val = 0; + signal_stat->update_req = 0; + } + + signal_stat->total_num++; + signal_stat->total_val += pattrib->phy_info.SignalQuality; + signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num; +} + +static void rtl8188e_process_phy_info(struct adapter *padapter, void *prframe) +{ + struct recv_frame *precvframe = (struct recv_frame *)prframe; + + /* Check RSSI */ + process_rssi(padapter, precvframe); + /* Check EVM */ + process_link_qual(padapter, precvframe); +} + +void update_recvframe_attrib_88e(struct recv_frame *precvframe, struct recv_stat *prxstat) +{ + struct rx_pkt_attrib *pattrib = &precvframe->attrib; + memset(pattrib, 0, sizeof(struct rx_pkt_attrib)); + + pattrib->crc_err = (le32_to_cpu(prxstat->rxdw0) >> 14) & 0x1; + + pattrib->pkt_rpt_type = (le32_to_cpu(prxstat->rxdw3) >> 14) & 0x3; + + if (pattrib->pkt_rpt_type == NORMAL_RX) { + pattrib->pkt_len = le32_to_cpu(prxstat->rxdw0) & 0x00003fff; + pattrib->drvinfo_sz = ((le32_to_cpu(prxstat->rxdw0) >> 16) & 0xf) * 8; + + pattrib->physt = (le32_to_cpu(prxstat->rxdw0) >> 26) & 0x1; + + pattrib->bdecrypted = (le32_to_cpu(prxstat->rxdw0) & BIT(27)) ? 0 : 1; + pattrib->encrypt = (le32_to_cpu(prxstat->rxdw0) >> 20) & 0x7; + + pattrib->qos = (le32_to_cpu(prxstat->rxdw0) >> 23) & 0x1; + pattrib->priority = (le32_to_cpu(prxstat->rxdw1) >> 8) & 0xf; + + pattrib->amsdu = (le32_to_cpu(prxstat->rxdw1) >> 13) & 0x1; + + pattrib->seq_num = le32_to_cpu(prxstat->rxdw2) & 0x00000fff; + pattrib->frag_num = (le32_to_cpu(prxstat->rxdw2) >> 12) & 0xf; + pattrib->mfrag = (le32_to_cpu(prxstat->rxdw1) >> 27) & 0x1; + pattrib->mdata = (le32_to_cpu(prxstat->rxdw1) >> 26) & 0x1; + + pattrib->mcs_rate = le32_to_cpu(prxstat->rxdw3) & 0x3f; + pattrib->rxht = (le32_to_cpu(prxstat->rxdw3) >> 6) & 0x1; + + pattrib->icv_err = (le32_to_cpu(prxstat->rxdw0) >> 15) & 0x1; + pattrib->shift_sz = (le32_to_cpu(prxstat->rxdw0) >> 24) & 0x3; + } else if (pattrib->pkt_rpt_type == TX_REPORT1) { /* CCX */ + pattrib->pkt_len = TX_RPT1_PKT_LEN; + } else if (pattrib->pkt_rpt_type == TX_REPORT2) { + pattrib->pkt_len = le32_to_cpu(prxstat->rxdw0) & 0x3FF; + + pattrib->MacIDValidEntry[0] = le32_to_cpu(prxstat->rxdw4); + pattrib->MacIDValidEntry[1] = le32_to_cpu(prxstat->rxdw5); + + } else if (pattrib->pkt_rpt_type == HIS_REPORT) { + pattrib->pkt_len = le32_to_cpu(prxstat->rxdw0) & 0x00003fff; + } +} + +/* + * Notice: + * Before calling this function, + * precvframe->rx_data should be ready! + */ +void update_recvframe_phyinfo_88e(struct recv_frame *precvframe, struct phy_stat *pphy_status) +{ + struct adapter *padapter = precvframe->adapter; + struct rx_pkt_attrib *pattrib = &precvframe->attrib; + struct hal_data_8188e *pHalData = &padapter->haldata; + struct phy_info *pPHYInfo = &pattrib->phy_info; + u8 *wlanhdr = precvframe->rx_data; + __le16 fc = *(__le16 *)wlanhdr; + struct odm_per_pkt_info pkt_info; + u8 *sa = NULL; + struct sta_priv *pstapriv; + struct sta_info *psta; + + pkt_info.bPacketMatchBSSID = ((!ieee80211_is_ctl(fc)) && + !pattrib->icv_err && !pattrib->crc_err && + !memcmp(get_hdr_bssid(wlanhdr), + get_bssid(&padapter->mlmepriv), ETH_ALEN)); + + pkt_info.bPacketToSelf = pkt_info.bPacketMatchBSSID && + (!memcmp(get_da(wlanhdr), + myid(&padapter->eeprompriv), ETH_ALEN)); + + pkt_info.bPacketBeacon = pkt_info.bPacketMatchBSSID && ieee80211_is_beacon(fc); + if (pkt_info.bPacketBeacon) { + if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE)) + sa = padapter->mlmepriv.cur_network.network.MacAddress; + /* to do Ad-hoc */ + } else { + sa = get_sa(wlanhdr); + } + + pstapriv = &padapter->stapriv; + pkt_info.StationID = 0xFF; + psta = rtw_get_stainfo(pstapriv, sa); + if (psta) + pkt_info.StationID = psta->mac_id; + pkt_info.Rate = pattrib->mcs_rate; + + ODM_PhyStatusQuery(&pHalData->odmpriv, pPHYInfo, (u8 *)pphy_status, &(pkt_info), padapter); + + precvframe->psta = NULL; + if (pkt_info.bPacketMatchBSSID && + (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE))) { + if (psta) { + precvframe->psta = psta; + rtl8188e_process_phy_info(padapter, precvframe); + } + } else if (pkt_info.bPacketToSelf || pkt_info.bPacketBeacon) { + if (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) { + if (psta) + precvframe->psta = psta; + } + rtl8188e_process_phy_info(padapter, precvframe); + } +} diff --git a/drivers/staging/r8188eu/hal/rtl8188eu_xmit.c b/drivers/staging/r8188eu/hal/rtl8188eu_xmit.c new file mode 100644 index 000000000..8e4a5acc0 --- /dev/null +++ b/drivers/staging/r8188eu/hal/rtl8188eu_xmit.c @@ -0,0 +1,642 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright(c) 2007 - 2011 Realtek Corporation. */ + +#define _RTL8188E_XMIT_C_ +#include "../include/osdep_service.h" +#include "../include/drv_types.h" +#include "../include/wifi.h" +#include "../include/osdep_intf.h" +#include "../include/usb_ops.h" +#include "../include/rtl8188e_hal.h" + +s32 rtl8188eu_init_xmit_priv(struct adapter *adapt) +{ + struct xmit_priv *pxmitpriv = &adapt->xmitpriv; + + tasklet_init(&pxmitpriv->xmit_tasklet, + rtl8188eu_xmit_tasklet, + (unsigned long)adapt); + return _SUCCESS; +} + +static void rtl8188eu_cal_txdesc_chksum(struct tx_desc *ptxdesc) +{ + u16 *usptr = (u16 *)ptxdesc; + u32 count = 16; /* (32 bytes / 2 bytes per XOR) => 16 times */ + u32 index; + u16 checksum = 0; + + /* Clear first */ + ptxdesc->txdw7 &= cpu_to_le32(0xffff0000); + + for (index = 0; index < count; index++) + checksum = checksum ^ le16_to_cpu(*(__le16 *)(usptr + index)); + ptxdesc->txdw7 |= cpu_to_le32(0x0000ffff & checksum); +} + +/* Description: In normal chip, we should send some packet to Hw which will be used by Fw */ +/* in FW LPS mode. The function is to fill the Tx descriptor of this packets, then */ +/* Fw can tell Hw to send these packet derectly. */ +void rtl8188e_fill_fake_txdesc(struct adapter *adapt, u8 *desc, u32 BufferLen, u8 ispspoll, u8 is_btqosnull) +{ + struct tx_desc *ptxdesc; + + /* Clear all status */ + ptxdesc = (struct tx_desc *)desc; + memset(desc, 0, TXDESC_SIZE); + + /* offset 0 */ + ptxdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG); /* own, bFirstSeg, bLastSeg; */ + + ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) << OFFSET_SHT) & 0x00ff0000); /* 32 bytes for TX Desc */ + + ptxdesc->txdw0 |= cpu_to_le32(BufferLen & 0x0000ffff); /* Buffer size + command header */ + + /* offset 4 */ + ptxdesc->txdw1 |= cpu_to_le32((QSLT_MGNT << QSEL_SHT) & 0x00001f00); /* Fixed queue of Mgnt queue */ + + /* Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error vlaue by Hw. */ + if (ispspoll) { + ptxdesc->txdw1 |= cpu_to_le32(NAVUSEHDR); + } else { + ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); /* Hw set sequence number */ + ptxdesc->txdw3 |= cpu_to_le32((8 << 28)); /* set bit3 to 1. Suugested by TimChen. 2009.12.29. */ + } + + if (is_btqosnull) + ptxdesc->txdw2 |= cpu_to_le32(BIT(23)); /* BT NULL */ + + /* offset 16 */ + ptxdesc->txdw4 |= cpu_to_le32(BIT(8));/* driver uses rate */ + + /* USB interface drop packet if the checksum of descriptor isn't correct. */ + /* Using this checksum can let hardware recovery from packet bulk out error (e.g. Cancel URC, Bulk out error.). */ + rtl8188eu_cal_txdesc_chksum(ptxdesc); +} + +static void fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc) +{ + if ((pattrib->encrypt > 0) && !pattrib->bswenc) { + switch (pattrib->encrypt) { + /* SEC_TYPE : 0:NO_ENC,1:WEP40/TKIP,2:WAPI,3:AES */ + case _WEP40_: + case _WEP104_: + ptxdesc->txdw1 |= cpu_to_le32((0x01 << SEC_TYPE_SHT) & 0x00c00000); + ptxdesc->txdw2 |= cpu_to_le32(0x7 << AMPDU_DENSITY_SHT); + break; + case _TKIP_: + case _TKIP_WTMIC_: + ptxdesc->txdw1 |= cpu_to_le32((0x01 << SEC_TYPE_SHT) & 0x00c00000); + ptxdesc->txdw2 |= cpu_to_le32(0x7 << AMPDU_DENSITY_SHT); + break; + case _AES_: + ptxdesc->txdw1 |= cpu_to_le32((0x03 << SEC_TYPE_SHT) & 0x00c00000); + ptxdesc->txdw2 |= cpu_to_le32(0x7 << AMPDU_DENSITY_SHT); + break; + case _NO_PRIVACY_: + default: + break; + } + } +} + +static void fill_txdesc_vcs(struct pkt_attrib *pattrib, __le32 *pdw) +{ + switch (pattrib->vcs_mode) { + case RTS_CTS: + *pdw |= cpu_to_le32(RTS_EN); + break; + case CTS_TO_SELF: + *pdw |= cpu_to_le32(CTS_2_SELF); + break; + case NONE_VCS: + default: + break; + } + if (pattrib->vcs_mode) { + *pdw |= cpu_to_le32(HW_RTS_EN); + /* Set RTS BW */ + if (pattrib->ht_en) { + *pdw |= (pattrib->bwmode & HT_CHANNEL_WIDTH_40) ? cpu_to_le32(BIT(27)) : 0; + + if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER) + *pdw |= cpu_to_le32((0x01 << 28) & 0x30000000); + else if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER) + *pdw |= cpu_to_le32((0x02 << 28) & 0x30000000); + else if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) + *pdw |= 0; + else + *pdw |= cpu_to_le32((0x03 << 28) & 0x30000000); + } + } +} + +static void fill_txdesc_phy(struct pkt_attrib *pattrib, __le32 *pdw) +{ + if (pattrib->ht_en) { + *pdw |= (pattrib->bwmode & HT_CHANNEL_WIDTH_40) ? cpu_to_le32(BIT(25)) : 0; + + if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER) + *pdw |= cpu_to_le32((0x01 << DATA_SC_SHT) & 0x003f0000); + else if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER) + *pdw |= cpu_to_le32((0x02 << DATA_SC_SHT) & 0x003f0000); + else if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) + *pdw |= 0; + else + *pdw |= cpu_to_le32((0x03 << DATA_SC_SHT) & 0x003f0000); + } +} + +static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz, u8 bagg_pkt) +{ + int pull = 0; + uint qsel; + u8 data_rate, pwr_status, offset; + struct adapter *adapt = pxmitframe->padapter; + struct pkt_attrib *pattrib = &pxmitframe->attrib; + struct hal_data_8188e *haldata = &adapt->haldata; + struct tx_desc *ptxdesc = (struct tx_desc *)pmem; + struct mlme_ext_priv *pmlmeext = &adapt->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + + memset(ptxdesc, 0, sizeof(struct tx_desc)); + + /* 4 offset 0 */ + ptxdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG); + ptxdesc->txdw0 |= cpu_to_le32(sz & 0x0000ffff);/* update TXPKTSIZE */ + + offset = TXDESC_SIZE + OFFSET_SZ; + + ptxdesc->txdw0 |= cpu_to_le32(((offset) << OFFSET_SHT) & 0x00ff0000);/* 32 bytes for TX Desc */ + + if (is_multicast_ether_addr(pattrib->ra)) + ptxdesc->txdw0 |= cpu_to_le32(BMC); + + /* pkt_offset, unit:8 bytes padding */ + if (pxmitframe->pkt_offset > 0) + ptxdesc->txdw1 |= cpu_to_le32((pxmitframe->pkt_offset << 26) & 0x7c000000); + + /* driver uses rate */ + ptxdesc->txdw4 |= cpu_to_le32(USERATE);/* rate control always by driver */ + + if ((pxmitframe->frame_tag & 0x0f) == DATA_FRAMETAG) { + /* offset 4 */ + ptxdesc->txdw1 |= cpu_to_le32(pattrib->mac_id & 0x3F); + + qsel = (uint)(pattrib->qsel & 0x0000001f); + ptxdesc->txdw1 |= cpu_to_le32((qsel << QSEL_SHT) & 0x00001f00); + + ptxdesc->txdw1 |= cpu_to_le32((pattrib->raid << RATE_ID_SHT) & 0x000F0000); + + fill_txdesc_sectype(pattrib, ptxdesc); + + if (pattrib->ampdu_en) { + ptxdesc->txdw2 |= cpu_to_le32(AGG_EN);/* AGG EN */ + ptxdesc->txdw6 = cpu_to_le32(0x6666f800); + } else { + ptxdesc->txdw2 |= cpu_to_le32(AGG_BK);/* AGG BK */ + } + + /* offset 8 */ + + /* offset 12 */ + ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum << SEQ_SHT) & 0x0FFF0000); + + /* offset 16 , offset 20 */ + if (pattrib->qos_en) + ptxdesc->txdw4 |= cpu_to_le32(QOS);/* QoS */ + + /* offset 20 */ + if (pxmitframe->agg_num > 1) + ptxdesc->txdw5 |= cpu_to_le32((pxmitframe->agg_num << USB_TXAGG_NUM_SHT) & 0xFF000000); + + if ((pattrib->ether_type != 0x888e) && + (pattrib->ether_type != 0x0806) && + (pattrib->ether_type != 0x88b4) && + (pattrib->dhcp_pkt != 1)) { + /* Non EAP & ARP & DHCP type data packet */ + + fill_txdesc_vcs(pattrib, &ptxdesc->txdw4); + fill_txdesc_phy(pattrib, &ptxdesc->txdw4); + + ptxdesc->txdw4 |= cpu_to_le32(0x00000008);/* RTS Rate=24M */ + ptxdesc->txdw5 |= cpu_to_le32(0x0001ff00);/* DATA/RTS Rate FB LMT */ + + if (pattrib->ht_en) { + if (ODM_RA_GetShortGI_8188E(&haldata->odmpriv, pattrib->mac_id)) + ptxdesc->txdw5 |= cpu_to_le32(SGI);/* SGI */ + } + data_rate = ODM_RA_GetDecisionRate_8188E(&haldata->odmpriv, pattrib->mac_id); + ptxdesc->txdw5 |= cpu_to_le32(data_rate & 0x3F); + pwr_status = ODM_RA_GetHwPwrStatus_8188E(&haldata->odmpriv, pattrib->mac_id); + ptxdesc->txdw4 |= cpu_to_le32((pwr_status & 0x7) << PWR_STATUS_SHT); + } else { + /* EAP data packet and ARP packet and DHCP. */ + /* Use the 1M data rate to send the EAP/ARP packet. */ + /* This will maybe make the handshake smooth. */ + ptxdesc->txdw2 |= cpu_to_le32(AGG_BK);/* AGG BK */ + if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT) + ptxdesc->txdw4 |= cpu_to_le32(BIT(24));/* DATA_SHORT */ + ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate)); + } + } else if ((pxmitframe->frame_tag & 0x0f) == MGNT_FRAMETAG) { + /* offset 4 */ + ptxdesc->txdw1 |= cpu_to_le32(pattrib->mac_id & 0x3f); + + qsel = (uint)(pattrib->qsel & 0x0000001f); + ptxdesc->txdw1 |= cpu_to_le32((qsel << QSEL_SHT) & 0x00001f00); + + ptxdesc->txdw1 |= cpu_to_le32((pattrib->raid << RATE_ID_SHT) & 0x000f0000); + + /* offset 8 */ + /* CCX-TXRPT ack for xmit mgmt frames. */ + if (pxmitframe->ack_report) + ptxdesc->txdw2 |= cpu_to_le32(BIT(19)); + + /* offset 12 */ + ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum << SEQ_SHT) & 0x0FFF0000); + + /* offset 20 */ + ptxdesc->txdw5 |= cpu_to_le32(RTY_LMT_EN);/* retry limit enable */ + if (pattrib->retry_ctrl) + ptxdesc->txdw5 |= cpu_to_le32(0x00180000);/* retry limit = 6 */ + else + ptxdesc->txdw5 |= cpu_to_le32(0x00300000);/* retry limit = 12 */ + + ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate)); + } else if ((pxmitframe->frame_tag & 0x0f) != TXAGG_FRAMETAG) { + /* offset 4 */ + ptxdesc->txdw1 |= cpu_to_le32((4) & 0x3f);/* CAM_ID(MAC_ID) */ + + ptxdesc->txdw1 |= cpu_to_le32((6 << RATE_ID_SHT) & 0x000f0000);/* raid */ + + /* offset 8 */ + + /* offset 12 */ + ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum << SEQ_SHT) & 0x0fff0000); + + /* offset 20 */ + ptxdesc->txdw5 |= cpu_to_le32(MRateToHwRate(pmlmeext->tx_rate)); + } + + /* 2009.11.05. tynli_test. Suggested by SD4 Filen for FW LPS. */ + /* (1) The sequence number of each non-Qos frame / broadcast / multicast / */ + /* mgnt frame should be controlled by Hw because Fw will also send null data */ + /* which we cannot control when Fw LPS enable. */ + /* --> default enable non-Qos data sequense number. 2010.06.23. by tynli. */ + /* (2) Enable HW SEQ control for beacon packet, because we use Hw beacon. */ + /* (3) Use HW Qos SEQ to control the seq num of Ext port non-Qos packets. */ + /* 2010.06.23. Added by tynli. */ + if (!pattrib->qos_en) { + ptxdesc->txdw3 |= cpu_to_le32(EN_HWSEQ); /* Hw set sequence number */ + ptxdesc->txdw4 |= cpu_to_le32(HW_SSN); /* Hw set sequence number */ + } + + ODM_SetTxAntByTxInfo_88E(&haldata->odmpriv, pmem, pattrib->mac_id); + + rtl8188eu_cal_txdesc_chksum(ptxdesc); + return pull; +} + +/* for non-agg data frame or management frame */ +static s32 rtw_dump_xframe(struct adapter *adapt, struct xmit_frame *pxmitframe) +{ + s32 ret = _SUCCESS; + s32 inner_ret = _SUCCESS; + int t, sz, w_sz, pull = 0; + u8 *mem_addr; + u32 ff_hwaddr; + struct xmit_buf *pxmitbuf = pxmitframe->pxmitbuf; + struct pkt_attrib *pattrib = &pxmitframe->attrib; + struct xmit_priv *pxmitpriv = &adapt->xmitpriv; + struct security_priv *psecuritypriv = &adapt->securitypriv; + if ((pxmitframe->frame_tag == DATA_FRAMETAG) && + (pxmitframe->attrib.ether_type != 0x0806) && + (pxmitframe->attrib.ether_type != 0x888e) && + (pxmitframe->attrib.ether_type != 0x88b4) && + (pxmitframe->attrib.dhcp_pkt != 1)) + rtw_issue_addbareq_cmd(adapt, pxmitframe); + mem_addr = pxmitframe->buf_addr; + + for (t = 0; t < pattrib->nr_frags; t++) { + if (inner_ret != _SUCCESS && ret == _SUCCESS) + ret = _FAIL; + + if (t != (pattrib->nr_frags - 1)) { + sz = pxmitpriv->frag_len; + sz = sz - 4 - (psecuritypriv->sw_encrypt ? 0 : pattrib->icv_len); + } else { + /* no frag */ + sz = pattrib->last_txcmdsz; + } + + pull = update_txdesc(pxmitframe, mem_addr, sz, false); + + if (pull) { + mem_addr += PACKET_OFFSET_SZ; /* pull txdesc head */ + pxmitframe->buf_addr = mem_addr; + w_sz = sz + TXDESC_SIZE; + } else { + w_sz = sz + TXDESC_SIZE + PACKET_OFFSET_SZ; + } + ff_hwaddr = rtw_get_ff_hwaddr(pxmitframe); + + inner_ret = rtw_write_port(adapt, ff_hwaddr, w_sz, (unsigned char *)pxmitbuf); + + rtw_count_tx_stats(adapt, pxmitframe, sz); + + mem_addr += w_sz; + + mem_addr = PTR_ALIGN(mem_addr, 4); + } + + rtw_free_xmitframe(pxmitpriv, pxmitframe); + + if (ret != _SUCCESS) + rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_UNKNOWN); + + return ret; +} + +static u32 xmitframe_need_length(struct xmit_frame *pxmitframe) +{ + struct pkt_attrib *pattrib = &pxmitframe->attrib; + + u32 len = 0; + + /* no consider fragement */ + len = pattrib->hdrlen + pattrib->iv_len + + SNAP_SIZE + sizeof(u16) + + pattrib->pktlen + + ((pattrib->bswenc) ? pattrib->icv_len : 0); + + if (pattrib->encrypt == _TKIP_) + len += 8; + + return len; +} + +bool rtl8188eu_xmitframe_complete(struct adapter *adapt, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf) +{ + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapt); + struct xmit_frame *pxmitframe = NULL; + struct xmit_frame *pfirstframe = NULL; + + /* aggregate variable */ + struct hw_xmit *phwxmit; + struct sta_info *psta = NULL; + struct tx_servq *ptxservq = NULL; + struct list_head *xmitframe_plist = NULL, *xmitframe_phead = NULL; + + u32 pbuf; /* next pkt address */ + u32 pbuf_tail; /* last pkt tail */ + u32 len; /* packet length, except TXDESC_SIZE and PKT_OFFSET */ + + u32 bulksize; + u8 desc_cnt; + u32 bulkptr; + + /* dump frame variable */ + u32 ff_hwaddr; + + if (pdvobjpriv->pusbdev->speed == USB_SPEED_HIGH) + bulksize = USB_HIGH_SPEED_BULK_SIZE; + else + bulksize = USB_FULL_SPEED_BULK_SIZE; + + /* check xmitbuffer is ok */ + if (!pxmitbuf) { + pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv); + if (!pxmitbuf) + return false; + } + + /* 3 1. pick up first frame */ + rtw_free_xmitframe(pxmitpriv, pxmitframe); + + pxmitframe = rtw_dequeue_xframe(pxmitpriv, pxmitpriv->hwxmits, pxmitpriv->hwxmit_entry); + if (!pxmitframe) { + /* no more xmit frame, release xmit buffer */ + rtw_free_xmitbuf(pxmitpriv, pxmitbuf); + return false; + } + + pxmitframe->pxmitbuf = pxmitbuf; + pxmitframe->buf_addr = pxmitbuf->pbuf; + pxmitbuf->priv_data = pxmitframe; + + pxmitframe->agg_num = 1; /* alloc xmitframe should assign to 1. */ + pxmitframe->pkt_offset = 1; /* first frame of aggregation, reserve offset */ + + rtw_xmitframe_coalesce(adapt, pxmitframe->pkt, pxmitframe); + + /* always return ndis_packet after rtw_xmitframe_coalesce */ + rtw_xmit_complete(adapt, pxmitframe); + + /* 3 2. aggregate same priority and same DA(AP or STA) frames */ + pfirstframe = pxmitframe; + len = xmitframe_need_length(pfirstframe) + TXDESC_SIZE + (pfirstframe->pkt_offset * PACKET_OFFSET_SZ); + pbuf_tail = len; + pbuf = round_up(pbuf_tail, 8); + + /* check pkt amount in one bulk */ + desc_cnt = 0; + bulkptr = bulksize; + if (pbuf < bulkptr) { + desc_cnt++; + } else { + desc_cnt = 0; + bulkptr = ((pbuf / bulksize) + 1) * bulksize; /* round to next bulksize */ + } + + /* dequeue same priority packet from station tx queue */ + psta = pfirstframe->attrib.psta; + switch (pfirstframe->attrib.priority) { + case 1: + case 2: + ptxservq = &psta->sta_xmitpriv.bk_q; + phwxmit = pxmitpriv->hwxmits + 3; + break; + case 4: + case 5: + ptxservq = &psta->sta_xmitpriv.vi_q; + phwxmit = pxmitpriv->hwxmits + 1; + break; + case 6: + case 7: + ptxservq = &psta->sta_xmitpriv.vo_q; + phwxmit = pxmitpriv->hwxmits; + break; + case 0: + case 3: + default: + ptxservq = &psta->sta_xmitpriv.be_q; + phwxmit = pxmitpriv->hwxmits + 2; + break; + } + spin_lock_bh(&pxmitpriv->lock); + + xmitframe_phead = get_list_head(&ptxservq->sta_pending); + xmitframe_plist = xmitframe_phead->next; + + while (xmitframe_phead != xmitframe_plist) { + pxmitframe = container_of(xmitframe_plist, struct xmit_frame, list); + xmitframe_plist = xmitframe_plist->next; + + pxmitframe->agg_num = 0; /* not first frame of aggregation */ + pxmitframe->pkt_offset = 0; /* not first frame of aggregation, no need to reserve offset */ + + len = xmitframe_need_length(pxmitframe) + TXDESC_SIZE + (pxmitframe->pkt_offset * PACKET_OFFSET_SZ); + + if (pbuf + len > MAX_XMITBUF_SZ) { + pxmitframe->agg_num = 1; + pxmitframe->pkt_offset = 1; + break; + } + list_del_init(&pxmitframe->list); + ptxservq->qcnt--; + phwxmit->accnt--; + + pxmitframe->buf_addr = pxmitbuf->pbuf + pbuf; + + rtw_xmitframe_coalesce(adapt, pxmitframe->pkt, pxmitframe); + /* always return ndis_packet after rtw_xmitframe_coalesce */ + rtw_xmit_complete(adapt, pxmitframe); + + /* (len - TXDESC_SIZE) == pxmitframe->attrib.last_txcmdsz */ + update_txdesc(pxmitframe, pxmitframe->buf_addr, pxmitframe->attrib.last_txcmdsz, true); + + /* don't need xmitframe any more */ + rtw_free_xmitframe(pxmitpriv, pxmitframe); + + /* handle pointer and stop condition */ + pbuf_tail = pbuf + len; + pbuf = round_up(pbuf_tail, 8); + + pfirstframe->agg_num++; + if (MAX_TX_AGG_PACKET_NUMBER == pfirstframe->agg_num) + break; + + if (pbuf < bulkptr) { + desc_cnt++; + if (desc_cnt == USB_TXAGG_DESC_NUM) + break; + } else { + desc_cnt = 0; + bulkptr = ((pbuf / bulksize) + 1) * bulksize; + } + } /* end while (aggregate same priority and same DA(AP or STA) frames) */ + + if (list_empty(&ptxservq->sta_pending.queue)) + list_del_init(&ptxservq->tx_pending); + + spin_unlock_bh(&pxmitpriv->lock); + if ((pfirstframe->attrib.ether_type != 0x0806) && + (pfirstframe->attrib.ether_type != 0x888e) && + (pfirstframe->attrib.ether_type != 0x88b4) && + (pfirstframe->attrib.dhcp_pkt != 1)) + rtw_issue_addbareq_cmd(adapt, pfirstframe); + /* 3 3. update first frame txdesc */ + if ((pbuf_tail % bulksize) == 0) { + /* remove pkt_offset */ + pbuf_tail -= PACKET_OFFSET_SZ; + pfirstframe->buf_addr += PACKET_OFFSET_SZ; + pfirstframe->pkt_offset--; + } + + update_txdesc(pfirstframe, pfirstframe->buf_addr, pfirstframe->attrib.last_txcmdsz, true); + + /* 3 4. write xmit buffer to USB FIFO */ + ff_hwaddr = rtw_get_ff_hwaddr(pfirstframe); + rtw_write_port(adapt, ff_hwaddr, pbuf_tail, (u8 *)pxmitbuf); + + /* 3 5. update statisitc */ + pbuf_tail -= (pfirstframe->agg_num * TXDESC_SIZE); + pbuf_tail -= (pfirstframe->pkt_offset * PACKET_OFFSET_SZ); + + rtw_count_tx_stats(adapt, pfirstframe, pbuf_tail); + + rtw_free_xmitframe(pxmitpriv, pfirstframe); + + return true; +} + +static s32 xmitframe_direct(struct adapter *adapt, struct xmit_frame *pxmitframe) +{ + s32 res = _SUCCESS; + + res = rtw_xmitframe_coalesce(adapt, pxmitframe->pkt, pxmitframe); + if (res == _SUCCESS) + rtw_dump_xframe(adapt, pxmitframe); + + return res; +} + +/* + * Return + * true dump packet directly + * false enqueue packet + */ +static s32 pre_xmitframe(struct adapter *adapt, struct xmit_frame *pxmitframe) +{ + s32 res; + struct xmit_buf *pxmitbuf = NULL; + struct xmit_priv *pxmitpriv = &adapt->xmitpriv; + struct pkt_attrib *pattrib = &pxmitframe->attrib; + struct mlme_priv *pmlmepriv = &adapt->mlmepriv; + + spin_lock_bh(&pxmitpriv->lock); + + if (rtw_txframes_sta_ac_pending(adapt, pattrib) > 0) + goto enqueue; + + if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY | _FW_UNDER_LINKING)) + goto enqueue; + + pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv); + if (!pxmitbuf) + goto enqueue; + + spin_unlock_bh(&pxmitpriv->lock); + + pxmitframe->pxmitbuf = pxmitbuf; + pxmitframe->buf_addr = pxmitbuf->pbuf; + pxmitbuf->priv_data = pxmitframe; + + if (xmitframe_direct(adapt, pxmitframe) != _SUCCESS) { + rtw_free_xmitbuf(pxmitpriv, pxmitbuf); + rtw_free_xmitframe(pxmitpriv, pxmitframe); + } + + return true; + +enqueue: + res = rtw_xmitframe_enqueue(adapt, pxmitframe); + spin_unlock_bh(&pxmitpriv->lock); + + if (res != _SUCCESS) { + rtw_free_xmitframe(pxmitpriv, pxmitframe); + + /* Trick, make the statistics correct */ + pxmitpriv->tx_pkts--; + pxmitpriv->tx_drop++; + return true; + } + + return false; +} + +s32 rtl8188eu_mgnt_xmit(struct adapter *adapt, struct xmit_frame *pmgntframe) +{ + return rtw_dump_xframe(adapt, pmgntframe); +} + +/* + * Return + * true dump packet directly ok + * false temporary can't transmit packets to hardware + */ +s32 rtl8188eu_hal_xmit(struct adapter *adapt, struct xmit_frame *pxmitframe) +{ + return pre_xmitframe(adapt, pxmitframe); +} diff --git a/drivers/staging/r8188eu/hal/usb_halinit.c b/drivers/staging/r8188eu/hal/usb_halinit.c new file mode 100644 index 000000000..d28b4dc2a --- /dev/null +++ b/drivers/staging/r8188eu/hal/usb_halinit.c @@ -0,0 +1,1076 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright(c) 2007 - 2011 Realtek Corporation. */ + +#define _HCI_HAL_INIT_C_ + +#include "../include/osdep_service.h" +#include "../include/drv_types.h" +#include "../include/rtw_efuse.h" +#include "../include/rtw_fw.h" +#include "../include/rtl8188e_hal.h" +#include "../include/rtw_iol.h" +#include "../include/usb_ops.h" +#include "../include/usb_osintf.h" +#include "../include/HalPwrSeqCmd.h" + +static void one_out_pipe(struct adapter *adapter) +{ + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapter); + + pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */ + pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */ + pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[0];/* BE */ + pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];/* BK */ +} + +static void two_out_pipe(struct adapter *adapter, bool wifi_cfg) +{ + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapter); + + /* 0:H, 1:L */ + + pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */ + pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];/* BE */ + + if (wifi_cfg) { + pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[1];/* VO */ + pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];/* BK */ + } else { + pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */ + pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */ + } +} + +static void three_out_pipe(struct adapter *adapter, bool wifi_cfg) +{ + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapter); + + /* 0:H, 1:N, 2:L */ + + pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */ + pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */ + pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */ + + pdvobjpriv->Queue2Pipe[3] = wifi_cfg ? + pdvobjpriv->RtOutPipe[1] : pdvobjpriv->RtOutPipe[2];/* BK */ +} + +int rtl8188eu_interface_configure(struct adapter *adapt) +{ + struct registry_priv *pregistrypriv = &adapt->registrypriv; + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapt); + struct hal_data_8188e *haldata = &adapt->haldata; + bool wifi_cfg = pregistrypriv->wifi_spec; + + pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */ + pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */ + pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */ + pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */ + + switch (pdvobjpriv->RtNumOutPipes) { + case 3: + haldata->out_ep_extra_queues = TX_SELE_LQ | TX_SELE_NQ; + three_out_pipe(adapt, wifi_cfg); + break; + case 2: + haldata->out_ep_extra_queues = TX_SELE_NQ; + two_out_pipe(adapt, wifi_cfg); + break; + case 1: + one_out_pipe(adapt); + break; + default: + return -ENXIO; + } + + return 0; +} + +u32 rtl8188eu_InitPowerOn(struct adapter *adapt) +{ + u16 value16; + int res; + + /* HW Power on sequence */ + struct hal_data_8188e *haldata = &adapt->haldata; + if (haldata->bMacPwrCtrlOn) + return _SUCCESS; + + if (!HalPwrSeqCmdParsing(adapt, PWR_ON_FLOW)) + return _FAIL; + + /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */ + /* Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31. */ + rtw_write16(adapt, REG_CR, 0x00); /* suggseted by zhouzhou, by page, 20111230 */ + + /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */ + res = rtw_read16(adapt, REG_CR, &value16); + if (res) + return _FAIL; + + value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN + | PROTOCOL_EN | SCHEDULE_EN | ENSEC | CALTMR_EN); + /* for SDIO - Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31. */ + + rtw_write16(adapt, REG_CR, value16); + haldata->bMacPwrCtrlOn = true; + + return _SUCCESS; +} + +/* Shall USB interface init this? */ +static void _InitInterrupt(struct adapter *Adapter) +{ + u32 imr, imr_ex; + u8 usb_opt; + int res; + + /* HISR write one to clear */ + rtw_write32(Adapter, REG_HISR_88E, 0xFFFFFFFF); + /* HIMR - */ + imr = IMR_PSTIMEOUT_88E | IMR_TBDER_88E | IMR_CPWM_88E | IMR_CPWM2_88E; + rtw_write32(Adapter, REG_HIMR_88E, imr); + + imr_ex = IMR_TXERR_88E | IMR_RXERR_88E | IMR_TXFOVW_88E | IMR_RXFOVW_88E; + rtw_write32(Adapter, REG_HIMRE_88E, imr_ex); + + /* REG_USB_SPECIAL_OPTION - BIT(4) */ + /* 0; Use interrupt endpoint to upload interrupt pkt */ + /* 1; Use bulk endpoint to upload interrupt pkt, */ + res = rtw_read8(Adapter, REG_USB_SPECIAL_OPTION, &usb_opt); + if (res) + return; + + if (adapter_to_dvobj(Adapter)->pusbdev->speed == USB_SPEED_HIGH) + usb_opt = usb_opt | (INT_BULK_SEL); + else + usb_opt = usb_opt & (~INT_BULK_SEL); + + rtw_write8(Adapter, REG_USB_SPECIAL_OPTION, usb_opt); +} + +static void _InitQueueReservedPage(struct adapter *Adapter) +{ + struct hal_data_8188e *haldata = &Adapter->haldata; + struct registry_priv *pregistrypriv = &Adapter->registrypriv; + u8 numLQ = 0; + u8 numNQ = 0; + u8 numPubQ; + + if (pregistrypriv->wifi_spec) { + if (haldata->out_ep_extra_queues & TX_SELE_LQ) + numLQ = 0x1C; + + /* NOTE: This step shall be proceed before writing REG_RQPN. */ + if (haldata->out_ep_extra_queues & TX_SELE_NQ) + numNQ = 0x1C; + + rtw_write8(Adapter, REG_RQPN_NPQ, numNQ); + + numPubQ = 0xA8 - NUM_HQ - numLQ - numNQ; + + /* TX DMA */ + rtw_write32(Adapter, REG_RQPN, LD_RQPN | numPubQ << 16 | numLQ << 8 | NUM_HQ); + } else { + rtw_write16(Adapter, REG_RQPN_NPQ, 0x0000);/* Just follow MP Team,??? Georgia 03/28 */ + rtw_write16(Adapter, REG_RQPN_NPQ, 0x0d); + rtw_write32(Adapter, REG_RQPN, 0x808E000d);/* reserve 7 page for LPS */ + } +} + +static void _InitTxBufferBoundary(struct adapter *Adapter, u8 txpktbuf_bndy) +{ + rtw_write8(Adapter, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); + rtw_write8(Adapter, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); + rtw_write8(Adapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy); + rtw_write8(Adapter, REG_TRXFF_BNDY, txpktbuf_bndy); + rtw_write8(Adapter, REG_TDECTRL + 1, txpktbuf_bndy); +} + +static void _InitPageBoundary(struct adapter *Adapter) +{ + /* RX Page Boundary */ + /* */ + u16 rxff_bndy = MAX_RX_DMA_BUFFER_SIZE_88E - 1; + + rtw_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy); +} + +static void _InitNormalChipRegPriority(struct adapter *Adapter, u16 beQ, + u16 bkQ, u16 viQ, u16 voQ, u16 mgtQ, + u16 hiQ) +{ + u16 value16; + int res; + + res = rtw_read16(Adapter, REG_TRXDMA_CTRL, &value16); + if (res) + return; + + value16 &= 0x7; + + value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) | + _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) | + _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ); + + rtw_write16(Adapter, REG_TRXDMA_CTRL, value16); +} + +static void _InitNormalChipTwoOutEpPriority(struct adapter *Adapter) +{ + struct registry_priv *pregistrypriv = &Adapter->registrypriv; + u16 bkQ, voQ; + + if (!pregistrypriv->wifi_spec) { + bkQ = QUEUE_NORMAL; + voQ = QUEUE_HIGH; + } else {/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */ + bkQ = QUEUE_HIGH; + voQ = QUEUE_NORMAL; + } + _InitNormalChipRegPriority(Adapter, QUEUE_NORMAL, bkQ, QUEUE_HIGH, + voQ, QUEUE_HIGH, QUEUE_HIGH); +} + +static void _InitNormalChipThreeOutEpPriority(struct adapter *Adapter) +{ + struct registry_priv *pregistrypriv = &Adapter->registrypriv; + u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ; + + if (!pregistrypriv->wifi_spec) {/* typical setting */ + beQ = QUEUE_LOW; + bkQ = QUEUE_LOW; + viQ = QUEUE_NORMAL; + voQ = QUEUE_HIGH; + mgtQ = QUEUE_HIGH; + hiQ = QUEUE_HIGH; + } else {/* for WMM */ + beQ = QUEUE_LOW; + bkQ = QUEUE_NORMAL; + viQ = QUEUE_NORMAL; + voQ = QUEUE_HIGH; + mgtQ = QUEUE_HIGH; + hiQ = QUEUE_HIGH; + } + _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ); +} + +static void _InitQueuePriority(struct adapter *Adapter) +{ + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter); + + switch (pdvobjpriv->RtNumOutPipes) { + case 1: + _InitNormalChipRegPriority(Adapter, QUEUE_HIGH, QUEUE_HIGH, QUEUE_HIGH, + QUEUE_HIGH, QUEUE_HIGH, QUEUE_HIGH); + break; + case 2: + _InitNormalChipTwoOutEpPriority(Adapter); + break; + case 3: + _InitNormalChipThreeOutEpPriority(Adapter); + break; + default: + break; + } +} + +static void _InitNetworkType(struct adapter *Adapter) +{ + u32 value32; + int res; + + res = rtw_read32(Adapter, REG_CR, &value32); + if (res) + return; + + /* TODO: use the other function to set network type */ + value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP); + + rtw_write32(Adapter, REG_CR, value32); +} + +static void _InitTransferPageSize(struct adapter *Adapter) +{ + /* Tx page size is always 128. */ + + u8 value8; + value8 = _PSRX(PBP_128) | _PSTX(PBP_128); + rtw_write8(Adapter, REG_PBP, value8); +} + +static void _InitDriverInfoSize(struct adapter *Adapter, u8 drvInfoSize) +{ + rtw_write8(Adapter, REG_RX_DRVINFO_SZ, drvInfoSize); +} + +static void _InitWMACSetting(struct adapter *Adapter) +{ + u32 receive_config = RCR_AAP | RCR_APM | RCR_AM | RCR_AB | + RCR_CBSSID_DATA | RCR_CBSSID_BCN | + RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | + RCR_APP_MIC | RCR_APP_PHYSTS; + + /* some REG_RCR will be modified later by phy_ConfigMACWithHeaderFile() */ + rtw_write32(Adapter, REG_RCR, receive_config); + + /* Accept all multicast address */ + rtw_write32(Adapter, REG_MAR, 0xFFFFFFFF); + rtw_write32(Adapter, REG_MAR + 4, 0xFFFFFFFF); +} + +static void _InitAdaptiveCtrl(struct adapter *Adapter) +{ + u16 value16; + u32 value32; + int res; + + /* Response Rate Set */ + res = rtw_read32(Adapter, REG_RRSR, &value32); + if (res) + return; + + value32 &= ~RATE_BITMAP_ALL; + value32 |= RATE_RRSR_CCK_ONLY_1M; + rtw_write32(Adapter, REG_RRSR, value32); + + /* CF-END Threshold */ + + /* SIFS (used in NAV) */ + value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10); + rtw_write16(Adapter, REG_SPEC_SIFS, value16); + + /* Retry Limit */ + value16 = _LRL(0x30) | _SRL(0x30); + rtw_write16(Adapter, REG_RL, value16); +} + +static void _InitEDCA(struct adapter *Adapter) +{ + /* Set Spec SIFS (used in NAV) */ + rtw_write16(Adapter, REG_SPEC_SIFS, 0x100a); + rtw_write16(Adapter, REG_MAC_SPEC_SIFS, 0x100a); + + /* Set SIFS for CCK */ + rtw_write16(Adapter, REG_SIFS_CTX, 0x100a); + + /* Set SIFS for OFDM */ + rtw_write16(Adapter, REG_SIFS_TRX, 0x100a); + + /* TXOP */ + rtw_write32(Adapter, REG_EDCA_BE_PARAM, 0x005EA42B); + rtw_write32(Adapter, REG_EDCA_BK_PARAM, 0x0000A44F); + rtw_write32(Adapter, REG_EDCA_VI_PARAM, 0x005EA324); + rtw_write32(Adapter, REG_EDCA_VO_PARAM, 0x002FA226); +} + +static void _InitRetryFunction(struct adapter *Adapter) +{ + u8 value8; + int res; + + res = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL, &value8); + if (res) + return; + + value8 |= EN_AMPDU_RTY_NEW; + rtw_write8(Adapter, REG_FWHW_TXQ_CTRL, value8); + + /* Set ACK timeout */ + rtw_write8(Adapter, REG_ACKTO, 0x40); +} + +/*----------------------------------------------------------------------------- + * Function: usb_AggSettingTxUpdate() + * + * Overview: Separate TX/RX parameters update independent for TP detection and + * dynamic TX/RX aggreagtion parameters update. + * + * Input: struct adapter * + * + * Output/Return: NONE + * + * Revised History: + * When Who Remark + * 12/10/2010 MHC Separate to smaller function. + * + *---------------------------------------------------------------------------*/ +static void usb_AggSettingTxUpdate(struct adapter *Adapter) +{ + u32 value32; + int res; + + if (Adapter->registrypriv.wifi_spec) + return; + + res = rtw_read32(Adapter, REG_TDECTRL, &value32); + if (res) + return; + + value32 = value32 & ~(BLK_DESC_NUM_MASK << BLK_DESC_NUM_SHIFT); + value32 |= ((USB_TXAGG_DESC_NUM & BLK_DESC_NUM_MASK) << BLK_DESC_NUM_SHIFT); + + rtw_write32(Adapter, REG_TDECTRL, value32); +} + +/*----------------------------------------------------------------------------- + * Function: usb_AggSettingRxUpdate() + * + * Overview: Separate TX/RX parameters update independent for TP detection and + * dynamic TX/RX aggreagtion parameters update. + * + * Input: struct adapter * + * + * Output/Return: NONE + * + * Revised History: + * When Who Remark + * 12/10/2010 MHC Separate to smaller function. + * + *---------------------------------------------------------------------------*/ +static void +usb_AggSettingRxUpdate( + struct adapter *Adapter + ) +{ + u8 valueDMA; + u8 valueUSB; + int res; + + res = rtw_read8(Adapter, REG_TRXDMA_CTRL, &valueDMA); + if (res) + return; + + res = rtw_read8(Adapter, REG_USB_SPECIAL_OPTION, &valueUSB); + if (res) + return; + + valueDMA |= RXDMA_AGG_EN; + valueUSB &= ~USB_AGG_EN; + + rtw_write8(Adapter, REG_TRXDMA_CTRL, valueDMA); + rtw_write8(Adapter, REG_USB_SPECIAL_OPTION, valueUSB); + + rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, USB_RXAGG_PAGE_COUNT); + rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH + 1, USB_RXAGG_PAGE_TIMEOUT); +} + +static void InitUsbAggregationSetting(struct adapter *Adapter) +{ + /* Tx aggregation setting */ + usb_AggSettingTxUpdate(Adapter); + + /* Rx aggregation setting */ + usb_AggSettingRxUpdate(Adapter); +} + +/* FIXME: add error handling in callers */ +static int _InitBeaconParameters(struct adapter *Adapter) +{ + struct hal_data_8188e *haldata = &Adapter->haldata; + int res; + + rtw_write16(Adapter, REG_BCN_CTRL, 0x1010); + + /* TODO: Remove these magic number */ + rtw_write16(Adapter, REG_TBTT_PROHIBIT, 0x6404);/* ms */ + rtw_write8(Adapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);/* 5ms */ + rtw_write8(Adapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME); /* 2ms */ + + /* Suggested by designer timchen. Change beacon AIFS to the largest number */ + /* beacause test chip does not contension before sending beacon. by tynli. 2009.11.03 */ + rtw_write16(Adapter, REG_BCNTCFG, 0x660F); + + res = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL + 2, &haldata->RegFwHwTxQCtrl); + if (res) + return res; + + res = rtw_read8(Adapter, REG_TBTT_PROHIBIT + 2, &haldata->RegReg542); + if (res) + return res; + + res = rtw_read8(Adapter, REG_CR + 1, &haldata->RegCR_1); + if (res) + return res; + + return 0; +} + +static void _BeaconFunctionEnable(struct adapter *Adapter) +{ + rtw_write8(Adapter, REG_BCN_CTRL, (BIT(4) | BIT(3) | BIT(1))); + + rtw_write8(Adapter, REG_RD_CTRL + 1, 0x6F); +} + +/* Set CCK and OFDM Block "ON" */ +static void _BBTurnOnBlock(struct adapter *Adapter) +{ + rtl8188e_PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1); + rtl8188e_PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1); +} + +static void _InitAntenna_Selection(struct adapter *Adapter) +{ + struct hal_data_8188e *haldata = &Adapter->haldata; + int res; + u32 reg; + + if (haldata->AntDivCfg == 0) + return; + + res = rtw_read32(Adapter, REG_LEDCFG0, ®); + if (res) + return; + + rtw_write32(Adapter, REG_LEDCFG0, reg | BIT(23)); + rtl8188e_PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, BIT(13), 0x01); + + if (rtl8188e_PHY_QueryBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300) == Antenna_A) + haldata->CurAntenna = Antenna_A; + else + haldata->CurAntenna = Antenna_B; +} + +static void hw_var_set_macaddr(struct adapter *Adapter, u8 *val) +{ + u8 idx = 0; + u32 reg_macid; + + reg_macid = REG_MACID; + + for (idx = 0; idx < 6; idx++) + rtw_write8(Adapter, (reg_macid + idx), val[idx]); +} + +u32 rtl8188eu_hal_init(struct adapter *Adapter) +{ + u8 value8 = 0; + u16 value16; + u32 status = _SUCCESS; + int res; + struct hal_data_8188e *haldata = &Adapter->haldata; + struct pwrctrl_priv *pwrctrlpriv = &Adapter->pwrctrlpriv; + struct registry_priv *pregistrypriv = &Adapter->registrypriv; + u32 reg; + + if (Adapter->pwrctrlpriv.bkeepfwalive) { + if (haldata->odmpriv.RFCalibrateInfo.bIQKInitialized) { + PHY_IQCalibrate_8188E(Adapter, true); + } else { + PHY_IQCalibrate_8188E(Adapter, false); + haldata->odmpriv.RFCalibrateInfo.bIQKInitialized = true; + } + + ODM_TXPowerTrackingCheck(&haldata->odmpriv); + PHY_LCCalibrate_8188E(Adapter); + + goto exit; + } + + status = rtl8188eu_InitPowerOn(Adapter); + if (status == _FAIL) + goto exit; + + /* Save target channel */ + haldata->CurrentChannel = 6;/* default set to 6 */ + + /* 2010/08/09 MH We need to check if we need to turnon or off RF after detecting */ + /* HW GPIO pin. Before PHY_RFConfig8192C. */ + /* 2010/08/26 MH If Efuse does not support sective suspend then disable the function. */ + + _InitQueueReservedPage(Adapter); + _InitQueuePriority(Adapter); + _InitPageBoundary(Adapter); + _InitTransferPageSize(Adapter); + + _InitTxBufferBoundary(Adapter, 0); + + status = rtl8188e_firmware_download(Adapter); + + if (status != _SUCCESS) { + Adapter->bFWReady = false; + haldata->fw_ractrl = false; + return status; + } else { + Adapter->bFWReady = true; + haldata->fw_ractrl = false; + } + /* Initialize firmware vars */ + Adapter->pwrctrlpriv.bFwCurrentInPSMode = false; + haldata->LastHMEBoxNum = 0; + + status = PHY_MACConfig8188E(Adapter); + if (status == _FAIL) + goto exit; + + /* */ + /* d. Initialize BB related configurations. */ + /* */ + status = PHY_BBConfig8188E(Adapter); + if (status == _FAIL) + goto exit; + + status = phy_RF6052_Config_ParaFile(Adapter); + if (status == _FAIL) + goto exit; + + status = rtl8188e_iol_efuse_patch(Adapter); + if (status == _FAIL) + goto exit; + + _InitTxBufferBoundary(Adapter, TX_PAGE_BOUNDARY_88E); + + status = InitLLTTable(Adapter, TX_PAGE_BOUNDARY_88E); + if (status == _FAIL) + goto exit; + + /* Get Rx PHY status in order to report RSSI and others. */ + _InitDriverInfoSize(Adapter, DRVINFO_SZ); + + _InitInterrupt(Adapter); + hw_var_set_macaddr(Adapter, Adapter->eeprompriv.mac_addr); + _InitNetworkType(Adapter);/* set msr */ + _InitWMACSetting(Adapter); + _InitAdaptiveCtrl(Adapter); + _InitEDCA(Adapter); + _InitRetryFunction(Adapter); + InitUsbAggregationSetting(Adapter); + _InitBeaconParameters(Adapter); + + /* */ + /* Init CR MACTXEN, MACRXEN after setting RxFF boundary REG_TRXFF_BNDY to patch */ + /* Hw bug which Hw initials RxFF boundary size to a value which is larger than the real Rx buffer size in 88E. */ + /* */ + /* Enable MACTXEN/MACRXEN block */ + res = rtw_read16(Adapter, REG_CR, &value16); + if (res) + return _FAIL; + + value16 |= (MACTXEN | MACRXEN); + rtw_write8(Adapter, REG_CR, value16); + + /* Enable TX Report */ + /* Enable Tx Report Timer */ + res = rtw_read8(Adapter, REG_TX_RPT_CTRL, &value8); + if (res) + return _FAIL; + + rtw_write8(Adapter, REG_TX_RPT_CTRL, (value8 | BIT(1) | BIT(0))); + /* Set MAX RPT MACID */ + rtw_write8(Adapter, REG_TX_RPT_CTRL + 1, 2);/* FOR sta mode ,0: bc/mc ,1:AP */ + /* Tx RPT Timer. Unit: 32us */ + rtw_write16(Adapter, REG_TX_RPT_TIME, 0xCdf0); + + rtw_write8(Adapter, REG_EARLY_MODE_CONTROL, 0); + + rtw_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */ + rtw_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */ + + /* Keep RfRegChnlVal for later use. */ + haldata->RfRegChnlVal = rtl8188e_PHY_QueryRFReg(Adapter, RF_CHNLBW, bRFRegOffsetMask); + + _BBTurnOnBlock(Adapter); + + invalidate_cam_all(Adapter); + + /* 2010/12/17 MH We need to set TX power according to EFUSE content at first. */ + PHY_SetTxPowerLevel8188E(Adapter, haldata->CurrentChannel); + +/* Move by Neo for USB SS to below setp */ +/* _RfPowerSave(Adapter); */ + + _InitAntenna_Selection(Adapter); + + /* */ + /* Disable BAR, suggested by Scott */ + /* 2010.04.09 add by hpfan */ + /* */ + rtw_write32(Adapter, REG_BAR_MODE_CTRL, 0x0201ffff); + + /* HW SEQ CTRL */ + /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */ + rtw_write8(Adapter, REG_HWSEQ_CTRL, 0xFF); + + if (pregistrypriv->wifi_spec) + rtw_write16(Adapter, REG_FAST_EDCA_CTRL, 0); + + /* Nav limit , suggest by scott */ + rtw_write8(Adapter, 0x652, 0x0); + + rtl8188e_InitHalDm(Adapter); + + /* 2010/08/11 MH Merge from 8192SE for Minicard init. We need to confirm current radio status */ + /* and then decide to enable RF or not.!!!??? For Selective suspend mode. We may not */ + /* call initstruct adapter. May cause some problem?? */ + /* Fix the bug that Hw/Sw radio off before S3/S4, the RF off action will not be executed */ + /* in MgntActSet_RF_State() after wake up, because the value of haldata->eRFPowerState */ + /* is the same as eRfOff, we should change it to eRfOn after we config RF parameters. */ + /* Added by tynli. 2010.03.30. */ + pwrctrlpriv->rf_pwrstate = rf_on; + + /* enable Tx report. */ + rtw_write8(Adapter, REG_FWHW_TXQ_CTRL + 1, 0x0F); + + /* Suggested by SD1 pisa. Added by tynli. 2011.10.21. */ + rtw_write8(Adapter, REG_EARLY_MODE_CONTROL + 3, 0x01);/* Pretx_en, for WEP/TKIP SEC */ + + /* tynli_test_tx_report. */ + rtw_write16(Adapter, REG_TX_RPT_TIME, 0x3DF0); + + /* enable tx DMA to drop the redundate data of packet */ + res = rtw_read16(Adapter, REG_TXDMA_OFFSET_CHK, &value16); + if (res) + return _FAIL; + + rtw_write16(Adapter, REG_TXDMA_OFFSET_CHK, (value16 | DROP_DATA_EN)); + + /* 2010/08/26 MH Merge from 8192CE. */ + if (pwrctrlpriv->rf_pwrstate == rf_on) { + if (haldata->odmpriv.RFCalibrateInfo.bIQKInitialized) { + PHY_IQCalibrate_8188E(Adapter, true); + } else { + PHY_IQCalibrate_8188E(Adapter, false); + haldata->odmpriv.RFCalibrateInfo.bIQKInitialized = true; + } + + ODM_TXPowerTrackingCheck(&haldata->odmpriv); + + PHY_LCCalibrate_8188E(Adapter); + } + +/* _InitPABias(Adapter); */ + rtw_write8(Adapter, REG_USB_HRPWM, 0); + + /* ack for xmit mgmt frames. */ + res = rtw_read32(Adapter, REG_FWHW_TXQ_CTRL, ®); + if (res) + return _FAIL; + + rtw_write32(Adapter, REG_FWHW_TXQ_CTRL, reg | BIT(12)); + +exit: + return status; +} + +static void CardDisableRTL8188EU(struct adapter *Adapter) +{ + u8 val8; + struct hal_data_8188e *haldata = &Adapter->haldata; + int res; + + /* Stop Tx Report Timer. 0x4EC[Bit1]=b'0 */ + res = rtw_read8(Adapter, REG_TX_RPT_CTRL, &val8); + if (res) + return; + + rtw_write8(Adapter, REG_TX_RPT_CTRL, val8 & (~BIT(1))); + + /* stop rx */ + rtw_write8(Adapter, REG_CR, 0x0); + + /* Run LPS WL RFOFF flow */ + HalPwrSeqCmdParsing(Adapter, LPS_ENTER_FLOW); + + /* 2. 0x1F[7:0] = 0 turn off RF */ + + res = rtw_read8(Adapter, REG_MCUFWDL, &val8); + if (res) + return; + + if ((val8 & RAM_DL_SEL) && Adapter->bFWReady) { /* 8051 RAM code */ + /* Reset MCU 0x2[10]=0. */ + res = rtw_read8(Adapter, REG_SYS_FUNC_EN + 1, &val8); + if (res) + return; + + val8 &= ~BIT(2); /* 0x2[10], FEN_CPUEN */ + rtw_write8(Adapter, REG_SYS_FUNC_EN + 1, val8); + } + + /* reset MCU ready status */ + rtw_write8(Adapter, REG_MCUFWDL, 0); + + /* YJ,add,111212 */ + /* Disable 32k */ + res = rtw_read8(Adapter, REG_32K_CTRL, &val8); + if (res) + return; + + rtw_write8(Adapter, REG_32K_CTRL, val8 & (~BIT(0))); + + /* Card disable power action flow */ + HalPwrSeqCmdParsing(Adapter, DISABLE_FLOW); + + /* Reset MCU IO Wrapper */ + res = rtw_read8(Adapter, REG_RSV_CTRL + 1, &val8); + if (res) + return; + + rtw_write8(Adapter, REG_RSV_CTRL + 1, (val8 & (~BIT(3)))); + + res = rtw_read8(Adapter, REG_RSV_CTRL + 1, &val8); + if (res) + return; + + rtw_write8(Adapter, REG_RSV_CTRL + 1, val8 | BIT(3)); + + /* YJ,test add, 111207. For Power Consumption. */ + res = rtw_read8(Adapter, GPIO_IN, &val8); + if (res) + return; + + rtw_write8(Adapter, GPIO_OUT, val8); + rtw_write8(Adapter, GPIO_IO_SEL, 0xFF);/* Reg0x46 */ + + res = rtw_read8(Adapter, REG_GPIO_IO_SEL, &val8); + if (res) + return; + + rtw_write8(Adapter, REG_GPIO_IO_SEL, (val8 << 4)); + res = rtw_read8(Adapter, REG_GPIO_IO_SEL + 1, &val8); + if (res) + return; + + rtw_write8(Adapter, REG_GPIO_IO_SEL + 1, val8 | 0x0F);/* Reg0x43 */ + rtw_write32(Adapter, REG_BB_PAD_CTRL, 0x00080808);/* set LNA ,TRSW,EX_PA Pin to output mode */ + haldata->bMacPwrCtrlOn = false; + Adapter->bFWReady = false; +} + +u32 rtl8188eu_hal_deinit(struct adapter *Adapter) +{ + rtw_write32(Adapter, REG_HIMR_88E, IMR_DISABLED_88E); + rtw_write32(Adapter, REG_HIMRE_88E, IMR_DISABLED_88E); + + if (!Adapter->pwrctrlpriv.bkeepfwalive) { + if (Adapter->hw_init_completed) { + CardDisableRTL8188EU(Adapter); + } + } + return _SUCCESS; + } + +unsigned int rtl8188eu_inirp_init(struct adapter *Adapter) +{ + u8 i; + struct recv_buf *precvbuf; + uint status; + struct recv_priv *precvpriv = &Adapter->recvpriv; + + status = _SUCCESS; + + /* issue Rx irp to receive data */ + precvbuf = (struct recv_buf *)precvpriv->precv_buf; + for (i = 0; i < NR_RECVBUFF; i++) { + if (!rtw_read_port(Adapter, (unsigned char *)precvbuf)) { + status = _FAIL; + goto exit; + } + + precvbuf++; + precvpriv->free_recv_buf_queue_cnt--; + } + +exit: + return status; +} + +/* */ +/* */ +/* EEPROM/EFUSE Content Parsing */ +/* */ +/* */ + +static void Hal_EfuseParseMACAddr_8188EU(struct adapter *adapt, u8 *hwinfo, bool AutoLoadFail) +{ + struct eeprom_priv *eeprom = &adapt->eeprompriv; + + if (AutoLoadFail) { + eth_random_addr(eeprom->mac_addr); + } else { + /* Read Permanent MAC address */ + memcpy(eeprom->mac_addr, &hwinfo[EEPROM_MAC_ADDR_88EU], ETH_ALEN); + } +} + +int ReadAdapterInfo8188EU(struct adapter *Adapter) +{ + struct eeprom_priv *eeprom = &Adapter->eeprompriv; + struct led_priv *ledpriv = &Adapter->ledpriv; + u8 *efuse_buf; + u8 eeValue; + int res; + + /* check system boot selection */ + res = rtw_read8(Adapter, REG_9346CR, &eeValue); + if (res) + return res; + + eeprom->bautoload_fail_flag = !(eeValue & EEPROM_EN); + + efuse_buf = kmalloc(EFUSE_MAP_LEN_88E, GFP_KERNEL); + if (!efuse_buf) + return -ENOMEM; + memset(efuse_buf, 0xFF, EFUSE_MAP_LEN_88E); + + if (!(eeValue & BOOT_FROM_EEPROM) && !eeprom->bautoload_fail_flag) { + rtl8188e_EfusePowerSwitch(Adapter, true); + rtl8188e_ReadEFuse(Adapter, EFUSE_MAP_LEN_88E, efuse_buf); + rtl8188e_EfusePowerSwitch(Adapter, false); + } + + /* parse the eeprom/efuse content */ + Hal_EfuseParseIDCode88E(Adapter, efuse_buf); + Hal_EfuseParseMACAddr_8188EU(Adapter, efuse_buf, eeprom->bautoload_fail_flag); + + Hal_ReadPowerSavingMode88E(Adapter, efuse_buf, eeprom->bautoload_fail_flag); + Hal_ReadTxPowerInfo88E(Adapter, efuse_buf, eeprom->bautoload_fail_flag); + rtl8188e_EfuseParseChnlPlan(Adapter, efuse_buf, eeprom->bautoload_fail_flag); + Hal_EfuseParseXtal_8188E(Adapter, efuse_buf, eeprom->bautoload_fail_flag); + Hal_ReadAntennaDiversity88E(Adapter, efuse_buf, eeprom->bautoload_fail_flag); + Hal_ReadThermalMeter_88E(Adapter, efuse_buf, eeprom->bautoload_fail_flag); + + ledpriv->bRegUseLed = true; + kfree(efuse_buf); + return 0; +} + +void UpdateHalRAMask8188EUsb(struct adapter *adapt, u32 mac_id, u8 rssi_level) +{ + u8 init_rate = 0; + u8 networkType, raid; + u32 mask, rate_bitmap; + u8 shortGIrate = false; + int supportRateNum = 0; + struct sta_info *psta; + struct hal_data_8188e *haldata = &adapt->haldata; + struct mlme_ext_priv *pmlmeext = &adapt->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + struct wlan_bssid_ex *cur_network = &pmlmeinfo->network; + + if (mac_id >= NUM_STA) /* CAM_SIZE */ + return; + psta = pmlmeinfo->FW_sta_info[mac_id].psta; + if (!psta) + return; + switch (mac_id) { + case 0:/* for infra mode */ + supportRateNum = rtw_get_rateset_len(cur_network->SupportedRates); + networkType = judge_network_type(adapt, cur_network->SupportedRates, supportRateNum) & 0xf; + raid = networktype_to_raid(networkType); + mask = update_supported_rate(cur_network->SupportedRates, supportRateNum); + mask |= (pmlmeinfo->HT_enable) ? update_MSC_rate(&pmlmeinfo->HT_caps) : 0; + if (support_short_GI(adapt, &pmlmeinfo->HT_caps)) + shortGIrate = true; + break; + case 1:/* for broadcast/multicast */ + supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates); + if (pmlmeext->cur_wireless_mode & WIRELESS_11B) + networkType = WIRELESS_11B; + else + networkType = WIRELESS_11G; + raid = networktype_to_raid(networkType); + mask = update_basic_rate(cur_network->SupportedRates, supportRateNum); + break; + default: /* for each sta in IBSS */ + supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates); + networkType = judge_network_type(adapt, pmlmeinfo->FW_sta_info[mac_id].SupportedRates, supportRateNum) & 0xf; + raid = networktype_to_raid(networkType); + mask = update_supported_rate(cur_network->SupportedRates, supportRateNum); + + /* todo: support HT in IBSS */ + break; + } + + rate_bitmap = 0x0fffffff; + rate_bitmap = ODM_Get_Rate_Bitmap(&haldata->odmpriv, mac_id, mask, rssi_level); + + mask &= rate_bitmap; + + init_rate = get_highest_rate_idx(mask) & 0x3f; + + if (haldata->fw_ractrl) { + mask |= ((raid << 28) & 0xf0000000); + psta->ra_mask = mask; + mask |= ((raid << 28) & 0xf0000000); + + /* to do ,for 8188E-SMIC */ + rtl8188e_set_raid_cmd(adapt, mask); + } else { + ODM_RA_UpdateRateInfo_8188E(&haldata->odmpriv, + mac_id, + raid, + mask, + shortGIrate + ); + } + /* set ra_id */ + psta->raid = raid; + psta->init_rate = init_rate; +} + +void SetBeaconRelatedRegisters8188EUsb(struct adapter *adapt) +{ + u32 value32; + struct mlme_ext_priv *pmlmeext = &adapt->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + u32 bcn_ctrl_reg = REG_BCN_CTRL; + int res; + u8 reg; + /* reset TSF, enable update TSF, correcting TSF On Beacon */ + + /* BCN interval */ + rtw_write16(adapt, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval); + rtw_write8(adapt, REG_ATIMWND, 0x02);/* 2ms */ + + _InitBeaconParameters(adapt); + + rtw_write8(adapt, REG_SLOT, 0x09); + + res = rtw_read32(adapt, REG_TCR, &value32); + if (res) + return; + + value32 &= ~TSFRST; + rtw_write32(adapt, REG_TCR, value32); + + value32 |= TSFRST; + rtw_write32(adapt, REG_TCR, value32); + + /* NOTE: Fix test chip's bug (about contention windows's randomness) */ + rtw_write8(adapt, REG_RXTSF_OFFSET_CCK, 0x50); + rtw_write8(adapt, REG_RXTSF_OFFSET_OFDM, 0x50); + + _BeaconFunctionEnable(adapt); + + rtw_resume_tx_beacon(adapt); + + res = rtw_read8(adapt, bcn_ctrl_reg, ®); + if (res) + return; + + rtw_write8(adapt, bcn_ctrl_reg, reg | BIT(1)); +} + +void rtl8188eu_init_default_value(struct adapter *adapt) +{ + struct hal_data_8188e *haldata = &adapt->haldata; + struct pwrctrl_priv *pwrctrlpriv; + u8 i; + + pwrctrlpriv = &adapt->pwrctrlpriv; + + /* init default value */ + haldata->fw_ractrl = false; + if (!pwrctrlpriv->bkeepfwalive) + haldata->LastHMEBoxNum = 0; + + /* init dm default value */ + haldata->odmpriv.RFCalibrateInfo.bIQKInitialized = false; + haldata->odmpriv.RFCalibrateInfo.TM_Trigger = 0;/* for IQK */ + haldata->pwrGroupCnt = 0; + haldata->odmpriv.RFCalibrateInfo.ThermalValue_HP_index = 0; + for (i = 0; i < HP_THERMAL_NUM; i++) + haldata->odmpriv.RFCalibrateInfo.ThermalValue_HP[i] = 0; +} diff --git a/drivers/staging/r8188eu/hal/usb_ops_linux.c b/drivers/staging/r8188eu/hal/usb_ops_linux.c new file mode 100644 index 000000000..7c72f5e04 --- /dev/null +++ b/drivers/staging/r8188eu/hal/usb_ops_linux.c @@ -0,0 +1,502 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright(c) 2007 - 2011 Realtek Corporation. */ + +#include "../include/osdep_service.h" +#include "../include/drv_types.h" +#include "../include/osdep_intf.h" +#include "../include/usb_ops.h" +#include "../include/rtl8188e_hal.h" + +static int usb_read(struct intf_hdl *intf, u16 value, void *data, u8 size) +{ + struct adapter *adapt = intf->padapter; + struct dvobj_priv *dvobjpriv = adapter_to_dvobj(adapt); + struct usb_device *udev = dvobjpriv->pusbdev; + int status; + u8 io_buf[4]; + + if (adapt->bSurpriseRemoved) + return -EPERM; + + status = usb_control_msg_recv(udev, 0, REALTEK_USB_VENQT_CMD_REQ, + REALTEK_USB_VENQT_READ, value, + REALTEK_USB_VENQT_CMD_IDX, io_buf, + size, RTW_USB_CONTROL_MSG_TIMEOUT, + GFP_KERNEL); + + if (status == -ESHUTDOWN || + status == -ENODEV || + status == -ENOENT) { + /* + * device or controller has been disabled due to + * some problem that could not be worked around, + * device or bus doesn’t exist, endpoint does not + * exist or is not enabled. + */ + adapt->bSurpriseRemoved = true; + return status; + } + + if (status < 0) { + if (rtw_inc_and_chk_continual_urb_error(dvobjpriv)) + adapt->bSurpriseRemoved = true; + + return status; + } + + rtw_reset_continual_urb_error(dvobjpriv); + memcpy(data, io_buf, size); + + return status; +} + +static int usb_write(struct intf_hdl *intf, u16 value, void *data, u8 size) +{ + struct adapter *adapt = intf->padapter; + struct dvobj_priv *dvobjpriv = adapter_to_dvobj(adapt); + struct usb_device *udev = dvobjpriv->pusbdev; + int status; + u8 io_buf[VENDOR_CMD_MAX_DATA_LEN]; + + if (adapt->bSurpriseRemoved) + return -EPERM; + + memcpy(io_buf, data, size); + status = usb_control_msg_send(udev, 0, REALTEK_USB_VENQT_CMD_REQ, + REALTEK_USB_VENQT_WRITE, value, + REALTEK_USB_VENQT_CMD_IDX, io_buf, + size, RTW_USB_CONTROL_MSG_TIMEOUT, + GFP_KERNEL); + + if (status == -ESHUTDOWN || + status == -ENODEV || + status == -ENOENT) { + /* + * device or controller has been disabled due to + * some problem that could not be worked around, + * device or bus doesn’t exist, endpoint does not + * exist or is not enabled. + */ + adapt->bSurpriseRemoved = true; + return status; + } + + if (status < 0) { + if (rtw_inc_and_chk_continual_urb_error(dvobjpriv)) + adapt->bSurpriseRemoved = true; + + return status; + } + + rtw_reset_continual_urb_error(dvobjpriv); + + return status; +} + +int __must_check rtw_read8(struct adapter *adapter, u32 addr, u8 *data) +{ + struct io_priv *io_priv = &adapter->iopriv; + struct intf_hdl *intf = &io_priv->intf; + u16 value = addr & 0xffff; + + return usb_read(intf, value, data, 1); +} + +int __must_check rtw_read16(struct adapter *adapter, u32 addr, u16 *data) +{ + struct io_priv *io_priv = &adapter->iopriv; + struct intf_hdl *intf = &io_priv->intf; + u16 value = addr & 0xffff; + __le16 le_data; + int res; + + res = usb_read(intf, value, &le_data, 2); + if (res) + return res; + + *data = le16_to_cpu(le_data); + + return 0; +} + +int __must_check rtw_read32(struct adapter *adapter, u32 addr, u32 *data) +{ + struct io_priv *io_priv = &adapter->iopriv; + struct intf_hdl *intf = &io_priv->intf; + u16 value = addr & 0xffff; + __le32 le_data; + int res; + + res = usb_read(intf, value, &le_data, 4); + if (res) + return res; + + *data = le32_to_cpu(le_data); + + return 0; +} + +int rtw_write8(struct adapter *adapter, u32 addr, u8 val) +{ + struct io_priv *io_priv = &adapter->iopriv; + struct intf_hdl *intf = &io_priv->intf; + u16 value = addr & 0xffff; + int ret; + + ret = usb_write(intf, value, &val, 1); + + return RTW_STATUS_CODE(ret); +} + +int rtw_write16(struct adapter *adapter, u32 addr, u16 val) +{ + struct io_priv *io_priv = &adapter->iopriv; + struct intf_hdl *intf = &io_priv->intf; + u16 value = addr & 0xffff; + __le16 data = cpu_to_le16(val); + int ret; + + ret = usb_write(intf, value, &data, 2); + + return RTW_STATUS_CODE(ret); +} + +int rtw_write32(struct adapter *adapter, u32 addr, u32 val) +{ + struct io_priv *io_priv = &adapter->iopriv; + struct intf_hdl *intf = &io_priv->intf; + u16 value = addr & 0xffff; + __le32 data = cpu_to_le32(val); + int ret; + + ret = usb_write(intf, value, &data, 4); + + return RTW_STATUS_CODE(ret); +} + +int rtw_writeN(struct adapter *adapter, u32 addr, u32 length, u8 *data) +{ + struct io_priv *io_priv = &adapter->iopriv; + struct intf_hdl *intf = &io_priv->intf; + u16 value = addr & 0xffff; + int ret; + + if (length > VENDOR_CMD_MAX_DATA_LEN) + return _FAIL; + + ret = usb_write(intf, value, data, length); + + return RTW_STATUS_CODE(ret); +} + +static void handle_txrpt_ccx_88e(struct adapter *adapter, u8 *buf) +{ + struct txrpt_ccx_88e *txrpt_ccx = (struct txrpt_ccx_88e *)buf; + + if (txrpt_ccx->int_ccx) { + if (txrpt_ccx->pkt_ok) + rtw_ack_tx_done(&adapter->xmitpriv, + RTW_SCTX_DONE_SUCCESS); + else + rtw_ack_tx_done(&adapter->xmitpriv, + RTW_SCTX_DONE_CCX_PKT_FAIL); + } +} + +static int recvbuf2recvframe(struct adapter *adapt, struct sk_buff *pskb) +{ + u8 *pbuf; + u8 shift_sz = 0; + u16 pkt_cnt; + u32 pkt_offset, skb_len, alloc_sz; + s32 transfer_len; + struct recv_stat *prxstat; + struct phy_stat *pphy_status = NULL; + struct sk_buff *pkt_copy = NULL; + struct recv_frame *precvframe = NULL; + struct rx_pkt_attrib *pattrib = NULL; + struct hal_data_8188e *haldata = &adapt->haldata; + struct recv_priv *precvpriv = &adapt->recvpriv; + struct __queue *pfree_recv_queue = &precvpriv->free_recv_queue; + + transfer_len = (s32)pskb->len; + pbuf = pskb->data; + + prxstat = (struct recv_stat *)pbuf; + pkt_cnt = (le32_to_cpu(prxstat->rxdw2) >> 16) & 0xff; + + do { + prxstat = (struct recv_stat *)pbuf; + + precvframe = rtw_alloc_recvframe(pfree_recv_queue); + if (!precvframe) + goto _exit_recvbuf2recvframe; + + INIT_LIST_HEAD(&precvframe->list); + precvframe->precvbuf = NULL; /* can't access the precvbuf for new arch. */ + precvframe->len = 0; + + update_recvframe_attrib_88e(precvframe, prxstat); + + pattrib = &precvframe->attrib; + + if ((pattrib->crc_err) || (pattrib->icv_err)) { + rtw_free_recvframe(precvframe, pfree_recv_queue); + goto _exit_recvbuf2recvframe; + } + + if ((pattrib->physt) && (pattrib->pkt_rpt_type == NORMAL_RX)) + pphy_status = (struct phy_stat *)(pbuf + RXDESC_OFFSET); + + pkt_offset = RXDESC_SIZE + pattrib->drvinfo_sz + pattrib->shift_sz + pattrib->pkt_len; + + if ((pattrib->pkt_len <= 0) || (pkt_offset > transfer_len)) { + rtw_free_recvframe(precvframe, pfree_recv_queue); + goto _exit_recvbuf2recvframe; + } + + /* Modified by Albert 20101213 */ + /* For 8 bytes IP header alignment. */ + if (pattrib->qos) /* Qos data, wireless lan header length is 26 */ + shift_sz = 6; + else + shift_sz = 0; + + skb_len = pattrib->pkt_len; + + /* for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet. */ + /* modify alloc_sz for recvive crc error packet by thomas 2011-06-02 */ + if ((pattrib->mfrag == 1) && (pattrib->frag_num == 0)) { + if (skb_len <= 1650) + alloc_sz = 1664; + else + alloc_sz = skb_len + 14; + } else { + alloc_sz = skb_len; + /* 6 is for IP header 8 bytes alignment in QoS packet case. */ + /* 8 is for skb->data 4 bytes alignment. */ + alloc_sz += 14; + } + + pkt_copy = netdev_alloc_skb(adapt->pnetdev, alloc_sz); + if (pkt_copy) { + precvframe->pkt = pkt_copy; + precvframe->rx_head = pkt_copy->data; + precvframe->rx_end = pkt_copy->data + alloc_sz; + skb_reserve(pkt_copy, 8 - ((size_t)(pkt_copy->data) & 7));/* force pkt_copy->data at 8-byte alignment address */ + skb_reserve(pkt_copy, shift_sz);/* force ip_hdr at 8-byte alignment address according to shift_sz. */ + memcpy(pkt_copy->data, (pbuf + pattrib->drvinfo_sz + RXDESC_SIZE), skb_len); + precvframe->rx_tail = pkt_copy->data; + precvframe->rx_data = pkt_copy->data; + } else { + if ((pattrib->mfrag == 1) && (pattrib->frag_num == 0)) { + rtw_free_recvframe(precvframe, pfree_recv_queue); + goto _exit_recvbuf2recvframe; + } + precvframe->pkt = skb_clone(pskb, GFP_ATOMIC); + if (precvframe->pkt) { + precvframe->rx_tail = pbuf + pattrib->drvinfo_sz + RXDESC_SIZE; + precvframe->rx_head = precvframe->rx_tail; + precvframe->rx_data = precvframe->rx_tail; + precvframe->rx_end = pbuf + pattrib->drvinfo_sz + RXDESC_SIZE + alloc_sz; + } else { + rtw_free_recvframe(precvframe, pfree_recv_queue); + goto _exit_recvbuf2recvframe; + } + } + + recvframe_put(precvframe, skb_len); + + pkt_offset = (u16)round_up(pkt_offset, 128); + + if (pattrib->pkt_rpt_type == NORMAL_RX) { /* Normal rx packet */ + if (pattrib->physt) + update_recvframe_phyinfo_88e(precvframe, (struct phy_stat *)pphy_status); + rtw_recv_entry(precvframe); + } else { + /* enqueue recvframe to txrtp queue */ + if (pattrib->pkt_rpt_type == TX_REPORT1) { + /* CCX-TXRPT ack for xmit mgmt frames. */ + handle_txrpt_ccx_88e(adapt, precvframe->rx_data); + } else if (pattrib->pkt_rpt_type == TX_REPORT2) { + ODM_RA_TxRPT2Handle_8188E( + &haldata->odmpriv, + precvframe->rx_data, + pattrib->pkt_len, + pattrib->MacIDValidEntry[0], + pattrib->MacIDValidEntry[1] + ); + } + rtw_free_recvframe(precvframe, pfree_recv_queue); + } + pkt_cnt--; + transfer_len -= pkt_offset; + pbuf += pkt_offset; + precvframe = NULL; + pkt_copy = NULL; + + if (transfer_len > 0 && pkt_cnt == 0) + pkt_cnt = (le32_to_cpu(prxstat->rxdw2) >> 16) & 0xff; + + } while ((transfer_len > 0) && (pkt_cnt > 0)); + +_exit_recvbuf2recvframe: + + return _SUCCESS; +} + +void rtl8188eu_recv_tasklet(unsigned long priv) +{ + struct sk_buff *pskb; + struct adapter *adapt = (struct adapter *)priv; + struct recv_priv *precvpriv = &adapt->recvpriv; + + while (NULL != (pskb = skb_dequeue(&precvpriv->rx_skb_queue))) { + if ((adapt->bDriverStopped) || (adapt->bSurpriseRemoved)) { + dev_kfree_skb_any(pskb); + break; + } + recvbuf2recvframe(adapt, pskb); + skb_reset_tail_pointer(pskb); + pskb->len = 0; + skb_queue_tail(&precvpriv->free_recv_skb_queue, pskb); + } +} + +static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) +{ + struct recv_buf *precvbuf = (struct recv_buf *)purb->context; + struct adapter *adapt = (struct adapter *)precvbuf->adapter; + struct recv_priv *precvpriv = &adapt->recvpriv; + + precvpriv->rx_pending_cnt--; + + if (adapt->bSurpriseRemoved || adapt->bDriverStopped || adapt->bReadPortCancel) { + precvbuf->reuse = true; + return; + } + + if (purb->status == 0) { /* SUCCESS */ + if ((purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE)) { + precvbuf->reuse = true; + rtw_read_port(adapt, (unsigned char *)precvbuf); + } else { + rtw_reset_continual_urb_error(adapter_to_dvobj(adapt)); + + skb_put(precvbuf->pskb, purb->actual_length); + skb_queue_tail(&precvpriv->rx_skb_queue, precvbuf->pskb); + + if (skb_queue_len(&precvpriv->rx_skb_queue) <= 1) + tasklet_schedule(&precvpriv->recv_tasklet); + + precvbuf->pskb = NULL; + precvbuf->reuse = false; + rtw_read_port(adapt, (unsigned char *)precvbuf); + } + } else { + skb_put(precvbuf->pskb, purb->actual_length); + precvbuf->pskb = NULL; + + if (rtw_inc_and_chk_continual_urb_error(adapter_to_dvobj(adapt))) + adapt->bSurpriseRemoved = true; + + switch (purb->status) { + case -EINVAL: + case -EPIPE: + case -ENODEV: + case -ESHUTDOWN: + case -ENOENT: + adapt->bDriverStopped = true; + break; + case -EPROTO: + case -EOVERFLOW: + precvbuf->reuse = true; + rtw_read_port(adapt, (unsigned char *)precvbuf); + break; + case -EINPROGRESS: + break; + default: + break; + } + } +} + +u32 rtw_read_port(struct adapter *adapter, u8 *rmem) +{ + struct urb *purb = NULL; + struct recv_buf *precvbuf = (struct recv_buf *)rmem; + struct dvobj_priv *pdvobj = adapter_to_dvobj(adapter); + struct recv_priv *precvpriv = &adapter->recvpriv; + struct usb_device *pusbd = pdvobj->pusbdev; + int err; + unsigned int pipe; + size_t tmpaddr = 0; + size_t alignment = 0; + u32 ret = _SUCCESS; + + if (adapter->bDriverStopped || adapter->bSurpriseRemoved) + return _FAIL; + + if (!precvbuf) + return _FAIL; + + if (!precvbuf->reuse || !precvbuf->pskb) { + precvbuf->pskb = skb_dequeue(&precvpriv->free_recv_skb_queue); + if (precvbuf->pskb) + precvbuf->reuse = true; + } + + /* re-assign for linux based on skb */ + if (!precvbuf->reuse || !precvbuf->pskb) { + precvbuf->pskb = netdev_alloc_skb(adapter->pnetdev, MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ); + if (!precvbuf->pskb) + return _FAIL; + + tmpaddr = (size_t)precvbuf->pskb->data; + alignment = tmpaddr & (RECVBUFF_ALIGN_SZ - 1); + skb_reserve(precvbuf->pskb, (RECVBUFF_ALIGN_SZ - alignment)); + } else { /* reuse skb */ + precvbuf->reuse = false; + } + + precvpriv->rx_pending_cnt++; + + purb = precvbuf->purb; + + /* translate DMA FIFO addr to pipehandle */ + pipe = usb_rcvbulkpipe(pusbd, pdvobj->RtInPipe); + + usb_fill_bulk_urb(purb, pusbd, pipe, + precvbuf->pskb->data, + MAX_RECVBUF_SZ, + usb_read_port_complete, + precvbuf);/* context is precvbuf */ + + err = usb_submit_urb(purb, GFP_ATOMIC); + if ((err) && (err != (-EPERM))) + ret = _FAIL; + + return ret; +} + +void rtl8188eu_xmit_tasklet(unsigned long priv) +{ + int ret = false; + struct adapter *adapt = (struct adapter *)priv; + struct xmit_priv *pxmitpriv = &adapt->xmitpriv; + + if (check_fwstate(&adapt->mlmepriv, _FW_UNDER_SURVEY)) + return; + + while (1) { + if ((adapt->bDriverStopped) || + (adapt->bSurpriseRemoved) || + (adapt->bWritePortCancel)) + break; + + ret = rtl8188eu_xmitframe_complete(adapt, pxmitpriv, NULL); + + if (!ret) + break; + } +} |