Adding upstream version 6.1.76.upstream/6.1.76upstream

Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>

1 files changed, 154 insertions, 0 deletions

diff --git a/tools/perf/pmu-events/arch/x86/bonnell/memory.json b/tools/perf/pmu-events/arch/x86/bonnell/memory.json
new file mode 100644
index 000000000..f8b45b6fb
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/bonnell/memory.json
@@ -0,0 +1,154 @@
+[
+    {
+        "BriefDescription": "Nonzero segbase 1 bubble",
+        "Counter": "0,1",
+        "EventCode": "0x5",
+        "EventName": "MISALIGN_MEM_REF.BUBBLE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x97"
+    },
+    {
+        "BriefDescription": "Nonzero segbase load 1 bubble",
+        "Counter": "0,1",
+        "EventCode": "0x5",
+        "EventName": "MISALIGN_MEM_REF.LD_BUBBLE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x91"
+    },
+    {
+        "BriefDescription": "Load splits",
+        "Counter": "0,1",
+        "EventCode": "0x5",
+        "EventName": "MISALIGN_MEM_REF.LD_SPLIT",
+        "SampleAfterValue": "200000",
+        "UMask": "0x9"
+    },
+    {
+        "BriefDescription": "Load splits (At Retirement)",
+        "Counter": "0,1",
+        "EventCode": "0x5",
+        "EventName": "MISALIGN_MEM_REF.LD_SPLIT.AR",
+        "SampleAfterValue": "200000",
+        "UMask": "0x89"
+    },
+    {
+        "BriefDescription": "Nonzero segbase ld-op-st 1 bubble",
+        "Counter": "0,1",
+        "EventCode": "0x5",
+        "EventName": "MISALIGN_MEM_REF.RMW_BUBBLE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x94"
+    },
+    {
+        "BriefDescription": "ld-op-st splits",
+        "Counter": "0,1",
+        "EventCode": "0x5",
+        "EventName": "MISALIGN_MEM_REF.RMW_SPLIT",
+        "SampleAfterValue": "200000",
+        "UMask": "0x8c"
+    },
+    {
+        "BriefDescription": "Memory references that cross an 8-byte boundary.",
+        "Counter": "0,1",
+        "EventCode": "0x5",
+        "EventName": "MISALIGN_MEM_REF.SPLIT",
+        "SampleAfterValue": "200000",
+        "UMask": "0xf"
+    },
+    {
+        "BriefDescription": "Memory references that cross an 8-byte boundary (At Retirement)",
+        "Counter": "0,1",
+        "EventCode": "0x5",
+        "EventName": "MISALIGN_MEM_REF.SPLIT.AR",
+        "SampleAfterValue": "200000",
+        "UMask": "0x8f"
+    },
+    {
+        "BriefDescription": "Nonzero segbase store 1 bubble",
+        "Counter": "0,1",
+        "EventCode": "0x5",
+        "EventName": "MISALIGN_MEM_REF.ST_BUBBLE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x92"
+    },
+    {
+        "BriefDescription": "Store splits",
+        "Counter": "0,1",
+        "EventCode": "0x5",
+        "EventName": "MISALIGN_MEM_REF.ST_SPLIT",
+        "SampleAfterValue": "200000",
+        "UMask": "0xa"
+    },
+    {
+        "BriefDescription": "Store splits (Ar Retirement)",
+        "Counter": "0,1",
+        "EventCode": "0x5",
+        "EventName": "MISALIGN_MEM_REF.ST_SPLIT.AR",
+        "SampleAfterValue": "200000",
+        "UMask": "0x8a"
+    },
+    {
+        "BriefDescription": "L1 hardware prefetch request",
+        "Counter": "0,1",
+        "EventCode": "0x7",
+        "EventName": "PREFETCH.HW_PREFETCH",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x10"
+    },
+    {
+        "BriefDescription": "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed",
+        "Counter": "0,1",
+        "EventCode": "0x7",
+        "EventName": "PREFETCH.PREFETCHNTA",
+        "SampleAfterValue": "200000",
+        "UMask": "0x88"
+    },
+    {
+        "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed.",
+        "Counter": "0,1",
+        "EventCode": "0x7",
+        "EventName": "PREFETCH.PREFETCHT0",
+        "SampleAfterValue": "200000",
+        "UMask": "0x81"
+    },
+    {
+        "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed.",
+        "Counter": "0,1",
+        "EventCode": "0x7",
+        "EventName": "PREFETCH.PREFETCHT1",
+        "SampleAfterValue": "200000",
+        "UMask": "0x82"
+    },
+    {
+        "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed.",
+        "Counter": "0,1",
+        "EventCode": "0x7",
+        "EventName": "PREFETCH.PREFETCHT2",
+        "SampleAfterValue": "200000",
+        "UMask": "0x84"
+    },
+    {
+        "BriefDescription": "Any Software prefetch",
+        "Counter": "0,1",
+        "EventCode": "0x7",
+        "EventName": "PREFETCH.SOFTWARE_PREFETCH",
+        "SampleAfterValue": "200000",
+        "UMask": "0xf"
+    },
+    {
+        "BriefDescription": "Any Software prefetch",
+        "Counter": "0,1",
+        "EventCode": "0x7",
+        "EventName": "PREFETCH.SOFTWARE_PREFETCH.AR",
+        "SampleAfterValue": "200000",
+        "UMask": "0x8f"
+    },
+    {
+        "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed",
+        "Counter": "0,1",
+        "EventCode": "0x7",
+        "EventName": "PREFETCH.SW_L2",
+        "SampleAfterValue": "200000",
+        "UMask": "0x86"
+    }
+]