Adding upstream version 6.1.76.upstream/6.1.76upstream

Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>

1 files changed, 69 insertions, 0 deletions

diff --git a/tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json b/tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json
new file mode 100644
index 000000000..b50cee3a5
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json
@@ -0,0 +1,69 @@
+[
+    {
+        "BriefDescription": "Loads missed DTLB",
+        "Counter": "0,1",
+        "EventCode": "0x04",
+        "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS",
+        "PEBS": "1",
+        "PublicDescription": "This event counts the number of load ops retired that had DTLB miss.",
+        "SampleAfterValue": "200003",
+        "UMask": "0x8"
+    },
+    {
+        "BriefDescription": "Total cycles for all the page walks. (I-side and D-side)",
+        "Counter": "0,1",
+        "EventCode": "0x05",
+        "EventName": "PAGE_WALKS.CYCLES",
+        "PublicDescription": "This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress.  Since a pagewalk implies a TLB miss, the approximate cost of a TLB miss can be determined from this event.",
+        "SampleAfterValue": "200003",
+        "UMask": "0x3"
+    },
+    {
+        "BriefDescription": "Duration of D-side page-walks in core cycles",
+        "Counter": "0,1",
+        "EventCode": "0x05",
+        "EventName": "PAGE_WALKS.D_SIDE_CYCLES",
+        "PublicDescription": "This event counts every cycle when a D-side (walks due to a load) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.",
+        "SampleAfterValue": "200003",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "D-side page-walks",
+        "Counter": "0,1",
+        "EdgeDetect": "1",
+        "EventCode": "0x05",
+        "EventName": "PAGE_WALKS.D_SIDE_WALKS",
+        "PublicDescription": "This event counts when a data (D) page walk is completed or started.  Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.",
+        "SampleAfterValue": "100003",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "Duration of I-side page-walks in core cycles",
+        "Counter": "0,1",
+        "EventCode": "0x05",
+        "EventName": "PAGE_WALKS.I_SIDE_CYCLES",
+        "PublicDescription": "This event counts every cycle when a I-side (walks due to an instruction fetch) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.",
+        "SampleAfterValue": "200003",
+        "UMask": "0x2"
+    },
+    {
+        "BriefDescription": "I-side page-walks",
+        "Counter": "0,1",
+        "EdgeDetect": "1",
+        "EventCode": "0x05",
+        "EventName": "PAGE_WALKS.I_SIDE_WALKS",
+        "PublicDescription": "This event counts when an instruction (I) page walk is completed or started.  Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.",
+        "SampleAfterValue": "100003",
+        "UMask": "0x2"
+    },
+    {
+        "BriefDescription": "Total page walks that are completed (I-side and D-side)",
+        "Counter": "0,1",
+        "EdgeDetect": "1",
+        "EventCode": "0x05",
+        "EventName": "PAGE_WALKS.WALKS",
+        "PublicDescription": "This event counts when a data (D) page walk or an instruction (I) page walk is completed or started.  Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.",
+        "SampleAfterValue": "100003",
+        "UMask": "0x3"
+    }
+]