diff options
Diffstat (limited to 'arch/sh/boards/mach-dreamcast')
| -rw-r--r-- | arch/sh/boards/mach-dreamcast/Makefile | 7 | ||||
| -rw-r--r-- | arch/sh/boards/mach-dreamcast/irq.c | 155 | ||||
| -rw-r--r-- | arch/sh/boards/mach-dreamcast/rtc.c | 96 | ||||
| -rw-r--r-- | arch/sh/boards/mach-dreamcast/setup.c | 39 |
4 files changed, 297 insertions, 0 deletions
diff --git a/arch/sh/boards/mach-dreamcast/Makefile b/arch/sh/boards/mach-dreamcast/Makefile new file mode 100644 index 000000000..37b245220 --- /dev/null +++ b/arch/sh/boards/mach-dreamcast/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for the Sega Dreamcast specific parts of the kernel +# + +obj-y := setup.o irq.o +obj-$(CONFIG_RTC_DRV_GENERIC) += rtc.o diff --git a/arch/sh/boards/mach-dreamcast/irq.c b/arch/sh/boards/mach-dreamcast/irq.c new file mode 100644 index 000000000..0eec82fb8 --- /dev/null +++ b/arch/sh/boards/mach-dreamcast/irq.c @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * arch/sh/boards/dreamcast/irq.c + * + * Holly IRQ support for the Sega Dreamcast. + * + * Copyright (c) 2001, 2002 M. R. Brown <mrbrown@0xd6.org> + * + * This file is part of the LinuxDC project (www.linuxdc.org) + */ +#include <linux/irq.h> +#include <linux/io.h> +#include <linux/export.h> +#include <linux/err.h> +#include <mach/sysasic.h> + +/* + * Dreamcast System ASIC Hardware Events - + * + * The Dreamcast's System ASIC (a.k.a. Holly) is responsible for receiving + * hardware events from system peripherals and triggering an SH7750 IRQ. + * Hardware events can trigger IRQs 13, 11, or 9 depending on which bits are + * set in the Event Mask Registers (EMRs). When a hardware event is + * triggered, its corresponding bit in the Event Status Registers (ESRs) + * is set, and that bit should be rewritten to the ESR to acknowledge that + * event. + * + * There are three 32-bit ESRs located at 0xa05f6900 - 0xa05f6908. Event + * types can be found in arch/sh/include/mach-dreamcast/mach/sysasic.h. + * There are three groups of EMRs that parallel the ESRs. Each EMR group + * corresponds to an IRQ, so 0xa05f6910 - 0xa05f6918 triggers IRQ 13, + * 0xa05f6920 - 0xa05f6928 triggers IRQ 11, and 0xa05f6930 - 0xa05f6938 + * triggers IRQ 9. + * + * In the kernel, these events are mapped to virtual IRQs so that drivers can + * respond to them as they would a normal interrupt. In order to keep this + * mapping simple, the events are mapped as: + * + * 6900/6910 - Events 0-31, IRQ 13 + * 6904/6924 - Events 32-63, IRQ 11 + * 6908/6938 - Events 64-95, IRQ 9 + * + */ + +#define ESR_BASE 0x005f6900 /* Base event status register */ +#define EMR_BASE 0x005f6910 /* Base event mask register */ + +/* + * Helps us determine the EMR group that this event belongs to: 0 = 0x6910, + * 1 = 0x6920, 2 = 0x6930; also determine the event offset. + */ +#define LEVEL(event) (((event) - HW_EVENT_IRQ_BASE) / 32) + +/* Return the hardware event's bit position within the EMR/ESR */ +#define EVENT_BIT(event) (((event) - HW_EVENT_IRQ_BASE) & 31) + +/* + * For each of these *_irq routines, the IRQ passed in is the virtual IRQ + * (logically mapped to the corresponding bit for the hardware event). + */ + +/* Disable the hardware event by masking its bit in its EMR */ +static inline void disable_systemasic_irq(struct irq_data *data) +{ + unsigned int irq = data->irq; + __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2); + __u32 mask; + + mask = inl(emr); + mask &= ~(1 << EVENT_BIT(irq)); + outl(mask, emr); +} + +/* Enable the hardware event by setting its bit in its EMR */ +static inline void enable_systemasic_irq(struct irq_data *data) +{ + unsigned int irq = data->irq; + __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2); + __u32 mask; + + mask = inl(emr); + mask |= (1 << EVENT_BIT(irq)); + outl(mask, emr); +} + +/* Acknowledge a hardware event by writing its bit back to its ESR */ +static void mask_ack_systemasic_irq(struct irq_data *data) +{ + unsigned int irq = data->irq; + __u32 esr = ESR_BASE + (LEVEL(irq) << 2); + disable_systemasic_irq(data); + outl((1 << EVENT_BIT(irq)), esr); +} + +struct irq_chip systemasic_int = { + .name = "System ASIC", + .irq_mask = disable_systemasic_irq, + .irq_mask_ack = mask_ack_systemasic_irq, + .irq_unmask = enable_systemasic_irq, +}; + +/* + * Map the hardware event indicated by the processor IRQ to a virtual IRQ. + */ +int systemasic_irq_demux(int irq) +{ + __u32 emr, esr, status, level; + __u32 j, bit; + + switch (irq) { + case 13 + 16: + level = 0; + break; + case 11 + 16: + level = 1; + break; + case 9 + 16: + level = 2; + break; + default: + return irq; + } + emr = EMR_BASE + (level << 4) + (level << 2); + esr = ESR_BASE + (level << 2); + + /* Mask the ESR to filter any spurious, unwanted interrupts */ + status = inl(esr); + status &= inl(emr); + + /* Now scan and find the first set bit as the event to map */ + for (bit = 1, j = 0; j < 32; bit <<= 1, j++) { + if (status & bit) { + irq = HW_EVENT_IRQ_BASE + j + (level << 5); + return irq; + } + } + + /* Not reached */ + return irq; +} + +void systemasic_irq_init(void) +{ + int irq_base, i; + + irq_base = irq_alloc_descs(HW_EVENT_IRQ_BASE, HW_EVENT_IRQ_BASE, + HW_EVENT_IRQ_MAX - HW_EVENT_IRQ_BASE, -1); + if (IS_ERR_VALUE(irq_base)) { + pr_err("%s: failed hooking irqs\n", __func__); + return; + } + + for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++) + irq_set_chip_and_handler(i, &systemasic_int, handle_level_irq); +} diff --git a/arch/sh/boards/mach-dreamcast/rtc.c b/arch/sh/boards/mach-dreamcast/rtc.c new file mode 100644 index 000000000..7873cd27e --- /dev/null +++ b/arch/sh/boards/mach-dreamcast/rtc.c @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * arch/sh/boards/dreamcast/rtc.c + * + * Dreamcast AICA RTC routines. + * + * Copyright (c) 2001, 2002 M. R. Brown <mrbrown@0xd6.org> + * Copyright (c) 2002 Paul Mundt <lethal@chaoticdreams.org> + */ + +#include <linux/time.h> +#include <linux/rtc.h> +#include <linux/io.h> +#include <linux/platform_device.h> + +/* The AICA RTC has an Epoch of 1/1/1950, so we must subtract 20 years (in + seconds) to get the standard Unix Epoch when getting the time, and add + 20 years when setting the time. */ +#define TWENTY_YEARS ((20 * 365LU + 5) * 86400) + +/* The AICA RTC is represented by a 32-bit seconds counter stored in 2 16-bit + registers.*/ +#define AICA_RTC_SECS_H 0xa0710000 +#define AICA_RTC_SECS_L 0xa0710004 + +/** + * aica_rtc_gettimeofday - Get the time from the AICA RTC + * @dev: the RTC device (ignored) + * @tm: pointer to resulting RTC time structure + * + * Grabs the current RTC seconds counter and adjusts it to the Unix Epoch. + */ +static int aica_rtc_gettimeofday(struct device *dev, struct rtc_time *tm) +{ + unsigned long val1, val2; + time64_t t; + + do { + val1 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | + (__raw_readl(AICA_RTC_SECS_L) & 0xffff); + + val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | + (__raw_readl(AICA_RTC_SECS_L) & 0xffff); + } while (val1 != val2); + + /* normalize to 1970..2106 time range */ + t = (u32)(val1 - TWENTY_YEARS); + + rtc_time64_to_tm(t, tm); + + return 0; +} + +/** + * aica_rtc_settimeofday - Set the AICA RTC to the current time + * @dev: the RTC device (ignored) + * @tm: pointer to new RTC time structure + * + * Adjusts the given @tv to the AICA Epoch and sets the RTC seconds counter. + */ +static int aica_rtc_settimeofday(struct device *dev, struct rtc_time *tm) +{ + unsigned long val1, val2; + time64_t secs = rtc_tm_to_time64(tm); + u32 adj = secs + TWENTY_YEARS; + + do { + __raw_writel((adj & 0xffff0000) >> 16, AICA_RTC_SECS_H); + __raw_writel((adj & 0xffff), AICA_RTC_SECS_L); + + val1 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | + (__raw_readl(AICA_RTC_SECS_L) & 0xffff); + + val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | + (__raw_readl(AICA_RTC_SECS_L) & 0xffff); + } while (val1 != val2); + + return 0; +} + +static const struct rtc_class_ops rtc_generic_ops = { + .read_time = aica_rtc_gettimeofday, + .set_time = aica_rtc_settimeofday, +}; + +static int __init aica_time_init(void) +{ + struct platform_device *pdev; + + pdev = platform_device_register_data(NULL, "rtc-generic", -1, + &rtc_generic_ops, + sizeof(rtc_generic_ops)); + + return PTR_ERR_OR_ZERO(pdev); +} +arch_initcall(aica_time_init); diff --git a/arch/sh/boards/mach-dreamcast/setup.c b/arch/sh/boards/mach-dreamcast/setup.c new file mode 100644 index 000000000..2d966c1c2 --- /dev/null +++ b/arch/sh/boards/mach-dreamcast/setup.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * arch/sh/boards/dreamcast/setup.c + * + * Hardware support for the Sega Dreamcast. + * + * Copyright (c) 2001, 2002 M. R. Brown <mrbrown@linuxdc.org> + * Copyright (c) 2002, 2003, 2004 Paul Mundt <lethal@linux-sh.org> + * + * This file is part of the LinuxDC project (www.linuxdc.org) + * + * This file originally bore the message (with enclosed-$): + * Id: setup_dc.c,v 1.5 2001/05/24 05:09:16 mrbrown Exp + * SEGA Dreamcast support + */ + +#include <linux/sched.h> +#include <linux/kernel.h> +#include <linux/param.h> +#include <linux/interrupt.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/device.h> +#include <asm/io.h> +#include <asm/irq.h> +#include <asm/rtc.h> +#include <asm/machvec.h> +#include <mach/sysasic.h> + +static void __init dreamcast_setup(char **cmdline_p) +{ +} + +static struct sh_machine_vector mv_dreamcast __initmv = { + .mv_name = "Sega Dreamcast", + .mv_setup = dreamcast_setup, + .mv_irq_demux = systemasic_irq_demux, + .mv_init_irq = systemasic_irq_init, +}; |